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/*
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 * i386 virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#define TARGET_HAS_ICE 1
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#ifdef TARGET_X86_64
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#define ELF_MACHINE        EM_X86_64
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#else
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#define ELF_MACHINE        EM_386
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#endif
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#define CPUState struct CPUX86State
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
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#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C           0x0001
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#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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/* hidden flags - used internally by qemu to represent additional cpu
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   states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
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   redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
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   position to ease oring with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
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#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_RF_SHIFT         16 /* must be same as eflags */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
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#define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
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#define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
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#define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
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#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
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#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_RF_MASK           (1 << HF_RF_SHIFT)
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#define HF_VM_MASK           (1 << HF_VM_SHIFT)
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#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
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#define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
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#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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/* hflags2 */
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#define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
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#define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
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#define HF2_NMI_SHIFT        2 /* CPU serving NMI */
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#define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
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#define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
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#define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT) 
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#define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
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#define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
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#define CR0_PE_SHIFT 0
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#define CR0_MP_SHIFT 1
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
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#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
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#define CR0_PG_MASK  (1 << 31)
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#define CR4_VME_MASK  (1 << 0)
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#define CR4_PVI_MASK  (1 << 1)
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#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_MCE_MASK  (1 << 6)
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#define CR4_PGE_MASK  (1 << 7)
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#define CR4_PCE_MASK  (1 << 8)
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#define CR4_OSFXSR_SHIFT 9
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#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
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#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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#define DR6_BD          (1 << 13)
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#define DR6_BS          (1 << 14)
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#define DR6_BT          (1 << 15)
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#define DR6_FIXED_1     0xffff0ff0
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#define DR7_GD          (1 << 13)
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#define DR7_TYPE_SHIFT  16
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#define DR7_LEN_SHIFT   18
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#define DR7_FIXED_1     0x00000400
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#define PG_PRESENT_BIT        0
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#define PG_RW_BIT        1
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#define PG_USER_BIT        2
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#define PG_PWT_BIT        3
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#define PG_PCD_BIT        4
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#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
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#define PG_PSE_BIT        7
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#define PG_GLOBAL_BIT        8
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#define PG_NX_BIT        63
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
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#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
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#define PG_NX_MASK         (1LL << PG_NX_BIT)
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#define PG_ERROR_W_BIT     1
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#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK    0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define PG_ERROR_I_D_MASK  0x10
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#define MCG_CTL_P        (1UL<<8)   /* MCG_CAP register available */
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#define MCE_CAP_DEF        MCG_CTL_P
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#define MCE_BANKS_DEF        10
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#define MCG_STATUS_MCIP        (1ULL<<2)   /* machine check in progress */
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#define MCI_STATUS_VAL        (1ULL<<63)  /* valid error */
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#define MCI_STATUS_OVER        (1ULL<<62)  /* previous errors lost */
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#define MCI_STATUS_UC        (1ULL<<61)  /* uncorrected error */
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#define MSR_IA32_TSC                    0x10
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#define MSR_IA32_APICBASE               0x1b
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#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_MTRRcap                        0xfe
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#define MSR_MTRRcap_VCNT                8
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#define MSR_MTRRcap_FIXRANGE_SUPPORT        (1 << 8)
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#define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_MCG_CAP                     0x179
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#define MSR_MCG_STATUS                  0x17a
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#define MSR_MCG_CTL                     0x17b
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#define MSR_IA32_PERF_STATUS            0x198
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#define MSR_MTRRphysBase(reg)                (0x200 + 2 * (reg))
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#define MSR_MTRRphysMask(reg)                (0x200 + 2 * (reg) + 1)
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#define MSR_MTRRfix64K_00000                0x250
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#define MSR_MTRRfix16K_80000                0x258
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#define MSR_MTRRfix16K_A0000                0x259
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#define MSR_MTRRfix4K_C0000                0x268
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#define MSR_MTRRfix4K_C8000                0x269
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#define MSR_MTRRfix4K_D0000                0x26a
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#define MSR_MTRRfix4K_D8000                0x26b
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#define MSR_MTRRfix4K_E0000                0x26c
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#define MSR_MTRRfix4K_E8000                0x26d
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#define MSR_MTRRfix4K_F0000                0x26e
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#define MSR_MTRRfix4K_F8000                0x26f
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#define MSR_PAT                         0x277
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#define MSR_MTRRdefType                        0x2ff
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#define MSR_MC0_CTL                        0x400
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#define MSR_MC0_STATUS                        0x401
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#define MSR_MC0_ADDR                        0x402
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#define MSR_MC0_MISC                        0x403
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#define MSR_EFER                        0xc0000080
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#define MSR_EFER_SCE   (1 << 0)
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#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_SVME  (1 << 12)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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#define MSR_TSC_AUX                     0xc0000103
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#define MSR_VM_HSAVE_PA                 0xc0010117
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/* cpuid_features bits */
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#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
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#define CPUID_PGE  (1 << 13)
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#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
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#define CPUID_PAT  (1 << 16)
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#define CPUID_PSE36   (1 << 17)
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#define CPUID_PN   (1 << 18)
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#define CPUID_CLFLUSH (1 << 19)
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#define CPUID_DTS (1 << 21)
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#define CPUID_ACPI (1 << 22)
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#define CPUID_MMX  (1 << 23)
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#define CPUID_FXSR (1 << 24)
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#define CPUID_SSE  (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define CPUID_SS (1 << 27)
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#define CPUID_HT (1 << 28)
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#define CPUID_TM (1 << 29)
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#define CPUID_IA64 (1 << 30)
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#define CPUID_PBE (1 << 31)
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#define CPUID_EXT_SSE3     (1 << 0)
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#define CPUID_EXT_DTES64   (1 << 2)
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#define CPUID_EXT_MONITOR  (1 << 3)
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#define CPUID_EXT_DSCPL    (1 << 4)
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#define CPUID_EXT_VMX      (1 << 5)
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#define CPUID_EXT_SMX      (1 << 6)
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#define CPUID_EXT_EST      (1 << 7)
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#define CPUID_EXT_TM2      (1 << 8)
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#define CPUID_EXT_SSSE3    (1 << 9)
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#define CPUID_EXT_CID      (1 << 10)
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#define CPUID_EXT_CX16     (1 << 13)
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#define CPUID_EXT_XTPR     (1 << 14)
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#define CPUID_EXT_PDCM     (1 << 15)
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#define CPUID_EXT_DCA      (1 << 18)
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#define CPUID_EXT_SSE41    (1 << 19)
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#define CPUID_EXT_SSE42    (1 << 20)
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#define CPUID_EXT_X2APIC   (1 << 21)
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#define CPUID_EXT_MOVBE    (1 << 22)
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#define CPUID_EXT_POPCNT   (1 << 23)
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#define CPUID_EXT_XSAVE    (1 << 26)
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#define CPUID_EXT_OSXSAVE  (1 << 27)
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#define CPUID_EXT_HYPERVISOR  (1 << 31)
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#define CPUID_EXT2_SYSCALL (1 << 11)
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#define CPUID_EXT2_MP      (1 << 19)
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#define CPUID_EXT2_NX      (1 << 20)
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#define CPUID_EXT2_MMXEXT  (1 << 22)
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#define CPUID_EXT2_FFXSR   (1 << 25)
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#define CPUID_EXT2_PDPE1GB (1 << 26)
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#define CPUID_EXT2_RDTSCP  (1 << 27)
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#define CPUID_EXT2_LM      (1 << 29)
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#define CPUID_EXT2_3DNOWEXT (1 << 30)
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#define CPUID_EXT2_3DNOW   (1 << 31)
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#define CPUID_EXT3_LAHF_LM (1 << 0)
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#define CPUID_EXT3_CMP_LEG (1 << 1)
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#define CPUID_EXT3_SVM     (1 << 2)
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#define CPUID_EXT3_EXTAPIC (1 << 3)
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#define CPUID_EXT3_CR8LEG  (1 << 4)
400
#define CPUID_EXT3_ABM     (1 << 5)
401
#define CPUID_EXT3_SSE4A   (1 << 6)
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#define CPUID_EXT3_MISALIGNSSE (1 << 7)
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#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
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#define CPUID_EXT3_OSVW    (1 << 9)
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#define CPUID_EXT3_IBS     (1 << 10)
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#define CPUID_EXT3_SKINIT  (1 << 12)
407

    
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#define CPUID_SVM_NPT          (1 << 0)
409
#define CPUID_SVM_LBRV         (1 << 1)
410
#define CPUID_SVM_SVMLOCK      (1 << 2)
411
#define CPUID_SVM_NRIPSAVE     (1 << 3)
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#define CPUID_SVM_TSCSCALE     (1 << 4)
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#define CPUID_SVM_VMCBCLEAN    (1 << 5)
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#define CPUID_SVM_FLUSHASID    (1 << 6)
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#define CPUID_SVM_DECODEASSIST (1 << 7)
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#define CPUID_SVM_PAUSEFILTER  (1 << 10)
417
#define CPUID_SVM_PFTHRESHOLD  (1 << 12)
418

    
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#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
420
#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
421
#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
422

    
423
#define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
424
#define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */ 
425
#define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
426

    
427
#define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
428
#define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
429

    
430
#define EXCP00_DIVZ        0
431
#define EXCP01_DB        1
432
#define EXCP02_NMI        2
433
#define EXCP03_INT3        3
434
#define EXCP04_INTO        4
435
#define EXCP05_BOUND        5
436
#define EXCP06_ILLOP        6
437
#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
439
#define EXCP09_XERR        9
440
#define EXCP0A_TSS        10
441
#define EXCP0B_NOSEG        11
442
#define EXCP0C_STACK        12
443
#define EXCP0D_GPF        13
444
#define EXCP0E_PAGE        14
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#define EXCP10_COPR        16
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#define EXCP11_ALGN        17
447
#define EXCP12_MCHK        18
448

    
449
#define EXCP_SYSCALL    0x100 /* only happens in user only emulation
450
                                 for syscall instruction */
451

    
452
enum {
453
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
454
    CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
455

    
456
    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
457
    CC_OP_MULW,
458
    CC_OP_MULL,
459
    CC_OP_MULQ,
460

    
461
    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
462
    CC_OP_ADDW,
463
    CC_OP_ADDL,
464
    CC_OP_ADDQ,
465

    
466
    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
467
    CC_OP_ADCW,
468
    CC_OP_ADCL,
469
    CC_OP_ADCQ,
470

    
471
    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
472
    CC_OP_SUBW,
473
    CC_OP_SUBL,
474
    CC_OP_SUBQ,
475

    
476
    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
477
    CC_OP_SBBW,
478
    CC_OP_SBBL,
479
    CC_OP_SBBQ,
480

    
481
    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
482
    CC_OP_LOGICW,
483
    CC_OP_LOGICL,
484
    CC_OP_LOGICQ,
485

    
486
    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
487
    CC_OP_INCW,
488
    CC_OP_INCL,
489
    CC_OP_INCQ,
490

    
491
    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
492
    CC_OP_DECW,
493
    CC_OP_DECL,
494
    CC_OP_DECQ,
495

    
496
    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
497
    CC_OP_SHLW,
498
    CC_OP_SHLL,
499
    CC_OP_SHLQ,
500

    
501
    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
502
    CC_OP_SARW,
503
    CC_OP_SARL,
504
    CC_OP_SARQ,
505

    
506
    CC_OP_NB,
507
};
508

    
509
#ifdef FLOATX80
510
#define USE_X86LDOUBLE
511
#endif
512

    
513
#ifdef USE_X86LDOUBLE
514
typedef floatx80 CPU86_LDouble;
515
#else
516
typedef float64 CPU86_LDouble;
517
#endif
518

    
519
typedef struct SegmentCache {
520
    uint32_t selector;
521
    target_ulong base;
522
    uint32_t limit;
523
    uint32_t flags;
524
} SegmentCache;
525

    
526
typedef union {
527
    uint8_t _b[16];
528
    uint16_t _w[8];
529
    uint32_t _l[4];
530
    uint64_t _q[2];
531
    float32 _s[4];
532
    float64 _d[2];
533
} XMMReg;
534

    
535
typedef union {
536
    uint8_t _b[8];
537
    uint16_t _w[4];
538
    uint32_t _l[2];
539
    float32 _s[2];
540
    uint64_t q;
541
} MMXReg;
542

    
543
#ifdef HOST_WORDS_BIGENDIAN
544
#define XMM_B(n) _b[15 - (n)]
545
#define XMM_W(n) _w[7 - (n)]
546
#define XMM_L(n) _l[3 - (n)]
547
#define XMM_S(n) _s[3 - (n)]
548
#define XMM_Q(n) _q[1 - (n)]
549
#define XMM_D(n) _d[1 - (n)]
550

    
551
#define MMX_B(n) _b[7 - (n)]
552
#define MMX_W(n) _w[3 - (n)]
553
#define MMX_L(n) _l[1 - (n)]
554
#define MMX_S(n) _s[1 - (n)]
555
#else
556
#define XMM_B(n) _b[n]
557
#define XMM_W(n) _w[n]
558
#define XMM_L(n) _l[n]
559
#define XMM_S(n) _s[n]
560
#define XMM_Q(n) _q[n]
561
#define XMM_D(n) _d[n]
562

    
563
#define MMX_B(n) _b[n]
564
#define MMX_W(n) _w[n]
565
#define MMX_L(n) _l[n]
566
#define MMX_S(n) _s[n]
567
#endif
568
#define MMX_Q(n) q
569

    
570
typedef union {
571
#ifdef USE_X86LDOUBLE
572
    CPU86_LDouble d __attribute__((aligned(16)));
573
#else
574
    CPU86_LDouble d;
575
#endif
576
    MMXReg mmx;
577
} FPReg;
578

    
579
typedef struct {
580
    uint64_t base;
581
    uint64_t mask;
582
} MTRRVar;
583

    
584
#define CPU_NB_REGS64 16
585
#define CPU_NB_REGS32 8
586

    
587
#ifdef TARGET_X86_64
588
#define CPU_NB_REGS CPU_NB_REGS64
589
#else
590
#define CPU_NB_REGS CPU_NB_REGS32
591
#endif
592

    
593
#define NB_MMU_MODES 2
594

    
595
typedef struct CPUX86State {
596
    /* standard registers */
597
    target_ulong regs[CPU_NB_REGS];
598
    target_ulong eip;
599
    target_ulong eflags; /* eflags register. During CPU emulation, CC
600
                        flags and DF are set to zero because they are
601
                        stored elsewhere */
602

    
603
    /* emulator internal eflags handling */
604
    target_ulong cc_src;
605
    target_ulong cc_dst;
606
    uint32_t cc_op;
607
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
608
    uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
609
                        are known at translation time. */
610
    uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
611

    
612
    /* segments */
613
    SegmentCache segs[6]; /* selector values */
614
    SegmentCache ldt;
615
    SegmentCache tr;
616
    SegmentCache gdt; /* only base and limit are used */
617
    SegmentCache idt; /* only base and limit are used */
618

    
619
    target_ulong cr[5]; /* NOTE: cr1 is unused */
620
    int32_t a20_mask;
621

    
622
    /* FPU state */
623
    unsigned int fpstt; /* top of stack index */
624
    uint16_t fpus;
625
    uint16_t fpuc;
626
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
627
    FPReg fpregs[8];
628

    
629
    /* emulator internal variables */
630
    float_status fp_status;
631
    CPU86_LDouble ft0;
632

    
633
    float_status mmx_status; /* for 3DNow! float ops */
634
    float_status sse_status;
635
    uint32_t mxcsr;
636
    XMMReg xmm_regs[CPU_NB_REGS];
637
    XMMReg xmm_t0;
638
    MMXReg mmx_t0;
639
    target_ulong cc_tmp; /* temporary for rcr/rcl */
640

    
641
    /* sysenter registers */
642
    uint32_t sysenter_cs;
643
    target_ulong sysenter_esp;
644
    target_ulong sysenter_eip;
645
    uint64_t efer;
646
    uint64_t star;
647

    
648
    uint64_t vm_hsave;
649
    uint64_t vm_vmcb;
650
    uint64_t tsc_offset;
651
    uint64_t intercept;
652
    uint16_t intercept_cr_read;
653
    uint16_t intercept_cr_write;
654
    uint16_t intercept_dr_read;
655
    uint16_t intercept_dr_write;
656
    uint32_t intercept_exceptions;
657
    uint8_t v_tpr;
658

    
659
#ifdef TARGET_X86_64
660
    target_ulong lstar;
661
    target_ulong cstar;
662
    target_ulong fmask;
663
    target_ulong kernelgsbase;
664
#endif
665
    uint64_t system_time_msr;
666
    uint64_t wall_clock_msr;
667

    
668
    uint64_t tsc;
669

    
670
    uint64_t pat;
671

    
672
    /* exception/interrupt handling */
673
    int error_code;
674
    int exception_is_int;
675
    target_ulong exception_next_eip;
676
    target_ulong dr[8]; /* debug registers */
677
    union {
678
        CPUBreakpoint *cpu_breakpoint[4];
679
        CPUWatchpoint *cpu_watchpoint[4];
680
    }; /* break/watchpoints for dr[0..3] */
681
    uint32_t smbase;
682
    int old_exception;  /* exception in flight */
683

    
684
    CPU_COMMON
685

    
686
    /* processor features (e.g. for CPUID insn) */
687
    uint32_t cpuid_level;
688
    uint32_t cpuid_vendor1;
689
    uint32_t cpuid_vendor2;
690
    uint32_t cpuid_vendor3;
691
    uint32_t cpuid_version;
692
    uint32_t cpuid_features;
693
    uint32_t cpuid_ext_features;
694
    uint32_t cpuid_xlevel;
695
    uint32_t cpuid_model[12];
696
    uint32_t cpuid_ext2_features;
697
    uint32_t cpuid_ext3_features;
698
    uint32_t cpuid_apic_id;
699
    int cpuid_vendor_override;
700

    
701
    /* MTRRs */
702
    uint64_t mtrr_fixed[11];
703
    uint64_t mtrr_deftype;
704
    MTRRVar mtrr_var[8];
705

    
706
    /* For KVM */
707
    uint32_t mp_state;
708
    int32_t exception_injected;
709
    int32_t interrupt_injected;
710
    uint8_t soft_interrupt;
711
    uint8_t nmi_injected;
712
    uint8_t nmi_pending;
713
    uint8_t has_error_code;
714
    uint32_t sipi_vector;
715
    uint32_t cpuid_kvm_features;
716
    uint32_t cpuid_svm_features;
717
    
718
    /* in order to simplify APIC support, we leave this pointer to the
719
       user */
720
    struct DeviceState *apic_state;
721

    
722
    uint64 mcg_cap;
723
    uint64 mcg_status;
724
    uint64 mcg_ctl;
725
    uint64 mce_banks[MCE_BANKS_DEF*4];
726

    
727
    uint64_t tsc_aux;
728

    
729
    /* vmstate */
730
    uint16_t fpus_vmstate;
731
    uint16_t fptag_vmstate;
732
    uint16_t fpregs_format_vmstate;
733

    
734
    uint64_t xstate_bv;
735
    XMMReg ymmh_regs[CPU_NB_REGS];
736

    
737
    uint64_t xcr0;
738
} CPUX86State;
739

    
740
CPUX86State *cpu_x86_init(const char *cpu_model);
741
int cpu_x86_exec(CPUX86State *s);
742
void cpu_x86_close(CPUX86State *s);
743
void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
744
                   const char *optarg);
745
void x86_cpudef_setup(void);
746

    
747
int cpu_get_pic_interrupt(CPUX86State *s);
748
/* MSDOS compatibility mode FPU exception support */
749
void cpu_set_ferr(CPUX86State *s);
750

    
751
/* this function must always be used to load data in the segment
752
   cache: it synchronizes the hflags with the segment cache values */
753
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
754
                                          int seg_reg, unsigned int selector,
755
                                          target_ulong base,
756
                                          unsigned int limit,
757
                                          unsigned int flags)
758
{
759
    SegmentCache *sc;
760
    unsigned int new_hflags;
761

    
762
    sc = &env->segs[seg_reg];
763
    sc->selector = selector;
764
    sc->base = base;
765
    sc->limit = limit;
766
    sc->flags = flags;
767

    
768
    /* update the hidden flags */
769
    {
770
        if (seg_reg == R_CS) {
771
#ifdef TARGET_X86_64
772
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
773
                /* long mode */
774
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
775
                env->hflags &= ~(HF_ADDSEG_MASK);
776
            } else
777
#endif
778
            {
779
                /* legacy / compatibility case */
780
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
781
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
782
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
783
                    new_hflags;
784
            }
785
        }
786
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
787
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
788
        if (env->hflags & HF_CS64_MASK) {
789
            /* zero base assumed for DS, ES and SS in long mode */
790
        } else if (!(env->cr[0] & CR0_PE_MASK) ||
791
                   (env->eflags & VM_MASK) ||
792
                   !(env->hflags & HF_CS32_MASK)) {
793
            /* XXX: try to avoid this test. The problem comes from the
794
               fact that is real mode or vm86 mode we only modify the
795
               'base' and 'selector' fields of the segment cache to go
796
               faster. A solution may be to force addseg to one in
797
               translate-i386.c. */
798
            new_hflags |= HF_ADDSEG_MASK;
799
        } else {
800
            new_hflags |= ((env->segs[R_DS].base |
801
                            env->segs[R_ES].base |
802
                            env->segs[R_SS].base) != 0) <<
803
                HF_ADDSEG_SHIFT;
804
        }
805
        env->hflags = (env->hflags &
806
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
807
    }
808
}
809

    
810
static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env,
811
                                               int sipi_vector)
812
{
813
    env->eip = 0;
814
    cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
815
                           sipi_vector << 12,
816
                           env->segs[R_CS].limit,
817
                           env->segs[R_CS].flags);
818
    env->halted = 0;
819
}
820

    
821
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
822
                            target_ulong *base, unsigned int *limit,
823
                            unsigned int *flags);
824

    
825
/* wrapper, just in case memory mappings must be changed */
826
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
827
{
828
#if HF_CPL_MASK == 3
829
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
830
#else
831
#error HF_CPL_MASK is hardcoded
832
#endif
833
}
834

    
835
/* op_helper.c */
836
/* used for debug or cpu save/restore */
837
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
838
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
839

    
840
/* cpu-exec.c */
841
/* the following helpers are only usable in user mode simulation as
842
   they can trigger unexpected exceptions */
843
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
844
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
845
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
846

    
847
/* you can call this signal handler from your SIGBUS and SIGSEGV
848
   signal handlers to inform the virtual CPU of exceptions. non zero
849
   is returned if the signal was handled by the virtual CPU.  */
850
int cpu_x86_signal_handler(int host_signum, void *pinfo,
851
                           void *puc);
852

    
853
/* cpuid.c */
854
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
855
                   uint32_t *eax, uint32_t *ebx,
856
                   uint32_t *ecx, uint32_t *edx);
857
int cpu_x86_register (CPUX86State *env, const char *cpu_model);
858
void cpu_clear_apic_feature(CPUX86State *env);
859

    
860
/* helper.c */
861
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
862
                             int is_write, int mmu_idx, int is_softmmu);
863
#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
864
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
865

    
866
static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
867
{
868
    return (dr7 >> (index * 2)) & 3;
869
}
870

    
871
static inline int hw_breakpoint_type(unsigned long dr7, int index)
872
{
873
    return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
874
}
875

    
876
static inline int hw_breakpoint_len(unsigned long dr7, int index)
877
{
878
    int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
879
    return (len == 2) ? 8 : len + 1;
880
}
881

    
882
void hw_breakpoint_insert(CPUX86State *env, int index);
883
void hw_breakpoint_remove(CPUX86State *env, int index);
884
int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
885

    
886
/* will be suppressed */
887
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
888
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
889
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
890

    
891
/* hw/pc.c */
892
void cpu_smm_update(CPUX86State *env);
893
uint64_t cpu_get_tsc(CPUX86State *env);
894

    
895
/* used to debug */
896
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
897
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
898

    
899
#define TARGET_PAGE_BITS 12
900

    
901
#ifdef TARGET_X86_64
902
#define TARGET_PHYS_ADDR_SPACE_BITS 52
903
/* ??? This is really 48 bits, sign-extended, but the only thing
904
   accessible to userland with bit 48 set is the VSYSCALL, and that
905
   is handled via other mechanisms.  */
906
#define TARGET_VIRT_ADDR_SPACE_BITS 47
907
#else
908
#define TARGET_PHYS_ADDR_SPACE_BITS 36
909
#define TARGET_VIRT_ADDR_SPACE_BITS 32
910
#endif
911

    
912
#define cpu_init cpu_x86_init
913
#define cpu_exec cpu_x86_exec
914
#define cpu_gen_code cpu_x86_gen_code
915
#define cpu_signal_handler cpu_x86_signal_handler
916
#define cpu_list_id x86_cpu_list
917
#define cpudef_setup        x86_cpudef_setup
918

    
919
#define CPU_SAVE_VERSION 12
920

    
921
/* MMU modes definitions */
922
#define MMU_MODE0_SUFFIX _kernel
923
#define MMU_MODE1_SUFFIX _user
924
#define MMU_USER_IDX 1
925
static inline int cpu_mmu_index (CPUState *env)
926
{
927
    return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
928
}
929

    
930
/* translate.c */
931
void optimize_flags_init(void);
932

    
933
typedef struct CCTable {
934
    int (*compute_all)(void); /* return all the flags */
935
    int (*compute_c)(void);  /* return the C flag */
936
} CCTable;
937

    
938
#if defined(CONFIG_USER_ONLY)
939
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
940
{
941
    if (newsp)
942
        env->regs[R_ESP] = newsp;
943
    env->regs[R_EAX] = 0;
944
}
945
#endif
946

    
947
#include "cpu-all.h"
948
#include "svm.h"
949

    
950
#if !defined(CONFIG_USER_ONLY)
951
#include "hw/apic.h"
952
#endif
953

    
954
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
955
                                        target_ulong *cs_base, int *flags)
956
{
957
    *cs_base = env->segs[R_CS].base;
958
    *pc = *cs_base + env->eip;
959
    *flags = env->hflags |
960
        (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
961
}
962

    
963
void do_cpu_init(CPUState *env);
964
void do_cpu_sipi(CPUState *env);
965
#endif /* CPU_I386_H */