Revision 29929e34 target-mips/op_helper.c
| b/target-mips/op_helper.c | ||
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cpu_abort(env, "mtc0 status irqraise debug\n"); |
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} |
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void do_tlbwi (void) |
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{
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cpu_abort(env, "tlbwi\n"); |
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} |
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void do_tlbwr (void) |
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{
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cpu_abort(env, "tlbwr\n"); |
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} |
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void do_tlbp (void) |
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{
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cpu_abort(env, "tlbp\n"); |
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} |
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void do_tlbr (void) |
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{
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cpu_abort(env, "tlbr\n"); |
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} |
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void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
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{
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cpu_abort(env, "mips_tlb_flush\n"); |
| ... | ... | |
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} |
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/* TLB management */ |
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#if defined(MIPS_USES_R4K_TLB) |
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void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
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{
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/* Flush qemu's TLB and discard all shadowed entries. */ |
| ... | ... | |
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env->tlb_in_use = env->nb_tlb; |
| 398 | 377 |
} |
| 399 | 378 |
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static void mips_tlb_flush_extra (CPUState *env, int first) |
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static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
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{
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/* Discard entries from env->tlb[first] onwards. */ |
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while (env->tlb_in_use > first) {
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invalidate_tlb(env, --env->tlb_in_use, 0); |
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r4k_invalidate_tlb(env, --env->tlb_in_use, 0);
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} |
| 406 | 385 |
} |
| 407 | 386 |
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static void fill_tlb (int idx) |
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static void r4k_fill_tlb (int idx)
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{
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tlb_t *tlb; |
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r4k_tlb_t *tlb;
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/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
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tlb = &env->tlb[idx]; |
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tlb = &env->mmu.r4k.tlb[idx];
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tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF; |
| 415 | 394 |
tlb->ASID = env->CP0_EntryHi & 0xFF; |
| 416 | 395 |
tlb->PageMask = env->CP0_PageMask; |
| ... | ... | |
| 425 | 404 |
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
| 426 | 405 |
} |
| 427 | 406 |
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void do_tlbwi (void) |
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void r4k_do_tlbwi (void)
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{
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/* Discard cached TLB entries. We could avoid doing this if the |
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tlbwi is just upgrading access permissions on the current entry; |
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that might be a further win. */ |
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mips_tlb_flush_extra (env, env->nb_tlb); |
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r4k_mips_tlb_flush_extra (env, env->nb_tlb);
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invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0); |
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fill_tlb(env->CP0_Index % env->nb_tlb); |
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r4k_invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
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r4k_fill_tlb(env->CP0_Index % env->nb_tlb);
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} |
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void do_tlbwr (void) |
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void r4k_do_tlbwr (void)
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{
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int r = cpu_mips_get_random(env); |
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invalidate_tlb(env, r, 1); |
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fill_tlb(r); |
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r4k_invalidate_tlb(env, r, 1);
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r4k_fill_tlb(r);
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} |
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void do_tlbp (void) |
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void r4k_do_tlbp (void)
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{
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tlb_t *tlb; |
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r4k_tlb_t *tlb;
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target_ulong tag; |
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uint8_t ASID; |
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int i; |
| ... | ... | |
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tag = env->CP0_EntryHi & (int32_t)0xFFFFE000; |
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ASID = env->CP0_EntryHi & 0xFF; |
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i]; |
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tlb = &env->mmu.r4k.tlb[i];
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/* Check ASID, virtual page number & size */ |
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if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
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/* TLB match */ |
| ... | ... | |
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if (i == env->nb_tlb) {
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/* No match. Discard any shadow entries, if any of them match. */ |
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for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
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tlb = &env->tlb[i]; |
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tlb = &env->mmu.r4k.tlb[i];
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/* Check ASID, virtual page number & size */ |
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if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
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mips_tlb_flush_extra (env, i); |
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r4k_mips_tlb_flush_extra (env, i);
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break; |
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} |
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} |
| ... | ... | |
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} |
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} |
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void do_tlbr (void) |
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void r4k_do_tlbr (void)
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{
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tlb_t *tlb; |
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r4k_tlb_t *tlb;
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uint8_t ASID; |
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ASID = env->CP0_EntryHi & 0xFF; |
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tlb = &env->tlb[env->CP0_Index % env->nb_tlb]; |
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tlb = &env->mmu.r4k.tlb[env->CP0_Index % env->nb_tlb];
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/* If this will change the current ASID, flush qemu's TLB. */ |
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if (ASID != tlb->ASID) |
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cpu_mips_tlb_flush (env, 1); |
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mips_tlb_flush_extra(env, env->nb_tlb); |
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r4k_mips_tlb_flush_extra(env, env->nb_tlb);
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env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
| 496 | 475 |
env->CP0_PageMask = tlb->PageMask; |
| ... | ... | |
| 499 | 478 |
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
| 500 | 479 |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
| 501 | 480 |
} |
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#endif |
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| 503 | 481 |
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#endif /* !CONFIG_USER_ONLY */ |
| 505 | 483 |
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