Revision 29929e34 target-mips/translate_init.c
| b/target-mips/translate_init.c | ||
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.Status_rw_bitmask = 0x3678FFFF, |
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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(1 << FCR0_D) | (1 << FCR0_S) | |
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(0x4 << FCR0_PRID) | (0x0 << FCR0_REV),
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(0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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}, |
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#endif |
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}; |
| ... | ... | |
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} |
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} |
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#ifndef CONFIG_USER_ONLY |
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static void no_mmu_init (CPUMIPSState *env, mips_def_t *def) |
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{
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env->nb_tlb = 1; |
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env->map_address = &no_mmu_map_address; |
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} |
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static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def) |
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{
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env->nb_tlb = 1; |
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env->map_address = &fixed_mmu_map_address; |
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} |
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static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def) |
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{
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env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
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env->map_address = &r4k_map_address; |
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env->do_tlbwi = r4k_do_tlbwi; |
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env->do_tlbwr = r4k_do_tlbwr; |
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env->do_tlbp = r4k_do_tlbp; |
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env->do_tlbr = r4k_do_tlbr; |
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} |
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#endif /* CONFIG_USER_ONLY */ |
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int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) |
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{
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if (!def) |
| ... | ... | |
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env->CCRes = def->CCRes; |
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env->Status_rw_bitmask = def->Status_rw_bitmask; |
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env->fcr0 = def->CP1_fcr0; |
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#if defined (MIPS_USES_R4K_TLB) |
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env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
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#ifndef CONFIG_USER_ONLY |
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switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
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case 0: |
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no_mmu_init(env, def); |
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break; |
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case 1: |
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r4k_mmu_init(env, def); |
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break; |
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case 3: |
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fixed_mmu_init(env, def); |
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break; |
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default: |
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/* Older CPUs like the R3000 may need nonstandard handling here. */ |
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cpu_abort(env, "MMU type not supported\n"); |
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} |
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env->CP0_Random = env->nb_tlb - 1; |
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env->tlb_in_use = env->nb_tlb; |
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#endif |
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#endif /* CONFIG_USER_ONLY */
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return 0; |
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} |
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