Revision 29e179bc target-sh4/helper.c
| b/target-sh4/helper.c | ||
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| 282 | 282 |
return match; |
| 283 | 283 |
} |
| 284 | 284 |
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static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb, |
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const tlb_t * needle) |
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{
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int i; |
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for (i = 0; i < nbtlb; i++) |
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if (!memcmp(&haystack[i], needle, sizeof(tlb_t))) |
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return 1; |
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return 0; |
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} |
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static void increment_urc(CPUState * env) |
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{
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uint8_t urb, urc; |
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/* Increment URC */ |
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urb = ((env->mmucr) >> 18) & 0x3f; |
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urc = ((env->mmucr) >> 10) & 0x3f; |
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urc++; |
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if (urc == urb || urc == UTLB_SIZE - 1) |
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urc = 0; |
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
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} |
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/* Find itlb entry - update itlb from utlb if necessary and asked for |
| 286 | 309 |
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE |
| 287 | 310 |
Update the itlb from utlb if update is not 0 |
| ... | ... | |
| 313 | 336 |
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ |
| 314 | 337 |
int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
| 315 | 338 |
{
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uint8_t urb, urc; |
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/* Increment URC */ |
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urb = ((env->mmucr) >> 18) & 0x3f; |
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urc = ((env->mmucr) >> 10) & 0x3f; |
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urc++; |
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if (urc == urb || urc == UTLB_SIZE - 1) |
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urc = 0; |
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
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/* per utlb access */ |
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increment_urc(env); |
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/* Return entry */ |
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return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
| ... | ... | |
| 407 | 423 |
return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE : |
| 408 | 424 |
MMU_DTLB_MISS_READ; |
| 409 | 425 |
} |
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/* Mask upper 3 bits */ |
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*physical = address & 0x1FFFFFFF; |
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if (address >= 0x80000000 && address < 0xc0000000) {
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/* Mask upper 3 bits for P1 and P2 areas */ |
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*physical = address & 0x1fffffff; |
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} else if (address >= 0xfc000000) {
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/* |
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* Mask upper 3 bits for control registers in P4 area, |
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* to unify access to control registers via P0-P3 area. |
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* The addresses for cache store queue, TLB address array |
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* are not masked. |
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*/ |
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*physical = address & 0x1fffffff; |
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} else {
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/* access to cache store queue, or TLB address array. */ |
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*physical = address; |
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} |
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*prot = PAGE_READ | PAGE_WRITE; |
| 413 | 442 |
return MMU_OK; |
| 414 | 443 |
} |
| ... | ... | |
| 543 | 572 |
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
| 544 | 573 |
} |
| 545 | 574 |
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void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, |
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uint32_t mem_value) |
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{
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int associate = addr & 0x0000080; |
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uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
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uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); |
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uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
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uint8_t asid = (uint8_t)(mem_value & 0x000000ff); |
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if (associate) {
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int i; |
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tlb_t * utlb_match_entry = NULL; |
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int needs_tlb_flush = 0; |
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/* search UTLB */ |
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for (i = 0; i < UTLB_SIZE; i++) {
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tlb_t * entry = &s->utlb[i]; |
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if (!entry->v) |
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continue; |
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if (entry->vpn == vpn && entry->asid == asid) {
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if (utlb_match_entry) {
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/* Multiple TLB Exception */ |
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s->exception_index = 0x140; |
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s->tea = addr; |
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break; |
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} |
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if (entry->v && !v) |
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needs_tlb_flush = 1; |
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entry->v = v; |
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entry->d = d; |
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utlb_match_entry = entry; |
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} |
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increment_urc(s); /* per utlb access */ |
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} |
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|
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/* search ITLB */ |
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for (i = 0; i < ITLB_SIZE; i++) {
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tlb_t * entry = &s->itlb[i]; |
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if (entry->vpn == vpn && entry->asid == asid) {
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if (entry->v && !v) |
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needs_tlb_flush = 1; |
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if (utlb_match_entry) |
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*entry = *utlb_match_entry; |
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else |
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entry->v = v; |
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break; |
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} |
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} |
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if (needs_tlb_flush) |
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tlb_flush_page(s, vpn << 10); |
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} else {
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int index = (addr & 0x00003f00) >> 8; |
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tlb_t * entry = &s->utlb[index]; |
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if (entry->v) {
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/* Overwriting valid entry in utlb. */ |
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target_ulong address = entry->vpn << 10; |
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if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
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tlb_flush_page(s, address); |
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} |
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} |
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entry->asid = asid; |
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entry->vpn = vpn; |
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entry->d = d; |
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entry->v = v; |
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increment_urc(s); |
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} |
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} |
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#endif |
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