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/*
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 * QEMU System Emulator header
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef likely
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#if __GNUC__ < 3
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#define __builtin_expect(x, n) (x)
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#endif
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x)   __builtin_expect(!!(x), 0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef always_inline
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#if __GNUC__ < 3
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#define always_inline inline
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#else
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#define always_inline __attribute__ (( always_inline )) inline
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#endif
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int alt_grab;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int cursor_hide;
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extern int graphic_rotate;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern int old_param;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128
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extern const char *prom_envs[MAX_PROM_ENVS];
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extern unsigned int nb_prom_envs;
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd,
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                         IOCanRWHandler *fd_read_poll,
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                         IOHandler *fd_read,
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                         IOHandler *fd_write,
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read,
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s,
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                           IOCanRWHandler *fd_can_read,
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds, const char *p);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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struct ParallelIOArg {
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    void *buffer;
389 5867c88a ths
    int count;
390 5867c88a ths
};
391 5867c88a ths
392 7c9d8e07 bellard
/* VLANs support */
393 7c9d8e07 bellard
394 7c9d8e07 bellard
typedef struct VLANClientState VLANClientState;
395 7c9d8e07 bellard
396 7c9d8e07 bellard
struct VLANClientState {
397 7c9d8e07 bellard
    IOReadHandler *fd_read;
398 d861b05e pbrook
    /* Packets may still be sent if this returns zero.  It's used to
399 d861b05e pbrook
       rate-limit the slirp code.  */
400 d861b05e pbrook
    IOCanRWHandler *fd_can_read;
401 7c9d8e07 bellard
    void *opaque;
402 7c9d8e07 bellard
    struct VLANClientState *next;
403 7c9d8e07 bellard
    struct VLANState *vlan;
404 7c9d8e07 bellard
    char info_str[256];
405 7c9d8e07 bellard
};
406 7c9d8e07 bellard
407 7c9d8e07 bellard
typedef struct VLANState {
408 7c9d8e07 bellard
    int id;
409 7c9d8e07 bellard
    VLANClientState *first_client;
410 7c9d8e07 bellard
    struct VLANState *next;
411 833c7174 blueswir1
    unsigned int nb_guest_devs, nb_host_devs;
412 7c9d8e07 bellard
} VLANState;
413 7c9d8e07 bellard
414 7c9d8e07 bellard
VLANState *qemu_find_vlan(int id);
415 7c9d8e07 bellard
VLANClientState *qemu_new_vlan_client(VLANState *vlan,
416 d861b05e pbrook
                                      IOReadHandler *fd_read,
417 d861b05e pbrook
                                      IOCanRWHandler *fd_can_read,
418 d861b05e pbrook
                                      void *opaque);
419 d861b05e pbrook
int qemu_can_send_packet(VLANClientState *vc);
420 7c9d8e07 bellard
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
421 d861b05e pbrook
void qemu_handler_true(void *opaque);
422 7c9d8e07 bellard
423 7c9d8e07 bellard
void do_info_network(void);
424 7c9d8e07 bellard
425 7fb843f8 bellard
/* TAP win32 */
426 7fb843f8 bellard
int tap_win32_init(VLANState *vlan, const char *ifname);
427 7fb843f8 bellard
428 7c9d8e07 bellard
/* NIC info */
429 c4b1fcc0 bellard
430 c4b1fcc0 bellard
#define MAX_NICS 8
431 c4b1fcc0 bellard
432 7c9d8e07 bellard
typedef struct NICInfo {
433 c4b1fcc0 bellard
    uint8_t macaddr[6];
434 a41b2ff2 pbrook
    const char *model;
435 7c9d8e07 bellard
    VLANState *vlan;
436 7c9d8e07 bellard
} NICInfo;
437 c4b1fcc0 bellard
438 c4b1fcc0 bellard
extern int nb_nics;
439 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
440 8a7ddc38 bellard
441 8a7ddc38 bellard
/* timers */
442 8a7ddc38 bellard
443 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
444 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
445 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
446 8a7ddc38 bellard
447 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
448 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
449 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
450 8a7ddc38 bellard
   Hz. */
451 8a7ddc38 bellard
extern QEMUClock *rt_clock;
452 8a7ddc38 bellard
453 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
454 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
455 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
456 8a7ddc38 bellard
extern QEMUClock *vm_clock;
457 8a7ddc38 bellard
458 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
459 8a7ddc38 bellard
460 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
461 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
462 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
463 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
464 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
465 8a7ddc38 bellard
466 8a7ddc38 bellard
extern int64_t ticks_per_sec;
467 8a7ddc38 bellard
468 1dce7c3c bellard
int64_t cpu_get_ticks(void);
469 8a7ddc38 bellard
void cpu_enable_ticks(void);
470 8a7ddc38 bellard
void cpu_disable_ticks(void);
471 8a7ddc38 bellard
472 8a7ddc38 bellard
/* VM Load/Save */
473 8a7ddc38 bellard
474 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
475 8a7ddc38 bellard
476 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
477 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
478 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
479 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
480 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
481 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
482 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
483 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
484 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
485 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
486 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
487 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
488 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
489 8a7ddc38 bellard
490 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
491 8a7ddc38 bellard
{
492 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
493 8a7ddc38 bellard
}
494 8a7ddc38 bellard
495 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
496 8a7ddc38 bellard
{
497 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
498 8a7ddc38 bellard
}
499 8a7ddc38 bellard
500 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
501 8a7ddc38 bellard
{
502 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
503 8a7ddc38 bellard
}
504 8a7ddc38 bellard
505 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
506 8a7ddc38 bellard
{
507 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
508 8a7ddc38 bellard
}
509 8a7ddc38 bellard
510 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
511 8a7ddc38 bellard
{
512 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
513 8a7ddc38 bellard
}
514 8a7ddc38 bellard
515 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
516 8a7ddc38 bellard
{
517 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
518 8a7ddc38 bellard
}
519 8a7ddc38 bellard
520 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
521 8a7ddc38 bellard
{
522 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
523 8a7ddc38 bellard
}
524 8a7ddc38 bellard
525 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
526 8a7ddc38 bellard
{
527 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
528 8a7ddc38 bellard
}
529 8a7ddc38 bellard
530 c27004ec bellard
#if TARGET_LONG_BITS == 64
531 c27004ec bellard
#define qemu_put_betl qemu_put_be64
532 c27004ec bellard
#define qemu_get_betl qemu_get_be64
533 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
534 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
535 c27004ec bellard
#else
536 c27004ec bellard
#define qemu_put_betl qemu_put_be32
537 c27004ec bellard
#define qemu_get_betl qemu_get_be32
538 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
539 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
540 c27004ec bellard
#endif
541 c27004ec bellard
542 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
543 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
544 8a7ddc38 bellard
545 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
546 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
547 8a7ddc38 bellard
548 5fafdf24 ths
int register_savevm(const char *idstr,
549 5fafdf24 ths
                    int instance_id,
550 8a7ddc38 bellard
                    int version_id,
551 8a7ddc38 bellard
                    SaveStateHandler *save_state,
552 8a7ddc38 bellard
                    LoadStateHandler *load_state,
553 8a7ddc38 bellard
                    void *opaque);
554 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
555 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
556 c4b1fcc0 bellard
557 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
558 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
559 6a00d601 bellard
560 faea38e7 bellard
void do_savevm(const char *name);
561 faea38e7 bellard
void do_loadvm(const char *name);
562 faea38e7 bellard
void do_delvm(const char *name);
563 faea38e7 bellard
void do_info_snapshots(void);
564 faea38e7 bellard
565 83f64091 bellard
/* bottom halves */
566 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
567 83f64091 bellard
568 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
569 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
570 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
571 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
572 6eb5733a bellard
int qemu_bh_poll(void);
573 83f64091 bellard
574 fc01f7e7 bellard
/* block.c */
575 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
576 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
577 ea2384d3 bellard
578 ea2384d3 bellard
extern BlockDriver bdrv_raw;
579 19cb3738 bellard
extern BlockDriver bdrv_host_device;
580 ea2384d3 bellard
extern BlockDriver bdrv_cow;
581 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
582 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
583 3c56521b bellard
extern BlockDriver bdrv_cloop;
584 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
585 a8753c34 bellard
extern BlockDriver bdrv_bochs;
586 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
587 de167e41 bellard
extern BlockDriver bdrv_vvfat;
588 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
589 6ada7453 ths
extern BlockDriver bdrv_parallels;
590 faea38e7 bellard
591 faea38e7 bellard
typedef struct BlockDriverInfo {
592 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
593 5fafdf24 ths
    int cluster_size;
594 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
595 5fafdf24 ths
    int64_t vm_state_offset;
596 faea38e7 bellard
} BlockDriverInfo;
597 faea38e7 bellard
598 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
599 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
600 faea38e7 bellard
    /* the following fields are informative. They are not needed for
601 faea38e7 bellard
       the consistency of the snapshot */
602 faea38e7 bellard
    char name[256]; /* user choosen name */
603 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
604 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
605 faea38e7 bellard
    uint32_t date_nsec;
606 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
607 faea38e7 bellard
} QEMUSnapshotInfo;
608 ea2384d3 bellard
609 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
610 83f64091 bellard
#define BDRV_O_RDWR        0x0002
611 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
612 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
613 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
614 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
615 83f64091 bellard
                                     use a disk image format on top of
616 83f64091 bellard
                                     it (default for
617 83f64091 bellard
                                     bdrv_file_open()) */
618 83f64091 bellard
619 ea2384d3 bellard
void bdrv_init(void);
620 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
621 5fafdf24 ths
int bdrv_create(BlockDriver *drv,
622 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
623 ea2384d3 bellard
                const char *backing_file, int flags);
624 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
625 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
626 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
627 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
628 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
629 ea2384d3 bellard
               BlockDriver *drv);
630 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
631 5fafdf24 ths
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
632 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
633 5fafdf24 ths
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
634 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
635 5fafdf24 ths
int bdrv_pread(BlockDriverState *bs, int64_t offset,
636 83f64091 bellard
               void *buf, int count);
637 5fafdf24 ths
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
638 83f64091 bellard
                const void *buf, int count);
639 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
640 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
641 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
642 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
643 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
644 83f64091 bellard
/* async block I/O */
645 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
646 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
647 83f64091 bellard
648 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
649 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
650 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
651 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
652 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
653 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
654 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
655 83f64091 bellard
656 83f64091 bellard
void qemu_aio_init(void);
657 83f64091 bellard
void qemu_aio_poll(void);
658 6192bc37 pbrook
void qemu_aio_flush(void);
659 83f64091 bellard
void qemu_aio_wait_start(void);
660 83f64091 bellard
void qemu_aio_wait(void);
661 83f64091 bellard
void qemu_aio_wait_end(void);
662 83f64091 bellard
663 2bac6019 balrog
int qemu_key_check(BlockDriverState *bs, const char *name);
664 2bac6019 balrog
665 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
666 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
667 33e3963e bellard
668 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
669 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
670 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
671 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
672 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
673 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
674 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
675 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
676 c4b1fcc0 bellard
677 5fafdf24 ths
void bdrv_set_geometry_hint(BlockDriverState *bs,
678 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
679 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
680 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
681 5fafdf24 ths
void bdrv_get_geometry_hint(BlockDriverState *bs,
682 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
683 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
684 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
685 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
686 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
687 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
688 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
689 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
690 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
691 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
692 5fafdf24 ths
void bdrv_set_change_cb(BlockDriverState *bs,
693 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
694 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
695 c4b1fcc0 bellard
void bdrv_info(void);
696 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
697 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
698 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
699 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
700 5fafdf24 ths
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
701 ea2384d3 bellard
                         void *opaque);
702 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
703 5fafdf24 ths
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
704 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
705 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
706 c4b1fcc0 bellard
707 5fafdf24 ths
void bdrv_get_backing_filename(BlockDriverState *bs,
708 83f64091 bellard
                               char *filename, int filename_size);
709 5fafdf24 ths
int bdrv_snapshot_create(BlockDriverState *bs,
710 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
711 5fafdf24 ths
int bdrv_snapshot_goto(BlockDriverState *bs,
712 faea38e7 bellard
                       const char *snapshot_id);
713 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
714 5fafdf24 ths
int bdrv_snapshot_list(BlockDriverState *bs,
715 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
716 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
717 faea38e7 bellard
718 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
719 83f64091 bellard
int path_is_absolute(const char *path);
720 83f64091 bellard
void path_combine(char *dest, int dest_size,
721 83f64091 bellard
                  const char *base_path,
722 83f64091 bellard
                  const char *filename);
723 ea2384d3 bellard
724 ea2384d3 bellard
#ifndef QEMU_TOOL
725 54fa5af5 bellard
726 5fafdf24 ths
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
727 54fa5af5 bellard
                                 int boot_device,
728 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
729 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
730 94fc95cd j_mayer
             const char *initrd_filename, const char *cpu_model);
731 54fa5af5 bellard
732 54fa5af5 bellard
typedef struct QEMUMachine {
733 54fa5af5 bellard
    const char *name;
734 54fa5af5 bellard
    const char *desc;
735 54fa5af5 bellard
    QEMUMachineInitFunc *init;
736 54fa5af5 bellard
    struct QEMUMachine *next;
737 54fa5af5 bellard
} QEMUMachine;
738 54fa5af5 bellard
739 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
740 54fa5af5 bellard
741 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
742 54fa5af5 bellard
743 94fc95cd j_mayer
#if defined(TARGET_PPC)
744 94fc95cd j_mayer
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
745 94fc95cd j_mayer
#endif
746 94fc95cd j_mayer
747 33d68b5f ths
#if defined(TARGET_MIPS)
748 33d68b5f ths
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
749 33d68b5f ths
#endif
750 33d68b5f ths
751 d537cf6c pbrook
#include "hw/irq.h"
752 d537cf6c pbrook
753 26aa7d72 bellard
/* ISA bus */
754 26aa7d72 bellard
755 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
756 26aa7d72 bellard
757 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
758 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
759 26aa7d72 bellard
760 5fafdf24 ths
int register_ioport_read(int start, int length, int size,
761 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
762 5fafdf24 ths
int register_ioport_write(int start, int length, int size,
763 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
764 69b91039 bellard
void isa_unassign_ioport(int start, int length);
765 69b91039 bellard
766 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
767 aef445bd pbrook
768 69b91039 bellard
/* PCI bus */
769 69b91039 bellard
770 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
771 69b91039 bellard
772 46e50e9d bellard
typedef struct PCIBus PCIBus;
773 69b91039 bellard
typedef struct PCIDevice PCIDevice;
774 69b91039 bellard
775 5fafdf24 ths
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
776 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
777 5fafdf24 ths
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
778 69b91039 bellard
                                   uint32_t address, int len);
779 5fafdf24 ths
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
780 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
781 69b91039 bellard
782 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
783 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
784 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
785 69b91039 bellard
786 69b91039 bellard
typedef struct PCIIORegion {
787 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
788 69b91039 bellard
    uint32_t size;
789 69b91039 bellard
    uint8_t type;
790 69b91039 bellard
    PCIMapIORegionFunc *map_func;
791 69b91039 bellard
} PCIIORegion;
792 69b91039 bellard
793 8a8696a3 bellard
#define PCI_ROM_SLOT 6
794 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
795 502a5395 pbrook
796 502a5395 pbrook
#define PCI_DEVICES_MAX 64
797 502a5395 pbrook
798 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
799 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
800 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
801 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
802 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
803 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
804 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
805 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
806 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
807 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
808 502a5395 pbrook
809 69b91039 bellard
struct PCIDevice {
810 69b91039 bellard
    /* PCI config space */
811 69b91039 bellard
    uint8_t config[256];
812 69b91039 bellard
813 69b91039 bellard
    /* the following fields are read only */
814 46e50e9d bellard
    PCIBus *bus;
815 69b91039 bellard
    int devfn;
816 69b91039 bellard
    char name[64];
817 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
818 3b46e624 ths
819 69b91039 bellard
    /* do not access the following fields */
820 69b91039 bellard
    PCIConfigReadFunc *config_read;
821 69b91039 bellard
    PCIConfigWriteFunc *config_write;
822 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
823 5768f5ac bellard
    int irq_index;
824 d2b59317 pbrook
825 d537cf6c pbrook
    /* IRQ objects for the INTA-INTD pins.  */
826 d537cf6c pbrook
    qemu_irq *irq;
827 d537cf6c pbrook
828 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
829 d2b59317 pbrook
    int irq_state[4];
830 69b91039 bellard
};
831 69b91039 bellard
832 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
833 46e50e9d bellard
                               int instance_size, int devfn,
834 5fafdf24 ths
                               PCIConfigReadFunc *config_read,
835 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
836 69b91039 bellard
837 5fafdf24 ths
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
838 5fafdf24 ths
                            uint32_t size, int type,
839 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
840 69b91039 bellard
841 5fafdf24 ths
uint32_t pci_default_read_config(PCIDevice *d,
842 5768f5ac bellard
                                 uint32_t address, int len);
843 5fafdf24 ths
void pci_default_write_config(PCIDevice *d,
844 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
845 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
846 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
847 5768f5ac bellard
848 d537cf6c pbrook
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
849 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
850 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
851 d537cf6c pbrook
                         qemu_irq *pic, int devfn_min, int nirq);
852 502a5395 pbrook
853 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
854 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
855 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
856 502a5395 pbrook
int pci_bus_num(PCIBus *s);
857 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
858 9995c51f bellard
859 5768f5ac bellard
void pci_info(void);
860 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
861 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
862 26aa7d72 bellard
863 502a5395 pbrook
/* prep_pci.c */
864 d537cf6c pbrook
PCIBus *pci_prep_init(qemu_irq *pic);
865 77d4bc34 bellard
866 502a5395 pbrook
/* grackle_pci.c */
867 d537cf6c pbrook
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
868 502a5395 pbrook
869 502a5395 pbrook
/* unin_pci.c */
870 d537cf6c pbrook
PCIBus *pci_pmac_init(qemu_irq *pic);
871 502a5395 pbrook
872 502a5395 pbrook
/* apb_pci.c */
873 5b9693dc blueswir1
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
874 d537cf6c pbrook
                     qemu_irq *pic);
875 502a5395 pbrook
876 d537cf6c pbrook
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
877 502a5395 pbrook
878 502a5395 pbrook
/* piix_pci.c */
879 d537cf6c pbrook
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
880 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
881 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
882 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
883 a41b2ff2 pbrook
884 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
885 5856de80 ths
886 28b9b5af bellard
/* openpic.c */
887 e9df014c j_mayer
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
888 47103572 j_mayer
enum {
889 e9df014c j_mayer
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
890 e9df014c j_mayer
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
891 e9df014c j_mayer
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
892 e9df014c j_mayer
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
893 e9df014c j_mayer
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
894 e9df014c j_mayer
    OPENPIC_OUTPUT_NB,
895 47103572 j_mayer
};
896 e9df014c j_mayer
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
897 e9df014c j_mayer
                        qemu_irq **irqs, qemu_irq irq_out);
898 28b9b5af bellard
899 54fa5af5 bellard
/* heathrow_pic.c */
900 d537cf6c pbrook
qemu_irq *heathrow_pic_init(int *pmem_index);
901 54fa5af5 bellard
902 fde7d5bd ths
/* gt64xxx.c */
903 d537cf6c pbrook
PCIBus *pci_gt64120_init(qemu_irq *pic);
904 fde7d5bd ths
905 6a36d84e bellard
#ifdef HAS_AUDIO
906 6a36d84e bellard
struct soundhw {
907 6a36d84e bellard
    const char *name;
908 6a36d84e bellard
    const char *descr;
909 6a36d84e bellard
    int enabled;
910 6a36d84e bellard
    int isa;
911 6a36d84e bellard
    union {
912 d537cf6c pbrook
        int (*init_isa) (AudioState *s, qemu_irq *pic);
913 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
914 6a36d84e bellard
    } init;
915 6a36d84e bellard
};
916 6a36d84e bellard
917 6a36d84e bellard
extern struct soundhw soundhw[];
918 6a36d84e bellard
#endif
919 6a36d84e bellard
920 313aa567 bellard
/* vga.c */
921 313aa567 bellard
922 eee0b836 blueswir1
#ifndef TARGET_SPARC
923 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
924 eee0b836 blueswir1
#else
925 eee0b836 blueswir1
#define VGA_RAM_SIZE (9 * 1024 * 1024)
926 eee0b836 blueswir1
#endif
927 313aa567 bellard
928 82c643ff bellard
struct DisplayState {
929 313aa567 bellard
    uint8_t *data;
930 313aa567 bellard
    int linesize;
931 313aa567 bellard
    int depth;
932 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
933 82c643ff bellard
    int width;
934 82c643ff bellard
    int height;
935 24236869 bellard
    void *opaque;
936 740733bb ths
    QEMUTimer *gui_timer;
937 24236869 bellard
938 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
939 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
940 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
941 d34cab9f ths
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
942 d34cab9f ths
                     int dst_x, int dst_y, int w, int h);
943 d34cab9f ths
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
944 d34cab9f ths
                     int w, int h, uint32_t c);
945 d34cab9f ths
    void (*mouse_set)(int x, int y, int on);
946 d34cab9f ths
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
947 d34cab9f ths
                          uint8_t *image, uint8_t *mask);
948 82c643ff bellard
};
949 313aa567 bellard
950 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
951 313aa567 bellard
{
952 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
953 313aa567 bellard
}
954 313aa567 bellard
955 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
956 313aa567 bellard
{
957 313aa567 bellard
    s->dpy_resize(s, w, h);
958 313aa567 bellard
}
959 313aa567 bellard
960 5fafdf24 ths
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
961 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
962 5fafdf24 ths
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
963 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
964 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
965 2abec30b ths
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
966 2abec30b ths
                    unsigned long vga_ram_offset, int vga_ram_size,
967 2abec30b ths
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
968 2abec30b ths
                    int it_shift);
969 313aa567 bellard
970 d6bfa22f bellard
/* cirrus_vga.c */
971 5fafdf24 ths
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
972 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
973 5fafdf24 ths
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
974 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
975 d6bfa22f bellard
976 d34cab9f ths
/* vmware_vga.c */
977 d34cab9f ths
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
978 d34cab9f ths
                     unsigned long vga_ram_offset, int vga_ram_size);
979 d34cab9f ths
980 313aa567 bellard
/* sdl.c */
981 43523e93 ths
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
982 313aa567 bellard
983 da4dbf74 bellard
/* cocoa.m */
984 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
985 da4dbf74 bellard
986 24236869 bellard
/* vnc.c */
987 71cab5ca ths
void vnc_display_init(DisplayState *ds);
988 71cab5ca ths
void vnc_display_close(DisplayState *ds);
989 71cab5ca ths
int vnc_display_open(DisplayState *ds, const char *display);
990 70848515 ths
int vnc_display_password(DisplayState *ds, const char *password);
991 a9ce8590 bellard
void do_info_vnc(void);
992 24236869 bellard
993 6070dd07 ths
/* x_keymap.c */
994 6070dd07 ths
extern uint8_t _translate_keycode(const int key);
995 6070dd07 ths
996 5391d806 bellard
/* ide.c */
997 5391d806 bellard
#define MAX_DISKS 4
998 5391d806 bellard
999 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
1000 a1bb27b1 pbrook
extern BlockDriverState *sd_bdrv;
1001 3e3d5815 balrog
extern BlockDriverState *mtd_bdrv;
1002 5391d806 bellard
1003 d537cf6c pbrook
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1004 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
1005 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1006 54fa5af5 bellard
                         int secondary_ide_enabled);
1007 d537cf6c pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1008 d537cf6c pbrook
                        qemu_irq *pic);
1009 afcc3cdf ths
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1010 afcc3cdf ths
                        qemu_irq *pic);
1011 d537cf6c pbrook
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1012 5391d806 bellard
1013 2e5d83bb pbrook
/* cdrom.c */
1014 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1015 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1016 2e5d83bb pbrook
1017 9542611a ths
/* ds1225y.c */
1018 9542611a ths
typedef struct ds1225y_t ds1225y_t;
1019 71db710f blueswir1
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1020 9542611a ths
1021 1d14ffa9 bellard
/* es1370.c */
1022 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
1023 1d14ffa9 bellard
1024 fb065187 bellard
/* sb16.c */
1025 d537cf6c pbrook
int SB16_init (AudioState *s, qemu_irq *pic);
1026 fb065187 bellard
1027 fb065187 bellard
/* adlib.c */
1028 d537cf6c pbrook
int Adlib_init (AudioState *s, qemu_irq *pic);
1029 fb065187 bellard
1030 fb065187 bellard
/* gus.c */
1031 d537cf6c pbrook
int GUS_init (AudioState *s, qemu_irq *pic);
1032 27503323 bellard
1033 27503323 bellard
/* dma.c */
1034 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1035 27503323 bellard
int DMA_get_channel_mode (int nchan);
1036 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1037 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1038 27503323 bellard
void DMA_hold_DREQ (int nchan);
1039 27503323 bellard
void DMA_release_DREQ (int nchan);
1040 16f62432 bellard
void DMA_schedule(int nchan);
1041 27503323 bellard
void DMA_run (void);
1042 28b9b5af bellard
void DMA_init (int high_page_enable);
1043 27503323 bellard
void DMA_register_channel (int nchan,
1044 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
1045 85571bc7 bellard
                           void *opaque);
1046 7138fcfb bellard
/* fdc.c */
1047 7138fcfb bellard
#define MAX_FD 2
1048 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
1049 7138fcfb bellard
1050 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
1051 baca51fa bellard
1052 5fafdf24 ths
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1053 5dcb6b91 blueswir1
                       target_phys_addr_t io_base,
1054 baca51fa bellard
                       BlockDriverState **fds);
1055 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1056 7138fcfb bellard
1057 663e8e51 ths
/* eepro100.c */
1058 663e8e51 ths
1059 663e8e51 ths
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1060 663e8e51 ths
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1061 663e8e51 ths
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1062 663e8e51 ths
1063 80cabfad bellard
/* ne2000.c */
1064 80cabfad bellard
1065 d537cf6c pbrook
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1066 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1067 80cabfad bellard
1068 a41b2ff2 pbrook
/* rtl8139.c */
1069 a41b2ff2 pbrook
1070 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1071 a41b2ff2 pbrook
1072 e3c2613f bellard
/* pcnet.c */
1073 e3c2613f bellard
1074 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1075 70c0de96 blueswir1
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1076 2d069bab blueswir1
                qemu_irq irq, qemu_irq *reset);
1077 67e999be bellard
1078 548df2ac ths
/* vmmouse.c */
1079 548df2ac ths
void *vmmouse_init(void *m);
1080 e3c2613f bellard
1081 591a6d62 ths
/* vmport.c */
1082 591a6d62 ths
#ifdef TARGET_I386
1083 591a6d62 ths
void vmport_init(CPUState *env);
1084 591a6d62 ths
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1085 591a6d62 ths
#endif
1086 591a6d62 ths
1087 80cabfad bellard
/* pckbd.c */
1088 80cabfad bellard
1089 b92bb99b ths
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1090 71db710f blueswir1
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1091 71db710f blueswir1
                   target_phys_addr_t base, int it_shift);
1092 80cabfad bellard
1093 80cabfad bellard
/* mc146818rtc.c */
1094 80cabfad bellard
1095 8a7ddc38 bellard
typedef struct RTCState RTCState;
1096 80cabfad bellard
1097 d537cf6c pbrook
RTCState *rtc_init(int base, qemu_irq irq);
1098 18c6e2ff ths
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1099 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
1100 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
1101 80cabfad bellard
1102 80cabfad bellard
/* serial.c */
1103 80cabfad bellard
1104 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1105 d537cf6c pbrook
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1106 71db710f blueswir1
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1107 d537cf6c pbrook
                             qemu_irq irq, CharDriverState *chr,
1108 a4bc3afc ths
                             int ioregister);
1109 a4bc3afc ths
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1110 a4bc3afc ths
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1111 a4bc3afc ths
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1112 a4bc3afc ths
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1113 a4bc3afc ths
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1114 a4bc3afc ths
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1115 80cabfad bellard
1116 6508fe59 bellard
/* parallel.c */
1117 6508fe59 bellard
1118 6508fe59 bellard
typedef struct ParallelState ParallelState;
1119 d537cf6c pbrook
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1120 d60532ca ths
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1121 6508fe59 bellard
1122 80cabfad bellard
/* i8259.c */
1123 80cabfad bellard
1124 3de388f6 bellard
typedef struct PicState2 PicState2;
1125 3de388f6 bellard
extern PicState2 *isa_pic;
1126 80cabfad bellard
void pic_set_irq(int irq, int level);
1127 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1128 d537cf6c pbrook
qemu_irq *i8259_init(qemu_irq parent_irq);
1129 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1130 d592d303 bellard
                          void *alt_irq_opaque);
1131 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1132 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1133 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1134 c20709aa bellard
void pic_info(void);
1135 4a0fb71e bellard
void irq_info(void);
1136 80cabfad bellard
1137 c27004ec bellard
/* APIC */
1138 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1139 d592d303 bellard
1140 c27004ec bellard
int apic_init(CPUState *env);
1141 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1142 d592d303 bellard
IOAPICState *ioapic_init(void);
1143 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1144 c27004ec bellard
1145 80cabfad bellard
/* i8254.c */
1146 80cabfad bellard
1147 80cabfad bellard
#define PIT_FREQ 1193182
1148 80cabfad bellard
1149 ec844b96 bellard
typedef struct PITState PITState;
1150 ec844b96 bellard
1151 d537cf6c pbrook
PITState *pit_init(int base, qemu_irq irq);
1152 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1153 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1154 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1155 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1156 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1157 80cabfad bellard
1158 31211df1 ths
/* jazz_led.c */
1159 31211df1 ths
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1160 31211df1 ths
1161 fd06c375 bellard
/* pcspk.c */
1162 fd06c375 bellard
void pcspk_init(PITState *);
1163 d537cf6c pbrook
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1164 fd06c375 bellard
1165 0ff596d0 pbrook
#include "hw/i2c.h"
1166 0ff596d0 pbrook
1167 3fffc223 ths
#include "hw/smbus.h"
1168 3fffc223 ths
1169 6515b203 bellard
/* acpi.c */
1170 6515b203 bellard
extern int acpi_enabled;
1171 7b717336 ths
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1172 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1173 6515b203 bellard
void acpi_bios_init(void);
1174 6515b203 bellard
1175 80cabfad bellard
/* pc.c */
1176 54fa5af5 bellard
extern QEMUMachine pc_machine;
1177 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1178 52ca8d6a bellard
extern int fd_bootchk;
1179 80cabfad bellard
1180 6a00d601 bellard
void ioport_set_a20(int enable);
1181 6a00d601 bellard
int ioport_get_a20(void);
1182 6a00d601 bellard
1183 26aa7d72 bellard
/* ppc.c */
1184 54fa5af5 bellard
extern QEMUMachine prep_machine;
1185 54fa5af5 bellard
extern QEMUMachine core99_machine;
1186 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1187 1a6c0886 j_mayer
extern QEMUMachine ref405ep_machine;
1188 1a6c0886 j_mayer
extern QEMUMachine taihu_machine;
1189 54fa5af5 bellard
1190 6af0bf9c bellard
/* mips_r4k.c */
1191 6af0bf9c bellard
extern QEMUMachine mips_machine;
1192 6af0bf9c bellard
1193 5856de80 ths
/* mips_malta.c */
1194 5856de80 ths
extern QEMUMachine mips_malta_machine;
1195 5856de80 ths
1196 ad6fe1d2 ths
/* mips_int.c */
1197 d537cf6c pbrook
extern void cpu_mips_irq_init_cpu(CPUState *env);
1198 4de9b249 ths
1199 ad6fe1d2 ths
/* mips_pica61.c */
1200 ad6fe1d2 ths
extern QEMUMachine mips_pica61_machine;
1201 ad6fe1d2 ths
1202 e16fe40c ths
/* mips_timer.c */
1203 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1204 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1205 e16fe40c ths
1206 27c7ca7e bellard
/* shix.c */
1207 27c7ca7e bellard
extern QEMUMachine shix_machine;
1208 27c7ca7e bellard
1209 8cc43fef bellard
#ifdef TARGET_PPC
1210 47103572 j_mayer
/* PowerPC hardware exceptions management helpers */
1211 8ecc7913 j_mayer
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1212 8ecc7913 j_mayer
typedef struct clk_setup_t clk_setup_t;
1213 8ecc7913 j_mayer
struct clk_setup_t {
1214 8ecc7913 j_mayer
    clk_setup_cb cb;
1215 8ecc7913 j_mayer
    void *opaque;
1216 8ecc7913 j_mayer
};
1217 8ecc7913 j_mayer
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1218 8ecc7913 j_mayer
{
1219 8ecc7913 j_mayer
    if (clk->cb != NULL)
1220 8ecc7913 j_mayer
        (*clk->cb)(clk->opaque, freq);
1221 8ecc7913 j_mayer
}
1222 8ecc7913 j_mayer
1223 8ecc7913 j_mayer
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1224 2e719ba3 j_mayer
/* Embedded PowerPC DCR management */
1225 2e719ba3 j_mayer
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1226 2e719ba3 j_mayer
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1227 2e719ba3 j_mayer
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1228 2e719ba3 j_mayer
                  int (*dcr_write_error)(int dcrn));
1229 2e719ba3 j_mayer
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1230 2e719ba3 j_mayer
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1231 8ecc7913 j_mayer
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1232 4a057712 j_mayer
/* Embedded PowerPC reset */
1233 4a057712 j_mayer
void ppc40x_core_reset (CPUState *env);
1234 4a057712 j_mayer
void ppc40x_chip_reset (CPUState *env);
1235 4a057712 j_mayer
void ppc40x_system_reset (CPUState *env);
1236 8cc43fef bellard
#endif
1237 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1238 77d4bc34 bellard
1239 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1240 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1241 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1242 26aa7d72 bellard
1243 e95c8d51 bellard
/* sun4m.c */
1244 e0353fe2 blueswir1
extern QEMUMachine ss5_machine, ss10_machine;
1245 e95c8d51 bellard
1246 e95c8d51 bellard
/* iommu.c */
1247 5dcb6b91 blueswir1
void *iommu_init(target_phys_addr_t addr);
1248 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1249 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1250 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1251 67e999be bellard
                                           target_phys_addr_t addr,
1252 67e999be bellard
                                           uint8_t *buf, int len)
1253 67e999be bellard
{
1254 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1255 67e999be bellard
}
1256 e95c8d51 bellard
1257 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1258 67e999be bellard
                                            target_phys_addr_t addr,
1259 67e999be bellard
                                            uint8_t *buf, int len)
1260 67e999be bellard
{
1261 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1262 67e999be bellard
}
1263 e95c8d51 bellard
1264 e95c8d51 bellard
/* tcx.c */
1265 5dcb6b91 blueswir1
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1266 5dcb6b91 blueswir1
              unsigned long vram_offset, int vram_size, int width, int height,
1267 eee0b836 blueswir1
              int depth);
1268 e80cfcfc bellard
1269 e80cfcfc bellard
/* slavio_intctl.c */
1270 5dcb6b91 blueswir1
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1271 d537cf6c pbrook
                         const uint32_t *intbit_to_level,
1272 d7edfd27 blueswir1
                         qemu_irq **irq, qemu_irq **cpu_irq,
1273 b3a23197 blueswir1
                         qemu_irq **parent_irq, unsigned int cputimer);
1274 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1275 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1276 e95c8d51 bellard
1277 5fe141fd bellard
/* loader.c */
1278 5fe141fd bellard
int get_image_size(const char *filename);
1279 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1280 74287114 ths
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1281 74287114 ths
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1282 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1283 1c7b3754 pbrook
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1284 e80cfcfc bellard
1285 e80cfcfc bellard
/* slavio_timer.c */
1286 d7edfd27 blueswir1
void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1287 8d5f07fa bellard
1288 e80cfcfc bellard
/* slavio_serial.c */
1289 5dcb6b91 blueswir1
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1290 5dcb6b91 blueswir1
                                CharDriverState *chr1, CharDriverState *chr2);
1291 5dcb6b91 blueswir1
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1292 e95c8d51 bellard
1293 3475187d bellard
/* slavio_misc.c */
1294 5dcb6b91 blueswir1
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1295 5dcb6b91 blueswir1
                       qemu_irq irq);
1296 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1297 3475187d bellard
1298 6f7e9aec bellard
/* esp.c */
1299 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1300 5dcb6b91 blueswir1
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1301 2d069bab blueswir1
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1302 67e999be bellard
1303 67e999be bellard
/* sparc32_dma.c */
1304 70c0de96 blueswir1
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1305 2d069bab blueswir1
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1306 5fafdf24 ths
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1307 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1308 5fafdf24 ths
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1309 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1310 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1311 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1312 6f7e9aec bellard
1313 b8174937 bellard
/* cs4231.c */
1314 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1315 b8174937 bellard
1316 3475187d bellard
/* sun4u.c */
1317 3475187d bellard
extern QEMUMachine sun4u_machine;
1318 3475187d bellard
1319 64201201 bellard
/* NVRAM helpers */
1320 64201201 bellard
#include "hw/m48t59.h"
1321 64201201 bellard
1322 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1323 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1324 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1325 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1326 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1327 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1328 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1329 64201201 bellard
                       const unsigned char *str, uint32_t max);
1330 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1331 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1332 64201201 bellard
                    uint32_t start, uint32_t count);
1333 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1334 64201201 bellard
                          const unsigned char *arch,
1335 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1336 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1337 28b9b5af bellard
                          const char *cmdline,
1338 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1339 28b9b5af bellard
                          uint32_t NVRAM_image,
1340 28b9b5af bellard
                          int width, int height, int depth);
1341 64201201 bellard
1342 63066f4f bellard
/* adb.c */
1343 63066f4f bellard
1344 63066f4f bellard
#define MAX_ADB_DEVICES 16
1345 63066f4f bellard
1346 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1347 63066f4f bellard
1348 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1349 63066f4f bellard
1350 e2733d20 bellard
/* buf = NULL means polling */
1351 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1352 e2733d20 bellard
                              const uint8_t *buf, int len);
1353 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1354 12c28fed bellard
1355 63066f4f bellard
struct ADBDevice {
1356 63066f4f bellard
    struct ADBBusState *bus;
1357 63066f4f bellard
    int devaddr;
1358 63066f4f bellard
    int handler;
1359 e2733d20 bellard
    ADBDeviceRequest *devreq;
1360 12c28fed bellard
    ADBDeviceReset *devreset;
1361 63066f4f bellard
    void *opaque;
1362 63066f4f bellard
};
1363 63066f4f bellard
1364 63066f4f bellard
typedef struct ADBBusState {
1365 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1366 63066f4f bellard
    int nb_devices;
1367 e2733d20 bellard
    int poll_index;
1368 63066f4f bellard
} ADBBusState;
1369 63066f4f bellard
1370 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1371 e2733d20 bellard
                const uint8_t *buf, int len);
1372 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1373 63066f4f bellard
1374 5fafdf24 ths
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1375 5fafdf24 ths
                               ADBDeviceRequest *devreq,
1376 5fafdf24 ths
                               ADBDeviceReset *devreset,
1377 63066f4f bellard
                               void *opaque);
1378 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1379 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1380 63066f4f bellard
1381 63066f4f bellard
/* cuda.c */
1382 63066f4f bellard
1383 63066f4f bellard
extern ADBBusState adb_bus;
1384 d537cf6c pbrook
int cuda_init(qemu_irq irq);
1385 63066f4f bellard
1386 bb36d470 bellard
#include "hw/usb.h"
1387 bb36d470 bellard
1388 a594cfbf bellard
/* usb ports of the VM */
1389 a594cfbf bellard
1390 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1391 0d92ed30 pbrook
                            usb_attachfn attach);
1392 a594cfbf bellard
1393 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1394 a594cfbf bellard
1395 a594cfbf bellard
void do_usb_add(const char *devname);
1396 a594cfbf bellard
void do_usb_del(const char *devname);
1397 a594cfbf bellard
void usb_info(void);
1398 a594cfbf bellard
1399 2e5d83bb pbrook
/* scsi-disk.c */
1400 4d611c9a pbrook
enum scsi_reason {
1401 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1402 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1403 4d611c9a pbrook
};
1404 4d611c9a pbrook
1405 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1406 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1407 a917d384 pbrook
                                  uint32_t arg);
1408 2e5d83bb pbrook
1409 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1410 a917d384 pbrook
                           int tcq,
1411 2e5d83bb pbrook
                           scsi_completionfn completion,
1412 2e5d83bb pbrook
                           void *opaque);
1413 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1414 2e5d83bb pbrook
1415 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1416 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1417 4d611c9a pbrook
   layer the completion routine may be called directly by
1418 4d611c9a pbrook
   scsi_{read,write}_data.  */
1419 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1420 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1421 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1422 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1423 2e5d83bb pbrook
1424 7d8406be pbrook
/* lsi53c895a.c */
1425 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1426 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1427 7d8406be pbrook
1428 b5ff1b31 bellard
/* integratorcp.c */
1429 3371d272 pbrook
extern QEMUMachine integratorcp_machine;
1430 b5ff1b31 bellard
1431 cdbdb648 pbrook
/* versatilepb.c */
1432 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1433 16406950 pbrook
extern QEMUMachine versatileab_machine;
1434 cdbdb648 pbrook
1435 e69954b9 pbrook
/* realview.c */
1436 e69954b9 pbrook
extern QEMUMachine realview_machine;
1437 e69954b9 pbrook
1438 b00052e4 balrog
/* spitz.c */
1439 b00052e4 balrog
extern QEMUMachine akitapda_machine;
1440 b00052e4 balrog
extern QEMUMachine spitzpda_machine;
1441 b00052e4 balrog
extern QEMUMachine borzoipda_machine;
1442 b00052e4 balrog
extern QEMUMachine terrierpda_machine;
1443 b00052e4 balrog
1444 c3d2689d balrog
/* palm.c */
1445 c3d2689d balrog
extern QEMUMachine palmte_machine;
1446 c3d2689d balrog
1447 daa57963 bellard
/* ps2.c */
1448 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1449 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1450 daa57963 bellard
void ps2_write_mouse(void *, int val);
1451 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1452 daa57963 bellard
uint32_t ps2_read_data(void *);
1453 daa57963 bellard
void ps2_queue(void *, int b);
1454 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1455 548df2ac ths
void ps2_mouse_fake_event(void *opaque);
1456 daa57963 bellard
1457 80337b66 bellard
/* smc91c111.c */
1458 d537cf6c pbrook
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1459 80337b66 bellard
1460 7e1543c2 pbrook
/* pl031.c */
1461 7e1543c2 pbrook
void pl031_init(uint32_t base, qemu_irq irq);
1462 7e1543c2 pbrook
1463 bdd5003a pbrook
/* pl110.c */
1464 d537cf6c pbrook
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1465 bdd5003a pbrook
1466 cdbdb648 pbrook
/* pl011.c */
1467 d537cf6c pbrook
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1468 cdbdb648 pbrook
1469 cdbdb648 pbrook
/* pl050.c */
1470 d537cf6c pbrook
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1471 cdbdb648 pbrook
1472 cdbdb648 pbrook
/* pl080.c */
1473 d537cf6c pbrook
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1474 cdbdb648 pbrook
1475 a1bb27b1 pbrook
/* pl181.c */
1476 a1bb27b1 pbrook
void pl181_init(uint32_t base, BlockDriverState *bd,
1477 d537cf6c pbrook
                qemu_irq irq0, qemu_irq irq1);
1478 a1bb27b1 pbrook
1479 cdbdb648 pbrook
/* pl190.c */
1480 d537cf6c pbrook
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1481 cdbdb648 pbrook
1482 cdbdb648 pbrook
/* arm-timer.c */
1483 d537cf6c pbrook
void sp804_init(uint32_t base, qemu_irq irq);
1484 d537cf6c pbrook
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1485 cdbdb648 pbrook
1486 e69954b9 pbrook
/* arm_sysctl.c */
1487 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1488 e69954b9 pbrook
1489 e69954b9 pbrook
/* arm_gic.c */
1490 d537cf6c pbrook
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1491 e69954b9 pbrook
1492 16406950 pbrook
/* arm_boot.c */
1493 16406950 pbrook
1494 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1495 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1496 9d551997 balrog
                     int board_id, target_phys_addr_t loader_start);
1497 16406950 pbrook
1498 27c7ca7e bellard
/* sh7750.c */
1499 27c7ca7e bellard
struct SH7750State;
1500 27c7ca7e bellard
1501 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1502 27c7ca7e bellard
1503 27c7ca7e bellard
typedef struct {
1504 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1505 27c7ca7e bellard
    uint16_t portamask_trigger;
1506 27c7ca7e bellard
    uint16_t portbmask_trigger;
1507 27c7ca7e bellard
    /* Return 0 if no action was taken */
1508 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1509 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1510 27c7ca7e bellard
                           uint16_t * periph_portdira,
1511 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1512 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1513 27c7ca7e bellard
} sh7750_io_device;
1514 27c7ca7e bellard
1515 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1516 27c7ca7e bellard
                              sh7750_io_device * device);
1517 27c7ca7e bellard
/* tc58128.c */
1518 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1519 27c7ca7e bellard
1520 29133e9a bellard
/* NOR flash devices */
1521 86f55663 j_mayer
#define MAX_PFLASH 4
1522 86f55663 j_mayer
extern BlockDriverState *pflash_table[MAX_PFLASH];
1523 29133e9a bellard
typedef struct pflash_t pflash_t;
1524 29133e9a bellard
1525 71db710f blueswir1
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1526 29133e9a bellard
                           BlockDriverState *bs,
1527 71db710f blueswir1
                           uint32_t sector_len, int nb_blocs, int width,
1528 5fafdf24 ths
                           uint16_t id0, uint16_t id1,
1529 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1530 29133e9a bellard
1531 3e3d5815 balrog
/* nand.c */
1532 3e3d5815 balrog
struct nand_flash_s;
1533 3e3d5815 balrog
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1534 3e3d5815 balrog
void nand_done(struct nand_flash_s *s);
1535 5fafdf24 ths
void nand_setpins(struct nand_flash_s *s,
1536 3e3d5815 balrog
                int cle, int ale, int ce, int wp, int gnd);
1537 3e3d5815 balrog
void nand_getpins(struct nand_flash_s *s, int *rb);
1538 3e3d5815 balrog
void nand_setio(struct nand_flash_s *s, uint8_t value);
1539 3e3d5815 balrog
uint8_t nand_getio(struct nand_flash_s *s);
1540 3e3d5815 balrog
1541 3e3d5815 balrog
#define NAND_MFR_TOSHIBA        0x98
1542 3e3d5815 balrog
#define NAND_MFR_SAMSUNG        0xec
1543 3e3d5815 balrog
#define NAND_MFR_FUJITSU        0x04
1544 3e3d5815 balrog
#define NAND_MFR_NATIONAL        0x8f
1545 3e3d5815 balrog
#define NAND_MFR_RENESAS        0x07
1546 3e3d5815 balrog
#define NAND_MFR_STMICRO        0x20
1547 3e3d5815 balrog
#define NAND_MFR_HYNIX                0xad
1548 3e3d5815 balrog
#define NAND_MFR_MICRON                0x2c
1549 3e3d5815 balrog
1550 9ff6755b balrog
/* ecc.c */
1551 9ff6755b balrog
struct ecc_state_s {
1552 9ff6755b balrog
    uint8_t cp;                /* Column parity */
1553 9ff6755b balrog
    uint16_t lp[2];        /* Line parity */
1554 9ff6755b balrog
    uint16_t count;
1555 9ff6755b balrog
};
1556 9ff6755b balrog
1557 9ff6755b balrog
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1558 9ff6755b balrog
void ecc_reset(struct ecc_state_s *s);
1559 9ff6755b balrog
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1560 9ff6755b balrog
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1561 3e3d5815 balrog
1562 2a1d1880 balrog
/* GPIO */
1563 2a1d1880 balrog
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1564 2a1d1880 balrog
1565 fd5a3b33 balrog
/* ads7846.c */
1566 fd5a3b33 balrog
struct ads7846_state_s;
1567 fd5a3b33 balrog
uint32_t ads7846_read(void *opaque);
1568 fd5a3b33 balrog
void ads7846_write(void *opaque, uint32_t value);
1569 fd5a3b33 balrog
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1570 fd5a3b33 balrog
1571 c824cacd balrog
/* max111x.c */
1572 c824cacd balrog
struct max111x_s;
1573 c824cacd balrog
uint32_t max111x_read(void *opaque);
1574 c824cacd balrog
void max111x_write(void *opaque, uint32_t value);
1575 c824cacd balrog
struct max111x_s *max1110_init(qemu_irq cb);
1576 c824cacd balrog
struct max111x_s *max1111_init(qemu_irq cb);
1577 c824cacd balrog
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1578 c824cacd balrog
1579 201a51fc balrog
/* PCMCIA/Cardbus */
1580 201a51fc balrog
1581 201a51fc balrog
struct pcmcia_socket_s {
1582 201a51fc balrog
    qemu_irq irq;
1583 201a51fc balrog
    int attached;
1584 201a51fc balrog
    const char *slot_string;
1585 201a51fc balrog
    const char *card_string;
1586 201a51fc balrog
};
1587 201a51fc balrog
1588 201a51fc balrog
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1589 201a51fc balrog
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1590 201a51fc balrog
void pcmcia_info(void);
1591 201a51fc balrog
1592 201a51fc balrog
struct pcmcia_card_s {
1593 201a51fc balrog
    void *state;
1594 201a51fc balrog
    struct pcmcia_socket_s *slot;
1595 201a51fc balrog
    int (*attach)(void *state);
1596 201a51fc balrog
    int (*detach)(void *state);
1597 201a51fc balrog
    const uint8_t *cis;
1598 201a51fc balrog
    int cis_len;
1599 201a51fc balrog
1600 201a51fc balrog
    /* Only valid if attached */
1601 9e315fa9 balrog
    uint8_t (*attr_read)(void *state, uint32_t address);
1602 9e315fa9 balrog
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1603 9e315fa9 balrog
    uint16_t (*common_read)(void *state, uint32_t address);
1604 9e315fa9 balrog
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1605 9e315fa9 balrog
    uint16_t (*io_read)(void *state, uint32_t address);
1606 9e315fa9 balrog
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1607 201a51fc balrog
};
1608 201a51fc balrog
1609 201a51fc balrog
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1610 201a51fc balrog
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1611 201a51fc balrog
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1612 201a51fc balrog
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1613 201a51fc balrog
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1614 201a51fc balrog
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1615 201a51fc balrog
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1616 201a51fc balrog
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1617 201a51fc balrog
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1618 201a51fc balrog
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1619 201a51fc balrog
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1620 201a51fc balrog
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1621 201a51fc balrog
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1622 201a51fc balrog
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1623 201a51fc balrog
#define CISTPL_END                0xff        /* Tuple End */
1624 201a51fc balrog
#define CISTPL_ENDMARK                0xff
1625 201a51fc balrog
1626 201a51fc balrog
/* dscm1xxxx.c */
1627 201a51fc balrog
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1628 201a51fc balrog
1629 6963d7af pbrook
/* ptimer.c */
1630 6963d7af pbrook
typedef struct ptimer_state ptimer_state;
1631 6963d7af pbrook
typedef void (*ptimer_cb)(void *opaque);
1632 6963d7af pbrook
1633 6963d7af pbrook
ptimer_state *ptimer_init(QEMUBH *bh);
1634 6963d7af pbrook
void ptimer_set_period(ptimer_state *s, int64_t period);
1635 6963d7af pbrook
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1636 8d05ea8a blueswir1
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1637 8d05ea8a blueswir1
uint64_t ptimer_get_count(ptimer_state *s);
1638 8d05ea8a blueswir1
void ptimer_set_count(ptimer_state *s, uint64_t count);
1639 6963d7af pbrook
void ptimer_run(ptimer_state *s, int oneshot);
1640 6963d7af pbrook
void ptimer_stop(ptimer_state *s);
1641 8d05ea8a blueswir1
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1642 8d05ea8a blueswir1
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1643 6963d7af pbrook
1644 c1713132 balrog
#include "hw/pxa.h"
1645 c1713132 balrog
1646 c3d2689d balrog
#include "hw/omap.h"
1647 c3d2689d balrog
1648 20dcee94 pbrook
/* mcf_uart.c */
1649 20dcee94 pbrook
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1650 20dcee94 pbrook
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1651 20dcee94 pbrook
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1652 20dcee94 pbrook
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1653 20dcee94 pbrook
                      CharDriverState *chr);
1654 20dcee94 pbrook
1655 20dcee94 pbrook
/* mcf_intc.c */
1656 20dcee94 pbrook
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1657 20dcee94 pbrook
1658 7e049b8a pbrook
/* mcf_fec.c */
1659 7e049b8a pbrook
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1660 7e049b8a pbrook
1661 0633879f pbrook
/* mcf5206.c */
1662 0633879f pbrook
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1663 0633879f pbrook
1664 0633879f pbrook
/* an5206.c */
1665 0633879f pbrook
extern QEMUMachine an5206_machine;
1666 0633879f pbrook
1667 20dcee94 pbrook
/* mcf5208.c */
1668 20dcee94 pbrook
extern QEMUMachine mcf5208evb_machine;
1669 20dcee94 pbrook
1670 4046d913 pbrook
#include "gdbstub.h"
1671 4046d913 pbrook
1672 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1673 ea2384d3 bellard
1674 c4b1fcc0 bellard
/* monitor.c */
1675 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1676 ea2384d3 bellard
void term_puts(const char *str);
1677 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1678 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1679 fef30743 ths
void term_print_filename(const char *filename);
1680 c4b1fcc0 bellard
void term_flush(void);
1681 c4b1fcc0 bellard
void term_print_help(void);
1682 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1683 ea2384d3 bellard
                      char *buf, int buf_size);
1684 ea2384d3 bellard
1685 ea2384d3 bellard
/* readline.c */
1686 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1687 ea2384d3 bellard
1688 ea2384d3 bellard
extern int completion_index;
1689 ea2384d3 bellard
void add_completion(const char *str);
1690 ea2384d3 bellard
void readline_handle_byte(int ch);
1691 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1692 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1693 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1694 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1695 c4b1fcc0 bellard
1696 5e6ad6f9 bellard
void kqemu_record_dump(void);
1697 5e6ad6f9 bellard
1698 fc01f7e7 bellard
#endif /* VL_H */