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/*
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 * QEMU System Emulator header
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef likely
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#if __GNUC__ < 3
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#define __builtin_expect(x, n) (x)
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#endif
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x)   __builtin_expect(!!(x), 0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef always_inline
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#if __GNUC__ < 3
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#define always_inline inline
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#else
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#define always_inline __attribute__ (( always_inline )) inline
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#endif
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int alt_grab;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int cursor_hide;
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extern int graphic_rotate;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern int old_param;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128
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extern const char *prom_envs[MAX_PROM_ENVS];
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extern unsigned int nb_prom_envs;
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd,
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                         IOCanRWHandler *fd_read_poll,
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                         IOHandler *fd_read,
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                         IOHandler *fd_write,
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read,
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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283
int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
285

    
286
#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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303
#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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323
typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
326
    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
327
    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s,
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                           IOCanRWHandler *fd_can_read,
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
372
CharDriverState *text_console_init(DisplayState *ds, const char *p);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
382

    
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#define MAX_PARALLEL_PORTS 3
384

    
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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387
struct ParallelIOArg {
388
    void *buffer;
389
    int count;
390
};
391

    
392
/* VLANs support */
393

    
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typedef struct VLANClientState VLANClientState;
395

    
396
struct VLANClientState {
397
    IOReadHandler *fd_read;
398
    /* Packets may still be sent if this returns zero.  It's used to
399
       rate-limit the slirp code.  */
400
    IOCanRWHandler *fd_can_read;
401
    void *opaque;
402
    struct VLANClientState *next;
403
    struct VLANState *vlan;
404
    char info_str[256];
405
};
406

    
407
typedef struct VLANState {
408
    int id;
409
    VLANClientState *first_client;
410
    struct VLANState *next;
411
    unsigned int nb_guest_devs, nb_host_devs;
412
} VLANState;
413

    
414
VLANState *qemu_find_vlan(int id);
415
VLANClientState *qemu_new_vlan_client(VLANState *vlan,
416
                                      IOReadHandler *fd_read,
417
                                      IOCanRWHandler *fd_can_read,
418
                                      void *opaque);
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int qemu_can_send_packet(VLANClientState *vc);
420
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
421
void qemu_handler_true(void *opaque);
422

    
423
void do_info_network(void);
424

    
425
/* TAP win32 */
426
int tap_win32_init(VLANState *vlan, const char *ifname);
427

    
428
/* NIC info */
429

    
430
#define MAX_NICS 8
431

    
432
typedef struct NICInfo {
433
    uint8_t macaddr[6];
434
    const char *model;
435
    VLANState *vlan;
436
} NICInfo;
437

    
438
extern int nb_nics;
439
extern NICInfo nd_table[MAX_NICS];
440

    
441
/* timers */
442

    
443
typedef struct QEMUClock QEMUClock;
444
typedef struct QEMUTimer QEMUTimer;
445
typedef void QEMUTimerCB(void *opaque);
446

    
447
/* The real time clock should be used only for stuff which does not
448
   change the virtual machine state, as it is run even if the virtual
449
   machine is stopped. The real time clock has a frequency of 1000
450
   Hz. */
451
extern QEMUClock *rt_clock;
452

    
453
/* The virtual clock is only run during the emulation. It is stopped
454
   when the virtual machine is stopped. Virtual timers use a high
455
   precision clock, usually cpu cycles (use ticks_per_sec). */
456
extern QEMUClock *vm_clock;
457

    
458
int64_t qemu_get_clock(QEMUClock *clock);
459

    
460
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
461
void qemu_free_timer(QEMUTimer *ts);
462
void qemu_del_timer(QEMUTimer *ts);
463
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
464
int qemu_timer_pending(QEMUTimer *ts);
465

    
466
extern int64_t ticks_per_sec;
467

    
468
int64_t cpu_get_ticks(void);
469
void cpu_enable_ticks(void);
470
void cpu_disable_ticks(void);
471

    
472
/* VM Load/Save */
473

    
474
typedef struct QEMUFile QEMUFile;
475

    
476
QEMUFile *qemu_fopen(const char *filename, const char *mode);
477
void qemu_fflush(QEMUFile *f);
478
void qemu_fclose(QEMUFile *f);
479
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
480
void qemu_put_byte(QEMUFile *f, int v);
481
void qemu_put_be16(QEMUFile *f, unsigned int v);
482
void qemu_put_be32(QEMUFile *f, unsigned int v);
483
void qemu_put_be64(QEMUFile *f, uint64_t v);
484
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
485
int qemu_get_byte(QEMUFile *f);
486
unsigned int qemu_get_be16(QEMUFile *f);
487
unsigned int qemu_get_be32(QEMUFile *f);
488
uint64_t qemu_get_be64(QEMUFile *f);
489

    
490
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
491
{
492
    qemu_put_be64(f, *pv);
493
}
494

    
495
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
496
{
497
    qemu_put_be32(f, *pv);
498
}
499

    
500
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
501
{
502
    qemu_put_be16(f, *pv);
503
}
504

    
505
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
506
{
507
    qemu_put_byte(f, *pv);
508
}
509

    
510
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
511
{
512
    *pv = qemu_get_be64(f);
513
}
514

    
515
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
516
{
517
    *pv = qemu_get_be32(f);
518
}
519

    
520
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
521
{
522
    *pv = qemu_get_be16(f);
523
}
524

    
525
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
526
{
527
    *pv = qemu_get_byte(f);
528
}
529

    
530
#if TARGET_LONG_BITS == 64
531
#define qemu_put_betl qemu_put_be64
532
#define qemu_get_betl qemu_get_be64
533
#define qemu_put_betls qemu_put_be64s
534
#define qemu_get_betls qemu_get_be64s
535
#else
536
#define qemu_put_betl qemu_put_be32
537
#define qemu_get_betl qemu_get_be32
538
#define qemu_put_betls qemu_put_be32s
539
#define qemu_get_betls qemu_get_be32s
540
#endif
541

    
542
int64_t qemu_ftell(QEMUFile *f);
543
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
544

    
545
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
546
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
547

    
548
int register_savevm(const char *idstr,
549
                    int instance_id,
550
                    int version_id,
551
                    SaveStateHandler *save_state,
552
                    LoadStateHandler *load_state,
553
                    void *opaque);
554
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
555
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
556

    
557
void cpu_save(QEMUFile *f, void *opaque);
558
int cpu_load(QEMUFile *f, void *opaque, int version_id);
559

    
560
void do_savevm(const char *name);
561
void do_loadvm(const char *name);
562
void do_delvm(const char *name);
563
void do_info_snapshots(void);
564

    
565
/* bottom halves */
566
typedef void QEMUBHFunc(void *opaque);
567

    
568
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
569
void qemu_bh_schedule(QEMUBH *bh);
570
void qemu_bh_cancel(QEMUBH *bh);
571
void qemu_bh_delete(QEMUBH *bh);
572
int qemu_bh_poll(void);
573

    
574
/* block.c */
575
typedef struct BlockDriverState BlockDriverState;
576
typedef struct BlockDriver BlockDriver;
577

    
578
extern BlockDriver bdrv_raw;
579
extern BlockDriver bdrv_host_device;
580
extern BlockDriver bdrv_cow;
581
extern BlockDriver bdrv_qcow;
582
extern BlockDriver bdrv_vmdk;
583
extern BlockDriver bdrv_cloop;
584
extern BlockDriver bdrv_dmg;
585
extern BlockDriver bdrv_bochs;
586
extern BlockDriver bdrv_vpc;
587
extern BlockDriver bdrv_vvfat;
588
extern BlockDriver bdrv_qcow2;
589
extern BlockDriver bdrv_parallels;
590

    
591
typedef struct BlockDriverInfo {
592
    /* in bytes, 0 if irrelevant */
593
    int cluster_size;
594
    /* offset at which the VM state can be saved (0 if not possible) */
595
    int64_t vm_state_offset;
596
} BlockDriverInfo;
597

    
598
typedef struct QEMUSnapshotInfo {
599
    char id_str[128]; /* unique snapshot id */
600
    /* the following fields are informative. They are not needed for
601
       the consistency of the snapshot */
602
    char name[256]; /* user choosen name */
603
    uint32_t vm_state_size; /* VM state info size */
604
    uint32_t date_sec; /* UTC date of the snapshot */
605
    uint32_t date_nsec;
606
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
607
} QEMUSnapshotInfo;
608

    
609
#define BDRV_O_RDONLY      0x0000
610
#define BDRV_O_RDWR        0x0002
611
#define BDRV_O_ACCESS      0x0003
612
#define BDRV_O_CREAT       0x0004 /* create an empty file */
613
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
614
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
615
                                     use a disk image format on top of
616
                                     it (default for
617
                                     bdrv_file_open()) */
618

    
619
void bdrv_init(void);
620
BlockDriver *bdrv_find_format(const char *format_name);
621
int bdrv_create(BlockDriver *drv,
622
                const char *filename, int64_t size_in_sectors,
623
                const char *backing_file, int flags);
624
BlockDriverState *bdrv_new(const char *device_name);
625
void bdrv_delete(BlockDriverState *bs);
626
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
627
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
628
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
629
               BlockDriver *drv);
630
void bdrv_close(BlockDriverState *bs);
631
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
632
              uint8_t *buf, int nb_sectors);
633
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
634
               const uint8_t *buf, int nb_sectors);
635
int bdrv_pread(BlockDriverState *bs, int64_t offset,
636
               void *buf, int count);
637
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
638
                const void *buf, int count);
639
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
640
int64_t bdrv_getlength(BlockDriverState *bs);
641
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
642
int bdrv_commit(BlockDriverState *bs);
643
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
644
/* async block I/O */
645
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
646
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
647

    
648
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
649
                                uint8_t *buf, int nb_sectors,
650
                                BlockDriverCompletionFunc *cb, void *opaque);
651
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
652
                                 const uint8_t *buf, int nb_sectors,
653
                                 BlockDriverCompletionFunc *cb, void *opaque);
654
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
655

    
656
void qemu_aio_init(void);
657
void qemu_aio_poll(void);
658
void qemu_aio_flush(void);
659
void qemu_aio_wait_start(void);
660
void qemu_aio_wait(void);
661
void qemu_aio_wait_end(void);
662

    
663
int qemu_key_check(BlockDriverState *bs, const char *name);
664

    
665
/* Ensure contents are flushed to disk.  */
666
void bdrv_flush(BlockDriverState *bs);
667

    
668
#define BDRV_TYPE_HD     0
669
#define BDRV_TYPE_CDROM  1
670
#define BDRV_TYPE_FLOPPY 2
671
#define BIOS_ATA_TRANSLATION_AUTO   0
672
#define BIOS_ATA_TRANSLATION_NONE   1
673
#define BIOS_ATA_TRANSLATION_LBA    2
674
#define BIOS_ATA_TRANSLATION_LARGE  3
675
#define BIOS_ATA_TRANSLATION_RECHS  4
676

    
677
void bdrv_set_geometry_hint(BlockDriverState *bs,
678
                            int cyls, int heads, int secs);
679
void bdrv_set_type_hint(BlockDriverState *bs, int type);
680
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
681
void bdrv_get_geometry_hint(BlockDriverState *bs,
682
                            int *pcyls, int *pheads, int *psecs);
683
int bdrv_get_type_hint(BlockDriverState *bs);
684
int bdrv_get_translation_hint(BlockDriverState *bs);
685
int bdrv_is_removable(BlockDriverState *bs);
686
int bdrv_is_read_only(BlockDriverState *bs);
687
int bdrv_is_inserted(BlockDriverState *bs);
688
int bdrv_media_changed(BlockDriverState *bs);
689
int bdrv_is_locked(BlockDriverState *bs);
690
void bdrv_set_locked(BlockDriverState *bs, int locked);
691
void bdrv_eject(BlockDriverState *bs, int eject_flag);
692
void bdrv_set_change_cb(BlockDriverState *bs,
693
                        void (*change_cb)(void *opaque), void *opaque);
694
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
695
void bdrv_info(void);
696
BlockDriverState *bdrv_find(const char *name);
697
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
698
int bdrv_is_encrypted(BlockDriverState *bs);
699
int bdrv_set_key(BlockDriverState *bs, const char *key);
700
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
701
                         void *opaque);
702
const char *bdrv_get_device_name(BlockDriverState *bs);
703
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
704
                          const uint8_t *buf, int nb_sectors);
705
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
706

    
707
void bdrv_get_backing_filename(BlockDriverState *bs,
708
                               char *filename, int filename_size);
709
int bdrv_snapshot_create(BlockDriverState *bs,
710
                         QEMUSnapshotInfo *sn_info);
711
int bdrv_snapshot_goto(BlockDriverState *bs,
712
                       const char *snapshot_id);
713
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
714
int bdrv_snapshot_list(BlockDriverState *bs,
715
                       QEMUSnapshotInfo **psn_info);
716
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
717

    
718
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
719
int path_is_absolute(const char *path);
720
void path_combine(char *dest, int dest_size,
721
                  const char *base_path,
722
                  const char *filename);
723

    
724
#ifndef QEMU_TOOL
725

    
726
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
727
                                 int boot_device,
728
             DisplayState *ds, const char **fd_filename, int snapshot,
729
             const char *kernel_filename, const char *kernel_cmdline,
730
             const char *initrd_filename, const char *cpu_model);
731

    
732
typedef struct QEMUMachine {
733
    const char *name;
734
    const char *desc;
735
    QEMUMachineInitFunc *init;
736
    struct QEMUMachine *next;
737
} QEMUMachine;
738

    
739
int qemu_register_machine(QEMUMachine *m);
740

    
741
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
742

    
743
#if defined(TARGET_PPC)
744
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
745
#endif
746

    
747
#if defined(TARGET_MIPS)
748
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
749
#endif
750

    
751
#include "hw/irq.h"
752

    
753
/* ISA bus */
754

    
755
extern target_phys_addr_t isa_mem_base;
756

    
757
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
758
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
759

    
760
int register_ioport_read(int start, int length, int size,
761
                         IOPortReadFunc *func, void *opaque);
762
int register_ioport_write(int start, int length, int size,
763
                          IOPortWriteFunc *func, void *opaque);
764
void isa_unassign_ioport(int start, int length);
765

    
766
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
767

    
768
/* PCI bus */
769

    
770
extern target_phys_addr_t pci_mem_base;
771

    
772
typedef struct PCIBus PCIBus;
773
typedef struct PCIDevice PCIDevice;
774

    
775
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
776
                                uint32_t address, uint32_t data, int len);
777
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
778
                                   uint32_t address, int len);
779
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
780
                                uint32_t addr, uint32_t size, int type);
781

    
782
#define PCI_ADDRESS_SPACE_MEM                0x00
783
#define PCI_ADDRESS_SPACE_IO                0x01
784
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
785

    
786
typedef struct PCIIORegion {
787
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
788
    uint32_t size;
789
    uint8_t type;
790
    PCIMapIORegionFunc *map_func;
791
} PCIIORegion;
792

    
793
#define PCI_ROM_SLOT 6
794
#define PCI_NUM_REGIONS 7
795

    
796
#define PCI_DEVICES_MAX 64
797

    
798
#define PCI_VENDOR_ID                0x00        /* 16 bits */
799
#define PCI_DEVICE_ID                0x02        /* 16 bits */
800
#define PCI_COMMAND                0x04        /* 16 bits */
801
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
802
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
803
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
804
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
805
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
806
#define PCI_MIN_GNT                0x3e        /* 8 bits */
807
#define PCI_MAX_LAT                0x3f        /* 8 bits */
808

    
809
struct PCIDevice {
810
    /* PCI config space */
811
    uint8_t config[256];
812

    
813
    /* the following fields are read only */
814
    PCIBus *bus;
815
    int devfn;
816
    char name[64];
817
    PCIIORegion io_regions[PCI_NUM_REGIONS];
818

    
819
    /* do not access the following fields */
820
    PCIConfigReadFunc *config_read;
821
    PCIConfigWriteFunc *config_write;
822
    /* ??? This is a PC-specific hack, and should be removed.  */
823
    int irq_index;
824

    
825
    /* IRQ objects for the INTA-INTD pins.  */
826
    qemu_irq *irq;
827

    
828
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
829
    int irq_state[4];
830
};
831

    
832
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
833
                               int instance_size, int devfn,
834
                               PCIConfigReadFunc *config_read,
835
                               PCIConfigWriteFunc *config_write);
836

    
837
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
838
                            uint32_t size, int type,
839
                            PCIMapIORegionFunc *map_func);
840

    
841
uint32_t pci_default_read_config(PCIDevice *d,
842
                                 uint32_t address, int len);
843
void pci_default_write_config(PCIDevice *d,
844
                              uint32_t address, uint32_t val, int len);
845
void pci_device_save(PCIDevice *s, QEMUFile *f);
846
int pci_device_load(PCIDevice *s, QEMUFile *f);
847

    
848
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
849
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
850
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
851
                         qemu_irq *pic, int devfn_min, int nirq);
852

    
853
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
854
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
855
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
856
int pci_bus_num(PCIBus *s);
857
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
858

    
859
void pci_info(void);
860
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
861
                        pci_map_irq_fn map_irq, const char *name);
862

    
863
/* prep_pci.c */
864
PCIBus *pci_prep_init(qemu_irq *pic);
865

    
866
/* grackle_pci.c */
867
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
868

    
869
/* unin_pci.c */
870
PCIBus *pci_pmac_init(qemu_irq *pic);
871

    
872
/* apb_pci.c */
873
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
874
                     qemu_irq *pic);
875

    
876
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
877

    
878
/* piix_pci.c */
879
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
880
void i440fx_set_smm(PCIDevice *d, int val);
881
int piix3_init(PCIBus *bus, int devfn);
882
void i440fx_init_memory_mappings(PCIDevice *d);
883

    
884
int piix4_init(PCIBus *bus, int devfn);
885

    
886
/* openpic.c */
887
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
888
enum {
889
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
890
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
891
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
892
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
893
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
894
    OPENPIC_OUTPUT_NB,
895
};
896
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
897
                        qemu_irq **irqs, qemu_irq irq_out);
898

    
899
/* heathrow_pic.c */
900
qemu_irq *heathrow_pic_init(int *pmem_index);
901

    
902
/* gt64xxx.c */
903
PCIBus *pci_gt64120_init(qemu_irq *pic);
904

    
905
#ifdef HAS_AUDIO
906
struct soundhw {
907
    const char *name;
908
    const char *descr;
909
    int enabled;
910
    int isa;
911
    union {
912
        int (*init_isa) (AudioState *s, qemu_irq *pic);
913
        int (*init_pci) (PCIBus *bus, AudioState *s);
914
    } init;
915
};
916

    
917
extern struct soundhw soundhw[];
918
#endif
919

    
920
/* vga.c */
921

    
922
#ifndef TARGET_SPARC
923
#define VGA_RAM_SIZE (8192 * 1024)
924
#else
925
#define VGA_RAM_SIZE (9 * 1024 * 1024)
926
#endif
927

    
928
struct DisplayState {
929
    uint8_t *data;
930
    int linesize;
931
    int depth;
932
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
933
    int width;
934
    int height;
935
    void *opaque;
936
    QEMUTimer *gui_timer;
937

    
938
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
939
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
940
    void (*dpy_refresh)(struct DisplayState *s);
941
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
942
                     int dst_x, int dst_y, int w, int h);
943
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
944
                     int w, int h, uint32_t c);
945
    void (*mouse_set)(int x, int y, int on);
946
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
947
                          uint8_t *image, uint8_t *mask);
948
};
949

    
950
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
951
{
952
    s->dpy_update(s, x, y, w, h);
953
}
954

    
955
static inline void dpy_resize(DisplayState *s, int w, int h)
956
{
957
    s->dpy_resize(s, w, h);
958
}
959

    
960
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
961
                 unsigned long vga_ram_offset, int vga_ram_size);
962
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
963
                 unsigned long vga_ram_offset, int vga_ram_size,
964
                 unsigned long vga_bios_offset, int vga_bios_size);
965
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
966
                    unsigned long vga_ram_offset, int vga_ram_size,
967
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
968
                    int it_shift);
969

    
970
/* cirrus_vga.c */
971
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
972
                         unsigned long vga_ram_offset, int vga_ram_size);
973
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
974
                         unsigned long vga_ram_offset, int vga_ram_size);
975

    
976
/* vmware_vga.c */
977
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
978
                     unsigned long vga_ram_offset, int vga_ram_size);
979

    
980
/* sdl.c */
981
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
982

    
983
/* cocoa.m */
984
void cocoa_display_init(DisplayState *ds, int full_screen);
985

    
986
/* vnc.c */
987
void vnc_display_init(DisplayState *ds);
988
void vnc_display_close(DisplayState *ds);
989
int vnc_display_open(DisplayState *ds, const char *display);
990
int vnc_display_password(DisplayState *ds, const char *password);
991
void do_info_vnc(void);
992

    
993
/* x_keymap.c */
994
extern uint8_t _translate_keycode(const int key);
995

    
996
/* ide.c */
997
#define MAX_DISKS 4
998

    
999
extern BlockDriverState *bs_table[MAX_DISKS + 1];
1000
extern BlockDriverState *sd_bdrv;
1001
extern BlockDriverState *mtd_bdrv;
1002

    
1003
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1004
                  BlockDriverState *hd0, BlockDriverState *hd1);
1005
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1006
                         int secondary_ide_enabled);
1007
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1008
                        qemu_irq *pic);
1009
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1010
                        qemu_irq *pic);
1011
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1012

    
1013
/* cdrom.c */
1014
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1015
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1016

    
1017
/* ds1225y.c */
1018
typedef struct ds1225y_t ds1225y_t;
1019
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1020

    
1021
/* es1370.c */
1022
int es1370_init (PCIBus *bus, AudioState *s);
1023

    
1024
/* sb16.c */
1025
int SB16_init (AudioState *s, qemu_irq *pic);
1026

    
1027
/* adlib.c */
1028
int Adlib_init (AudioState *s, qemu_irq *pic);
1029

    
1030
/* gus.c */
1031
int GUS_init (AudioState *s, qemu_irq *pic);
1032

    
1033
/* dma.c */
1034
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1035
int DMA_get_channel_mode (int nchan);
1036
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1037
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1038
void DMA_hold_DREQ (int nchan);
1039
void DMA_release_DREQ (int nchan);
1040
void DMA_schedule(int nchan);
1041
void DMA_run (void);
1042
void DMA_init (int high_page_enable);
1043
void DMA_register_channel (int nchan,
1044
                           DMA_transfer_handler transfer_handler,
1045
                           void *opaque);
1046
/* fdc.c */
1047
#define MAX_FD 2
1048
extern BlockDriverState *fd_table[MAX_FD];
1049

    
1050
typedef struct fdctrl_t fdctrl_t;
1051

    
1052
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1053
                       target_phys_addr_t io_base,
1054
                       BlockDriverState **fds);
1055
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1056

    
1057
/* eepro100.c */
1058

    
1059
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1060
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1061
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1062

    
1063
/* ne2000.c */
1064

    
1065
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1066
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1067

    
1068
/* rtl8139.c */
1069

    
1070
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1071

    
1072
/* pcnet.c */
1073

    
1074
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1075
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1076
                qemu_irq irq, qemu_irq *reset);
1077

    
1078
/* vmmouse.c */
1079
void *vmmouse_init(void *m);
1080

    
1081
/* vmport.c */
1082
#ifdef TARGET_I386
1083
void vmport_init(CPUState *env);
1084
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1085
#endif
1086

    
1087
/* pckbd.c */
1088

    
1089
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1090
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1091
                   target_phys_addr_t base, int it_shift);
1092

    
1093
/* mc146818rtc.c */
1094

    
1095
typedef struct RTCState RTCState;
1096

    
1097
RTCState *rtc_init(int base, qemu_irq irq);
1098
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1099
void rtc_set_memory(RTCState *s, int addr, int val);
1100
void rtc_set_date(RTCState *s, const struct tm *tm);
1101

    
1102
/* serial.c */
1103

    
1104
typedef struct SerialState SerialState;
1105
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1106
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1107
                             qemu_irq irq, CharDriverState *chr,
1108
                             int ioregister);
1109
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1110
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1111
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1112
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1113
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1114
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1115

    
1116
/* parallel.c */
1117

    
1118
typedef struct ParallelState ParallelState;
1119
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1120
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1121

    
1122
/* i8259.c */
1123

    
1124
typedef struct PicState2 PicState2;
1125
extern PicState2 *isa_pic;
1126
void pic_set_irq(int irq, int level);
1127
void pic_set_irq_new(void *opaque, int irq, int level);
1128
qemu_irq *i8259_init(qemu_irq parent_irq);
1129
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1130
                          void *alt_irq_opaque);
1131
int pic_read_irq(PicState2 *s);
1132
void pic_update_irq(PicState2 *s);
1133
uint32_t pic_intack_read(PicState2 *s);
1134
void pic_info(void);
1135
void irq_info(void);
1136

    
1137
/* APIC */
1138
typedef struct IOAPICState IOAPICState;
1139

    
1140
int apic_init(CPUState *env);
1141
int apic_get_interrupt(CPUState *env);
1142
IOAPICState *ioapic_init(void);
1143
void ioapic_set_irq(void *opaque, int vector, int level);
1144

    
1145
/* i8254.c */
1146

    
1147
#define PIT_FREQ 1193182
1148

    
1149
typedef struct PITState PITState;
1150

    
1151
PITState *pit_init(int base, qemu_irq irq);
1152
void pit_set_gate(PITState *pit, int channel, int val);
1153
int pit_get_gate(PITState *pit, int channel);
1154
int pit_get_initial_count(PITState *pit, int channel);
1155
int pit_get_mode(PITState *pit, int channel);
1156
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1157

    
1158
/* jazz_led.c */
1159
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1160

    
1161
/* pcspk.c */
1162
void pcspk_init(PITState *);
1163
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1164

    
1165
#include "hw/i2c.h"
1166

    
1167
#include "hw/smbus.h"
1168

    
1169
/* acpi.c */
1170
extern int acpi_enabled;
1171
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1172
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1173
void acpi_bios_init(void);
1174

    
1175
/* pc.c */
1176
extern QEMUMachine pc_machine;
1177
extern QEMUMachine isapc_machine;
1178
extern int fd_bootchk;
1179

    
1180
void ioport_set_a20(int enable);
1181
int ioport_get_a20(void);
1182

    
1183
/* ppc.c */
1184
extern QEMUMachine prep_machine;
1185
extern QEMUMachine core99_machine;
1186
extern QEMUMachine heathrow_machine;
1187
extern QEMUMachine ref405ep_machine;
1188
extern QEMUMachine taihu_machine;
1189

    
1190
/* mips_r4k.c */
1191
extern QEMUMachine mips_machine;
1192

    
1193
/* mips_malta.c */
1194
extern QEMUMachine mips_malta_machine;
1195

    
1196
/* mips_int.c */
1197
extern void cpu_mips_irq_init_cpu(CPUState *env);
1198

    
1199
/* mips_pica61.c */
1200
extern QEMUMachine mips_pica61_machine;
1201

    
1202
/* mips_timer.c */
1203
extern void cpu_mips_clock_init(CPUState *);
1204
extern void cpu_mips_irqctrl_init (void);
1205

    
1206
/* shix.c */
1207
extern QEMUMachine shix_machine;
1208

    
1209
#ifdef TARGET_PPC
1210
/* PowerPC hardware exceptions management helpers */
1211
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1212
typedef struct clk_setup_t clk_setup_t;
1213
struct clk_setup_t {
1214
    clk_setup_cb cb;
1215
    void *opaque;
1216
};
1217
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1218
{
1219
    if (clk->cb != NULL)
1220
        (*clk->cb)(clk->opaque, freq);
1221
}
1222

    
1223
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1224
/* Embedded PowerPC DCR management */
1225
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1226
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1227
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1228
                  int (*dcr_write_error)(int dcrn));
1229
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1230
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1231
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1232
/* Embedded PowerPC reset */
1233
void ppc40x_core_reset (CPUState *env);
1234
void ppc40x_chip_reset (CPUState *env);
1235
void ppc40x_system_reset (CPUState *env);
1236
#endif
1237
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1238

    
1239
extern CPUWriteMemoryFunc *PPC_io_write[];
1240
extern CPUReadMemoryFunc *PPC_io_read[];
1241
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1242

    
1243
/* sun4m.c */
1244
extern QEMUMachine ss5_machine, ss10_machine;
1245

    
1246
/* iommu.c */
1247
void *iommu_init(target_phys_addr_t addr);
1248
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1249
                                 uint8_t *buf, int len, int is_write);
1250
static inline void sparc_iommu_memory_read(void *opaque,
1251
                                           target_phys_addr_t addr,
1252
                                           uint8_t *buf, int len)
1253
{
1254
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1255
}
1256

    
1257
static inline void sparc_iommu_memory_write(void *opaque,
1258
                                            target_phys_addr_t addr,
1259
                                            uint8_t *buf, int len)
1260
{
1261
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1262
}
1263

    
1264
/* tcx.c */
1265
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1266
              unsigned long vram_offset, int vram_size, int width, int height,
1267
              int depth);
1268

    
1269
/* slavio_intctl.c */
1270
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1271
                         const uint32_t *intbit_to_level,
1272
                         qemu_irq **irq, qemu_irq **cpu_irq,
1273
                         qemu_irq **parent_irq, unsigned int cputimer);
1274
void slavio_pic_info(void *opaque);
1275
void slavio_irq_info(void *opaque);
1276

    
1277
/* loader.c */
1278
int get_image_size(const char *filename);
1279
int load_image(const char *filename, uint8_t *addr);
1280
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1281
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1282
int load_aout(const char *filename, uint8_t *addr);
1283
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1284

    
1285
/* slavio_timer.c */
1286
void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1287

    
1288
/* slavio_serial.c */
1289
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1290
                                CharDriverState *chr1, CharDriverState *chr2);
1291
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1292

    
1293
/* slavio_misc.c */
1294
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1295
                       qemu_irq irq);
1296
void slavio_set_power_fail(void *opaque, int power_failing);
1297

    
1298
/* esp.c */
1299
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1300
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1301
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1302

    
1303
/* sparc32_dma.c */
1304
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1305
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1306
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1307
                       uint8_t *buf, int len, int do_bswap);
1308
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1309
                        uint8_t *buf, int len, int do_bswap);
1310
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1311
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1312

    
1313
/* cs4231.c */
1314
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1315

    
1316
/* sun4u.c */
1317
extern QEMUMachine sun4u_machine;
1318

    
1319
/* NVRAM helpers */
1320
#include "hw/m48t59.h"
1321

    
1322
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1323
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1324
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1325
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1326
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1327
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1328
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1329
                       const unsigned char *str, uint32_t max);
1330
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1331
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1332
                    uint32_t start, uint32_t count);
1333
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1334
                          const unsigned char *arch,
1335
                          uint32_t RAM_size, int boot_device,
1336
                          uint32_t kernel_image, uint32_t kernel_size,
1337
                          const char *cmdline,
1338
                          uint32_t initrd_image, uint32_t initrd_size,
1339
                          uint32_t NVRAM_image,
1340
                          int width, int height, int depth);
1341

    
1342
/* adb.c */
1343

    
1344
#define MAX_ADB_DEVICES 16
1345

    
1346
#define ADB_MAX_OUT_LEN 16
1347

    
1348
typedef struct ADBDevice ADBDevice;
1349

    
1350
/* buf = NULL means polling */
1351
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1352
                              const uint8_t *buf, int len);
1353
typedef int ADBDeviceReset(ADBDevice *d);
1354

    
1355
struct ADBDevice {
1356
    struct ADBBusState *bus;
1357
    int devaddr;
1358
    int handler;
1359
    ADBDeviceRequest *devreq;
1360
    ADBDeviceReset *devreset;
1361
    void *opaque;
1362
};
1363

    
1364
typedef struct ADBBusState {
1365
    ADBDevice devices[MAX_ADB_DEVICES];
1366
    int nb_devices;
1367
    int poll_index;
1368
} ADBBusState;
1369

    
1370
int adb_request(ADBBusState *s, uint8_t *buf_out,
1371
                const uint8_t *buf, int len);
1372
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1373

    
1374
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1375
                               ADBDeviceRequest *devreq,
1376
                               ADBDeviceReset *devreset,
1377
                               void *opaque);
1378
void adb_kbd_init(ADBBusState *bus);
1379
void adb_mouse_init(ADBBusState *bus);
1380

    
1381
/* cuda.c */
1382

    
1383
extern ADBBusState adb_bus;
1384
int cuda_init(qemu_irq irq);
1385

    
1386
#include "hw/usb.h"
1387

    
1388
/* usb ports of the VM */
1389

    
1390
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1391
                            usb_attachfn attach);
1392

    
1393
#define VM_USB_HUB_SIZE 8
1394

    
1395
void do_usb_add(const char *devname);
1396
void do_usb_del(const char *devname);
1397
void usb_info(void);
1398

    
1399
/* scsi-disk.c */
1400
enum scsi_reason {
1401
    SCSI_REASON_DONE, /* Command complete.  */
1402
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1403
};
1404

    
1405
typedef struct SCSIDevice SCSIDevice;
1406
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1407
                                  uint32_t arg);
1408

    
1409
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1410
                           int tcq,
1411
                           scsi_completionfn completion,
1412
                           void *opaque);
1413
void scsi_disk_destroy(SCSIDevice *s);
1414

    
1415
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1416
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1417
   layer the completion routine may be called directly by
1418
   scsi_{read,write}_data.  */
1419
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1420
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1421
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1422
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1423

    
1424
/* lsi53c895a.c */
1425
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1426
void *lsi_scsi_init(PCIBus *bus, int devfn);
1427

    
1428
/* integratorcp.c */
1429
extern QEMUMachine integratorcp_machine;
1430

    
1431
/* versatilepb.c */
1432
extern QEMUMachine versatilepb_machine;
1433
extern QEMUMachine versatileab_machine;
1434

    
1435
/* realview.c */
1436
extern QEMUMachine realview_machine;
1437

    
1438
/* spitz.c */
1439
extern QEMUMachine akitapda_machine;
1440
extern QEMUMachine spitzpda_machine;
1441
extern QEMUMachine borzoipda_machine;
1442
extern QEMUMachine terrierpda_machine;
1443

    
1444
/* palm.c */
1445
extern QEMUMachine palmte_machine;
1446

    
1447
/* ps2.c */
1448
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1449
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1450
void ps2_write_mouse(void *, int val);
1451
void ps2_write_keyboard(void *, int val);
1452
uint32_t ps2_read_data(void *);
1453
void ps2_queue(void *, int b);
1454
void ps2_keyboard_set_translation(void *opaque, int mode);
1455
void ps2_mouse_fake_event(void *opaque);
1456

    
1457
/* smc91c111.c */
1458
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1459

    
1460
/* pl031.c */
1461
void pl031_init(uint32_t base, qemu_irq irq);
1462

    
1463
/* pl110.c */
1464
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1465

    
1466
/* pl011.c */
1467
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1468

    
1469
/* pl050.c */
1470
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1471

    
1472
/* pl080.c */
1473
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1474

    
1475
/* pl181.c */
1476
void pl181_init(uint32_t base, BlockDriverState *bd,
1477
                qemu_irq irq0, qemu_irq irq1);
1478

    
1479
/* pl190.c */
1480
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1481

    
1482
/* arm-timer.c */
1483
void sp804_init(uint32_t base, qemu_irq irq);
1484
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1485

    
1486
/* arm_sysctl.c */
1487
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1488

    
1489
/* arm_gic.c */
1490
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1491

    
1492
/* arm_boot.c */
1493

    
1494
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1495
                     const char *kernel_cmdline, const char *initrd_filename,
1496
                     int board_id, target_phys_addr_t loader_start);
1497

    
1498
/* sh7750.c */
1499
struct SH7750State;
1500

    
1501
struct SH7750State *sh7750_init(CPUState * cpu);
1502

    
1503
typedef struct {
1504
    /* The callback will be triggered if any of the designated lines change */
1505
    uint16_t portamask_trigger;
1506
    uint16_t portbmask_trigger;
1507
    /* Return 0 if no action was taken */
1508
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1509
                           uint16_t * periph_pdtra,
1510
                           uint16_t * periph_portdira,
1511
                           uint16_t * periph_pdtrb,
1512
                           uint16_t * periph_portdirb);
1513
} sh7750_io_device;
1514

    
1515
int sh7750_register_io_device(struct SH7750State *s,
1516
                              sh7750_io_device * device);
1517
/* tc58128.c */
1518
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1519

    
1520
/* NOR flash devices */
1521
#define MAX_PFLASH 4
1522
extern BlockDriverState *pflash_table[MAX_PFLASH];
1523
typedef struct pflash_t pflash_t;
1524

    
1525
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1526
                           BlockDriverState *bs,
1527
                           uint32_t sector_len, int nb_blocs, int width,
1528
                           uint16_t id0, uint16_t id1,
1529
                           uint16_t id2, uint16_t id3);
1530

    
1531
/* nand.c */
1532
struct nand_flash_s;
1533
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1534
void nand_done(struct nand_flash_s *s);
1535
void nand_setpins(struct nand_flash_s *s,
1536
                int cle, int ale, int ce, int wp, int gnd);
1537
void nand_getpins(struct nand_flash_s *s, int *rb);
1538
void nand_setio(struct nand_flash_s *s, uint8_t value);
1539
uint8_t nand_getio(struct nand_flash_s *s);
1540

    
1541
#define NAND_MFR_TOSHIBA        0x98
1542
#define NAND_MFR_SAMSUNG        0xec
1543
#define NAND_MFR_FUJITSU        0x04
1544
#define NAND_MFR_NATIONAL        0x8f
1545
#define NAND_MFR_RENESAS        0x07
1546
#define NAND_MFR_STMICRO        0x20
1547
#define NAND_MFR_HYNIX                0xad
1548
#define NAND_MFR_MICRON                0x2c
1549

    
1550
/* ecc.c */
1551
struct ecc_state_s {
1552
    uint8_t cp;                /* Column parity */
1553
    uint16_t lp[2];        /* Line parity */
1554
    uint16_t count;
1555
};
1556

    
1557
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1558
void ecc_reset(struct ecc_state_s *s);
1559
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1560
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1561

    
1562
/* GPIO */
1563
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1564

    
1565
/* ads7846.c */
1566
struct ads7846_state_s;
1567
uint32_t ads7846_read(void *opaque);
1568
void ads7846_write(void *opaque, uint32_t value);
1569
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1570

    
1571
/* max111x.c */
1572
struct max111x_s;
1573
uint32_t max111x_read(void *opaque);
1574
void max111x_write(void *opaque, uint32_t value);
1575
struct max111x_s *max1110_init(qemu_irq cb);
1576
struct max111x_s *max1111_init(qemu_irq cb);
1577
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1578

    
1579
/* PCMCIA/Cardbus */
1580

    
1581
struct pcmcia_socket_s {
1582
    qemu_irq irq;
1583
    int attached;
1584
    const char *slot_string;
1585
    const char *card_string;
1586
};
1587

    
1588
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1589
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1590
void pcmcia_info(void);
1591

    
1592
struct pcmcia_card_s {
1593
    void *state;
1594
    struct pcmcia_socket_s *slot;
1595
    int (*attach)(void *state);
1596
    int (*detach)(void *state);
1597
    const uint8_t *cis;
1598
    int cis_len;
1599

    
1600
    /* Only valid if attached */
1601
    uint8_t (*attr_read)(void *state, uint32_t address);
1602
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1603
    uint16_t (*common_read)(void *state, uint32_t address);
1604
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1605
    uint16_t (*io_read)(void *state, uint32_t address);
1606
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1607
};
1608

    
1609
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1610
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1611
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1612
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1613
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1614
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1615
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1616
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1617
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1618
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1619
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1620
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1621
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1622
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1623
#define CISTPL_END                0xff        /* Tuple End */
1624
#define CISTPL_ENDMARK                0xff
1625

    
1626
/* dscm1xxxx.c */
1627
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1628

    
1629
/* ptimer.c */
1630
typedef struct ptimer_state ptimer_state;
1631
typedef void (*ptimer_cb)(void *opaque);
1632

    
1633
ptimer_state *ptimer_init(QEMUBH *bh);
1634
void ptimer_set_period(ptimer_state *s, int64_t period);
1635
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1636
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1637
uint64_t ptimer_get_count(ptimer_state *s);
1638
void ptimer_set_count(ptimer_state *s, uint64_t count);
1639
void ptimer_run(ptimer_state *s, int oneshot);
1640
void ptimer_stop(ptimer_state *s);
1641
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1642
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1643

    
1644
#include "hw/pxa.h"
1645

    
1646
#include "hw/omap.h"
1647

    
1648
/* mcf_uart.c */
1649
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1650
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1651
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1652
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1653
                      CharDriverState *chr);
1654

    
1655
/* mcf_intc.c */
1656
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1657

    
1658
/* mcf_fec.c */
1659
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1660

    
1661
/* mcf5206.c */
1662
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1663

    
1664
/* an5206.c */
1665
extern QEMUMachine an5206_machine;
1666

    
1667
/* mcf5208.c */
1668
extern QEMUMachine mcf5208evb_machine;
1669

    
1670
#include "gdbstub.h"
1671

    
1672
#endif /* defined(QEMU_TOOL) */
1673

    
1674
/* monitor.c */
1675
void monitor_init(CharDriverState *hd, int show_banner);
1676
void term_puts(const char *str);
1677
void term_vprintf(const char *fmt, va_list ap);
1678
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1679
void term_print_filename(const char *filename);
1680
void term_flush(void);
1681
void term_print_help(void);
1682
void monitor_readline(const char *prompt, int is_password,
1683
                      char *buf, int buf_size);
1684

    
1685
/* readline.c */
1686
typedef void ReadLineFunc(void *opaque, const char *str);
1687

    
1688
extern int completion_index;
1689
void add_completion(const char *str);
1690
void readline_handle_byte(int ch);
1691
void readline_find_completion(const char *cmdline);
1692
const char *readline_get_history(unsigned int index);
1693
void readline_start(const char *prompt, int is_password,
1694
                    ReadLineFunc *readline_func, void *opaque);
1695

    
1696
void kqemu_record_dump(void);
1697

    
1698
#endif /* VL_H */