Revision 29fe0e34

b/target-mips/translate_init.c
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    {
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        .name = "5Kc",
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        .CP0_PRid = 0x00018100,
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        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
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        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
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                    (MMU_TYPE_R4000 << CP0C0_MT),
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        .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
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		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
......
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    {
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        .name = "5Kf",
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        .CP0_PRid = 0x00018100,
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        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
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        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
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                    (MMU_TYPE_R4000 << CP0C0_MT),
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        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
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		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
......
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	/* We emulate a later version of the 20Kc, earlier ones had a broken
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           WAIT instruction. */
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        .CP0_PRid = 0x000182a0,
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        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
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        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
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                    (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
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        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
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		    (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |

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