Revision 2a0308c5 target-arm/translate.c

b/target-arm/translate.c
8378 8378
                tcg_gen_addi_i32(addr, addr, imm);
8379 8379
            } else {
8380 8380
                imm = insn & 0xff;
8381
                switch ((insn >> 8) & 7) {
8382
                case 0: case 8: /* Shifted Register.  */
8381
                switch ((insn >> 8) & 0xf) {
8382
                case 0x0: /* Shifted Register.  */
8383 8383
                    shift = (insn >> 4) & 0xf;
8384
                    if (shift > 3)
8384
                    if (shift > 3) {
8385
                        tcg_temp_free_i32(addr);
8385 8386
                        goto illegal_op;
8387
                    }
8386 8388
                    tmp = load_reg(s, rm);
8387 8389
                    if (shift)
8388 8390
                        tcg_gen_shli_i32(tmp, tmp, shift);
8389 8391
                    tcg_gen_add_i32(addr, addr, tmp);
8390 8392
                    tcg_temp_free_i32(tmp);
8391 8393
                    break;
8392
                case 4: /* Negative offset.  */
8394
                case 0xc: /* Negative offset.  */
8393 8395
                    tcg_gen_addi_i32(addr, addr, -imm);
8394 8396
                    break;
8395
                case 6: /* User privilege.  */
8397
                case 0xe: /* User privilege.  */
8396 8398
                    tcg_gen_addi_i32(addr, addr, imm);
8397 8399
                    user = 1;
8398 8400
                    break;
8399
                case 1: /* Post-decrement.  */
8401
                case 0x9: /* Post-decrement.  */
8400 8402
                    imm = -imm;
8401 8403
                    /* Fall through.  */
8402
                case 3: /* Post-increment.  */
8404
                case 0xb: /* Post-increment.  */
8403 8405
                    postinc = 1;
8404 8406
                    writeback = 1;
8405 8407
                    break;
8406
                case 5: /* Pre-decrement.  */
8408
                case 0xd: /* Pre-decrement.  */
8407 8409
                    imm = -imm;
8408 8410
                    /* Fall through.  */
8409
                case 7: /* Pre-increment.  */
8411
                case 0xf: /* Pre-increment.  */
8410 8412
                    tcg_gen_addi_i32(addr, addr, imm);
8411 8413
                    writeback = 1;
8412 8414
                    break;
8413 8415
                default:
8416
                    tcg_temp_free_i32(addr);
8414 8417
                    goto illegal_op;
8415 8418
                }
8416 8419
            }
......
8423 8426
            case 1: tmp = gen_ld16u(addr, user); break;
8424 8427
            case 5: tmp = gen_ld16s(addr, user); break;
8425 8428
            case 2: tmp = gen_ld32(addr, user); break;
8426
            default: goto illegal_op;
8429
            default:
8430
                tcg_temp_free_i32(addr);
8431
                goto illegal_op;
8427 8432
            }
8428 8433
            if (rs == 15) {
8429 8434
                gen_bx(s, tmp);
......
8437 8442
            case 0: gen_st8(tmp, addr, user); break;
8438 8443
            case 1: gen_st16(tmp, addr, user); break;
8439 8444
            case 2: gen_st32(tmp, addr, user); break;
8440
            default: goto illegal_op;
8445
            default:
8446
                tcg_temp_free_i32(addr);
8447
                goto illegal_op;
8441 8448
            }
8442 8449
        }
8443 8450
        if (postinc)

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