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root / target-arm @ 2a2af967

Name Size
cpu.h 18.3 kB
helper.c 95.9 kB
helper.h 17.1 kB
iwmmxt_helper.c 24.7 kB
machine.c 7.6 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 9.6 kB
translate.c 347.4 kB

Latest revisions

# Date Author Comment
0b03bdfc 01/25/2012 05:10 pm Peter Maydell

Add Cortex-A15 CPU definition

Add a definition of a Cortex-A15 CPU. Note that for the moment we do
not implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc)...
0383ac00 01/25/2012 02:42 pm Peter Maydell

Add dummy implementation of generic timer cp15 registers

Add a dummy implementation of the cp15 registers for the generic
timer (found in the Cortex-A15), just sufficient for Linux to
decide that it can't use it. This requires at least CNTP_CTL and
CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14....
dc8714ca 01/25/2012 01:49 pm Peter Maydell

target-arm: Fix implementation of TLB invalidate operations

Fix some bugs in the implementation of the TLB invalidate
operations on ARM: * the 'invalidate all' op was not passing flush_global=1
to tlb_flush(); this doesn't have a practical effect since...
85836979 01/25/2012 01:49 pm Peter Maydell

target-arm/helper.c: Don't assume softfloat int32 is 32 bits only

In the helper routines for VCVT float-to-int conversions, add
an explicit cast rather than relying on the softfloat int32
type being exactly 32 bits wide (which it is not guaranteed to be)....
5fe91019 01/25/2012 01:49 pm Mark Langsdorf

arm: store the config_base_register during cpu_reset

Long term, the config_base_register will be a QDM parameter. In the
meantime, models that use it need to be able to preserve it across
cpu_reset() calls.

Signed-off-by: Mark Langsdorf <>...
d3cb6e2b 01/13/2012 07:25 pm Peter Maydell

target-arm: Fix errors in decode of M profile CPS

Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK)
bits was reversed * the FAULTMASK system register number is 19, not 17

This fixes an issue reported as LP:913925....
2be27624 01/13/2012 07:25 pm Rob Herring

arm: Add dummy support for co-processor 15's secure config register

Signed-off-by: Rob Herring <>
Signed-off-by: Mark Langsdorf <>
Signed-off-by: Peter Maydell <>
1b9e01c1 01/05/2012 05:49 pm Peter Maydell

target-arm: Don't use cpu_single_env in bank_number()

Avoid using cpu_single_env in bank_number() -- if we were
called via the gdb stub reading or writing the CPSR then
it is NULL and we will segfault if we take the cpu_abort().

Signed-off-by: Peter Maydell <>
37064a8b 01/05/2012 05:49 pm Peter Maydell

target-arm: Ignore attempts to set invalid modes in CPSR

Ignore attempts to set the CPSR mode field to an invalid value.
This is UNPREDICTABLE, but we should not cpu_abort() for things
a malicious guest (or a confused user on the gdbstub interface)
can provoke....
7da362d0 01/05/2012 05:49 pm Mark Langsdorf

arm: add dummy A9-specific cp15 registers

Add dummy register support for the cp15, CRn=c15 registers.

config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.

Signed-off-by: Mark Langsdorf <>...

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