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/*
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 * QEMU System Emulator header
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL on code which does not depend on the target CPU
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   type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef likely
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#if __GNUC__ < 3
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#define __builtin_expect(x, n) (x)
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#endif
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x)   __builtin_expect(!!(x), 0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef always_inline
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#if (__GNUC__ < 3) || defined(__APPLE__)
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#define always_inline inline
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#else
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#define always_inline __attribute__ (( always_inline )) inline
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#endif
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#endif
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#include "audio/audio.h"
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern const char *bios_name;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int rtc_start_date;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int alt_grab;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int cursor_hide;
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extern int graphic_rotate;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern int old_param;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128
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extern const char *prom_envs[MAX_PROM_ENVS];
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extern unsigned int nb_prom_envs;
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC)
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#define BIOS_SIZE (1024 * 1024)
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#elif defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd,
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                         IOCanRWHandler *fd_read_poll,
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                         IOHandler *fd_read,
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                         IOHandler *fd_write,
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read,
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s,
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                           IOCanRWHandler *fd_can_read,
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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struct DisplayState {
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    uint8_t *data;
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    int linesize;
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    int depth;
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    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
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    int width;
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    int height;
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    void *opaque;
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    struct QEMUTimer *gui_timer;
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    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
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    void (*dpy_resize)(struct DisplayState *s, int w, int h);
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    void (*dpy_refresh)(struct DisplayState *s);
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    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
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                     int dst_x, int dst_y, int w, int h);
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    void (*dpy_fill)(struct DisplayState *s, int x, int y,
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                     int w, int h, uint32_t c);
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    void (*mouse_set)(int x, int y, int on);
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    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
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                          uint8_t *image, uint8_t *mask);
384 4728efa3 bellard
};
385 4728efa3 bellard
386 4728efa3 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
387 4728efa3 bellard
{
388 4728efa3 bellard
    s->dpy_update(s, x, y, w, h);
389 4728efa3 bellard
}
390 4728efa3 bellard
391 4728efa3 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
392 4728efa3 bellard
{
393 4728efa3 bellard
    s->dpy_resize(s, w, h);
394 4728efa3 bellard
}
395 4728efa3 bellard
396 95219897 pbrook
typedef void (*vga_hw_update_ptr)(void *);
397 95219897 pbrook
typedef void (*vga_hw_invalidate_ptr)(void *);
398 95219897 pbrook
typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
399 95219897 pbrook
400 95219897 pbrook
TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
401 95219897 pbrook
                                  vga_hw_invalidate_ptr invalidate,
402 95219897 pbrook
                                  vga_hw_screen_dump_ptr screen_dump,
403 95219897 pbrook
                                  void *opaque);
404 95219897 pbrook
void vga_hw_update(void);
405 95219897 pbrook
void vga_hw_invalidate(void);
406 95219897 pbrook
void vga_hw_screen_dump(const char *filename);
407 95219897 pbrook
408 95219897 pbrook
int is_graphic_console(void);
409 af3a9031 ths
CharDriverState *text_console_init(DisplayState *ds, const char *p);
410 82c643ff bellard
void console_select(unsigned int index);
411 a528b80c balrog
void console_color_init(DisplayState *ds);
412 82c643ff bellard
413 8d11df9e bellard
/* serial ports */
414 8d11df9e bellard
415 8d11df9e bellard
#define MAX_SERIAL_PORTS 4
416 8d11df9e bellard
417 8d11df9e bellard
extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
418 8d11df9e bellard
419 6508fe59 bellard
/* parallel ports */
420 6508fe59 bellard
421 6508fe59 bellard
#define MAX_PARALLEL_PORTS 3
422 6508fe59 bellard
423 6508fe59 bellard
extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
424 6508fe59 bellard
425 5867c88a ths
struct ParallelIOArg {
426 5867c88a ths
    void *buffer;
427 5867c88a ths
    int count;
428 5867c88a ths
};
429 5867c88a ths
430 7c9d8e07 bellard
/* VLANs support */
431 7c9d8e07 bellard
432 7c9d8e07 bellard
typedef struct VLANClientState VLANClientState;
433 7c9d8e07 bellard
434 7c9d8e07 bellard
struct VLANClientState {
435 7c9d8e07 bellard
    IOReadHandler *fd_read;
436 d861b05e pbrook
    /* Packets may still be sent if this returns zero.  It's used to
437 d861b05e pbrook
       rate-limit the slirp code.  */
438 d861b05e pbrook
    IOCanRWHandler *fd_can_read;
439 7c9d8e07 bellard
    void *opaque;
440 7c9d8e07 bellard
    struct VLANClientState *next;
441 7c9d8e07 bellard
    struct VLANState *vlan;
442 7c9d8e07 bellard
    char info_str[256];
443 7c9d8e07 bellard
};
444 7c9d8e07 bellard
445 7c9d8e07 bellard
typedef struct VLANState {
446 7c9d8e07 bellard
    int id;
447 7c9d8e07 bellard
    VLANClientState *first_client;
448 7c9d8e07 bellard
    struct VLANState *next;
449 833c7174 blueswir1
    unsigned int nb_guest_devs, nb_host_devs;
450 7c9d8e07 bellard
} VLANState;
451 7c9d8e07 bellard
452 7c9d8e07 bellard
VLANState *qemu_find_vlan(int id);
453 7c9d8e07 bellard
VLANClientState *qemu_new_vlan_client(VLANState *vlan,
454 d861b05e pbrook
                                      IOReadHandler *fd_read,
455 d861b05e pbrook
                                      IOCanRWHandler *fd_can_read,
456 d861b05e pbrook
                                      void *opaque);
457 d861b05e pbrook
int qemu_can_send_packet(VLANClientState *vc);
458 7c9d8e07 bellard
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
459 d861b05e pbrook
void qemu_handler_true(void *opaque);
460 7c9d8e07 bellard
461 7c9d8e07 bellard
void do_info_network(void);
462 7c9d8e07 bellard
463 7fb843f8 bellard
/* TAP win32 */
464 7fb843f8 bellard
int tap_win32_init(VLANState *vlan, const char *ifname);
465 7fb843f8 bellard
466 7c9d8e07 bellard
/* NIC info */
467 c4b1fcc0 bellard
468 c4b1fcc0 bellard
#define MAX_NICS 8
469 c4b1fcc0 bellard
470 7c9d8e07 bellard
typedef struct NICInfo {
471 c4b1fcc0 bellard
    uint8_t macaddr[6];
472 a41b2ff2 pbrook
    const char *model;
473 7c9d8e07 bellard
    VLANState *vlan;
474 7c9d8e07 bellard
} NICInfo;
475 c4b1fcc0 bellard
476 c4b1fcc0 bellard
extern int nb_nics;
477 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
478 8a7ddc38 bellard
479 31a60e22 blueswir1
/* SLIRP */
480 31a60e22 blueswir1
void do_info_slirp(void);
481 31a60e22 blueswir1
482 8a7ddc38 bellard
/* timers */
483 8a7ddc38 bellard
484 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
485 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
486 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
487 8a7ddc38 bellard
488 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
489 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
490 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
491 8a7ddc38 bellard
   Hz. */
492 8a7ddc38 bellard
extern QEMUClock *rt_clock;
493 8a7ddc38 bellard
494 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
495 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
496 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
497 8a7ddc38 bellard
extern QEMUClock *vm_clock;
498 8a7ddc38 bellard
499 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
500 8a7ddc38 bellard
501 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
502 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
503 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
504 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
505 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
506 8a7ddc38 bellard
507 8a7ddc38 bellard
extern int64_t ticks_per_sec;
508 8a7ddc38 bellard
509 1dce7c3c bellard
int64_t cpu_get_ticks(void);
510 8a7ddc38 bellard
void cpu_enable_ticks(void);
511 8a7ddc38 bellard
void cpu_disable_ticks(void);
512 8a7ddc38 bellard
513 8a7ddc38 bellard
/* VM Load/Save */
514 8a7ddc38 bellard
515 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
516 8a7ddc38 bellard
517 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
518 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
519 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
520 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
521 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
522 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
523 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
524 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
525 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
526 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
527 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
528 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
529 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
530 8a7ddc38 bellard
531 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
532 8a7ddc38 bellard
{
533 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
534 8a7ddc38 bellard
}
535 8a7ddc38 bellard
536 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
537 8a7ddc38 bellard
{
538 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
539 8a7ddc38 bellard
}
540 8a7ddc38 bellard
541 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
542 8a7ddc38 bellard
{
543 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
544 8a7ddc38 bellard
}
545 8a7ddc38 bellard
546 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
547 8a7ddc38 bellard
{
548 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
549 8a7ddc38 bellard
}
550 8a7ddc38 bellard
551 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
552 8a7ddc38 bellard
{
553 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
554 8a7ddc38 bellard
}
555 8a7ddc38 bellard
556 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
557 8a7ddc38 bellard
{
558 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
559 8a7ddc38 bellard
}
560 8a7ddc38 bellard
561 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
562 8a7ddc38 bellard
{
563 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
564 8a7ddc38 bellard
}
565 8a7ddc38 bellard
566 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
567 8a7ddc38 bellard
{
568 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
569 8a7ddc38 bellard
}
570 8a7ddc38 bellard
571 c27004ec bellard
#if TARGET_LONG_BITS == 64
572 c27004ec bellard
#define qemu_put_betl qemu_put_be64
573 c27004ec bellard
#define qemu_get_betl qemu_get_be64
574 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
575 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
576 c27004ec bellard
#else
577 c27004ec bellard
#define qemu_put_betl qemu_put_be32
578 c27004ec bellard
#define qemu_get_betl qemu_get_be32
579 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
580 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
581 c27004ec bellard
#endif
582 c27004ec bellard
583 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
584 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
585 8a7ddc38 bellard
586 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
587 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
588 8a7ddc38 bellard
589 5fafdf24 ths
int register_savevm(const char *idstr,
590 5fafdf24 ths
                    int instance_id,
591 8a7ddc38 bellard
                    int version_id,
592 8a7ddc38 bellard
                    SaveStateHandler *save_state,
593 8a7ddc38 bellard
                    LoadStateHandler *load_state,
594 8a7ddc38 bellard
                    void *opaque);
595 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
596 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
597 c4b1fcc0 bellard
598 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
599 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
600 6a00d601 bellard
601 faea38e7 bellard
void do_savevm(const char *name);
602 faea38e7 bellard
void do_loadvm(const char *name);
603 faea38e7 bellard
void do_delvm(const char *name);
604 faea38e7 bellard
void do_info_snapshots(void);
605 faea38e7 bellard
606 83f64091 bellard
/* bottom halves */
607 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
608 83f64091 bellard
609 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
610 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
611 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
612 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
613 6eb5733a bellard
int qemu_bh_poll(void);
614 83f64091 bellard
615 fc01f7e7 bellard
/* block.c */
616 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
617 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
618 ea2384d3 bellard
619 ea2384d3 bellard
extern BlockDriver bdrv_raw;
620 19cb3738 bellard
extern BlockDriver bdrv_host_device;
621 ea2384d3 bellard
extern BlockDriver bdrv_cow;
622 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
623 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
624 3c56521b bellard
extern BlockDriver bdrv_cloop;
625 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
626 a8753c34 bellard
extern BlockDriver bdrv_bochs;
627 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
628 de167e41 bellard
extern BlockDriver bdrv_vvfat;
629 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
630 6ada7453 ths
extern BlockDriver bdrv_parallels;
631 faea38e7 bellard
632 faea38e7 bellard
typedef struct BlockDriverInfo {
633 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
634 5fafdf24 ths
    int cluster_size;
635 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
636 5fafdf24 ths
    int64_t vm_state_offset;
637 faea38e7 bellard
} BlockDriverInfo;
638 faea38e7 bellard
639 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
640 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
641 faea38e7 bellard
    /* the following fields are informative. They are not needed for
642 faea38e7 bellard
       the consistency of the snapshot */
643 faea38e7 bellard
    char name[256]; /* user choosen name */
644 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
645 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
646 faea38e7 bellard
    uint32_t date_nsec;
647 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
648 faea38e7 bellard
} QEMUSnapshotInfo;
649 ea2384d3 bellard
650 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
651 83f64091 bellard
#define BDRV_O_RDWR        0x0002
652 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
653 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
654 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
655 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
656 83f64091 bellard
                                     use a disk image format on top of
657 83f64091 bellard
                                     it (default for
658 83f64091 bellard
                                     bdrv_file_open()) */
659 83f64091 bellard
660 ea2384d3 bellard
void bdrv_init(void);
661 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
662 5fafdf24 ths
int bdrv_create(BlockDriver *drv,
663 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
664 ea2384d3 bellard
                const char *backing_file, int flags);
665 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
666 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
667 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
668 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
669 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
670 ea2384d3 bellard
               BlockDriver *drv);
671 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
672 5fafdf24 ths
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
673 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
674 5fafdf24 ths
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
675 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
676 5fafdf24 ths
int bdrv_pread(BlockDriverState *bs, int64_t offset,
677 83f64091 bellard
               void *buf, int count);
678 5fafdf24 ths
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
679 83f64091 bellard
                const void *buf, int count);
680 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
681 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
682 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
683 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
684 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
685 83f64091 bellard
/* async block I/O */
686 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
687 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
688 83f64091 bellard
689 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
690 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
691 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
692 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
693 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
694 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
695 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
696 83f64091 bellard
697 83f64091 bellard
void qemu_aio_init(void);
698 83f64091 bellard
void qemu_aio_poll(void);
699 6192bc37 pbrook
void qemu_aio_flush(void);
700 83f64091 bellard
void qemu_aio_wait_start(void);
701 83f64091 bellard
void qemu_aio_wait(void);
702 83f64091 bellard
void qemu_aio_wait_end(void);
703 83f64091 bellard
704 2bac6019 balrog
int qemu_key_check(BlockDriverState *bs, const char *name);
705 2bac6019 balrog
706 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
707 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
708 33e3963e bellard
709 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
710 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
711 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
712 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
713 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
714 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
715 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
716 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
717 c4b1fcc0 bellard
718 5fafdf24 ths
void bdrv_set_geometry_hint(BlockDriverState *bs,
719 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
720 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
721 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
722 5fafdf24 ths
void bdrv_get_geometry_hint(BlockDriverState *bs,
723 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
724 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
725 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
726 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
727 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
728 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
729 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
730 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
731 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
732 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
733 5fafdf24 ths
void bdrv_set_change_cb(BlockDriverState *bs,
734 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
735 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
736 c4b1fcc0 bellard
void bdrv_info(void);
737 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
738 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
739 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
740 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
741 5fafdf24 ths
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
742 ea2384d3 bellard
                         void *opaque);
743 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
744 5fafdf24 ths
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
745 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
746 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
747 c4b1fcc0 bellard
748 5fafdf24 ths
void bdrv_get_backing_filename(BlockDriverState *bs,
749 83f64091 bellard
                               char *filename, int filename_size);
750 5fafdf24 ths
int bdrv_snapshot_create(BlockDriverState *bs,
751 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
752 5fafdf24 ths
int bdrv_snapshot_goto(BlockDriverState *bs,
753 faea38e7 bellard
                       const char *snapshot_id);
754 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
755 5fafdf24 ths
int bdrv_snapshot_list(BlockDriverState *bs,
756 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
757 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
758 faea38e7 bellard
759 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
760 83f64091 bellard
int path_is_absolute(const char *path);
761 83f64091 bellard
void path_combine(char *dest, int dest_size,
762 83f64091 bellard
                  const char *base_path,
763 83f64091 bellard
                  const char *filename);
764 ea2384d3 bellard
765 4728efa3 bellard
766 4728efa3 bellard
/* monitor.c */
767 4728efa3 bellard
void monitor_init(CharDriverState *hd, int show_banner);
768 4728efa3 bellard
void term_puts(const char *str);
769 4728efa3 bellard
void term_vprintf(const char *fmt, va_list ap);
770 4728efa3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
771 4728efa3 bellard
void term_print_filename(const char *filename);
772 4728efa3 bellard
void term_flush(void);
773 4728efa3 bellard
void term_print_help(void);
774 4728efa3 bellard
void monitor_readline(const char *prompt, int is_password,
775 4728efa3 bellard
                      char *buf, int buf_size);
776 4728efa3 bellard
777 4728efa3 bellard
/* readline.c */
778 4728efa3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
779 4728efa3 bellard
780 4728efa3 bellard
extern int completion_index;
781 4728efa3 bellard
void add_completion(const char *str);
782 4728efa3 bellard
void readline_handle_byte(int ch);
783 4728efa3 bellard
void readline_find_completion(const char *cmdline);
784 4728efa3 bellard
const char *readline_get_history(unsigned int index);
785 4728efa3 bellard
void readline_start(const char *prompt, int is_password,
786 4728efa3 bellard
                    ReadLineFunc *readline_func, void *opaque);
787 4728efa3 bellard
788 4728efa3 bellard
void kqemu_record_dump(void);
789 4728efa3 bellard
790 2a324a26 bellard
/* sdl.c */
791 2a324a26 bellard
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
792 2a324a26 bellard
793 2a324a26 bellard
/* cocoa.m */
794 2a324a26 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
795 2a324a26 bellard
796 2a324a26 bellard
/* vnc.c */
797 2a324a26 bellard
void vnc_display_init(DisplayState *ds);
798 2a324a26 bellard
void vnc_display_close(DisplayState *ds);
799 2a324a26 bellard
int vnc_display_open(DisplayState *ds, const char *display);
800 2a324a26 bellard
int vnc_display_password(DisplayState *ds, const char *password);
801 2a324a26 bellard
void do_info_vnc(void);
802 2a324a26 bellard
803 2a324a26 bellard
/* x_keymap.c */
804 2a324a26 bellard
extern uint8_t _translate_keycode(const int key);
805 2a324a26 bellard
806 ea2384d3 bellard
#ifndef QEMU_TOOL
807 54fa5af5 bellard
808 5fafdf24 ths
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
809 6ac0e82d balrog
                                 const char *boot_device,
810 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
811 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
812 94fc95cd j_mayer
             const char *initrd_filename, const char *cpu_model);
813 54fa5af5 bellard
814 54fa5af5 bellard
typedef struct QEMUMachine {
815 54fa5af5 bellard
    const char *name;
816 54fa5af5 bellard
    const char *desc;
817 54fa5af5 bellard
    QEMUMachineInitFunc *init;
818 54fa5af5 bellard
    struct QEMUMachine *next;
819 54fa5af5 bellard
} QEMUMachine;
820 54fa5af5 bellard
821 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
822 54fa5af5 bellard
823 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
824 54fa5af5 bellard
825 d537cf6c pbrook
#include "hw/irq.h"
826 d537cf6c pbrook
827 26aa7d72 bellard
/* ISA bus */
828 26aa7d72 bellard
829 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
830 26aa7d72 bellard
831 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
832 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
833 26aa7d72 bellard
834 5fafdf24 ths
int register_ioport_read(int start, int length, int size,
835 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
836 5fafdf24 ths
int register_ioport_write(int start, int length, int size,
837 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
838 69b91039 bellard
void isa_unassign_ioport(int start, int length);
839 69b91039 bellard
840 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
841 aef445bd pbrook
842 69b91039 bellard
/* PCI bus */
843 69b91039 bellard
844 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
845 69b91039 bellard
846 46e50e9d bellard
typedef struct PCIBus PCIBus;
847 69b91039 bellard
typedef struct PCIDevice PCIDevice;
848 69b91039 bellard
849 5fafdf24 ths
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
850 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
851 5fafdf24 ths
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
852 69b91039 bellard
                                   uint32_t address, int len);
853 5fafdf24 ths
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
854 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
855 69b91039 bellard
856 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
857 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
858 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
859 69b91039 bellard
860 69b91039 bellard
typedef struct PCIIORegion {
861 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
862 69b91039 bellard
    uint32_t size;
863 69b91039 bellard
    uint8_t type;
864 69b91039 bellard
    PCIMapIORegionFunc *map_func;
865 69b91039 bellard
} PCIIORegion;
866 69b91039 bellard
867 8a8696a3 bellard
#define PCI_ROM_SLOT 6
868 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
869 502a5395 pbrook
870 502a5395 pbrook
#define PCI_DEVICES_MAX 64
871 502a5395 pbrook
872 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
873 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
874 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
875 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
876 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
877 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
878 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
879 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
880 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
881 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
882 502a5395 pbrook
883 69b91039 bellard
struct PCIDevice {
884 69b91039 bellard
    /* PCI config space */
885 69b91039 bellard
    uint8_t config[256];
886 69b91039 bellard
887 69b91039 bellard
    /* the following fields are read only */
888 46e50e9d bellard
    PCIBus *bus;
889 69b91039 bellard
    int devfn;
890 69b91039 bellard
    char name[64];
891 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
892 3b46e624 ths
893 69b91039 bellard
    /* do not access the following fields */
894 69b91039 bellard
    PCIConfigReadFunc *config_read;
895 69b91039 bellard
    PCIConfigWriteFunc *config_write;
896 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
897 5768f5ac bellard
    int irq_index;
898 d2b59317 pbrook
899 d537cf6c pbrook
    /* IRQ objects for the INTA-INTD pins.  */
900 d537cf6c pbrook
    qemu_irq *irq;
901 d537cf6c pbrook
902 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
903 d2b59317 pbrook
    int irq_state[4];
904 69b91039 bellard
};
905 69b91039 bellard
906 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
907 46e50e9d bellard
                               int instance_size, int devfn,
908 5fafdf24 ths
                               PCIConfigReadFunc *config_read,
909 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
910 69b91039 bellard
911 5fafdf24 ths
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
912 5fafdf24 ths
                            uint32_t size, int type,
913 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
914 69b91039 bellard
915 5fafdf24 ths
uint32_t pci_default_read_config(PCIDevice *d,
916 5768f5ac bellard
                                 uint32_t address, int len);
917 5fafdf24 ths
void pci_default_write_config(PCIDevice *d,
918 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
919 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
920 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
921 5768f5ac bellard
922 d537cf6c pbrook
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
923 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
924 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
925 d537cf6c pbrook
                         qemu_irq *pic, int devfn_min, int nirq);
926 502a5395 pbrook
927 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
928 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
929 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
930 502a5395 pbrook
int pci_bus_num(PCIBus *s);
931 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
932 9995c51f bellard
933 5768f5ac bellard
void pci_info(void);
934 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
935 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
936 26aa7d72 bellard
937 502a5395 pbrook
/* prep_pci.c */
938 d537cf6c pbrook
PCIBus *pci_prep_init(qemu_irq *pic);
939 77d4bc34 bellard
940 502a5395 pbrook
/* apb_pci.c */
941 5b9693dc blueswir1
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
942 d537cf6c pbrook
                     qemu_irq *pic);
943 502a5395 pbrook
944 d537cf6c pbrook
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
945 502a5395 pbrook
946 502a5395 pbrook
/* piix_pci.c */
947 d537cf6c pbrook
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
948 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
949 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
950 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
951 a41b2ff2 pbrook
952 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
953 5856de80 ths
954 28b9b5af bellard
/* openpic.c */
955 e9df014c j_mayer
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
956 47103572 j_mayer
enum {
957 e9df014c j_mayer
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
958 e9df014c j_mayer
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
959 e9df014c j_mayer
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
960 e9df014c j_mayer
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
961 e9df014c j_mayer
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
962 e9df014c j_mayer
    OPENPIC_OUTPUT_NB,
963 47103572 j_mayer
};
964 e9df014c j_mayer
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
965 e9df014c j_mayer
                        qemu_irq **irqs, qemu_irq irq_out);
966 28b9b5af bellard
967 fde7d5bd ths
/* gt64xxx.c */
968 d537cf6c pbrook
PCIBus *pci_gt64120_init(qemu_irq *pic);
969 fde7d5bd ths
970 6a36d84e bellard
#ifdef HAS_AUDIO
971 6a36d84e bellard
struct soundhw {
972 6a36d84e bellard
    const char *name;
973 6a36d84e bellard
    const char *descr;
974 6a36d84e bellard
    int enabled;
975 6a36d84e bellard
    int isa;
976 6a36d84e bellard
    union {
977 d537cf6c pbrook
        int (*init_isa) (AudioState *s, qemu_irq *pic);
978 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
979 6a36d84e bellard
    } init;
980 6a36d84e bellard
};
981 6a36d84e bellard
982 6a36d84e bellard
extern struct soundhw soundhw[];
983 6a36d84e bellard
#endif
984 6a36d84e bellard
985 313aa567 bellard
/* vga.c */
986 313aa567 bellard
987 eee0b836 blueswir1
#ifndef TARGET_SPARC
988 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
989 eee0b836 blueswir1
#else
990 eee0b836 blueswir1
#define VGA_RAM_SIZE (9 * 1024 * 1024)
991 eee0b836 blueswir1
#endif
992 313aa567 bellard
993 5fafdf24 ths
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
994 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
995 5fafdf24 ths
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
996 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
997 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
998 2abec30b ths
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
999 2abec30b ths
                    unsigned long vga_ram_offset, int vga_ram_size,
1000 2abec30b ths
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
1001 2abec30b ths
                    int it_shift);
1002 313aa567 bellard
1003 d6bfa22f bellard
/* cirrus_vga.c */
1004 5fafdf24 ths
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1005 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
1006 5fafdf24 ths
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1007 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
1008 d6bfa22f bellard
1009 d34cab9f ths
/* vmware_vga.c */
1010 d34cab9f ths
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1011 d34cab9f ths
                     unsigned long vga_ram_offset, int vga_ram_size);
1012 d34cab9f ths
1013 5391d806 bellard
/* ide.c */
1014 5391d806 bellard
#define MAX_DISKS 4
1015 5391d806 bellard
1016 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
1017 a1bb27b1 pbrook
extern BlockDriverState *sd_bdrv;
1018 3e3d5815 balrog
extern BlockDriverState *mtd_bdrv;
1019 5391d806 bellard
1020 d537cf6c pbrook
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1021 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
1022 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1023 54fa5af5 bellard
                         int secondary_ide_enabled);
1024 d537cf6c pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1025 d537cf6c pbrook
                        qemu_irq *pic);
1026 afcc3cdf ths
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1027 afcc3cdf ths
                        qemu_irq *pic);
1028 5391d806 bellard
1029 2e5d83bb pbrook
/* cdrom.c */
1030 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1031 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1032 2e5d83bb pbrook
1033 9542611a ths
/* ds1225y.c */
1034 9542611a ths
typedef struct ds1225y_t ds1225y_t;
1035 71db710f blueswir1
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1036 9542611a ths
1037 1d14ffa9 bellard
/* es1370.c */
1038 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
1039 1d14ffa9 bellard
1040 fb065187 bellard
/* sb16.c */
1041 d537cf6c pbrook
int SB16_init (AudioState *s, qemu_irq *pic);
1042 fb065187 bellard
1043 fb065187 bellard
/* adlib.c */
1044 d537cf6c pbrook
int Adlib_init (AudioState *s, qemu_irq *pic);
1045 fb065187 bellard
1046 fb065187 bellard
/* gus.c */
1047 d537cf6c pbrook
int GUS_init (AudioState *s, qemu_irq *pic);
1048 27503323 bellard
1049 27503323 bellard
/* dma.c */
1050 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1051 27503323 bellard
int DMA_get_channel_mode (int nchan);
1052 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1053 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1054 27503323 bellard
void DMA_hold_DREQ (int nchan);
1055 27503323 bellard
void DMA_release_DREQ (int nchan);
1056 16f62432 bellard
void DMA_schedule(int nchan);
1057 27503323 bellard
void DMA_run (void);
1058 28b9b5af bellard
void DMA_init (int high_page_enable);
1059 27503323 bellard
void DMA_register_channel (int nchan,
1060 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
1061 85571bc7 bellard
                           void *opaque);
1062 7138fcfb bellard
/* fdc.c */
1063 7138fcfb bellard
#define MAX_FD 2
1064 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
1065 7138fcfb bellard
1066 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
1067 baca51fa bellard
1068 5fafdf24 ths
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1069 5dcb6b91 blueswir1
                       target_phys_addr_t io_base,
1070 baca51fa bellard
                       BlockDriverState **fds);
1071 741402f9 blueswir1
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1072 741402f9 blueswir1
                             BlockDriverState **fds);
1073 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1074 7138fcfb bellard
1075 663e8e51 ths
/* eepro100.c */
1076 663e8e51 ths
1077 663e8e51 ths
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1078 663e8e51 ths
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1079 663e8e51 ths
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1080 663e8e51 ths
1081 80cabfad bellard
/* ne2000.c */
1082 80cabfad bellard
1083 d537cf6c pbrook
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1084 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1085 80cabfad bellard
1086 a41b2ff2 pbrook
/* rtl8139.c */
1087 a41b2ff2 pbrook
1088 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1089 a41b2ff2 pbrook
1090 e3c2613f bellard
/* pcnet.c */
1091 e3c2613f bellard
1092 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1093 70c0de96 blueswir1
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1094 2d069bab blueswir1
                qemu_irq irq, qemu_irq *reset);
1095 67e999be bellard
1096 6bf5b4e8 ths
/* mipsnet.c */
1097 6bf5b4e8 ths
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1098 6bf5b4e8 ths
1099 548df2ac ths
/* vmmouse.c */
1100 548df2ac ths
void *vmmouse_init(void *m);
1101 e3c2613f bellard
1102 591a6d62 ths
/* vmport.c */
1103 591a6d62 ths
#ifdef TARGET_I386
1104 591a6d62 ths
void vmport_init(CPUState *env);
1105 591a6d62 ths
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1106 591a6d62 ths
#endif
1107 591a6d62 ths
1108 80cabfad bellard
/* pckbd.c */
1109 80cabfad bellard
1110 b92bb99b ths
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1111 71db710f blueswir1
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1112 71db710f blueswir1
                   target_phys_addr_t base, int it_shift);
1113 80cabfad bellard
1114 80cabfad bellard
/* mc146818rtc.c */
1115 80cabfad bellard
1116 8a7ddc38 bellard
typedef struct RTCState RTCState;
1117 80cabfad bellard
1118 d537cf6c pbrook
RTCState *rtc_init(int base, qemu_irq irq);
1119 18c6e2ff ths
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1120 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
1121 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
1122 80cabfad bellard
1123 80cabfad bellard
/* serial.c */
1124 80cabfad bellard
1125 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1126 d537cf6c pbrook
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1127 71db710f blueswir1
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1128 d537cf6c pbrook
                             qemu_irq irq, CharDriverState *chr,
1129 a4bc3afc ths
                             int ioregister);
1130 a4bc3afc ths
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1131 a4bc3afc ths
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1132 a4bc3afc ths
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1133 a4bc3afc ths
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1134 a4bc3afc ths
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1135 a4bc3afc ths
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1136 80cabfad bellard
1137 6508fe59 bellard
/* parallel.c */
1138 6508fe59 bellard
1139 6508fe59 bellard
typedef struct ParallelState ParallelState;
1140 d537cf6c pbrook
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1141 d60532ca ths
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1142 6508fe59 bellard
1143 80cabfad bellard
/* i8259.c */
1144 80cabfad bellard
1145 3de388f6 bellard
typedef struct PicState2 PicState2;
1146 3de388f6 bellard
extern PicState2 *isa_pic;
1147 80cabfad bellard
void pic_set_irq(int irq, int level);
1148 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1149 d537cf6c pbrook
qemu_irq *i8259_init(qemu_irq parent_irq);
1150 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1151 d592d303 bellard
                          void *alt_irq_opaque);
1152 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1153 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1154 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1155 c20709aa bellard
void pic_info(void);
1156 4a0fb71e bellard
void irq_info(void);
1157 80cabfad bellard
1158 c27004ec bellard
/* APIC */
1159 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1160 d592d303 bellard
1161 c27004ec bellard
int apic_init(CPUState *env);
1162 0e21e12b ths
int apic_accept_pic_intr(CPUState *env);
1163 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1164 d592d303 bellard
IOAPICState *ioapic_init(void);
1165 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1166 c27004ec bellard
1167 80cabfad bellard
/* i8254.c */
1168 80cabfad bellard
1169 80cabfad bellard
#define PIT_FREQ 1193182
1170 80cabfad bellard
1171 ec844b96 bellard
typedef struct PITState PITState;
1172 ec844b96 bellard
1173 d537cf6c pbrook
PITState *pit_init(int base, qemu_irq irq);
1174 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1175 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1176 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1177 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1178 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1179 80cabfad bellard
1180 31211df1 ths
/* jazz_led.c */
1181 31211df1 ths
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1182 31211df1 ths
1183 fd06c375 bellard
/* pcspk.c */
1184 fd06c375 bellard
void pcspk_init(PITState *);
1185 d537cf6c pbrook
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1186 fd06c375 bellard
1187 0ff596d0 pbrook
#include "hw/i2c.h"
1188 0ff596d0 pbrook
1189 3fffc223 ths
#include "hw/smbus.h"
1190 3fffc223 ths
1191 6515b203 bellard
/* acpi.c */
1192 6515b203 bellard
extern int acpi_enabled;
1193 7b717336 ths
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1194 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1195 6515b203 bellard
void acpi_bios_init(void);
1196 6515b203 bellard
1197 f1ccf904 ths
/* Axis ETRAX.  */
1198 f1ccf904 ths
extern QEMUMachine bareetraxfs_machine;
1199 f1ccf904 ths
1200 80cabfad bellard
/* pc.c */
1201 54fa5af5 bellard
extern QEMUMachine pc_machine;
1202 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1203 52ca8d6a bellard
extern int fd_bootchk;
1204 80cabfad bellard
1205 6a00d601 bellard
void ioport_set_a20(int enable);
1206 6a00d601 bellard
int ioport_get_a20(void);
1207 6a00d601 bellard
1208 26aa7d72 bellard
/* ppc.c */
1209 54fa5af5 bellard
extern QEMUMachine prep_machine;
1210 54fa5af5 bellard
extern QEMUMachine core99_machine;
1211 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1212 1a6c0886 j_mayer
extern QEMUMachine ref405ep_machine;
1213 1a6c0886 j_mayer
extern QEMUMachine taihu_machine;
1214 54fa5af5 bellard
1215 6af0bf9c bellard
/* mips_r4k.c */
1216 6af0bf9c bellard
extern QEMUMachine mips_machine;
1217 6af0bf9c bellard
1218 5856de80 ths
/* mips_malta.c */
1219 5856de80 ths
extern QEMUMachine mips_malta_machine;
1220 5856de80 ths
1221 ad6fe1d2 ths
/* mips_pica61.c */
1222 ad6fe1d2 ths
extern QEMUMachine mips_pica61_machine;
1223 ad6fe1d2 ths
1224 6bf5b4e8 ths
/* mips_mipssim.c */
1225 6bf5b4e8 ths
extern QEMUMachine mips_mipssim_machine;
1226 6bf5b4e8 ths
1227 6bf5b4e8 ths
/* mips_int.c */
1228 6bf5b4e8 ths
extern void cpu_mips_irq_init_cpu(CPUState *env);
1229 6bf5b4e8 ths
1230 e16fe40c ths
/* mips_timer.c */
1231 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1232 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1233 e16fe40c ths
1234 27c7ca7e bellard
/* shix.c */
1235 27c7ca7e bellard
extern QEMUMachine shix_machine;
1236 27c7ca7e bellard
1237 0d78f544 ths
/* r2d.c */
1238 0d78f544 ths
extern QEMUMachine r2d_machine;
1239 0d78f544 ths
1240 8cc43fef bellard
#ifdef TARGET_PPC
1241 47103572 j_mayer
/* PowerPC hardware exceptions management helpers */
1242 8ecc7913 j_mayer
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1243 8ecc7913 j_mayer
typedef struct clk_setup_t clk_setup_t;
1244 8ecc7913 j_mayer
struct clk_setup_t {
1245 8ecc7913 j_mayer
    clk_setup_cb cb;
1246 8ecc7913 j_mayer
    void *opaque;
1247 8ecc7913 j_mayer
};
1248 8ecc7913 j_mayer
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1249 8ecc7913 j_mayer
{
1250 8ecc7913 j_mayer
    if (clk->cb != NULL)
1251 8ecc7913 j_mayer
        (*clk->cb)(clk->opaque, freq);
1252 8ecc7913 j_mayer
}
1253 8ecc7913 j_mayer
1254 8ecc7913 j_mayer
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1255 2e719ba3 j_mayer
/* Embedded PowerPC DCR management */
1256 2e719ba3 j_mayer
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1257 2e719ba3 j_mayer
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1258 2e719ba3 j_mayer
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1259 2e719ba3 j_mayer
                  int (*dcr_write_error)(int dcrn));
1260 2e719ba3 j_mayer
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1261 2e719ba3 j_mayer
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1262 8ecc7913 j_mayer
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1263 4a057712 j_mayer
/* Embedded PowerPC reset */
1264 4a057712 j_mayer
void ppc40x_core_reset (CPUState *env);
1265 4a057712 j_mayer
void ppc40x_chip_reset (CPUState *env);
1266 4a057712 j_mayer
void ppc40x_system_reset (CPUState *env);
1267 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1268 77d4bc34 bellard
1269 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1270 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1271 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1272 3cbee15b j_mayer
#endif
1273 26aa7d72 bellard
1274 e95c8d51 bellard
/* sun4m.c */
1275 e0353fe2 blueswir1
extern QEMUMachine ss5_machine, ss10_machine;
1276 e95c8d51 bellard
1277 e95c8d51 bellard
/* iommu.c */
1278 5dcb6b91 blueswir1
void *iommu_init(target_phys_addr_t addr);
1279 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1280 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1281 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1282 67e999be bellard
                                           target_phys_addr_t addr,
1283 67e999be bellard
                                           uint8_t *buf, int len)
1284 67e999be bellard
{
1285 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1286 67e999be bellard
}
1287 e95c8d51 bellard
1288 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1289 67e999be bellard
                                            target_phys_addr_t addr,
1290 67e999be bellard
                                            uint8_t *buf, int len)
1291 67e999be bellard
{
1292 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1293 67e999be bellard
}
1294 e95c8d51 bellard
1295 e95c8d51 bellard
/* tcx.c */
1296 5dcb6b91 blueswir1
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1297 5dcb6b91 blueswir1
              unsigned long vram_offset, int vram_size, int width, int height,
1298 eee0b836 blueswir1
              int depth);
1299 e80cfcfc bellard
1300 e80cfcfc bellard
/* slavio_intctl.c */
1301 5dcb6b91 blueswir1
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1302 d537cf6c pbrook
                         const uint32_t *intbit_to_level,
1303 d7edfd27 blueswir1
                         qemu_irq **irq, qemu_irq **cpu_irq,
1304 b3a23197 blueswir1
                         qemu_irq **parent_irq, unsigned int cputimer);
1305 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1306 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1307 e95c8d51 bellard
1308 5fe141fd bellard
/* loader.c */
1309 5fe141fd bellard
int get_image_size(const char *filename);
1310 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1311 74287114 ths
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1312 74287114 ths
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1313 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1314 1c7b3754 pbrook
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1315 e80cfcfc bellard
1316 e80cfcfc bellard
/* slavio_timer.c */
1317 81732d19 blueswir1
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1318 81732d19 blueswir1
                           qemu_irq *cpu_irqs);
1319 8d5f07fa bellard
1320 e80cfcfc bellard
/* slavio_serial.c */
1321 5dcb6b91 blueswir1
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1322 5dcb6b91 blueswir1
                                CharDriverState *chr1, CharDriverState *chr2);
1323 5dcb6b91 blueswir1
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1324 e95c8d51 bellard
1325 3475187d bellard
/* slavio_misc.c */
1326 5dcb6b91 blueswir1
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1327 5dcb6b91 blueswir1
                       qemu_irq irq);
1328 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1329 3475187d bellard
1330 6f7e9aec bellard
/* esp.c */
1331 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1332 5dcb6b91 blueswir1
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1333 2d069bab blueswir1
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1334 67e999be bellard
1335 67e999be bellard
/* sparc32_dma.c */
1336 70c0de96 blueswir1
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1337 2d069bab blueswir1
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1338 5fafdf24 ths
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1339 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1340 5fafdf24 ths
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1341 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1342 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1343 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1344 6f7e9aec bellard
1345 b8174937 bellard
/* cs4231.c */
1346 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1347 b8174937 bellard
1348 3475187d bellard
/* sun4u.c */
1349 3475187d bellard
extern QEMUMachine sun4u_machine;
1350 3475187d bellard
1351 64201201 bellard
/* NVRAM helpers */
1352 3cbee15b j_mayer
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
1353 3cbee15b j_mayer
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
1354 3cbee15b j_mayer
typedef struct nvram_t {
1355 3cbee15b j_mayer
    void *opaque;
1356 3cbee15b j_mayer
    nvram_read_t read_fn;
1357 3cbee15b j_mayer
    nvram_write_t write_fn;
1358 3cbee15b j_mayer
} nvram_t;
1359 3cbee15b j_mayer
1360 64201201 bellard
#include "hw/m48t59.h"
1361 64201201 bellard
1362 3cbee15b j_mayer
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
1363 3cbee15b j_mayer
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
1364 3cbee15b j_mayer
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
1365 3cbee15b j_mayer
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
1366 3cbee15b j_mayer
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
1367 3cbee15b j_mayer
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
1368 3cbee15b j_mayer
void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1369 64201201 bellard
                       const unsigned char *str, uint32_t max);
1370 3cbee15b j_mayer
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
1371 3cbee15b j_mayer
void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
1372 64201201 bellard
                    uint32_t start, uint32_t count);
1373 3cbee15b j_mayer
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1374 64201201 bellard
                          const unsigned char *arch,
1375 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1376 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1377 28b9b5af bellard
                          const char *cmdline,
1378 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1379 28b9b5af bellard
                          uint32_t NVRAM_image,
1380 28b9b5af bellard
                          int width, int height, int depth);
1381 64201201 bellard
1382 63066f4f bellard
/* adb.c */
1383 63066f4f bellard
1384 63066f4f bellard
#define MAX_ADB_DEVICES 16
1385 63066f4f bellard
1386 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1387 63066f4f bellard
1388 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1389 63066f4f bellard
1390 e2733d20 bellard
/* buf = NULL means polling */
1391 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1392 e2733d20 bellard
                              const uint8_t *buf, int len);
1393 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1394 12c28fed bellard
1395 63066f4f bellard
struct ADBDevice {
1396 63066f4f bellard
    struct ADBBusState *bus;
1397 63066f4f bellard
    int devaddr;
1398 63066f4f bellard
    int handler;
1399 e2733d20 bellard
    ADBDeviceRequest *devreq;
1400 12c28fed bellard
    ADBDeviceReset *devreset;
1401 63066f4f bellard
    void *opaque;
1402 63066f4f bellard
};
1403 63066f4f bellard
1404 63066f4f bellard
typedef struct ADBBusState {
1405 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1406 63066f4f bellard
    int nb_devices;
1407 e2733d20 bellard
    int poll_index;
1408 63066f4f bellard
} ADBBusState;
1409 63066f4f bellard
1410 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1411 e2733d20 bellard
                const uint8_t *buf, int len);
1412 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1413 63066f4f bellard
1414 5fafdf24 ths
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1415 5fafdf24 ths
                               ADBDeviceRequest *devreq,
1416 5fafdf24 ths
                               ADBDeviceReset *devreset,
1417 63066f4f bellard
                               void *opaque);
1418 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1419 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1420 63066f4f bellard
1421 63066f4f bellard
extern ADBBusState adb_bus;
1422 63066f4f bellard
1423 bb36d470 bellard
#include "hw/usb.h"
1424 bb36d470 bellard
1425 a594cfbf bellard
/* usb ports of the VM */
1426 a594cfbf bellard
1427 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1428 0d92ed30 pbrook
                            usb_attachfn attach);
1429 a594cfbf bellard
1430 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1431 a594cfbf bellard
1432 a594cfbf bellard
void do_usb_add(const char *devname);
1433 a594cfbf bellard
void do_usb_del(const char *devname);
1434 a594cfbf bellard
void usb_info(void);
1435 a594cfbf bellard
1436 2e5d83bb pbrook
/* scsi-disk.c */
1437 4d611c9a pbrook
enum scsi_reason {
1438 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1439 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1440 4d611c9a pbrook
};
1441 4d611c9a pbrook
1442 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1443 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1444 a917d384 pbrook
                                  uint32_t arg);
1445 2e5d83bb pbrook
1446 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1447 a917d384 pbrook
                           int tcq,
1448 2e5d83bb pbrook
                           scsi_completionfn completion,
1449 2e5d83bb pbrook
                           void *opaque);
1450 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1451 2e5d83bb pbrook
1452 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1453 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1454 4d611c9a pbrook
   layer the completion routine may be called directly by
1455 4d611c9a pbrook
   scsi_{read,write}_data.  */
1456 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1457 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1458 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1459 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1460 2e5d83bb pbrook
1461 7d8406be pbrook
/* lsi53c895a.c */
1462 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1463 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1464 7d8406be pbrook
1465 b5ff1b31 bellard
/* integratorcp.c */
1466 3371d272 pbrook
extern QEMUMachine integratorcp_machine;
1467 b5ff1b31 bellard
1468 cdbdb648 pbrook
/* versatilepb.c */
1469 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1470 16406950 pbrook
extern QEMUMachine versatileab_machine;
1471 cdbdb648 pbrook
1472 e69954b9 pbrook
/* realview.c */
1473 e69954b9 pbrook
extern QEMUMachine realview_machine;
1474 e69954b9 pbrook
1475 b00052e4 balrog
/* spitz.c */
1476 b00052e4 balrog
extern QEMUMachine akitapda_machine;
1477 b00052e4 balrog
extern QEMUMachine spitzpda_machine;
1478 b00052e4 balrog
extern QEMUMachine borzoipda_machine;
1479 b00052e4 balrog
extern QEMUMachine terrierpda_machine;
1480 b00052e4 balrog
1481 c3d2689d balrog
/* palm.c */
1482 c3d2689d balrog
extern QEMUMachine palmte_machine;
1483 c3d2689d balrog
1484 daa57963 bellard
/* ps2.c */
1485 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1486 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1487 daa57963 bellard
void ps2_write_mouse(void *, int val);
1488 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1489 daa57963 bellard
uint32_t ps2_read_data(void *);
1490 daa57963 bellard
void ps2_queue(void *, int b);
1491 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1492 548df2ac ths
void ps2_mouse_fake_event(void *opaque);
1493 daa57963 bellard
1494 80337b66 bellard
/* smc91c111.c */
1495 d537cf6c pbrook
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1496 80337b66 bellard
1497 7e1543c2 pbrook
/* pl031.c */
1498 7e1543c2 pbrook
void pl031_init(uint32_t base, qemu_irq irq);
1499 7e1543c2 pbrook
1500 bdd5003a pbrook
/* pl110.c */
1501 d537cf6c pbrook
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1502 bdd5003a pbrook
1503 cdbdb648 pbrook
/* pl011.c */
1504 d537cf6c pbrook
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1505 cdbdb648 pbrook
1506 cdbdb648 pbrook
/* pl050.c */
1507 d537cf6c pbrook
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1508 cdbdb648 pbrook
1509 cdbdb648 pbrook
/* pl080.c */
1510 d537cf6c pbrook
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1511 cdbdb648 pbrook
1512 a1bb27b1 pbrook
/* pl181.c */
1513 a1bb27b1 pbrook
void pl181_init(uint32_t base, BlockDriverState *bd,
1514 d537cf6c pbrook
                qemu_irq irq0, qemu_irq irq1);
1515 a1bb27b1 pbrook
1516 cdbdb648 pbrook
/* pl190.c */
1517 d537cf6c pbrook
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1518 cdbdb648 pbrook
1519 cdbdb648 pbrook
/* arm-timer.c */
1520 d537cf6c pbrook
void sp804_init(uint32_t base, qemu_irq irq);
1521 d537cf6c pbrook
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1522 cdbdb648 pbrook
1523 e69954b9 pbrook
/* arm_sysctl.c */
1524 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1525 e69954b9 pbrook
1526 e69954b9 pbrook
/* arm_gic.c */
1527 d537cf6c pbrook
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1528 e69954b9 pbrook
1529 16406950 pbrook
/* arm_boot.c */
1530 16406950 pbrook
1531 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1532 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1533 9d551997 balrog
                     int board_id, target_phys_addr_t loader_start);
1534 16406950 pbrook
1535 27c7ca7e bellard
/* sh7750.c */
1536 27c7ca7e bellard
struct SH7750State;
1537 27c7ca7e bellard
1538 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1539 27c7ca7e bellard
1540 27c7ca7e bellard
typedef struct {
1541 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1542 27c7ca7e bellard
    uint16_t portamask_trigger;
1543 27c7ca7e bellard
    uint16_t portbmask_trigger;
1544 27c7ca7e bellard
    /* Return 0 if no action was taken */
1545 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1546 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1547 27c7ca7e bellard
                           uint16_t * periph_portdira,
1548 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1549 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1550 27c7ca7e bellard
} sh7750_io_device;
1551 27c7ca7e bellard
1552 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1553 27c7ca7e bellard
                              sh7750_io_device * device);
1554 cd1a3f68 ths
/* sh_timer.c */
1555 cd1a3f68 ths
#define TMU012_FEAT_TOCR   (1 << 0)
1556 cd1a3f68 ths
#define TMU012_FEAT_3CHAN  (1 << 1)
1557 cd1a3f68 ths
#define TMU012_FEAT_EXTCLK (1 << 2)
1558 cd1a3f68 ths
void tmu012_init(uint32_t base, int feat, uint32_t freq);
1559 cd1a3f68 ths
1560 2f062c72 ths
/* sh_serial.c */
1561 2f062c72 ths
#define SH_SERIAL_FEAT_SCIF (1 << 0)
1562 2f062c72 ths
void sh_serial_init (target_phys_addr_t base, int feat,
1563 2f062c72 ths
                     uint32_t freq, CharDriverState *chr);
1564 2f062c72 ths
1565 27c7ca7e bellard
/* tc58128.c */
1566 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1567 27c7ca7e bellard
1568 29133e9a bellard
/* NOR flash devices */
1569 86f55663 j_mayer
#define MAX_PFLASH 4
1570 86f55663 j_mayer
extern BlockDriverState *pflash_table[MAX_PFLASH];
1571 29133e9a bellard
typedef struct pflash_t pflash_t;
1572 29133e9a bellard
1573 71db710f blueswir1
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1574 29133e9a bellard
                           BlockDriverState *bs,
1575 71db710f blueswir1
                           uint32_t sector_len, int nb_blocs, int width,
1576 5fafdf24 ths
                           uint16_t id0, uint16_t id1,
1577 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1578 29133e9a bellard
1579 3e3d5815 balrog
/* nand.c */
1580 3e3d5815 balrog
struct nand_flash_s;
1581 3e3d5815 balrog
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1582 3e3d5815 balrog
void nand_done(struct nand_flash_s *s);
1583 5fafdf24 ths
void nand_setpins(struct nand_flash_s *s,
1584 3e3d5815 balrog
                int cle, int ale, int ce, int wp, int gnd);
1585 3e3d5815 balrog
void nand_getpins(struct nand_flash_s *s, int *rb);
1586 3e3d5815 balrog
void nand_setio(struct nand_flash_s *s, uint8_t value);
1587 3e3d5815 balrog
uint8_t nand_getio(struct nand_flash_s *s);
1588 3e3d5815 balrog
1589 3e3d5815 balrog
#define NAND_MFR_TOSHIBA        0x98
1590 3e3d5815 balrog
#define NAND_MFR_SAMSUNG        0xec
1591 3e3d5815 balrog
#define NAND_MFR_FUJITSU        0x04
1592 3e3d5815 balrog
#define NAND_MFR_NATIONAL        0x8f
1593 3e3d5815 balrog
#define NAND_MFR_RENESAS        0x07
1594 3e3d5815 balrog
#define NAND_MFR_STMICRO        0x20
1595 3e3d5815 balrog
#define NAND_MFR_HYNIX                0xad
1596 3e3d5815 balrog
#define NAND_MFR_MICRON                0x2c
1597 3e3d5815 balrog
1598 9ff6755b balrog
/* ecc.c */
1599 9ff6755b balrog
struct ecc_state_s {
1600 9ff6755b balrog
    uint8_t cp;                /* Column parity */
1601 9ff6755b balrog
    uint16_t lp[2];        /* Line parity */
1602 9ff6755b balrog
    uint16_t count;
1603 9ff6755b balrog
};
1604 9ff6755b balrog
1605 9ff6755b balrog
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1606 9ff6755b balrog
void ecc_reset(struct ecc_state_s *s);
1607 9ff6755b balrog
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1608 9ff6755b balrog
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1609 3e3d5815 balrog
1610 2a1d1880 balrog
/* GPIO */
1611 2a1d1880 balrog
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1612 2a1d1880 balrog
1613 fd5a3b33 balrog
/* ads7846.c */
1614 fd5a3b33 balrog
struct ads7846_state_s;
1615 fd5a3b33 balrog
uint32_t ads7846_read(void *opaque);
1616 fd5a3b33 balrog
void ads7846_write(void *opaque, uint32_t value);
1617 fd5a3b33 balrog
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1618 fd5a3b33 balrog
1619 c824cacd balrog
/* max111x.c */
1620 c824cacd balrog
struct max111x_s;
1621 c824cacd balrog
uint32_t max111x_read(void *opaque);
1622 c824cacd balrog
void max111x_write(void *opaque, uint32_t value);
1623 c824cacd balrog
struct max111x_s *max1110_init(qemu_irq cb);
1624 c824cacd balrog
struct max111x_s *max1111_init(qemu_irq cb);
1625 c824cacd balrog
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1626 c824cacd balrog
1627 201a51fc balrog
/* PCMCIA/Cardbus */
1628 201a51fc balrog
1629 201a51fc balrog
struct pcmcia_socket_s {
1630 201a51fc balrog
    qemu_irq irq;
1631 201a51fc balrog
    int attached;
1632 201a51fc balrog
    const char *slot_string;
1633 201a51fc balrog
    const char *card_string;
1634 201a51fc balrog
};
1635 201a51fc balrog
1636 201a51fc balrog
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1637 201a51fc balrog
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1638 201a51fc balrog
void pcmcia_info(void);
1639 201a51fc balrog
1640 201a51fc balrog
struct pcmcia_card_s {
1641 201a51fc balrog
    void *state;
1642 201a51fc balrog
    struct pcmcia_socket_s *slot;
1643 201a51fc balrog
    int (*attach)(void *state);
1644 201a51fc balrog
    int (*detach)(void *state);
1645 201a51fc balrog
    const uint8_t *cis;
1646 201a51fc balrog
    int cis_len;
1647 201a51fc balrog
1648 201a51fc balrog
    /* Only valid if attached */
1649 9e315fa9 balrog
    uint8_t (*attr_read)(void *state, uint32_t address);
1650 9e315fa9 balrog
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1651 9e315fa9 balrog
    uint16_t (*common_read)(void *state, uint32_t address);
1652 9e315fa9 balrog
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1653 9e315fa9 balrog
    uint16_t (*io_read)(void *state, uint32_t address);
1654 9e315fa9 balrog
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1655 201a51fc balrog
};
1656 201a51fc balrog
1657 201a51fc balrog
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1658 201a51fc balrog
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1659 201a51fc balrog
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1660 201a51fc balrog
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1661 201a51fc balrog
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1662 201a51fc balrog
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1663 201a51fc balrog
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1664 201a51fc balrog
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1665 201a51fc balrog
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1666 201a51fc balrog
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1667 201a51fc balrog
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1668 201a51fc balrog
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1669 201a51fc balrog
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1670 201a51fc balrog
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1671 201a51fc balrog
#define CISTPL_END                0xff        /* Tuple End */
1672 201a51fc balrog
#define CISTPL_ENDMARK                0xff
1673 201a51fc balrog
1674 201a51fc balrog
/* dscm1xxxx.c */
1675 201a51fc balrog
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1676 201a51fc balrog
1677 6963d7af pbrook
/* ptimer.c */
1678 6963d7af pbrook
typedef struct ptimer_state ptimer_state;
1679 6963d7af pbrook
typedef void (*ptimer_cb)(void *opaque);
1680 6963d7af pbrook
1681 6963d7af pbrook
ptimer_state *ptimer_init(QEMUBH *bh);
1682 6963d7af pbrook
void ptimer_set_period(ptimer_state *s, int64_t period);
1683 6963d7af pbrook
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1684 8d05ea8a blueswir1
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1685 8d05ea8a blueswir1
uint64_t ptimer_get_count(ptimer_state *s);
1686 8d05ea8a blueswir1
void ptimer_set_count(ptimer_state *s, uint64_t count);
1687 6963d7af pbrook
void ptimer_run(ptimer_state *s, int oneshot);
1688 6963d7af pbrook
void ptimer_stop(ptimer_state *s);
1689 8d05ea8a blueswir1
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1690 8d05ea8a blueswir1
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1691 6963d7af pbrook
1692 c1713132 balrog
#include "hw/pxa.h"
1693 c1713132 balrog
1694 c3d2689d balrog
#include "hw/omap.h"
1695 c3d2689d balrog
1696 3efda49d balrog
/* tsc210x.c */
1697 d8f699cb balrog
struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
1698 d8f699cb balrog
struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
1699 3efda49d balrog
1700 20dcee94 pbrook
/* mcf_uart.c */
1701 20dcee94 pbrook
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1702 20dcee94 pbrook
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1703 20dcee94 pbrook
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1704 20dcee94 pbrook
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1705 20dcee94 pbrook
                      CharDriverState *chr);
1706 20dcee94 pbrook
1707 20dcee94 pbrook
/* mcf_intc.c */
1708 20dcee94 pbrook
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1709 20dcee94 pbrook
1710 7e049b8a pbrook
/* mcf_fec.c */
1711 7e049b8a pbrook
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1712 7e049b8a pbrook
1713 0633879f pbrook
/* mcf5206.c */
1714 0633879f pbrook
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1715 0633879f pbrook
1716 0633879f pbrook
/* an5206.c */
1717 0633879f pbrook
extern QEMUMachine an5206_machine;
1718 0633879f pbrook
1719 20dcee94 pbrook
/* mcf5208.c */
1720 20dcee94 pbrook
extern QEMUMachine mcf5208evb_machine;
1721 20dcee94 pbrook
1722 4046d913 pbrook
#include "gdbstub.h"
1723 4046d913 pbrook
1724 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1725 fc01f7e7 bellard
#endif /* VL_H */