Statistics
| Branch: | Revision:

root / vl.h @ 2a324a26

History | View | Annotate | Download (55.4 kB)

1
/*
2
 * QEMU System Emulator header
3
 *
4
 * Copyright (c) 2003 Fabrice Bellard
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24
#ifndef VL_H
25
#define VL_H
26

    
27
/* we put basic includes here to avoid repeating them in device drivers */
28
#include <stdlib.h>
29
#include <stdio.h>
30
#include <stdarg.h>
31
#include <string.h>
32
#include <inttypes.h>
33
#include <limits.h>
34
#include <time.h>
35
#include <ctype.h>
36
#include <errno.h>
37
#include <unistd.h>
38
#include <fcntl.h>
39
#include <sys/stat.h>
40

    
41
#ifndef O_LARGEFILE
42
#define O_LARGEFILE 0
43
#endif
44
#ifndef O_BINARY
45
#define O_BINARY 0
46
#endif
47

    
48
#ifndef ENOMEDIUM
49
#define ENOMEDIUM ENODEV
50
#endif
51

    
52
#ifdef _WIN32
53
#include <windows.h>
54
#define fsync _commit
55
#define lseek _lseeki64
56
#define ENOTSUP 4096
57
extern int qemu_ftruncate64(int, int64_t);
58
#define ftruncate qemu_ftruncate64
59

    
60

    
61
static inline char *realpath(const char *path, char *resolved_path)
62
{
63
    _fullpath(resolved_path, path, _MAX_PATH);
64
    return resolved_path;
65
}
66

    
67
#define PRId64 "I64d"
68
#define PRIx64 "I64x"
69
#define PRIu64 "I64u"
70
#define PRIo64 "I64o"
71
#endif
72

    
73
#ifdef QEMU_TOOL
74

    
75
/* we use QEMU_TOOL on code which does not depend on the target CPU
76
   type */
77
#include "config-host.h"
78
#include <setjmp.h>
79
#include "osdep.h"
80
#include "bswap.h"
81

    
82
#else
83

    
84
#include "cpu.h"
85

    
86
#endif /* !defined(QEMU_TOOL) */
87

    
88
#ifndef glue
89
#define xglue(x, y) x ## y
90
#define glue(x, y) xglue(x, y)
91
#define stringify(s)        tostring(s)
92
#define tostring(s)        #s
93
#endif
94

    
95
#ifndef likely
96
#if __GNUC__ < 3
97
#define __builtin_expect(x, n) (x)
98
#endif
99

    
100
#define likely(x)   __builtin_expect(!!(x), 1)
101
#define unlikely(x)   __builtin_expect(!!(x), 0)
102
#endif
103

    
104
#ifndef MIN
105
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
106
#endif
107
#ifndef MAX
108
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
109
#endif
110

    
111
#ifndef always_inline
112
#if (__GNUC__ < 3) || defined(__APPLE__)
113
#define always_inline inline
114
#else
115
#define always_inline __attribute__ (( always_inline )) inline
116
#endif
117
#endif
118

    
119
#include "audio/audio.h"
120

    
121
/* cutils.c */
122
void pstrcpy(char *buf, int buf_size, const char *str);
123
char *pstrcat(char *buf, int buf_size, const char *s);
124
int strstart(const char *str, const char *val, const char **ptr);
125
int stristart(const char *str, const char *val, const char **ptr);
126

    
127
/* vl.c */
128
uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
129

    
130
void hw_error(const char *fmt, ...);
131

    
132
extern const char *bios_dir;
133
extern const char *bios_name;
134

    
135
extern int vm_running;
136
extern const char *qemu_name;
137

    
138
typedef struct vm_change_state_entry VMChangeStateEntry;
139
typedef void VMChangeStateHandler(void *opaque, int running);
140
typedef void VMStopHandler(void *opaque, int reason);
141

    
142
VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
143
                                                     void *opaque);
144
void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
145

    
146
int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
147
void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
148

    
149
void vm_start(void);
150
void vm_stop(int reason);
151

    
152
typedef void QEMUResetHandler(void *opaque);
153

    
154
void qemu_register_reset(QEMUResetHandler *func, void *opaque);
155
void qemu_system_reset_request(void);
156
void qemu_system_shutdown_request(void);
157
void qemu_system_powerdown_request(void);
158
#if !defined(TARGET_SPARC)
159
// Please implement a power failure function to signal the OS
160
#define qemu_system_powerdown() do{}while(0)
161
#else
162
void qemu_system_powerdown(void);
163
#endif
164

    
165
void main_loop_wait(int timeout);
166

    
167
extern int ram_size;
168
extern int bios_size;
169
extern int rtc_utc;
170
extern int rtc_start_date;
171
extern int cirrus_vga_enabled;
172
extern int vmsvga_enabled;
173
extern int graphic_width;
174
extern int graphic_height;
175
extern int graphic_depth;
176
extern const char *keyboard_layout;
177
extern int kqemu_allowed;
178
extern int win2k_install_hack;
179
extern int alt_grab;
180
extern int usb_enabled;
181
extern int smp_cpus;
182
extern int cursor_hide;
183
extern int graphic_rotate;
184
extern int no_quit;
185
extern int semihosting_enabled;
186
extern int autostart;
187
extern int old_param;
188
extern const char *bootp_filename;
189

    
190
#define MAX_OPTION_ROMS 16
191
extern const char *option_rom[MAX_OPTION_ROMS];
192
extern int nb_option_roms;
193

    
194
#ifdef TARGET_SPARC
195
#define MAX_PROM_ENVS 128
196
extern const char *prom_envs[MAX_PROM_ENVS];
197
extern unsigned int nb_prom_envs;
198
#endif
199

    
200
/* XXX: make it dynamic */
201
#define MAX_BIOS_SIZE (4 * 1024 * 1024)
202
#if defined (TARGET_PPC)
203
#define BIOS_SIZE (1024 * 1024)
204
#elif defined (TARGET_SPARC64)
205
#define BIOS_SIZE ((512 + 32) * 1024)
206
#elif defined(TARGET_MIPS)
207
#define BIOS_SIZE (4 * 1024 * 1024)
208
#endif
209

    
210
/* keyboard/mouse support */
211

    
212
#define MOUSE_EVENT_LBUTTON 0x01
213
#define MOUSE_EVENT_RBUTTON 0x02
214
#define MOUSE_EVENT_MBUTTON 0x04
215

    
216
typedef void QEMUPutKBDEvent(void *opaque, int keycode);
217
typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
218

    
219
typedef struct QEMUPutMouseEntry {
220
    QEMUPutMouseEvent *qemu_put_mouse_event;
221
    void *qemu_put_mouse_event_opaque;
222
    int qemu_put_mouse_event_absolute;
223
    char *qemu_put_mouse_event_name;
224

    
225
    /* used internally by qemu for handling mice */
226
    struct QEMUPutMouseEntry *next;
227
} QEMUPutMouseEntry;
228

    
229
void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
230
QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
231
                                                void *opaque, int absolute,
232
                                                const char *name);
233
void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
234

    
235
void kbd_put_keycode(int keycode);
236
void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
237
int kbd_mouse_is_absolute(void);
238

    
239
void do_info_mice(void);
240
void do_mouse_set(int index);
241

    
242
/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
243
   constants) */
244
#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
245
#define QEMU_KEY_BACKSPACE  0x007f
246
#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
247
#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
248
#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
249
#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
250
#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
251
#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
252
#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
253
#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
254
#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
255

    
256
#define QEMU_KEY_CTRL_UP         0xe400
257
#define QEMU_KEY_CTRL_DOWN       0xe401
258
#define QEMU_KEY_CTRL_LEFT       0xe402
259
#define QEMU_KEY_CTRL_RIGHT      0xe403
260
#define QEMU_KEY_CTRL_HOME       0xe404
261
#define QEMU_KEY_CTRL_END        0xe405
262
#define QEMU_KEY_CTRL_PAGEUP     0xe406
263
#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
264

    
265
void kbd_put_keysym(int keysym);
266

    
267
/* async I/O support */
268

    
269
typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
270
typedef int IOCanRWHandler(void *opaque);
271
typedef void IOHandler(void *opaque);
272

    
273
int qemu_set_fd_handler2(int fd,
274
                         IOCanRWHandler *fd_read_poll,
275
                         IOHandler *fd_read,
276
                         IOHandler *fd_write,
277
                         void *opaque);
278
int qemu_set_fd_handler(int fd,
279
                        IOHandler *fd_read,
280
                        IOHandler *fd_write,
281
                        void *opaque);
282

    
283
/* Polling handling */
284

    
285
/* return TRUE if no sleep should be done afterwards */
286
typedef int PollingFunc(void *opaque);
287

    
288
int qemu_add_polling_cb(PollingFunc *func, void *opaque);
289
void qemu_del_polling_cb(PollingFunc *func, void *opaque);
290

    
291
#ifdef _WIN32
292
/* Wait objects handling */
293
typedef void WaitObjectFunc(void *opaque);
294

    
295
int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
296
void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
297
#endif
298

    
299
typedef struct QEMUBH QEMUBH;
300

    
301
/* character device */
302

    
303
#define CHR_EVENT_BREAK 0 /* serial break char */
304
#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
305
#define CHR_EVENT_RESET 2 /* new connection established */
306

    
307

    
308
#define CHR_IOCTL_SERIAL_SET_PARAMS   1
309
typedef struct {
310
    int speed;
311
    int parity;
312
    int data_bits;
313
    int stop_bits;
314
} QEMUSerialSetParams;
315

    
316
#define CHR_IOCTL_SERIAL_SET_BREAK    2
317

    
318
#define CHR_IOCTL_PP_READ_DATA        3
319
#define CHR_IOCTL_PP_WRITE_DATA       4
320
#define CHR_IOCTL_PP_READ_CONTROL     5
321
#define CHR_IOCTL_PP_WRITE_CONTROL    6
322
#define CHR_IOCTL_PP_READ_STATUS      7
323
#define CHR_IOCTL_PP_EPP_READ_ADDR    8
324
#define CHR_IOCTL_PP_EPP_READ         9
325
#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
326
#define CHR_IOCTL_PP_EPP_WRITE       11
327

    
328
typedef void IOEventHandler(void *opaque, int event);
329

    
330
typedef struct CharDriverState {
331
    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
332
    void (*chr_update_read_handler)(struct CharDriverState *s);
333
    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
334
    IOEventHandler *chr_event;
335
    IOCanRWHandler *chr_can_read;
336
    IOReadHandler *chr_read;
337
    void *handler_opaque;
338
    void (*chr_send_event)(struct CharDriverState *chr, int event);
339
    void (*chr_close)(struct CharDriverState *chr);
340
    void *opaque;
341
    int focus;
342
    QEMUBH *bh;
343
} CharDriverState;
344

    
345
CharDriverState *qemu_chr_open(const char *filename);
346
void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
347
int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
348
void qemu_chr_send_event(CharDriverState *s, int event);
349
void qemu_chr_add_handlers(CharDriverState *s,
350
                           IOCanRWHandler *fd_can_read,
351
                           IOReadHandler *fd_read,
352
                           IOEventHandler *fd_event,
353
                           void *opaque);
354
int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
355
void qemu_chr_reset(CharDriverState *s);
356
int qemu_chr_can_read(CharDriverState *s);
357
void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
358

    
359
/* consoles */
360

    
361
typedef struct DisplayState DisplayState;
362
typedef struct TextConsole TextConsole;
363

    
364
struct DisplayState {
365
    uint8_t *data;
366
    int linesize;
367
    int depth;
368
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
369
    int width;
370
    int height;
371
    void *opaque;
372
    struct QEMUTimer *gui_timer;
373

    
374
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
375
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
376
    void (*dpy_refresh)(struct DisplayState *s);
377
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
378
                     int dst_x, int dst_y, int w, int h);
379
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
380
                     int w, int h, uint32_t c);
381
    void (*mouse_set)(int x, int y, int on);
382
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
383
                          uint8_t *image, uint8_t *mask);
384
};
385

    
386
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
387
{
388
    s->dpy_update(s, x, y, w, h);
389
}
390

    
391
static inline void dpy_resize(DisplayState *s, int w, int h)
392
{
393
    s->dpy_resize(s, w, h);
394
}
395

    
396
typedef void (*vga_hw_update_ptr)(void *);
397
typedef void (*vga_hw_invalidate_ptr)(void *);
398
typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
399

    
400
TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
401
                                  vga_hw_invalidate_ptr invalidate,
402
                                  vga_hw_screen_dump_ptr screen_dump,
403
                                  void *opaque);
404
void vga_hw_update(void);
405
void vga_hw_invalidate(void);
406
void vga_hw_screen_dump(const char *filename);
407

    
408
int is_graphic_console(void);
409
CharDriverState *text_console_init(DisplayState *ds, const char *p);
410
void console_select(unsigned int index);
411
void console_color_init(DisplayState *ds);
412

    
413
/* serial ports */
414

    
415
#define MAX_SERIAL_PORTS 4
416

    
417
extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
418

    
419
/* parallel ports */
420

    
421
#define MAX_PARALLEL_PORTS 3
422

    
423
extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
424

    
425
struct ParallelIOArg {
426
    void *buffer;
427
    int count;
428
};
429

    
430
/* VLANs support */
431

    
432
typedef struct VLANClientState VLANClientState;
433

    
434
struct VLANClientState {
435
    IOReadHandler *fd_read;
436
    /* Packets may still be sent if this returns zero.  It's used to
437
       rate-limit the slirp code.  */
438
    IOCanRWHandler *fd_can_read;
439
    void *opaque;
440
    struct VLANClientState *next;
441
    struct VLANState *vlan;
442
    char info_str[256];
443
};
444

    
445
typedef struct VLANState {
446
    int id;
447
    VLANClientState *first_client;
448
    struct VLANState *next;
449
    unsigned int nb_guest_devs, nb_host_devs;
450
} VLANState;
451

    
452
VLANState *qemu_find_vlan(int id);
453
VLANClientState *qemu_new_vlan_client(VLANState *vlan,
454
                                      IOReadHandler *fd_read,
455
                                      IOCanRWHandler *fd_can_read,
456
                                      void *opaque);
457
int qemu_can_send_packet(VLANClientState *vc);
458
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
459
void qemu_handler_true(void *opaque);
460

    
461
void do_info_network(void);
462

    
463
/* TAP win32 */
464
int tap_win32_init(VLANState *vlan, const char *ifname);
465

    
466
/* NIC info */
467

    
468
#define MAX_NICS 8
469

    
470
typedef struct NICInfo {
471
    uint8_t macaddr[6];
472
    const char *model;
473
    VLANState *vlan;
474
} NICInfo;
475

    
476
extern int nb_nics;
477
extern NICInfo nd_table[MAX_NICS];
478

    
479
/* SLIRP */
480
void do_info_slirp(void);
481

    
482
/* timers */
483

    
484
typedef struct QEMUClock QEMUClock;
485
typedef struct QEMUTimer QEMUTimer;
486
typedef void QEMUTimerCB(void *opaque);
487

    
488
/* The real time clock should be used only for stuff which does not
489
   change the virtual machine state, as it is run even if the virtual
490
   machine is stopped. The real time clock has a frequency of 1000
491
   Hz. */
492
extern QEMUClock *rt_clock;
493

    
494
/* The virtual clock is only run during the emulation. It is stopped
495
   when the virtual machine is stopped. Virtual timers use a high
496
   precision clock, usually cpu cycles (use ticks_per_sec). */
497
extern QEMUClock *vm_clock;
498

    
499
int64_t qemu_get_clock(QEMUClock *clock);
500

    
501
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
502
void qemu_free_timer(QEMUTimer *ts);
503
void qemu_del_timer(QEMUTimer *ts);
504
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
505
int qemu_timer_pending(QEMUTimer *ts);
506

    
507
extern int64_t ticks_per_sec;
508

    
509
int64_t cpu_get_ticks(void);
510
void cpu_enable_ticks(void);
511
void cpu_disable_ticks(void);
512

    
513
/* VM Load/Save */
514

    
515
typedef struct QEMUFile QEMUFile;
516

    
517
QEMUFile *qemu_fopen(const char *filename, const char *mode);
518
void qemu_fflush(QEMUFile *f);
519
void qemu_fclose(QEMUFile *f);
520
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
521
void qemu_put_byte(QEMUFile *f, int v);
522
void qemu_put_be16(QEMUFile *f, unsigned int v);
523
void qemu_put_be32(QEMUFile *f, unsigned int v);
524
void qemu_put_be64(QEMUFile *f, uint64_t v);
525
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
526
int qemu_get_byte(QEMUFile *f);
527
unsigned int qemu_get_be16(QEMUFile *f);
528
unsigned int qemu_get_be32(QEMUFile *f);
529
uint64_t qemu_get_be64(QEMUFile *f);
530

    
531
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
532
{
533
    qemu_put_be64(f, *pv);
534
}
535

    
536
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
537
{
538
    qemu_put_be32(f, *pv);
539
}
540

    
541
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
542
{
543
    qemu_put_be16(f, *pv);
544
}
545

    
546
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
547
{
548
    qemu_put_byte(f, *pv);
549
}
550

    
551
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
552
{
553
    *pv = qemu_get_be64(f);
554
}
555

    
556
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
557
{
558
    *pv = qemu_get_be32(f);
559
}
560

    
561
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
562
{
563
    *pv = qemu_get_be16(f);
564
}
565

    
566
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
567
{
568
    *pv = qemu_get_byte(f);
569
}
570

    
571
#if TARGET_LONG_BITS == 64
572
#define qemu_put_betl qemu_put_be64
573
#define qemu_get_betl qemu_get_be64
574
#define qemu_put_betls qemu_put_be64s
575
#define qemu_get_betls qemu_get_be64s
576
#else
577
#define qemu_put_betl qemu_put_be32
578
#define qemu_get_betl qemu_get_be32
579
#define qemu_put_betls qemu_put_be32s
580
#define qemu_get_betls qemu_get_be32s
581
#endif
582

    
583
int64_t qemu_ftell(QEMUFile *f);
584
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
585

    
586
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
587
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
588

    
589
int register_savevm(const char *idstr,
590
                    int instance_id,
591
                    int version_id,
592
                    SaveStateHandler *save_state,
593
                    LoadStateHandler *load_state,
594
                    void *opaque);
595
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
596
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
597

    
598
void cpu_save(QEMUFile *f, void *opaque);
599
int cpu_load(QEMUFile *f, void *opaque, int version_id);
600

    
601
void do_savevm(const char *name);
602
void do_loadvm(const char *name);
603
void do_delvm(const char *name);
604
void do_info_snapshots(void);
605

    
606
/* bottom halves */
607
typedef void QEMUBHFunc(void *opaque);
608

    
609
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
610
void qemu_bh_schedule(QEMUBH *bh);
611
void qemu_bh_cancel(QEMUBH *bh);
612
void qemu_bh_delete(QEMUBH *bh);
613
int qemu_bh_poll(void);
614

    
615
/* block.c */
616
typedef struct BlockDriverState BlockDriverState;
617
typedef struct BlockDriver BlockDriver;
618

    
619
extern BlockDriver bdrv_raw;
620
extern BlockDriver bdrv_host_device;
621
extern BlockDriver bdrv_cow;
622
extern BlockDriver bdrv_qcow;
623
extern BlockDriver bdrv_vmdk;
624
extern BlockDriver bdrv_cloop;
625
extern BlockDriver bdrv_dmg;
626
extern BlockDriver bdrv_bochs;
627
extern BlockDriver bdrv_vpc;
628
extern BlockDriver bdrv_vvfat;
629
extern BlockDriver bdrv_qcow2;
630
extern BlockDriver bdrv_parallels;
631

    
632
typedef struct BlockDriverInfo {
633
    /* in bytes, 0 if irrelevant */
634
    int cluster_size;
635
    /* offset at which the VM state can be saved (0 if not possible) */
636
    int64_t vm_state_offset;
637
} BlockDriverInfo;
638

    
639
typedef struct QEMUSnapshotInfo {
640
    char id_str[128]; /* unique snapshot id */
641
    /* the following fields are informative. They are not needed for
642
       the consistency of the snapshot */
643
    char name[256]; /* user choosen name */
644
    uint32_t vm_state_size; /* VM state info size */
645
    uint32_t date_sec; /* UTC date of the snapshot */
646
    uint32_t date_nsec;
647
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
648
} QEMUSnapshotInfo;
649

    
650
#define BDRV_O_RDONLY      0x0000
651
#define BDRV_O_RDWR        0x0002
652
#define BDRV_O_ACCESS      0x0003
653
#define BDRV_O_CREAT       0x0004 /* create an empty file */
654
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
655
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
656
                                     use a disk image format on top of
657
                                     it (default for
658
                                     bdrv_file_open()) */
659

    
660
void bdrv_init(void);
661
BlockDriver *bdrv_find_format(const char *format_name);
662
int bdrv_create(BlockDriver *drv,
663
                const char *filename, int64_t size_in_sectors,
664
                const char *backing_file, int flags);
665
BlockDriverState *bdrv_new(const char *device_name);
666
void bdrv_delete(BlockDriverState *bs);
667
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
668
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
669
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
670
               BlockDriver *drv);
671
void bdrv_close(BlockDriverState *bs);
672
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
673
              uint8_t *buf, int nb_sectors);
674
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
675
               const uint8_t *buf, int nb_sectors);
676
int bdrv_pread(BlockDriverState *bs, int64_t offset,
677
               void *buf, int count);
678
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
679
                const void *buf, int count);
680
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
681
int64_t bdrv_getlength(BlockDriverState *bs);
682
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
683
int bdrv_commit(BlockDriverState *bs);
684
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
685
/* async block I/O */
686
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
687
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
688

    
689
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
690
                                uint8_t *buf, int nb_sectors,
691
                                BlockDriverCompletionFunc *cb, void *opaque);
692
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
693
                                 const uint8_t *buf, int nb_sectors,
694
                                 BlockDriverCompletionFunc *cb, void *opaque);
695
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
696

    
697
void qemu_aio_init(void);
698
void qemu_aio_poll(void);
699
void qemu_aio_flush(void);
700
void qemu_aio_wait_start(void);
701
void qemu_aio_wait(void);
702
void qemu_aio_wait_end(void);
703

    
704
int qemu_key_check(BlockDriverState *bs, const char *name);
705

    
706
/* Ensure contents are flushed to disk.  */
707
void bdrv_flush(BlockDriverState *bs);
708

    
709
#define BDRV_TYPE_HD     0
710
#define BDRV_TYPE_CDROM  1
711
#define BDRV_TYPE_FLOPPY 2
712
#define BIOS_ATA_TRANSLATION_AUTO   0
713
#define BIOS_ATA_TRANSLATION_NONE   1
714
#define BIOS_ATA_TRANSLATION_LBA    2
715
#define BIOS_ATA_TRANSLATION_LARGE  3
716
#define BIOS_ATA_TRANSLATION_RECHS  4
717

    
718
void bdrv_set_geometry_hint(BlockDriverState *bs,
719
                            int cyls, int heads, int secs);
720
void bdrv_set_type_hint(BlockDriverState *bs, int type);
721
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
722
void bdrv_get_geometry_hint(BlockDriverState *bs,
723
                            int *pcyls, int *pheads, int *psecs);
724
int bdrv_get_type_hint(BlockDriverState *bs);
725
int bdrv_get_translation_hint(BlockDriverState *bs);
726
int bdrv_is_removable(BlockDriverState *bs);
727
int bdrv_is_read_only(BlockDriverState *bs);
728
int bdrv_is_inserted(BlockDriverState *bs);
729
int bdrv_media_changed(BlockDriverState *bs);
730
int bdrv_is_locked(BlockDriverState *bs);
731
void bdrv_set_locked(BlockDriverState *bs, int locked);
732
void bdrv_eject(BlockDriverState *bs, int eject_flag);
733
void bdrv_set_change_cb(BlockDriverState *bs,
734
                        void (*change_cb)(void *opaque), void *opaque);
735
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
736
void bdrv_info(void);
737
BlockDriverState *bdrv_find(const char *name);
738
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
739
int bdrv_is_encrypted(BlockDriverState *bs);
740
int bdrv_set_key(BlockDriverState *bs, const char *key);
741
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
742
                         void *opaque);
743
const char *bdrv_get_device_name(BlockDriverState *bs);
744
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
745
                          const uint8_t *buf, int nb_sectors);
746
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
747

    
748
void bdrv_get_backing_filename(BlockDriverState *bs,
749
                               char *filename, int filename_size);
750
int bdrv_snapshot_create(BlockDriverState *bs,
751
                         QEMUSnapshotInfo *sn_info);
752
int bdrv_snapshot_goto(BlockDriverState *bs,
753
                       const char *snapshot_id);
754
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
755
int bdrv_snapshot_list(BlockDriverState *bs,
756
                       QEMUSnapshotInfo **psn_info);
757
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
758

    
759
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
760
int path_is_absolute(const char *path);
761
void path_combine(char *dest, int dest_size,
762
                  const char *base_path,
763
                  const char *filename);
764

    
765

    
766
/* monitor.c */
767
void monitor_init(CharDriverState *hd, int show_banner);
768
void term_puts(const char *str);
769
void term_vprintf(const char *fmt, va_list ap);
770
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
771
void term_print_filename(const char *filename);
772
void term_flush(void);
773
void term_print_help(void);
774
void monitor_readline(const char *prompt, int is_password,
775
                      char *buf, int buf_size);
776

    
777
/* readline.c */
778
typedef void ReadLineFunc(void *opaque, const char *str);
779

    
780
extern int completion_index;
781
void add_completion(const char *str);
782
void readline_handle_byte(int ch);
783
void readline_find_completion(const char *cmdline);
784
const char *readline_get_history(unsigned int index);
785
void readline_start(const char *prompt, int is_password,
786
                    ReadLineFunc *readline_func, void *opaque);
787

    
788
void kqemu_record_dump(void);
789

    
790
/* sdl.c */
791
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
792

    
793
/* cocoa.m */
794
void cocoa_display_init(DisplayState *ds, int full_screen);
795

    
796
/* vnc.c */
797
void vnc_display_init(DisplayState *ds);
798
void vnc_display_close(DisplayState *ds);
799
int vnc_display_open(DisplayState *ds, const char *display);
800
int vnc_display_password(DisplayState *ds, const char *password);
801
void do_info_vnc(void);
802

    
803
/* x_keymap.c */
804
extern uint8_t _translate_keycode(const int key);
805

    
806
#ifndef QEMU_TOOL
807

    
808
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
809
                                 const char *boot_device,
810
             DisplayState *ds, const char **fd_filename, int snapshot,
811
             const char *kernel_filename, const char *kernel_cmdline,
812
             const char *initrd_filename, const char *cpu_model);
813

    
814
typedef struct QEMUMachine {
815
    const char *name;
816
    const char *desc;
817
    QEMUMachineInitFunc *init;
818
    struct QEMUMachine *next;
819
} QEMUMachine;
820

    
821
int qemu_register_machine(QEMUMachine *m);
822

    
823
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
824

    
825
#include "hw/irq.h"
826

    
827
/* ISA bus */
828

    
829
extern target_phys_addr_t isa_mem_base;
830

    
831
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
832
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
833

    
834
int register_ioport_read(int start, int length, int size,
835
                         IOPortReadFunc *func, void *opaque);
836
int register_ioport_write(int start, int length, int size,
837
                          IOPortWriteFunc *func, void *opaque);
838
void isa_unassign_ioport(int start, int length);
839

    
840
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
841

    
842
/* PCI bus */
843

    
844
extern target_phys_addr_t pci_mem_base;
845

    
846
typedef struct PCIBus PCIBus;
847
typedef struct PCIDevice PCIDevice;
848

    
849
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
850
                                uint32_t address, uint32_t data, int len);
851
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
852
                                   uint32_t address, int len);
853
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
854
                                uint32_t addr, uint32_t size, int type);
855

    
856
#define PCI_ADDRESS_SPACE_MEM                0x00
857
#define PCI_ADDRESS_SPACE_IO                0x01
858
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
859

    
860
typedef struct PCIIORegion {
861
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
862
    uint32_t size;
863
    uint8_t type;
864
    PCIMapIORegionFunc *map_func;
865
} PCIIORegion;
866

    
867
#define PCI_ROM_SLOT 6
868
#define PCI_NUM_REGIONS 7
869

    
870
#define PCI_DEVICES_MAX 64
871

    
872
#define PCI_VENDOR_ID                0x00        /* 16 bits */
873
#define PCI_DEVICE_ID                0x02        /* 16 bits */
874
#define PCI_COMMAND                0x04        /* 16 bits */
875
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
876
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
877
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
878
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
879
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
880
#define PCI_MIN_GNT                0x3e        /* 8 bits */
881
#define PCI_MAX_LAT                0x3f        /* 8 bits */
882

    
883
struct PCIDevice {
884
    /* PCI config space */
885
    uint8_t config[256];
886

    
887
    /* the following fields are read only */
888
    PCIBus *bus;
889
    int devfn;
890
    char name[64];
891
    PCIIORegion io_regions[PCI_NUM_REGIONS];
892

    
893
    /* do not access the following fields */
894
    PCIConfigReadFunc *config_read;
895
    PCIConfigWriteFunc *config_write;
896
    /* ??? This is a PC-specific hack, and should be removed.  */
897
    int irq_index;
898

    
899
    /* IRQ objects for the INTA-INTD pins.  */
900
    qemu_irq *irq;
901

    
902
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
903
    int irq_state[4];
904
};
905

    
906
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
907
                               int instance_size, int devfn,
908
                               PCIConfigReadFunc *config_read,
909
                               PCIConfigWriteFunc *config_write);
910

    
911
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
912
                            uint32_t size, int type,
913
                            PCIMapIORegionFunc *map_func);
914

    
915
uint32_t pci_default_read_config(PCIDevice *d,
916
                                 uint32_t address, int len);
917
void pci_default_write_config(PCIDevice *d,
918
                              uint32_t address, uint32_t val, int len);
919
void pci_device_save(PCIDevice *s, QEMUFile *f);
920
int pci_device_load(PCIDevice *s, QEMUFile *f);
921

    
922
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
923
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
924
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
925
                         qemu_irq *pic, int devfn_min, int nirq);
926

    
927
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
928
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
929
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
930
int pci_bus_num(PCIBus *s);
931
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
932

    
933
void pci_info(void);
934
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
935
                        pci_map_irq_fn map_irq, const char *name);
936

    
937
/* prep_pci.c */
938
PCIBus *pci_prep_init(qemu_irq *pic);
939

    
940
/* apb_pci.c */
941
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
942
                     qemu_irq *pic);
943

    
944
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
945

    
946
/* piix_pci.c */
947
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
948
void i440fx_set_smm(PCIDevice *d, int val);
949
int piix3_init(PCIBus *bus, int devfn);
950
void i440fx_init_memory_mappings(PCIDevice *d);
951

    
952
int piix4_init(PCIBus *bus, int devfn);
953

    
954
/* openpic.c */
955
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
956
enum {
957
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
958
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
959
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
960
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
961
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
962
    OPENPIC_OUTPUT_NB,
963
};
964
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
965
                        qemu_irq **irqs, qemu_irq irq_out);
966

    
967
/* gt64xxx.c */
968
PCIBus *pci_gt64120_init(qemu_irq *pic);
969

    
970
#ifdef HAS_AUDIO
971
struct soundhw {
972
    const char *name;
973
    const char *descr;
974
    int enabled;
975
    int isa;
976
    union {
977
        int (*init_isa) (AudioState *s, qemu_irq *pic);
978
        int (*init_pci) (PCIBus *bus, AudioState *s);
979
    } init;
980
};
981

    
982
extern struct soundhw soundhw[];
983
#endif
984

    
985
/* vga.c */
986

    
987
#ifndef TARGET_SPARC
988
#define VGA_RAM_SIZE (8192 * 1024)
989
#else
990
#define VGA_RAM_SIZE (9 * 1024 * 1024)
991
#endif
992

    
993
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
994
                 unsigned long vga_ram_offset, int vga_ram_size);
995
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
996
                 unsigned long vga_ram_offset, int vga_ram_size,
997
                 unsigned long vga_bios_offset, int vga_bios_size);
998
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
999
                    unsigned long vga_ram_offset, int vga_ram_size,
1000
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
1001
                    int it_shift);
1002

    
1003
/* cirrus_vga.c */
1004
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1005
                         unsigned long vga_ram_offset, int vga_ram_size);
1006
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1007
                         unsigned long vga_ram_offset, int vga_ram_size);
1008

    
1009
/* vmware_vga.c */
1010
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1011
                     unsigned long vga_ram_offset, int vga_ram_size);
1012

    
1013
/* ide.c */
1014
#define MAX_DISKS 4
1015

    
1016
extern BlockDriverState *bs_table[MAX_DISKS + 1];
1017
extern BlockDriverState *sd_bdrv;
1018
extern BlockDriverState *mtd_bdrv;
1019

    
1020
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1021
                  BlockDriverState *hd0, BlockDriverState *hd1);
1022
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1023
                         int secondary_ide_enabled);
1024
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1025
                        qemu_irq *pic);
1026
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1027
                        qemu_irq *pic);
1028

    
1029
/* cdrom.c */
1030
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1031
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1032

    
1033
/* ds1225y.c */
1034
typedef struct ds1225y_t ds1225y_t;
1035
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1036

    
1037
/* es1370.c */
1038
int es1370_init (PCIBus *bus, AudioState *s);
1039

    
1040
/* sb16.c */
1041
int SB16_init (AudioState *s, qemu_irq *pic);
1042

    
1043
/* adlib.c */
1044
int Adlib_init (AudioState *s, qemu_irq *pic);
1045

    
1046
/* gus.c */
1047
int GUS_init (AudioState *s, qemu_irq *pic);
1048

    
1049
/* dma.c */
1050
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1051
int DMA_get_channel_mode (int nchan);
1052
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1053
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1054
void DMA_hold_DREQ (int nchan);
1055
void DMA_release_DREQ (int nchan);
1056
void DMA_schedule(int nchan);
1057
void DMA_run (void);
1058
void DMA_init (int high_page_enable);
1059
void DMA_register_channel (int nchan,
1060
                           DMA_transfer_handler transfer_handler,
1061
                           void *opaque);
1062
/* fdc.c */
1063
#define MAX_FD 2
1064
extern BlockDriverState *fd_table[MAX_FD];
1065

    
1066
typedef struct fdctrl_t fdctrl_t;
1067

    
1068
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1069
                       target_phys_addr_t io_base,
1070
                       BlockDriverState **fds);
1071
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1072
                             BlockDriverState **fds);
1073
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1074

    
1075
/* eepro100.c */
1076

    
1077
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1078
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1079
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1080

    
1081
/* ne2000.c */
1082

    
1083
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1084
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1085

    
1086
/* rtl8139.c */
1087

    
1088
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1089

    
1090
/* pcnet.c */
1091

    
1092
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1093
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1094
                qemu_irq irq, qemu_irq *reset);
1095

    
1096
/* mipsnet.c */
1097
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1098

    
1099
/* vmmouse.c */
1100
void *vmmouse_init(void *m);
1101

    
1102
/* vmport.c */
1103
#ifdef TARGET_I386
1104
void vmport_init(CPUState *env);
1105
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1106
#endif
1107

    
1108
/* pckbd.c */
1109

    
1110
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1111
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1112
                   target_phys_addr_t base, int it_shift);
1113

    
1114
/* mc146818rtc.c */
1115

    
1116
typedef struct RTCState RTCState;
1117

    
1118
RTCState *rtc_init(int base, qemu_irq irq);
1119
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1120
void rtc_set_memory(RTCState *s, int addr, int val);
1121
void rtc_set_date(RTCState *s, const struct tm *tm);
1122

    
1123
/* serial.c */
1124

    
1125
typedef struct SerialState SerialState;
1126
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1127
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1128
                             qemu_irq irq, CharDriverState *chr,
1129
                             int ioregister);
1130
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1131
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1132
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1133
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1134
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1135
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1136

    
1137
/* parallel.c */
1138

    
1139
typedef struct ParallelState ParallelState;
1140
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1141
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1142

    
1143
/* i8259.c */
1144

    
1145
typedef struct PicState2 PicState2;
1146
extern PicState2 *isa_pic;
1147
void pic_set_irq(int irq, int level);
1148
void pic_set_irq_new(void *opaque, int irq, int level);
1149
qemu_irq *i8259_init(qemu_irq parent_irq);
1150
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1151
                          void *alt_irq_opaque);
1152
int pic_read_irq(PicState2 *s);
1153
void pic_update_irq(PicState2 *s);
1154
uint32_t pic_intack_read(PicState2 *s);
1155
void pic_info(void);
1156
void irq_info(void);
1157

    
1158
/* APIC */
1159
typedef struct IOAPICState IOAPICState;
1160

    
1161
int apic_init(CPUState *env);
1162
int apic_accept_pic_intr(CPUState *env);
1163
int apic_get_interrupt(CPUState *env);
1164
IOAPICState *ioapic_init(void);
1165
void ioapic_set_irq(void *opaque, int vector, int level);
1166

    
1167
/* i8254.c */
1168

    
1169
#define PIT_FREQ 1193182
1170

    
1171
typedef struct PITState PITState;
1172

    
1173
PITState *pit_init(int base, qemu_irq irq);
1174
void pit_set_gate(PITState *pit, int channel, int val);
1175
int pit_get_gate(PITState *pit, int channel);
1176
int pit_get_initial_count(PITState *pit, int channel);
1177
int pit_get_mode(PITState *pit, int channel);
1178
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1179

    
1180
/* jazz_led.c */
1181
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1182

    
1183
/* pcspk.c */
1184
void pcspk_init(PITState *);
1185
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1186

    
1187
#include "hw/i2c.h"
1188

    
1189
#include "hw/smbus.h"
1190

    
1191
/* acpi.c */
1192
extern int acpi_enabled;
1193
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1194
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1195
void acpi_bios_init(void);
1196

    
1197
/* Axis ETRAX.  */
1198
extern QEMUMachine bareetraxfs_machine;
1199

    
1200
/* pc.c */
1201
extern QEMUMachine pc_machine;
1202
extern QEMUMachine isapc_machine;
1203
extern int fd_bootchk;
1204

    
1205
void ioport_set_a20(int enable);
1206
int ioport_get_a20(void);
1207

    
1208
/* ppc.c */
1209
extern QEMUMachine prep_machine;
1210
extern QEMUMachine core99_machine;
1211
extern QEMUMachine heathrow_machine;
1212
extern QEMUMachine ref405ep_machine;
1213
extern QEMUMachine taihu_machine;
1214

    
1215
/* mips_r4k.c */
1216
extern QEMUMachine mips_machine;
1217

    
1218
/* mips_malta.c */
1219
extern QEMUMachine mips_malta_machine;
1220

    
1221
/* mips_pica61.c */
1222
extern QEMUMachine mips_pica61_machine;
1223

    
1224
/* mips_mipssim.c */
1225
extern QEMUMachine mips_mipssim_machine;
1226

    
1227
/* mips_int.c */
1228
extern void cpu_mips_irq_init_cpu(CPUState *env);
1229

    
1230
/* mips_timer.c */
1231
extern void cpu_mips_clock_init(CPUState *);
1232
extern void cpu_mips_irqctrl_init (void);
1233

    
1234
/* shix.c */
1235
extern QEMUMachine shix_machine;
1236

    
1237
/* r2d.c */
1238
extern QEMUMachine r2d_machine;
1239

    
1240
#ifdef TARGET_PPC
1241
/* PowerPC hardware exceptions management helpers */
1242
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1243
typedef struct clk_setup_t clk_setup_t;
1244
struct clk_setup_t {
1245
    clk_setup_cb cb;
1246
    void *opaque;
1247
};
1248
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1249
{
1250
    if (clk->cb != NULL)
1251
        (*clk->cb)(clk->opaque, freq);
1252
}
1253

    
1254
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1255
/* Embedded PowerPC DCR management */
1256
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1257
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1258
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1259
                  int (*dcr_write_error)(int dcrn));
1260
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1261
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1262
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1263
/* Embedded PowerPC reset */
1264
void ppc40x_core_reset (CPUState *env);
1265
void ppc40x_chip_reset (CPUState *env);
1266
void ppc40x_system_reset (CPUState *env);
1267
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1268

    
1269
extern CPUWriteMemoryFunc *PPC_io_write[];
1270
extern CPUReadMemoryFunc *PPC_io_read[];
1271
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1272
#endif
1273

    
1274
/* sun4m.c */
1275
extern QEMUMachine ss5_machine, ss10_machine;
1276

    
1277
/* iommu.c */
1278
void *iommu_init(target_phys_addr_t addr);
1279
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1280
                                 uint8_t *buf, int len, int is_write);
1281
static inline void sparc_iommu_memory_read(void *opaque,
1282
                                           target_phys_addr_t addr,
1283
                                           uint8_t *buf, int len)
1284
{
1285
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1286
}
1287

    
1288
static inline void sparc_iommu_memory_write(void *opaque,
1289
                                            target_phys_addr_t addr,
1290
                                            uint8_t *buf, int len)
1291
{
1292
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1293
}
1294

    
1295
/* tcx.c */
1296
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1297
              unsigned long vram_offset, int vram_size, int width, int height,
1298
              int depth);
1299

    
1300
/* slavio_intctl.c */
1301
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1302
                         const uint32_t *intbit_to_level,
1303
                         qemu_irq **irq, qemu_irq **cpu_irq,
1304
                         qemu_irq **parent_irq, unsigned int cputimer);
1305
void slavio_pic_info(void *opaque);
1306
void slavio_irq_info(void *opaque);
1307

    
1308
/* loader.c */
1309
int get_image_size(const char *filename);
1310
int load_image(const char *filename, uint8_t *addr);
1311
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1312
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1313
int load_aout(const char *filename, uint8_t *addr);
1314
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1315

    
1316
/* slavio_timer.c */
1317
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1318
                           qemu_irq *cpu_irqs);
1319

    
1320
/* slavio_serial.c */
1321
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1322
                                CharDriverState *chr1, CharDriverState *chr2);
1323
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1324

    
1325
/* slavio_misc.c */
1326
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1327
                       qemu_irq irq);
1328
void slavio_set_power_fail(void *opaque, int power_failing);
1329

    
1330
/* esp.c */
1331
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1332
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1333
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1334

    
1335
/* sparc32_dma.c */
1336
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1337
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1338
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1339
                       uint8_t *buf, int len, int do_bswap);
1340
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1341
                        uint8_t *buf, int len, int do_bswap);
1342
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1343
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1344

    
1345
/* cs4231.c */
1346
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1347

    
1348
/* sun4u.c */
1349
extern QEMUMachine sun4u_machine;
1350

    
1351
/* NVRAM helpers */
1352
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
1353
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
1354
typedef struct nvram_t {
1355
    void *opaque;
1356
    nvram_read_t read_fn;
1357
    nvram_write_t write_fn;
1358
} nvram_t;
1359

    
1360
#include "hw/m48t59.h"
1361

    
1362
void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
1363
uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
1364
void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
1365
uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
1366
void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
1367
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
1368
void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1369
                       const unsigned char *str, uint32_t max);
1370
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
1371
void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
1372
                    uint32_t start, uint32_t count);
1373
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1374
                          const unsigned char *arch,
1375
                          uint32_t RAM_size, int boot_device,
1376
                          uint32_t kernel_image, uint32_t kernel_size,
1377
                          const char *cmdline,
1378
                          uint32_t initrd_image, uint32_t initrd_size,
1379
                          uint32_t NVRAM_image,
1380
                          int width, int height, int depth);
1381

    
1382
/* adb.c */
1383

    
1384
#define MAX_ADB_DEVICES 16
1385

    
1386
#define ADB_MAX_OUT_LEN 16
1387

    
1388
typedef struct ADBDevice ADBDevice;
1389

    
1390
/* buf = NULL means polling */
1391
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1392
                              const uint8_t *buf, int len);
1393
typedef int ADBDeviceReset(ADBDevice *d);
1394

    
1395
struct ADBDevice {
1396
    struct ADBBusState *bus;
1397
    int devaddr;
1398
    int handler;
1399
    ADBDeviceRequest *devreq;
1400
    ADBDeviceReset *devreset;
1401
    void *opaque;
1402
};
1403

    
1404
typedef struct ADBBusState {
1405
    ADBDevice devices[MAX_ADB_DEVICES];
1406
    int nb_devices;
1407
    int poll_index;
1408
} ADBBusState;
1409

    
1410
int adb_request(ADBBusState *s, uint8_t *buf_out,
1411
                const uint8_t *buf, int len);
1412
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1413

    
1414
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1415
                               ADBDeviceRequest *devreq,
1416
                               ADBDeviceReset *devreset,
1417
                               void *opaque);
1418
void adb_kbd_init(ADBBusState *bus);
1419
void adb_mouse_init(ADBBusState *bus);
1420

    
1421
extern ADBBusState adb_bus;
1422

    
1423
#include "hw/usb.h"
1424

    
1425
/* usb ports of the VM */
1426

    
1427
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1428
                            usb_attachfn attach);
1429

    
1430
#define VM_USB_HUB_SIZE 8
1431

    
1432
void do_usb_add(const char *devname);
1433
void do_usb_del(const char *devname);
1434
void usb_info(void);
1435

    
1436
/* scsi-disk.c */
1437
enum scsi_reason {
1438
    SCSI_REASON_DONE, /* Command complete.  */
1439
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1440
};
1441

    
1442
typedef struct SCSIDevice SCSIDevice;
1443
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1444
                                  uint32_t arg);
1445

    
1446
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1447
                           int tcq,
1448
                           scsi_completionfn completion,
1449
                           void *opaque);
1450
void scsi_disk_destroy(SCSIDevice *s);
1451

    
1452
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1453
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1454
   layer the completion routine may be called directly by
1455
   scsi_{read,write}_data.  */
1456
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1457
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1458
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1459
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1460

    
1461
/* lsi53c895a.c */
1462
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1463
void *lsi_scsi_init(PCIBus *bus, int devfn);
1464

    
1465
/* integratorcp.c */
1466
extern QEMUMachine integratorcp_machine;
1467

    
1468
/* versatilepb.c */
1469
extern QEMUMachine versatilepb_machine;
1470
extern QEMUMachine versatileab_machine;
1471

    
1472
/* realview.c */
1473
extern QEMUMachine realview_machine;
1474

    
1475
/* spitz.c */
1476
extern QEMUMachine akitapda_machine;
1477
extern QEMUMachine spitzpda_machine;
1478
extern QEMUMachine borzoipda_machine;
1479
extern QEMUMachine terrierpda_machine;
1480

    
1481
/* palm.c */
1482
extern QEMUMachine palmte_machine;
1483

    
1484
/* ps2.c */
1485
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1486
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1487
void ps2_write_mouse(void *, int val);
1488
void ps2_write_keyboard(void *, int val);
1489
uint32_t ps2_read_data(void *);
1490
void ps2_queue(void *, int b);
1491
void ps2_keyboard_set_translation(void *opaque, int mode);
1492
void ps2_mouse_fake_event(void *opaque);
1493

    
1494
/* smc91c111.c */
1495
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1496

    
1497
/* pl031.c */
1498
void pl031_init(uint32_t base, qemu_irq irq);
1499

    
1500
/* pl110.c */
1501
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1502

    
1503
/* pl011.c */
1504
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1505

    
1506
/* pl050.c */
1507
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1508

    
1509
/* pl080.c */
1510
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1511

    
1512
/* pl181.c */
1513
void pl181_init(uint32_t base, BlockDriverState *bd,
1514
                qemu_irq irq0, qemu_irq irq1);
1515

    
1516
/* pl190.c */
1517
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1518

    
1519
/* arm-timer.c */
1520
void sp804_init(uint32_t base, qemu_irq irq);
1521
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1522

    
1523
/* arm_sysctl.c */
1524
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1525

    
1526
/* arm_gic.c */
1527
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1528

    
1529
/* arm_boot.c */
1530

    
1531
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1532
                     const char *kernel_cmdline, const char *initrd_filename,
1533
                     int board_id, target_phys_addr_t loader_start);
1534

    
1535
/* sh7750.c */
1536
struct SH7750State;
1537

    
1538
struct SH7750State *sh7750_init(CPUState * cpu);
1539

    
1540
typedef struct {
1541
    /* The callback will be triggered if any of the designated lines change */
1542
    uint16_t portamask_trigger;
1543
    uint16_t portbmask_trigger;
1544
    /* Return 0 if no action was taken */
1545
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1546
                           uint16_t * periph_pdtra,
1547
                           uint16_t * periph_portdira,
1548
                           uint16_t * periph_pdtrb,
1549
                           uint16_t * periph_portdirb);
1550
} sh7750_io_device;
1551

    
1552
int sh7750_register_io_device(struct SH7750State *s,
1553
                              sh7750_io_device * device);
1554
/* sh_timer.c */
1555
#define TMU012_FEAT_TOCR   (1 << 0)
1556
#define TMU012_FEAT_3CHAN  (1 << 1)
1557
#define TMU012_FEAT_EXTCLK (1 << 2)
1558
void tmu012_init(uint32_t base, int feat, uint32_t freq);
1559

    
1560
/* sh_serial.c */
1561
#define SH_SERIAL_FEAT_SCIF (1 << 0)
1562
void sh_serial_init (target_phys_addr_t base, int feat,
1563
                     uint32_t freq, CharDriverState *chr);
1564

    
1565
/* tc58128.c */
1566
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1567

    
1568
/* NOR flash devices */
1569
#define MAX_PFLASH 4
1570
extern BlockDriverState *pflash_table[MAX_PFLASH];
1571
typedef struct pflash_t pflash_t;
1572

    
1573
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1574
                           BlockDriverState *bs,
1575
                           uint32_t sector_len, int nb_blocs, int width,
1576
                           uint16_t id0, uint16_t id1,
1577
                           uint16_t id2, uint16_t id3);
1578

    
1579
/* nand.c */
1580
struct nand_flash_s;
1581
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1582
void nand_done(struct nand_flash_s *s);
1583
void nand_setpins(struct nand_flash_s *s,
1584
                int cle, int ale, int ce, int wp, int gnd);
1585
void nand_getpins(struct nand_flash_s *s, int *rb);
1586
void nand_setio(struct nand_flash_s *s, uint8_t value);
1587
uint8_t nand_getio(struct nand_flash_s *s);
1588

    
1589
#define NAND_MFR_TOSHIBA        0x98
1590
#define NAND_MFR_SAMSUNG        0xec
1591
#define NAND_MFR_FUJITSU        0x04
1592
#define NAND_MFR_NATIONAL        0x8f
1593
#define NAND_MFR_RENESAS        0x07
1594
#define NAND_MFR_STMICRO        0x20
1595
#define NAND_MFR_HYNIX                0xad
1596
#define NAND_MFR_MICRON                0x2c
1597

    
1598
/* ecc.c */
1599
struct ecc_state_s {
1600
    uint8_t cp;                /* Column parity */
1601
    uint16_t lp[2];        /* Line parity */
1602
    uint16_t count;
1603
};
1604

    
1605
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1606
void ecc_reset(struct ecc_state_s *s);
1607
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1608
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1609

    
1610
/* GPIO */
1611
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1612

    
1613
/* ads7846.c */
1614
struct ads7846_state_s;
1615
uint32_t ads7846_read(void *opaque);
1616
void ads7846_write(void *opaque, uint32_t value);
1617
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1618

    
1619
/* max111x.c */
1620
struct max111x_s;
1621
uint32_t max111x_read(void *opaque);
1622
void max111x_write(void *opaque, uint32_t value);
1623
struct max111x_s *max1110_init(qemu_irq cb);
1624
struct max111x_s *max1111_init(qemu_irq cb);
1625
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1626

    
1627
/* PCMCIA/Cardbus */
1628

    
1629
struct pcmcia_socket_s {
1630
    qemu_irq irq;
1631
    int attached;
1632
    const char *slot_string;
1633
    const char *card_string;
1634
};
1635

    
1636
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1637
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1638
void pcmcia_info(void);
1639

    
1640
struct pcmcia_card_s {
1641
    void *state;
1642
    struct pcmcia_socket_s *slot;
1643
    int (*attach)(void *state);
1644
    int (*detach)(void *state);
1645
    const uint8_t *cis;
1646
    int cis_len;
1647

    
1648
    /* Only valid if attached */
1649
    uint8_t (*attr_read)(void *state, uint32_t address);
1650
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1651
    uint16_t (*common_read)(void *state, uint32_t address);
1652
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1653
    uint16_t (*io_read)(void *state, uint32_t address);
1654
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1655
};
1656

    
1657
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1658
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1659
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1660
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1661
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1662
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1663
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1664
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1665
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1666
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1667
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1668
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1669
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1670
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1671
#define CISTPL_END                0xff        /* Tuple End */
1672
#define CISTPL_ENDMARK                0xff
1673

    
1674
/* dscm1xxxx.c */
1675
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1676

    
1677
/* ptimer.c */
1678
typedef struct ptimer_state ptimer_state;
1679
typedef void (*ptimer_cb)(void *opaque);
1680

    
1681
ptimer_state *ptimer_init(QEMUBH *bh);
1682
void ptimer_set_period(ptimer_state *s, int64_t period);
1683
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1684
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1685
uint64_t ptimer_get_count(ptimer_state *s);
1686
void ptimer_set_count(ptimer_state *s, uint64_t count);
1687
void ptimer_run(ptimer_state *s, int oneshot);
1688
void ptimer_stop(ptimer_state *s);
1689
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1690
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1691

    
1692
#include "hw/pxa.h"
1693

    
1694
#include "hw/omap.h"
1695

    
1696
/* tsc210x.c */
1697
struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
1698
struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
1699

    
1700
/* mcf_uart.c */
1701
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1702
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1703
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1704
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1705
                      CharDriverState *chr);
1706

    
1707
/* mcf_intc.c */
1708
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1709

    
1710
/* mcf_fec.c */
1711
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1712

    
1713
/* mcf5206.c */
1714
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1715

    
1716
/* an5206.c */
1717
extern QEMUMachine an5206_machine;
1718

    
1719
/* mcf5208.c */
1720
extern QEMUMachine mcf5208evb_machine;
1721

    
1722
#include "gdbstub.h"
1723

    
1724
#endif /* defined(QEMU_TOOL) */
1725
#endif /* VL_H */