root / hw / lan9118.c @ 2a424990
History | View | Annotate | Download (29 kB)
1 | 2a424990 | Paul Brook | /*
|
---|---|---|---|
2 | 2a424990 | Paul Brook | * SMSC LAN9118 Ethernet interface emulation
|
3 | 2a424990 | Paul Brook | *
|
4 | 2a424990 | Paul Brook | * Copyright (c) 2009 CodeSourcery, LLC.
|
5 | 2a424990 | Paul Brook | * Written by Paul Brook
|
6 | 2a424990 | Paul Brook | *
|
7 | 2a424990 | Paul Brook | * This code is licenced under the GNU GPL v2
|
8 | 2a424990 | Paul Brook | */
|
9 | 2a424990 | Paul Brook | |
10 | 2a424990 | Paul Brook | #include "sysbus.h" |
11 | 2a424990 | Paul Brook | #include "net.h" |
12 | 2a424990 | Paul Brook | #include "devices.h" |
13 | 2a424990 | Paul Brook | /* For crc32 */
|
14 | 2a424990 | Paul Brook | #include <zlib.h> |
15 | 2a424990 | Paul Brook | |
16 | 2a424990 | Paul Brook | //#define DEBUG_LAN9118
|
17 | 2a424990 | Paul Brook | |
18 | 2a424990 | Paul Brook | #ifdef DEBUG_LAN9118
|
19 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) \
|
20 | 2a424990 | Paul Brook | do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) |
21 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
|
22 | 2a424990 | Paul Brook | do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
23 | 2a424990 | Paul Brook | #else
|
24 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) do {} while(0) |
25 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
|
26 | 2a424990 | Paul Brook | do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
27 | 2a424990 | Paul Brook | #endif
|
28 | 2a424990 | Paul Brook | |
29 | 2a424990 | Paul Brook | #define CSR_ID_REV 0x50 |
30 | 2a424990 | Paul Brook | #define CSR_IRQ_CFG 0x54 |
31 | 2a424990 | Paul Brook | #define CSR_INT_STS 0x58 |
32 | 2a424990 | Paul Brook | #define CSR_INT_EN 0x5c |
33 | 2a424990 | Paul Brook | #define CSR_BYTE_TEST 0x64 |
34 | 2a424990 | Paul Brook | #define CSR_FIFO_INT 0x68 |
35 | 2a424990 | Paul Brook | #define CSR_RX_CFG 0x6c |
36 | 2a424990 | Paul Brook | #define CSR_TX_CFG 0x70 |
37 | 2a424990 | Paul Brook | #define CSR_HW_CFG 0x74 |
38 | 2a424990 | Paul Brook | #define CSR_RX_DP_CTRL 0x78 |
39 | 2a424990 | Paul Brook | #define CSR_RX_FIFO_INF 0x7c |
40 | 2a424990 | Paul Brook | #define CSR_TX_FIFO_INF 0x80 |
41 | 2a424990 | Paul Brook | #define CSR_PMT_CTRL 0x84 |
42 | 2a424990 | Paul Brook | #define CSR_GPIO_CFG 0x88 |
43 | 2a424990 | Paul Brook | #define CSR_GPT_CFG 0x8c /* TODO */ |
44 | 2a424990 | Paul Brook | #define CSR_GPT_CNT 0x90 /* TODO */ |
45 | 2a424990 | Paul Brook | #define CSR_WORD_SWAP 0x98 |
46 | 2a424990 | Paul Brook | #define CSR_FREE_RUN 0x9c |
47 | 2a424990 | Paul Brook | #define CSR_RX_DROP 0xa0 |
48 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_CMD 0xa4 |
49 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_DATA 0xa8 |
50 | 2a424990 | Paul Brook | #define CSR_AFC_CFG 0xac |
51 | 2a424990 | Paul Brook | #define CSR_E2P_CMD 0xb0 |
52 | 2a424990 | Paul Brook | #define CSR_E2P_DATA 0xb4 |
53 | 2a424990 | Paul Brook | |
54 | 2a424990 | Paul Brook | /* IRQ_CFG */
|
55 | 2a424990 | Paul Brook | #define IRQ_EN 0x00000100 |
56 | 2a424990 | Paul Brook | #define IRQ_POL 0x00000010 |
57 | 2a424990 | Paul Brook | #define IRQ_TYPE 0x00000001 |
58 | 2a424990 | Paul Brook | |
59 | 2a424990 | Paul Brook | /* INT_STS/INT_EN */
|
60 | 2a424990 | Paul Brook | #define SW_INT 0x80000000 |
61 | 2a424990 | Paul Brook | #define TXSTOP_INT 0x02000000 |
62 | 2a424990 | Paul Brook | #define RXSTOP_INT 0x01000000 |
63 | 2a424990 | Paul Brook | #define RXDFH_INT 0x00800000 |
64 | 2a424990 | Paul Brook | #define TX_IOC_INT 0x00200000 |
65 | 2a424990 | Paul Brook | #define RXD_INT 0x00100000 |
66 | 2a424990 | Paul Brook | #define GPT_INT 0x00080000 |
67 | 2a424990 | Paul Brook | #define PHY_INT 0x00040000 |
68 | 2a424990 | Paul Brook | #define PME_INT 0x00020000 |
69 | 2a424990 | Paul Brook | #define TXSO_INT 0x00010000 |
70 | 2a424990 | Paul Brook | #define RWT_INT 0x00008000 |
71 | 2a424990 | Paul Brook | #define RXE_INT 0x00004000 |
72 | 2a424990 | Paul Brook | #define TXE_INT 0x00002000 |
73 | 2a424990 | Paul Brook | #define TDFU_INT 0x00000800 |
74 | 2a424990 | Paul Brook | #define TDFO_INT 0x00000400 |
75 | 2a424990 | Paul Brook | #define TDFA_INT 0x00000200 |
76 | 2a424990 | Paul Brook | #define TSFF_INT 0x00000100 |
77 | 2a424990 | Paul Brook | #define TSFL_INT 0x00000080 |
78 | 2a424990 | Paul Brook | #define RXDF_INT 0x00000040 |
79 | 2a424990 | Paul Brook | #define RDFL_INT 0x00000020 |
80 | 2a424990 | Paul Brook | #define RSFF_INT 0x00000010 |
81 | 2a424990 | Paul Brook | #define RSFL_INT 0x00000008 |
82 | 2a424990 | Paul Brook | #define GPIO2_INT 0x00000004 |
83 | 2a424990 | Paul Brook | #define GPIO1_INT 0x00000002 |
84 | 2a424990 | Paul Brook | #define GPIO0_INT 0x00000001 |
85 | 2a424990 | Paul Brook | #define RESERVED_INT 0x7c001000 |
86 | 2a424990 | Paul Brook | |
87 | 2a424990 | Paul Brook | #define MAC_CR 1 |
88 | 2a424990 | Paul Brook | #define MAC_ADDRH 2 |
89 | 2a424990 | Paul Brook | #define MAC_ADDRL 3 |
90 | 2a424990 | Paul Brook | #define MAC_HASHH 4 |
91 | 2a424990 | Paul Brook | #define MAC_HASHL 5 |
92 | 2a424990 | Paul Brook | #define MAC_MII_ACC 6 |
93 | 2a424990 | Paul Brook | #define MAC_MII_DATA 7 |
94 | 2a424990 | Paul Brook | #define MAC_FLOW 8 |
95 | 2a424990 | Paul Brook | #define MAC_VLAN1 9 /* TODO */ |
96 | 2a424990 | Paul Brook | #define MAC_VLAN2 10 /* TODO */ |
97 | 2a424990 | Paul Brook | #define MAC_WUFF 11 /* TODO */ |
98 | 2a424990 | Paul Brook | #define MAC_WUCSR 12 /* TODO */ |
99 | 2a424990 | Paul Brook | |
100 | 2a424990 | Paul Brook | #define MAC_CR_RXALL 0x80000000 |
101 | 2a424990 | Paul Brook | #define MAC_CR_RCVOWN 0x00800000 |
102 | 2a424990 | Paul Brook | #define MAC_CR_LOOPBK 0x00200000 |
103 | 2a424990 | Paul Brook | #define MAC_CR_FDPX 0x00100000 |
104 | 2a424990 | Paul Brook | #define MAC_CR_MCPAS 0x00080000 |
105 | 2a424990 | Paul Brook | #define MAC_CR_PRMS 0x00040000 |
106 | 2a424990 | Paul Brook | #define MAC_CR_INVFILT 0x00020000 |
107 | 2a424990 | Paul Brook | #define MAC_CR_PASSBAD 0x00010000 |
108 | 2a424990 | Paul Brook | #define MAC_CR_HO 0x00008000 |
109 | 2a424990 | Paul Brook | #define MAC_CR_HPFILT 0x00002000 |
110 | 2a424990 | Paul Brook | #define MAC_CR_LCOLL 0x00001000 |
111 | 2a424990 | Paul Brook | #define MAC_CR_BCAST 0x00000800 |
112 | 2a424990 | Paul Brook | #define MAC_CR_DISRTY 0x00000400 |
113 | 2a424990 | Paul Brook | #define MAC_CR_PADSTR 0x00000100 |
114 | 2a424990 | Paul Brook | #define MAC_CR_BOLMT 0x000000c0 |
115 | 2a424990 | Paul Brook | #define MAC_CR_DFCHK 0x00000020 |
116 | 2a424990 | Paul Brook | #define MAC_CR_TXEN 0x00000008 |
117 | 2a424990 | Paul Brook | #define MAC_CR_RXEN 0x00000004 |
118 | 2a424990 | Paul Brook | #define MAC_CR_RESERVED 0x7f404213 |
119 | 2a424990 | Paul Brook | |
120 | 2a424990 | Paul Brook | enum tx_state {
|
121 | 2a424990 | Paul Brook | TX_IDLE, |
122 | 2a424990 | Paul Brook | TX_B, |
123 | 2a424990 | Paul Brook | TX_DATA |
124 | 2a424990 | Paul Brook | }; |
125 | 2a424990 | Paul Brook | |
126 | 2a424990 | Paul Brook | typedef struct { |
127 | 2a424990 | Paul Brook | enum tx_state state;
|
128 | 2a424990 | Paul Brook | uint32_t cmd_a; |
129 | 2a424990 | Paul Brook | uint32_t cmd_b; |
130 | 2a424990 | Paul Brook | int buffer_size;
|
131 | 2a424990 | Paul Brook | int offset;
|
132 | 2a424990 | Paul Brook | int pad;
|
133 | 2a424990 | Paul Brook | int fifo_used;
|
134 | 2a424990 | Paul Brook | int len;
|
135 | 2a424990 | Paul Brook | uint8_t data[2048];
|
136 | 2a424990 | Paul Brook | } LAN9118Packet; |
137 | 2a424990 | Paul Brook | |
138 | 2a424990 | Paul Brook | typedef struct { |
139 | 2a424990 | Paul Brook | SysBusDevice busdev; |
140 | 2a424990 | Paul Brook | VLANClientState *vc; |
141 | 2a424990 | Paul Brook | NICConf conf; |
142 | 2a424990 | Paul Brook | qemu_irq irq; |
143 | 2a424990 | Paul Brook | int mmio_index;
|
144 | 2a424990 | Paul Brook | |
145 | 2a424990 | Paul Brook | uint32_t irq_cfg; |
146 | 2a424990 | Paul Brook | uint32_t int_sts; |
147 | 2a424990 | Paul Brook | uint32_t int_en; |
148 | 2a424990 | Paul Brook | uint32_t fifo_int; |
149 | 2a424990 | Paul Brook | uint32_t rx_cfg; |
150 | 2a424990 | Paul Brook | uint32_t tx_cfg; |
151 | 2a424990 | Paul Brook | uint32_t hw_cfg; |
152 | 2a424990 | Paul Brook | uint32_t pmt_ctrl; |
153 | 2a424990 | Paul Brook | uint32_t gpio_cfg; |
154 | 2a424990 | Paul Brook | uint32_t word_swap; |
155 | 2a424990 | Paul Brook | uint32_t free_timer_start; |
156 | 2a424990 | Paul Brook | uint32_t mac_cmd; |
157 | 2a424990 | Paul Brook | uint32_t mac_data; |
158 | 2a424990 | Paul Brook | uint32_t afc_cfg; |
159 | 2a424990 | Paul Brook | uint32_t e2p_cmd; |
160 | 2a424990 | Paul Brook | uint32_t e2p_data; |
161 | 2a424990 | Paul Brook | |
162 | 2a424990 | Paul Brook | uint32_t mac_cr; |
163 | 2a424990 | Paul Brook | uint32_t mac_hashh; |
164 | 2a424990 | Paul Brook | uint32_t mac_hashl; |
165 | 2a424990 | Paul Brook | uint32_t mac_mii_acc; |
166 | 2a424990 | Paul Brook | uint32_t mac_mii_data; |
167 | 2a424990 | Paul Brook | uint32_t mac_flow; |
168 | 2a424990 | Paul Brook | |
169 | 2a424990 | Paul Brook | uint32_t phy_status; |
170 | 2a424990 | Paul Brook | uint32_t phy_control; |
171 | 2a424990 | Paul Brook | uint32_t phy_advertise; |
172 | 2a424990 | Paul Brook | |
173 | 2a424990 | Paul Brook | int eeprom_writable;
|
174 | 2a424990 | Paul Brook | uint8_t eeprom[8];
|
175 | 2a424990 | Paul Brook | |
176 | 2a424990 | Paul Brook | int tx_fifo_size;
|
177 | 2a424990 | Paul Brook | LAN9118Packet *txp; |
178 | 2a424990 | Paul Brook | LAN9118Packet tx_packet; |
179 | 2a424990 | Paul Brook | |
180 | 2a424990 | Paul Brook | int tx_status_fifo_used;
|
181 | 2a424990 | Paul Brook | int tx_status_fifo_head;
|
182 | 2a424990 | Paul Brook | uint32_t tx_status_fifo[512];
|
183 | 2a424990 | Paul Brook | |
184 | 2a424990 | Paul Brook | int rx_status_fifo_size;
|
185 | 2a424990 | Paul Brook | int rx_status_fifo_used;
|
186 | 2a424990 | Paul Brook | int rx_status_fifo_head;
|
187 | 2a424990 | Paul Brook | uint32_t rx_status_fifo[896];
|
188 | 2a424990 | Paul Brook | int rx_fifo_size;
|
189 | 2a424990 | Paul Brook | int rx_fifo_used;
|
190 | 2a424990 | Paul Brook | int rx_fifo_head;
|
191 | 2a424990 | Paul Brook | uint32_t rx_fifo[3360];
|
192 | 2a424990 | Paul Brook | int rx_packet_size_head;
|
193 | 2a424990 | Paul Brook | int rx_packet_size_tail;
|
194 | 2a424990 | Paul Brook | int rx_packet_size[1024]; |
195 | 2a424990 | Paul Brook | |
196 | 2a424990 | Paul Brook | int rxp_offset;
|
197 | 2a424990 | Paul Brook | int rxp_size;
|
198 | 2a424990 | Paul Brook | int rxp_pad;
|
199 | 2a424990 | Paul Brook | } lan9118_state; |
200 | 2a424990 | Paul Brook | |
201 | 2a424990 | Paul Brook | static void lan9118_update(lan9118_state *s) |
202 | 2a424990 | Paul Brook | { |
203 | 2a424990 | Paul Brook | int level;
|
204 | 2a424990 | Paul Brook | |
205 | 2a424990 | Paul Brook | /* TODO: Implement FIFO level IRQs. */
|
206 | 2a424990 | Paul Brook | level = (s->int_sts & s->int_en) != 0;
|
207 | 2a424990 | Paul Brook | if ((s->irq_cfg & IRQ_EN) == 0) { |
208 | 2a424990 | Paul Brook | level = 0;
|
209 | 2a424990 | Paul Brook | } |
210 | 2a424990 | Paul Brook | qemu_set_irq(s->irq, level); |
211 | 2a424990 | Paul Brook | } |
212 | 2a424990 | Paul Brook | |
213 | 2a424990 | Paul Brook | static void lan9118_mac_changed(lan9118_state *s) |
214 | 2a424990 | Paul Brook | { |
215 | 2a424990 | Paul Brook | qemu_format_nic_info_str(s->vc, s->conf.macaddr.a); |
216 | 2a424990 | Paul Brook | } |
217 | 2a424990 | Paul Brook | |
218 | 2a424990 | Paul Brook | static void lan9118_reload_eeprom(lan9118_state *s) |
219 | 2a424990 | Paul Brook | { |
220 | 2a424990 | Paul Brook | int i;
|
221 | 2a424990 | Paul Brook | if (s->eeprom[0] != 0xa5) { |
222 | 2a424990 | Paul Brook | s->e2p_cmd &= ~0x10;
|
223 | 2a424990 | Paul Brook | DPRINTF("MACADDR load failed\n");
|
224 | 2a424990 | Paul Brook | return;
|
225 | 2a424990 | Paul Brook | } |
226 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
227 | 2a424990 | Paul Brook | s->conf.macaddr.a[i] = s->eeprom[i + 1];
|
228 | 2a424990 | Paul Brook | } |
229 | 2a424990 | Paul Brook | s->e2p_cmd |= 0x10;
|
230 | 2a424990 | Paul Brook | DPRINTF("MACADDR loaded from eeprom\n");
|
231 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
232 | 2a424990 | Paul Brook | } |
233 | 2a424990 | Paul Brook | |
234 | 2a424990 | Paul Brook | static void phy_update_link(lan9118_state *s) |
235 | 2a424990 | Paul Brook | { |
236 | 2a424990 | Paul Brook | /* Autonegotiation status mirrors link status. */
|
237 | 2a424990 | Paul Brook | if (s->vc->link_down) {
|
238 | 2a424990 | Paul Brook | s->phy_status &= ~0x0024;
|
239 | 2a424990 | Paul Brook | } else {
|
240 | 2a424990 | Paul Brook | s->phy_status |= 0x0024;
|
241 | 2a424990 | Paul Brook | } |
242 | 2a424990 | Paul Brook | } |
243 | 2a424990 | Paul Brook | |
244 | 2a424990 | Paul Brook | static void lan9118_set_link(VLANClientState *vc) |
245 | 2a424990 | Paul Brook | { |
246 | 2a424990 | Paul Brook | phy_update_link(vc->opaque); |
247 | 2a424990 | Paul Brook | } |
248 | 2a424990 | Paul Brook | |
249 | 2a424990 | Paul Brook | static void phy_reset(lan9118_state *s) |
250 | 2a424990 | Paul Brook | { |
251 | 2a424990 | Paul Brook | s->phy_status = 0x7805;
|
252 | 2a424990 | Paul Brook | s->phy_control = 0x3000;
|
253 | 2a424990 | Paul Brook | s->phy_advertise = 0x01e1;
|
254 | 2a424990 | Paul Brook | phy_update_link(s); |
255 | 2a424990 | Paul Brook | } |
256 | 2a424990 | Paul Brook | |
257 | 2a424990 | Paul Brook | static void lan9118_reset(DeviceState *d) |
258 | 2a424990 | Paul Brook | { |
259 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d)); |
260 | 2a424990 | Paul Brook | |
261 | 2a424990 | Paul Brook | s->irq_cfg &= ~(IRQ_TYPE | IRQ_POL); |
262 | 2a424990 | Paul Brook | s->int_sts = 0;
|
263 | 2a424990 | Paul Brook | s->int_en = 0;
|
264 | 2a424990 | Paul Brook | s->fifo_int = 0x48000000;
|
265 | 2a424990 | Paul Brook | s->rx_cfg = 0;
|
266 | 2a424990 | Paul Brook | s->tx_cfg = 0;
|
267 | 2a424990 | Paul Brook | s->hw_cfg = 0x00050000;
|
268 | 2a424990 | Paul Brook | s->pmt_ctrl &= 0x45;
|
269 | 2a424990 | Paul Brook | s->gpio_cfg = 0;
|
270 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
271 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
272 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffffu;
|
273 | 2a424990 | Paul Brook | s->txp->cmd_b = 0xffffffffu;
|
274 | 2a424990 | Paul Brook | s->txp->len = 0;
|
275 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
276 | 2a424990 | Paul Brook | s->tx_fifo_size = 4608;
|
277 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
|
278 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 704;
|
279 | 2a424990 | Paul Brook | s->rx_fifo_size = 2640;
|
280 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
|
281 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 176;
|
282 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
|
283 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
284 | 2a424990 | Paul Brook | s->rxp_size = 0;
|
285 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
286 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
287 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
288 | 2a424990 | Paul Brook | s->mac_cmd = 0;
|
289 | 2a424990 | Paul Brook | s->mac_data = 0;
|
290 | 2a424990 | Paul Brook | s->afc_cfg = 0;
|
291 | 2a424990 | Paul Brook | s->e2p_cmd = 0;
|
292 | 2a424990 | Paul Brook | s->e2p_data = 0;
|
293 | 2a424990 | Paul Brook | s->free_timer_start = qemu_get_clock(vm_clock) / 40;
|
294 | 2a424990 | Paul Brook | |
295 | 2a424990 | Paul Brook | s->mac_cr = MAC_CR_PRMS; |
296 | 2a424990 | Paul Brook | s->mac_hashh = 0;
|
297 | 2a424990 | Paul Brook | s->mac_hashl = 0;
|
298 | 2a424990 | Paul Brook | s->mac_mii_acc = 0;
|
299 | 2a424990 | Paul Brook | s->mac_mii_data = 0;
|
300 | 2a424990 | Paul Brook | s->mac_flow = 0;
|
301 | 2a424990 | Paul Brook | |
302 | 2a424990 | Paul Brook | phy_reset(s); |
303 | 2a424990 | Paul Brook | |
304 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
|
305 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
306 | 2a424990 | Paul Brook | } |
307 | 2a424990 | Paul Brook | |
308 | 2a424990 | Paul Brook | static int lan9118_can_receive(VLANClientState *vc) |
309 | 2a424990 | Paul Brook | { |
310 | 2a424990 | Paul Brook | return 1; |
311 | 2a424990 | Paul Brook | } |
312 | 2a424990 | Paul Brook | |
313 | 2a424990 | Paul Brook | static void rx_fifo_push(lan9118_state *s, uint32_t val) |
314 | 2a424990 | Paul Brook | { |
315 | 2a424990 | Paul Brook | int fifo_pos;
|
316 | 2a424990 | Paul Brook | fifo_pos = s->rx_fifo_head + s->rx_fifo_used; |
317 | 2a424990 | Paul Brook | if (fifo_pos >= s->rx_fifo_size)
|
318 | 2a424990 | Paul Brook | fifo_pos -= s->rx_fifo_size; |
319 | 2a424990 | Paul Brook | s->rx_fifo[fifo_pos] = val; |
320 | 2a424990 | Paul Brook | s->rx_fifo_used++; |
321 | 2a424990 | Paul Brook | } |
322 | 2a424990 | Paul Brook | |
323 | 2a424990 | Paul Brook | /* Return nonzero if the packet is accepted by the filter. */
|
324 | 2a424990 | Paul Brook | static int lan9118_filter(lan9118_state *s, const uint8_t *addr) |
325 | 2a424990 | Paul Brook | { |
326 | 2a424990 | Paul Brook | int multicast;
|
327 | 2a424990 | Paul Brook | uint32_t hash; |
328 | 2a424990 | Paul Brook | |
329 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_PRMS) {
|
330 | 2a424990 | Paul Brook | return 1; |
331 | 2a424990 | Paul Brook | } |
332 | 2a424990 | Paul Brook | if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff && |
333 | 2a424990 | Paul Brook | addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) { |
334 | 2a424990 | Paul Brook | return (s->mac_cr & MAC_CR_BCAST) == 0; |
335 | 2a424990 | Paul Brook | } |
336 | 2a424990 | Paul Brook | |
337 | 2a424990 | Paul Brook | multicast = addr[0] & 1; |
338 | 2a424990 | Paul Brook | if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
|
339 | 2a424990 | Paul Brook | return 1; |
340 | 2a424990 | Paul Brook | } |
341 | 2a424990 | Paul Brook | if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0 |
342 | 2a424990 | Paul Brook | : (s->mac_cr & MAC_CR_HO) == 0) {
|
343 | 2a424990 | Paul Brook | /* Exact matching. */
|
344 | 2a424990 | Paul Brook | hash = memcmp(addr, s->conf.macaddr.a, 6);
|
345 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_INVFILT) {
|
346 | 2a424990 | Paul Brook | return hash != 0; |
347 | 2a424990 | Paul Brook | } else {
|
348 | 2a424990 | Paul Brook | return hash == 0; |
349 | 2a424990 | Paul Brook | } |
350 | 2a424990 | Paul Brook | } else {
|
351 | 2a424990 | Paul Brook | /* Hash matching */
|
352 | 2a424990 | Paul Brook | hash = (crc32(~0, addr, 6) >> 26); |
353 | 2a424990 | Paul Brook | if (hash & 0x20) { |
354 | 2a424990 | Paul Brook | return (s->mac_hashh >> (hash & 0x1f)) & 1; |
355 | 2a424990 | Paul Brook | } else {
|
356 | 2a424990 | Paul Brook | return (s->mac_hashl >> (hash & 0x1f)) & 1; |
357 | 2a424990 | Paul Brook | } |
358 | 2a424990 | Paul Brook | } |
359 | 2a424990 | Paul Brook | } |
360 | 2a424990 | Paul Brook | |
361 | 2a424990 | Paul Brook | static ssize_t lan9118_receive(VLANClientState *vc, const uint8_t *buf, |
362 | 2a424990 | Paul Brook | size_t size) |
363 | 2a424990 | Paul Brook | { |
364 | 2a424990 | Paul Brook | lan9118_state *s = vc->opaque; |
365 | 2a424990 | Paul Brook | int fifo_len;
|
366 | 2a424990 | Paul Brook | int offset;
|
367 | 2a424990 | Paul Brook | int src_pos;
|
368 | 2a424990 | Paul Brook | int n;
|
369 | 2a424990 | Paul Brook | int filter;
|
370 | 2a424990 | Paul Brook | uint32_t val; |
371 | 2a424990 | Paul Brook | uint32_t crc; |
372 | 2a424990 | Paul Brook | uint32_t status; |
373 | 2a424990 | Paul Brook | |
374 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) == 0) { |
375 | 2a424990 | Paul Brook | return -1; |
376 | 2a424990 | Paul Brook | } |
377 | 2a424990 | Paul Brook | |
378 | 2a424990 | Paul Brook | if (size >= 2048 || size < 14) { |
379 | 2a424990 | Paul Brook | return -1; |
380 | 2a424990 | Paul Brook | } |
381 | 2a424990 | Paul Brook | |
382 | 2a424990 | Paul Brook | /* TODO: Implement FIFO overflow notification. */
|
383 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
|
384 | 2a424990 | Paul Brook | return -1; |
385 | 2a424990 | Paul Brook | } |
386 | 2a424990 | Paul Brook | |
387 | 2a424990 | Paul Brook | filter = lan9118_filter(s, buf); |
388 | 2a424990 | Paul Brook | if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) { |
389 | 2a424990 | Paul Brook | return size;
|
390 | 2a424990 | Paul Brook | } |
391 | 2a424990 | Paul Brook | |
392 | 2a424990 | Paul Brook | offset = (s->rx_cfg >> 8) & 0x1f; |
393 | 2a424990 | Paul Brook | n = offset & 3;
|
394 | 2a424990 | Paul Brook | fifo_len = (size + n + 3) >> 2; |
395 | 2a424990 | Paul Brook | /* Add a word for the CRC. */
|
396 | 2a424990 | Paul Brook | fifo_len++; |
397 | 2a424990 | Paul Brook | if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
|
398 | 2a424990 | Paul Brook | return -1; |
399 | 2a424990 | Paul Brook | } |
400 | 2a424990 | Paul Brook | |
401 | 2a424990 | Paul Brook | DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
|
402 | 2a424990 | Paul Brook | (int)size, fifo_len, filter ? "pass" : "fail"); |
403 | 2a424990 | Paul Brook | val = 0;
|
404 | 2a424990 | Paul Brook | crc = bswap32(crc32(~0, buf, size));
|
405 | 2a424990 | Paul Brook | for (src_pos = 0; src_pos < size; src_pos++) { |
406 | 2a424990 | Paul Brook | val = (val >> 8) | ((uint32_t)buf[src_pos] << 24); |
407 | 2a424990 | Paul Brook | n++; |
408 | 2a424990 | Paul Brook | if (n == 4) { |
409 | 2a424990 | Paul Brook | n = 0;
|
410 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
411 | 2a424990 | Paul Brook | val = 0;
|
412 | 2a424990 | Paul Brook | } |
413 | 2a424990 | Paul Brook | } |
414 | 2a424990 | Paul Brook | if (n) {
|
415 | 2a424990 | Paul Brook | val >>= ((4 - n) * 8); |
416 | 2a424990 | Paul Brook | val |= crc << (n * 8);
|
417 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
418 | 2a424990 | Paul Brook | val = crc >> ((4 - n) * 8); |
419 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
420 | 2a424990 | Paul Brook | } else {
|
421 | 2a424990 | Paul Brook | rx_fifo_push(s, crc); |
422 | 2a424990 | Paul Brook | } |
423 | 2a424990 | Paul Brook | n = s->rx_status_fifo_head + s->rx_status_fifo_used; |
424 | 2a424990 | Paul Brook | if (n >= s->rx_status_fifo_size) {
|
425 | 2a424990 | Paul Brook | n -= s->rx_status_fifo_size; |
426 | 2a424990 | Paul Brook | } |
427 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_tail] = fifo_len; |
428 | 2a424990 | Paul Brook | s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023; |
429 | 2a424990 | Paul Brook | s->rx_status_fifo_used++; |
430 | 2a424990 | Paul Brook | |
431 | 2a424990 | Paul Brook | status = (size + 4) << 16; |
432 | 2a424990 | Paul Brook | if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && |
433 | 2a424990 | Paul Brook | buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) { |
434 | 2a424990 | Paul Brook | status |= 0x00002000;
|
435 | 2a424990 | Paul Brook | } else if (buf[0] & 1) { |
436 | 2a424990 | Paul Brook | status |= 0x00000400;
|
437 | 2a424990 | Paul Brook | } |
438 | 2a424990 | Paul Brook | if (!filter) {
|
439 | 2a424990 | Paul Brook | status |= 0x40000000;
|
440 | 2a424990 | Paul Brook | } |
441 | 2a424990 | Paul Brook | s->rx_status_fifo[n] = status; |
442 | 2a424990 | Paul Brook | |
443 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) { |
444 | 2a424990 | Paul Brook | s->int_sts |= RSFL_INT; |
445 | 2a424990 | Paul Brook | } |
446 | 2a424990 | Paul Brook | lan9118_update(s); |
447 | 2a424990 | Paul Brook | |
448 | 2a424990 | Paul Brook | return size;
|
449 | 2a424990 | Paul Brook | } |
450 | 2a424990 | Paul Brook | |
451 | 2a424990 | Paul Brook | static uint32_t rx_fifo_pop(lan9118_state *s)
|
452 | 2a424990 | Paul Brook | { |
453 | 2a424990 | Paul Brook | int n;
|
454 | 2a424990 | Paul Brook | uint32_t val; |
455 | 2a424990 | Paul Brook | |
456 | 2a424990 | Paul Brook | if (s->rxp_size == 0 && s->rxp_pad == 0) { |
457 | 2a424990 | Paul Brook | s->rxp_size = s->rx_packet_size[s->rx_packet_size_head]; |
458 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
459 | 2a424990 | Paul Brook | if (s->rxp_size != 0) { |
460 | 2a424990 | Paul Brook | s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023; |
461 | 2a424990 | Paul Brook | s->rxp_offset = (s->rx_cfg >> 10) & 7; |
462 | 2a424990 | Paul Brook | n = s->rxp_offset + s->rxp_size; |
463 | 2a424990 | Paul Brook | switch (s->rx_cfg >> 30) { |
464 | 2a424990 | Paul Brook | case 1: |
465 | 2a424990 | Paul Brook | n = (-n) & 3;
|
466 | 2a424990 | Paul Brook | break;
|
467 | 2a424990 | Paul Brook | case 2: |
468 | 2a424990 | Paul Brook | n = (-n) & 7;
|
469 | 2a424990 | Paul Brook | break;
|
470 | 2a424990 | Paul Brook | default:
|
471 | 2a424990 | Paul Brook | n = 0;
|
472 | 2a424990 | Paul Brook | break;
|
473 | 2a424990 | Paul Brook | } |
474 | 2a424990 | Paul Brook | s->rxp_pad = n; |
475 | 2a424990 | Paul Brook | DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
|
476 | 2a424990 | Paul Brook | s->rxp_size, s->rxp_offset, s->rxp_pad); |
477 | 2a424990 | Paul Brook | } |
478 | 2a424990 | Paul Brook | } |
479 | 2a424990 | Paul Brook | if (s->rxp_offset > 0) { |
480 | 2a424990 | Paul Brook | s->rxp_offset--; |
481 | 2a424990 | Paul Brook | val = 0;
|
482 | 2a424990 | Paul Brook | } else if (s->rxp_size > 0) { |
483 | 2a424990 | Paul Brook | s->rxp_size--; |
484 | 2a424990 | Paul Brook | val = s->rx_fifo[s->rx_fifo_head++]; |
485 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
486 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
487 | 2a424990 | Paul Brook | } |
488 | 2a424990 | Paul Brook | s->rx_fifo_used--; |
489 | 2a424990 | Paul Brook | } else if (s->rxp_pad > 0) { |
490 | 2a424990 | Paul Brook | s->rxp_pad--; |
491 | 2a424990 | Paul Brook | val = 0;
|
492 | 2a424990 | Paul Brook | } else {
|
493 | 2a424990 | Paul Brook | DPRINTF("RX underflow\n");
|
494 | 2a424990 | Paul Brook | s->int_sts |= RXE_INT; |
495 | 2a424990 | Paul Brook | val = 0;
|
496 | 2a424990 | Paul Brook | } |
497 | 2a424990 | Paul Brook | lan9118_update(s); |
498 | 2a424990 | Paul Brook | return val;
|
499 | 2a424990 | Paul Brook | } |
500 | 2a424990 | Paul Brook | |
501 | 2a424990 | Paul Brook | static void do_tx_packet(lan9118_state *s) |
502 | 2a424990 | Paul Brook | { |
503 | 2a424990 | Paul Brook | int n;
|
504 | 2a424990 | Paul Brook | uint32_t status; |
505 | 2a424990 | Paul Brook | |
506 | 2a424990 | Paul Brook | /* FIXME: Honor TX disable, and allow queueing of packets. */
|
507 | 2a424990 | Paul Brook | if (s->phy_control & 0x4000) { |
508 | 2a424990 | Paul Brook | /* This assumes the receive routine doesn't touch the VLANClient. */
|
509 | 2a424990 | Paul Brook | lan9118_receive(s->vc, s->txp->data, s->txp->len); |
510 | 2a424990 | Paul Brook | } else {
|
511 | 2a424990 | Paul Brook | qemu_send_packet(s->vc, s->txp->data, s->txp->len); |
512 | 2a424990 | Paul Brook | } |
513 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
514 | 2a424990 | Paul Brook | |
515 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
516 | 2a424990 | Paul Brook | /* Status FIFO full */
|
517 | 2a424990 | Paul Brook | return;
|
518 | 2a424990 | Paul Brook | } |
519 | 2a424990 | Paul Brook | /* Add entry to status FIFO. */
|
520 | 2a424990 | Paul Brook | status = s->txp->cmd_b & 0xffff0000u;
|
521 | 2a424990 | Paul Brook | DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len); |
522 | 2a424990 | Paul Brook | n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
|
523 | 2a424990 | Paul Brook | s->tx_status_fifo[n] = status; |
524 | 2a424990 | Paul Brook | s->tx_status_fifo_used++; |
525 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
526 | 2a424990 | Paul Brook | s->int_sts |= TSFF_INT; |
527 | 2a424990 | Paul Brook | /* TODO: Stop transmission. */
|
528 | 2a424990 | Paul Brook | } |
529 | 2a424990 | Paul Brook | } |
530 | 2a424990 | Paul Brook | |
531 | 2a424990 | Paul Brook | static uint32_t rx_status_fifo_pop(lan9118_state *s)
|
532 | 2a424990 | Paul Brook | { |
533 | 2a424990 | Paul Brook | uint32_t val; |
534 | 2a424990 | Paul Brook | |
535 | 2a424990 | Paul Brook | val = s->rx_status_fifo[s->rx_status_fifo_head]; |
536 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used != 0) { |
537 | 2a424990 | Paul Brook | s->rx_status_fifo_used--; |
538 | 2a424990 | Paul Brook | s->rx_status_fifo_head++; |
539 | 2a424990 | Paul Brook | if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
|
540 | 2a424990 | Paul Brook | s->rx_status_fifo_head -= s->rx_status_fifo_size; |
541 | 2a424990 | Paul Brook | } |
542 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
543 | 2a424990 | Paul Brook | DPRINTF("RX status pop 0x%08x\n", val);
|
544 | 2a424990 | Paul Brook | } |
545 | 2a424990 | Paul Brook | return val;
|
546 | 2a424990 | Paul Brook | } |
547 | 2a424990 | Paul Brook | |
548 | 2a424990 | Paul Brook | static uint32_t tx_status_fifo_pop(lan9118_state *s)
|
549 | 2a424990 | Paul Brook | { |
550 | 2a424990 | Paul Brook | uint32_t val; |
551 | 2a424990 | Paul Brook | |
552 | 2a424990 | Paul Brook | val = s->tx_status_fifo[s->tx_status_fifo_head]; |
553 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used != 0) { |
554 | 2a424990 | Paul Brook | s->tx_status_fifo_used--; |
555 | 2a424990 | Paul Brook | s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511; |
556 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
557 | 2a424990 | Paul Brook | } |
558 | 2a424990 | Paul Brook | return val;
|
559 | 2a424990 | Paul Brook | } |
560 | 2a424990 | Paul Brook | |
561 | 2a424990 | Paul Brook | static void tx_fifo_push(lan9118_state *s, uint32_t val) |
562 | 2a424990 | Paul Brook | { |
563 | 2a424990 | Paul Brook | int n;
|
564 | 2a424990 | Paul Brook | |
565 | 2a424990 | Paul Brook | if (s->txp->fifo_used == s->tx_fifo_size) {
|
566 | 2a424990 | Paul Brook | s->int_sts |= TDFO_INT; |
567 | 2a424990 | Paul Brook | return;
|
568 | 2a424990 | Paul Brook | } |
569 | 2a424990 | Paul Brook | switch (s->txp->state) {
|
570 | 2a424990 | Paul Brook | case TX_IDLE:
|
571 | 2a424990 | Paul Brook | s->txp->cmd_a = val & 0x831f37ff;
|
572 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
573 | 2a424990 | Paul Brook | s->txp->state = TX_B; |
574 | 2a424990 | Paul Brook | break;
|
575 | 2a424990 | Paul Brook | case TX_B:
|
576 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x2000) { |
577 | 2a424990 | Paul Brook | /* First segment */
|
578 | 2a424990 | Paul Brook | s->txp->cmd_b = val; |
579 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
580 | 2a424990 | Paul Brook | s->txp->buffer_size = s->txp->cmd_a & 0x7ff;
|
581 | 2a424990 | Paul Brook | s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f; |
582 | 2a424990 | Paul Brook | /* End alignment does not include command words. */
|
583 | 2a424990 | Paul Brook | n = (s->txp->buffer_size + s->txp->offset + 3) >> 2; |
584 | 2a424990 | Paul Brook | switch ((n >> 24) & 3) { |
585 | 2a424990 | Paul Brook | case 1: |
586 | 2a424990 | Paul Brook | n = (-n) & 3;
|
587 | 2a424990 | Paul Brook | break;
|
588 | 2a424990 | Paul Brook | case 2: |
589 | 2a424990 | Paul Brook | n = (-n) & 7;
|
590 | 2a424990 | Paul Brook | break;
|
591 | 2a424990 | Paul Brook | default:
|
592 | 2a424990 | Paul Brook | n = 0;
|
593 | 2a424990 | Paul Brook | } |
594 | 2a424990 | Paul Brook | s->txp->pad = n; |
595 | 2a424990 | Paul Brook | s->txp->len = 0;
|
596 | 2a424990 | Paul Brook | } |
597 | 2a424990 | Paul Brook | DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
|
598 | 2a424990 | Paul Brook | s->txp->buffer_size, s->txp->offset, s->txp->pad, |
599 | 2a424990 | Paul Brook | s->txp->cmd_a); |
600 | 2a424990 | Paul Brook | s->txp->state = TX_DATA; |
601 | 2a424990 | Paul Brook | break;
|
602 | 2a424990 | Paul Brook | case TX_DATA:
|
603 | 2a424990 | Paul Brook | if (s->txp->offset >= 4) { |
604 | 2a424990 | Paul Brook | s->txp->offset -= 4;
|
605 | 2a424990 | Paul Brook | break;
|
606 | 2a424990 | Paul Brook | } |
607 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad != 0) { |
608 | 2a424990 | Paul Brook | s->txp->pad--; |
609 | 2a424990 | Paul Brook | } else {
|
610 | 2a424990 | Paul Brook | n = 4;
|
611 | 2a424990 | Paul Brook | while (s->txp->offset) {
|
612 | 2a424990 | Paul Brook | val >>= 8;
|
613 | 2a424990 | Paul Brook | n--; |
614 | 2a424990 | Paul Brook | s->txp->offset--; |
615 | 2a424990 | Paul Brook | } |
616 | 2a424990 | Paul Brook | /* Documentation is somewhat unclear on the ordering of bytes
|
617 | 2a424990 | Paul Brook | in FIFO words. Empirical results show it to be little-endian.
|
618 | 2a424990 | Paul Brook | */
|
619 | 2a424990 | Paul Brook | /* TODO: FIFO overflow checking. */
|
620 | 2a424990 | Paul Brook | while (n--) {
|
621 | 2a424990 | Paul Brook | s->txp->data[s->txp->len] = val & 0xff;
|
622 | 2a424990 | Paul Brook | s->txp->len++; |
623 | 2a424990 | Paul Brook | val >>= 8;
|
624 | 2a424990 | Paul Brook | s->txp->buffer_size--; |
625 | 2a424990 | Paul Brook | } |
626 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
627 | 2a424990 | Paul Brook | } |
628 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad == 0) { |
629 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x1000) { |
630 | 2a424990 | Paul Brook | do_tx_packet(s); |
631 | 2a424990 | Paul Brook | } |
632 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x80000000) { |
633 | 2a424990 | Paul Brook | s->int_sts |= TX_IOC_INT; |
634 | 2a424990 | Paul Brook | } |
635 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
636 | 2a424990 | Paul Brook | } |
637 | 2a424990 | Paul Brook | break;
|
638 | 2a424990 | Paul Brook | } |
639 | 2a424990 | Paul Brook | } |
640 | 2a424990 | Paul Brook | |
641 | 2a424990 | Paul Brook | static uint32_t do_phy_read(lan9118_state *s, int reg) |
642 | 2a424990 | Paul Brook | { |
643 | 2a424990 | Paul Brook | switch (reg) {
|
644 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
645 | 2a424990 | Paul Brook | return s->phy_control;
|
646 | 2a424990 | Paul Brook | case 1: /* Basic Status */ |
647 | 2a424990 | Paul Brook | return s->phy_status;
|
648 | 2a424990 | Paul Brook | case 2: /* ID1 */ |
649 | 2a424990 | Paul Brook | return 0x0007; |
650 | 2a424990 | Paul Brook | case 3: /* ID2 */ |
651 | 2a424990 | Paul Brook | return 0xc0d1; |
652 | 2a424990 | Paul Brook | case 4: /* Auto-neg advertisment */ |
653 | 2a424990 | Paul Brook | return s->phy_advertise;
|
654 | 2a424990 | Paul Brook | case 5: /* Auto-neg Link Partner Ability */ |
655 | 2a424990 | Paul Brook | return 0x0f71; |
656 | 2a424990 | Paul Brook | case 6: /* Auto-neg Expansion */ |
657 | 2a424990 | Paul Brook | return 1; |
658 | 2a424990 | Paul Brook | /* TODO 17, 18, 27, 29, 30, 31 */
|
659 | 2a424990 | Paul Brook | default:
|
660 | 2a424990 | Paul Brook | BADF("PHY read reg %d\n", reg);
|
661 | 2a424990 | Paul Brook | return 0; |
662 | 2a424990 | Paul Brook | } |
663 | 2a424990 | Paul Brook | } |
664 | 2a424990 | Paul Brook | |
665 | 2a424990 | Paul Brook | static void do_phy_write(lan9118_state *s, int reg, uint32_t val) |
666 | 2a424990 | Paul Brook | { |
667 | 2a424990 | Paul Brook | switch (reg) {
|
668 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
669 | 2a424990 | Paul Brook | if (val & 0x8000) { |
670 | 2a424990 | Paul Brook | phy_reset(s); |
671 | 2a424990 | Paul Brook | break;
|
672 | 2a424990 | Paul Brook | } |
673 | 2a424990 | Paul Brook | s->phy_control = val & 0x7980;
|
674 | 2a424990 | Paul Brook | /* Complete autonegotiation imediately. */
|
675 | 2a424990 | Paul Brook | if (val & 0x1000) { |
676 | 2a424990 | Paul Brook | s->phy_status |= 0x0020;
|
677 | 2a424990 | Paul Brook | } |
678 | 2a424990 | Paul Brook | break;
|
679 | 2a424990 | Paul Brook | case 4: /* Auto-neg advertisment */ |
680 | 2a424990 | Paul Brook | s->phy_advertise = (val & 0x2d7f) | 0x80; |
681 | 2a424990 | Paul Brook | break;
|
682 | 2a424990 | Paul Brook | /* TODO 17, 18, 27, 29, 30, 31 */
|
683 | 2a424990 | Paul Brook | default:
|
684 | 2a424990 | Paul Brook | BADF("PHY write reg %d = 0x%04x\n", reg, val);
|
685 | 2a424990 | Paul Brook | } |
686 | 2a424990 | Paul Brook | } |
687 | 2a424990 | Paul Brook | |
688 | 2a424990 | Paul Brook | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) |
689 | 2a424990 | Paul Brook | { |
690 | 2a424990 | Paul Brook | switch (reg) {
|
691 | 2a424990 | Paul Brook | case MAC_CR:
|
692 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) { |
693 | 2a424990 | Paul Brook | s->int_sts |= RXSTOP_INT; |
694 | 2a424990 | Paul Brook | } |
695 | 2a424990 | Paul Brook | s->mac_cr = val & ~MAC_CR_RESERVED; |
696 | 2a424990 | Paul Brook | DPRINTF("MAC_CR: %08x\n", val);
|
697 | 2a424990 | Paul Brook | break;
|
698 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
699 | 2a424990 | Paul Brook | s->conf.macaddr.a[4] = val & 0xff; |
700 | 2a424990 | Paul Brook | s->conf.macaddr.a[5] = (val >> 8) & 0xff; |
701 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
702 | 2a424990 | Paul Brook | break;
|
703 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
704 | 2a424990 | Paul Brook | s->conf.macaddr.a[0] = val & 0xff; |
705 | 2a424990 | Paul Brook | s->conf.macaddr.a[1] = (val >> 8) & 0xff; |
706 | 2a424990 | Paul Brook | s->conf.macaddr.a[2] = (val >> 16) & 0xff; |
707 | 2a424990 | Paul Brook | s->conf.macaddr.a[3] = (val >> 24) & 0xff; |
708 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
709 | 2a424990 | Paul Brook | break;
|
710 | 2a424990 | Paul Brook | case MAC_HASHH:
|
711 | 2a424990 | Paul Brook | s->mac_hashh = val; |
712 | 2a424990 | Paul Brook | break;
|
713 | 2a424990 | Paul Brook | case MAC_HASHL:
|
714 | 2a424990 | Paul Brook | s->mac_hashl = val; |
715 | 2a424990 | Paul Brook | break;
|
716 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
717 | 2a424990 | Paul Brook | s->mac_mii_acc = val & 0xffc2;
|
718 | 2a424990 | Paul Brook | if (val & 2) { |
719 | 2a424990 | Paul Brook | DPRINTF("PHY write %d = 0x%04x\n",
|
720 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
721 | 2a424990 | Paul Brook | do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); |
722 | 2a424990 | Paul Brook | } else {
|
723 | 2a424990 | Paul Brook | s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); |
724 | 2a424990 | Paul Brook | DPRINTF("PHY read %d = 0x%04x\n",
|
725 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
726 | 2a424990 | Paul Brook | } |
727 | 2a424990 | Paul Brook | break;
|
728 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
729 | 2a424990 | Paul Brook | s->mac_mii_data = val & 0xffff;
|
730 | 2a424990 | Paul Brook | break;
|
731 | 2a424990 | Paul Brook | case MAC_FLOW:
|
732 | 2a424990 | Paul Brook | s->mac_flow = val & 0xffff0000;
|
733 | 2a424990 | Paul Brook | break;
|
734 | 2a424990 | Paul Brook | default:
|
735 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
|
736 | 2a424990 | Paul Brook | s->mac_cmd & 0xf, val);
|
737 | 2a424990 | Paul Brook | } |
738 | 2a424990 | Paul Brook | } |
739 | 2a424990 | Paul Brook | |
740 | 2a424990 | Paul Brook | static uint32_t do_mac_read(lan9118_state *s, int reg) |
741 | 2a424990 | Paul Brook | { |
742 | 2a424990 | Paul Brook | switch (reg) {
|
743 | 2a424990 | Paul Brook | case MAC_CR:
|
744 | 2a424990 | Paul Brook | return s->mac_cr;
|
745 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
746 | 2a424990 | Paul Brook | return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); |
747 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
748 | 2a424990 | Paul Brook | return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) |
749 | 2a424990 | Paul Brook | | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24); |
750 | 2a424990 | Paul Brook | case MAC_HASHH:
|
751 | 2a424990 | Paul Brook | return s->mac_hashh;
|
752 | 2a424990 | Paul Brook | break;
|
753 | 2a424990 | Paul Brook | case MAC_HASHL:
|
754 | 2a424990 | Paul Brook | return s->mac_hashl;
|
755 | 2a424990 | Paul Brook | break;
|
756 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
757 | 2a424990 | Paul Brook | return s->mac_mii_acc;
|
758 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
759 | 2a424990 | Paul Brook | return s->mac_mii_data;
|
760 | 2a424990 | Paul Brook | case MAC_FLOW:
|
761 | 2a424990 | Paul Brook | return s->mac_flow;
|
762 | 2a424990 | Paul Brook | default:
|
763 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register read: %d\n",
|
764 | 2a424990 | Paul Brook | s->mac_cmd & 0xf);
|
765 | 2a424990 | Paul Brook | } |
766 | 2a424990 | Paul Brook | } |
767 | 2a424990 | Paul Brook | |
768 | 2a424990 | Paul Brook | static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr) |
769 | 2a424990 | Paul Brook | { |
770 | 2a424990 | Paul Brook | s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr; |
771 | 2a424990 | Paul Brook | switch (cmd) {
|
772 | 2a424990 | Paul Brook | case 0: |
773 | 2a424990 | Paul Brook | s->e2p_data = s->eeprom[addr]; |
774 | 2a424990 | Paul Brook | DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
|
775 | 2a424990 | Paul Brook | break;
|
776 | 2a424990 | Paul Brook | case 1: |
777 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
|
778 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Disable\n");
|
779 | 2a424990 | Paul Brook | break;
|
780 | 2a424990 | Paul Brook | case 2: /* EWEN */ |
781 | 2a424990 | Paul Brook | s->eeprom_writable = 1;
|
782 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Enable\n");
|
783 | 2a424990 | Paul Brook | break;
|
784 | 2a424990 | Paul Brook | case 3: /* WRITE */ |
785 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
786 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
787 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
|
788 | 2a424990 | Paul Brook | } else {
|
789 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d (ignored)\n", addr);
|
790 | 2a424990 | Paul Brook | } |
791 | 2a424990 | Paul Brook | break;
|
792 | 2a424990 | Paul Brook | case 4: /* WRAL */ |
793 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
794 | 2a424990 | Paul Brook | for (addr = 0; addr < 128; addr++) { |
795 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
796 | 2a424990 | Paul Brook | } |
797 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
|
798 | 2a424990 | Paul Brook | } else {
|
799 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All (ignored)\n");
|
800 | 2a424990 | Paul Brook | } |
801 | 2a424990 | Paul Brook | case 5: /* ERASE */ |
802 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
803 | 2a424990 | Paul Brook | s->eeprom[addr] = 0xff;
|
804 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d\n", addr);
|
805 | 2a424990 | Paul Brook | } else {
|
806 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d (ignored)\n", addr);
|
807 | 2a424990 | Paul Brook | } |
808 | 2a424990 | Paul Brook | break;
|
809 | 2a424990 | Paul Brook | case 6: /* ERAL */ |
810 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
811 | 2a424990 | Paul Brook | memset(s->eeprom, 0xff, 128); |
812 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All\n");
|
813 | 2a424990 | Paul Brook | } else {
|
814 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All (ignored)\n");
|
815 | 2a424990 | Paul Brook | } |
816 | 2a424990 | Paul Brook | break;
|
817 | 2a424990 | Paul Brook | case 7: /* RELOAD */ |
818 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
819 | 2a424990 | Paul Brook | break;
|
820 | 2a424990 | Paul Brook | } |
821 | 2a424990 | Paul Brook | } |
822 | 2a424990 | Paul Brook | |
823 | 2a424990 | Paul Brook | static void lan9118_writel(void *opaque, target_phys_addr_t offset, |
824 | 2a424990 | Paul Brook | uint32_t val) |
825 | 2a424990 | Paul Brook | { |
826 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
827 | 2a424990 | Paul Brook | offset &= 0xff;
|
828 | 2a424990 | Paul Brook | |
829 | 2a424990 | Paul Brook | //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
|
830 | 2a424990 | Paul Brook | if (offset >= 0x20 && offset < 0x40) { |
831 | 2a424990 | Paul Brook | /* TX FIFO */
|
832 | 2a424990 | Paul Brook | tx_fifo_push(s, val); |
833 | 2a424990 | Paul Brook | return;
|
834 | 2a424990 | Paul Brook | } |
835 | 2a424990 | Paul Brook | switch (offset) {
|
836 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
837 | 2a424990 | Paul Brook | /* TODO: Implement interrupt deassertion intervals. */
|
838 | 2a424990 | Paul Brook | s->irq_cfg = (val & IRQ_EN); |
839 | 2a424990 | Paul Brook | break;
|
840 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
841 | 2a424990 | Paul Brook | s->int_sts &= ~val; |
842 | 2a424990 | Paul Brook | break;
|
843 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
844 | 2a424990 | Paul Brook | s->int_en = val & ~RESERVED_INT; |
845 | 2a424990 | Paul Brook | s->int_sts |= val & SW_INT; |
846 | 2a424990 | Paul Brook | break;
|
847 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
848 | 2a424990 | Paul Brook | DPRINTF("FIFO INT levels %08x\n", val);
|
849 | 2a424990 | Paul Brook | s->fifo_int = val; |
850 | 2a424990 | Paul Brook | break;
|
851 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
852 | 2a424990 | Paul Brook | if (val & 0x8000) { |
853 | 2a424990 | Paul Brook | /* RX_DUMP */
|
854 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
|
855 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
|
856 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
857 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
858 | 2a424990 | Paul Brook | } |
859 | 2a424990 | Paul Brook | s->rx_cfg = val & 0xcfff1ff0;
|
860 | 2a424990 | Paul Brook | break;
|
861 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
862 | 2a424990 | Paul Brook | if (val & 0x8000) { |
863 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
|
864 | 2a424990 | Paul Brook | } |
865 | 2a424990 | Paul Brook | if (val & 0x4000) { |
866 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
867 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
868 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffff;
|
869 | 2a424990 | Paul Brook | } |
870 | 2a424990 | Paul Brook | s->tx_cfg = val & 6;
|
871 | 2a424990 | Paul Brook | break;
|
872 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
873 | 2a424990 | Paul Brook | if (val & 1) { |
874 | 2a424990 | Paul Brook | /* SRST */
|
875 | 2a424990 | Paul Brook | lan9118_reset(&s->busdev.qdev); |
876 | 2a424990 | Paul Brook | } else {
|
877 | 2a424990 | Paul Brook | s->hw_cfg = val & 0x003f300;
|
878 | 2a424990 | Paul Brook | } |
879 | 2a424990 | Paul Brook | break;
|
880 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
881 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
882 | 2a424990 | Paul Brook | /* Skip forward to next packet. */
|
883 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
884 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
885 | 2a424990 | Paul Brook | if (s->rxp_size == 0) { |
886 | 2a424990 | Paul Brook | /* Pop a word to start the next packet. */
|
887 | 2a424990 | Paul Brook | rx_fifo_pop(s); |
888 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
889 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
890 | 2a424990 | Paul Brook | } |
891 | 2a424990 | Paul Brook | s->rx_fifo_head += s->rxp_size; |
892 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
893 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
894 | 2a424990 | Paul Brook | } |
895 | 2a424990 | Paul Brook | } |
896 | 2a424990 | Paul Brook | break;
|
897 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
898 | 2a424990 | Paul Brook | if (val & 0x400) { |
899 | 2a424990 | Paul Brook | phy_reset(s); |
900 | 2a424990 | Paul Brook | } |
901 | 2a424990 | Paul Brook | s->pmt_ctrl &= ~0x34e;
|
902 | 2a424990 | Paul Brook | s->pmt_ctrl |= (val & 0x34e);
|
903 | 2a424990 | Paul Brook | break;
|
904 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
905 | 2a424990 | Paul Brook | /* Probably just enabling LEDs. */
|
906 | 2a424990 | Paul Brook | s->gpio_cfg = val & 0x7777071f;
|
907 | 2a424990 | Paul Brook | break;
|
908 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
909 | 2a424990 | Paul Brook | /* Ignored because we're in 32-bit mode. */
|
910 | 2a424990 | Paul Brook | s->word_swap = val; |
911 | 2a424990 | Paul Brook | break;
|
912 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
913 | 2a424990 | Paul Brook | s->mac_cmd = val & 0x4000000f;
|
914 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
915 | 2a424990 | Paul Brook | if (val & 0x40000000) { |
916 | 2a424990 | Paul Brook | s->mac_data = do_mac_read(s, val & 0xf);
|
917 | 2a424990 | Paul Brook | DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data); |
918 | 2a424990 | Paul Brook | } else {
|
919 | 2a424990 | Paul Brook | DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data); |
920 | 2a424990 | Paul Brook | do_mac_write(s, val & 0xf, s->mac_data);
|
921 | 2a424990 | Paul Brook | } |
922 | 2a424990 | Paul Brook | } |
923 | 2a424990 | Paul Brook | break;
|
924 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
925 | 2a424990 | Paul Brook | s->mac_data = val; |
926 | 2a424990 | Paul Brook | break;
|
927 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
928 | 2a424990 | Paul Brook | s->afc_cfg = val & 0x00ffffff;
|
929 | 2a424990 | Paul Brook | break;
|
930 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
931 | 2a424990 | Paul Brook | lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0xff); |
932 | 2a424990 | Paul Brook | break;
|
933 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
934 | 2a424990 | Paul Brook | s->e2p_data = val & 0xff;
|
935 | 2a424990 | Paul Brook | break;
|
936 | 2a424990 | Paul Brook | |
937 | 2a424990 | Paul Brook | default:
|
938 | 2a424990 | Paul Brook | hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, val); |
939 | 2a424990 | Paul Brook | break;
|
940 | 2a424990 | Paul Brook | } |
941 | 2a424990 | Paul Brook | lan9118_update(s); |
942 | 2a424990 | Paul Brook | } |
943 | 2a424990 | Paul Brook | |
944 | 2a424990 | Paul Brook | static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset) |
945 | 2a424990 | Paul Brook | { |
946 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
947 | 2a424990 | Paul Brook | |
948 | 2a424990 | Paul Brook | //DPRINTF("Read reg 0x%02x\n", (int)offset);
|
949 | 2a424990 | Paul Brook | if (offset < 0x20) { |
950 | 2a424990 | Paul Brook | /* RX FIFO */
|
951 | 2a424990 | Paul Brook | return rx_fifo_pop(s);
|
952 | 2a424990 | Paul Brook | } |
953 | 2a424990 | Paul Brook | switch (offset) {
|
954 | 2a424990 | Paul Brook | case 0x40: |
955 | 2a424990 | Paul Brook | return rx_status_fifo_pop(s);
|
956 | 2a424990 | Paul Brook | case 0x44: |
957 | 2a424990 | Paul Brook | return s->rx_status_fifo[s->tx_status_fifo_head];
|
958 | 2a424990 | Paul Brook | case 0x48: |
959 | 2a424990 | Paul Brook | return tx_status_fifo_pop(s);
|
960 | 2a424990 | Paul Brook | case 0x4c: |
961 | 2a424990 | Paul Brook | return s->tx_status_fifo[s->tx_status_fifo_head];
|
962 | 2a424990 | Paul Brook | case CSR_ID_REV:
|
963 | 2a424990 | Paul Brook | return 0x01180001; |
964 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
965 | 2a424990 | Paul Brook | return s->irq_cfg;
|
966 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
967 | 2a424990 | Paul Brook | return s->int_sts;
|
968 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
969 | 2a424990 | Paul Brook | return s->int_en;
|
970 | 2a424990 | Paul Brook | case CSR_BYTE_TEST:
|
971 | 2a424990 | Paul Brook | return 0x87654321; |
972 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
973 | 2a424990 | Paul Brook | return s->fifo_int;
|
974 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
975 | 2a424990 | Paul Brook | return s->rx_cfg;
|
976 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
977 | 2a424990 | Paul Brook | return s->tx_cfg;
|
978 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
979 | 2a424990 | Paul Brook | return s->hw_cfg | 0x4; |
980 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
981 | 2a424990 | Paul Brook | return 0; |
982 | 2a424990 | Paul Brook | case CSR_RX_FIFO_INF:
|
983 | 2a424990 | Paul Brook | return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2); |
984 | 2a424990 | Paul Brook | case CSR_TX_FIFO_INF:
|
985 | 2a424990 | Paul Brook | return (s->tx_status_fifo_used << 16) |
986 | 2a424990 | Paul Brook | | (s->tx_fifo_size - s->txp->fifo_used); |
987 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
988 | 2a424990 | Paul Brook | return s->pmt_ctrl;
|
989 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
990 | 2a424990 | Paul Brook | return s->gpio_cfg;
|
991 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
992 | 2a424990 | Paul Brook | return s->word_swap;
|
993 | 2a424990 | Paul Brook | case CSR_FREE_RUN:
|
994 | 2a424990 | Paul Brook | return (qemu_get_clock(vm_clock) / 40) - s->free_timer_start; |
995 | 2a424990 | Paul Brook | case CSR_RX_DROP:
|
996 | 2a424990 | Paul Brook | /* TODO: Implement dropped frames counter. */
|
997 | 2a424990 | Paul Brook | return 0; |
998 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
999 | 2a424990 | Paul Brook | return s->mac_cmd;
|
1000 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
1001 | 2a424990 | Paul Brook | return s->mac_data;
|
1002 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
1003 | 2a424990 | Paul Brook | return s->afc_cfg;
|
1004 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
1005 | 2a424990 | Paul Brook | return s->e2p_cmd;
|
1006 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
1007 | 2a424990 | Paul Brook | return s->e2p_data;
|
1008 | 2a424990 | Paul Brook | } |
1009 | 2a424990 | Paul Brook | hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset); |
1010 | 2a424990 | Paul Brook | return 0; |
1011 | 2a424990 | Paul Brook | } |
1012 | 2a424990 | Paul Brook | |
1013 | 2a424990 | Paul Brook | static CPUReadMemoryFunc * const lan9118_readfn[] = { |
1014 | 2a424990 | Paul Brook | lan9118_readl, |
1015 | 2a424990 | Paul Brook | lan9118_readl, |
1016 | 2a424990 | Paul Brook | lan9118_readl |
1017 | 2a424990 | Paul Brook | }; |
1018 | 2a424990 | Paul Brook | |
1019 | 2a424990 | Paul Brook | static CPUWriteMemoryFunc * const lan9118_writefn[] = { |
1020 | 2a424990 | Paul Brook | lan9118_writel, |
1021 | 2a424990 | Paul Brook | lan9118_writel, |
1022 | 2a424990 | Paul Brook | lan9118_writel |
1023 | 2a424990 | Paul Brook | }; |
1024 | 2a424990 | Paul Brook | |
1025 | 2a424990 | Paul Brook | static void lan9118_cleanup(VLANClientState *vc) |
1026 | 2a424990 | Paul Brook | { |
1027 | 2a424990 | Paul Brook | lan9118_state *s = vc->opaque; |
1028 | 2a424990 | Paul Brook | |
1029 | 2a424990 | Paul Brook | s->vc = NULL;
|
1030 | 2a424990 | Paul Brook | } |
1031 | 2a424990 | Paul Brook | |
1032 | 2a424990 | Paul Brook | static int lan9118_init1(SysBusDevice *dev) |
1033 | 2a424990 | Paul Brook | { |
1034 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, dev); |
1035 | 2a424990 | Paul Brook | int i;
|
1036 | 2a424990 | Paul Brook | |
1037 | 2a424990 | Paul Brook | s->mmio_index = cpu_register_io_memory(lan9118_readfn, |
1038 | 2a424990 | Paul Brook | lan9118_writefn, s); |
1039 | 2a424990 | Paul Brook | sysbus_init_mmio(dev, 0x100, s->mmio_index);
|
1040 | 2a424990 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
1041 | 2a424990 | Paul Brook | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
1042 | 2a424990 | Paul Brook | |
1043 | 2a424990 | Paul Brook | s->vc = qemu_new_vlan_client(NET_CLIENT_TYPE_NIC, |
1044 | 2a424990 | Paul Brook | s->conf.vlan, s->conf.peer, |
1045 | 2a424990 | Paul Brook | dev->qdev.info->name, dev->qdev.id, |
1046 | 2a424990 | Paul Brook | lan9118_can_receive, lan9118_receive, NULL,
|
1047 | 2a424990 | Paul Brook | NULL, lan9118_cleanup, s);
|
1048 | 2a424990 | Paul Brook | s->vc->link_status_changed = lan9118_set_link; |
1049 | 2a424990 | Paul Brook | qemu_format_nic_info_str(s->vc, s->conf.macaddr.a); |
1050 | 2a424990 | Paul Brook | s->eeprom[0] = 0xa5; |
1051 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
1052 | 2a424990 | Paul Brook | s->eeprom[i + 1] = s->conf.macaddr.a[i];
|
1053 | 2a424990 | Paul Brook | } |
1054 | 2a424990 | Paul Brook | s->pmt_ctrl = 1;
|
1055 | 2a424990 | Paul Brook | s->txp = &s->tx_packet; |
1056 | 2a424990 | Paul Brook | |
1057 | 2a424990 | Paul Brook | /* ??? Save/restore. */
|
1058 | 2a424990 | Paul Brook | return 0; |
1059 | 2a424990 | Paul Brook | } |
1060 | 2a424990 | Paul Brook | |
1061 | 2a424990 | Paul Brook | static SysBusDeviceInfo lan9118_info = {
|
1062 | 2a424990 | Paul Brook | .init = lan9118_init1, |
1063 | 2a424990 | Paul Brook | .qdev.name = "lan9118",
|
1064 | 2a424990 | Paul Brook | .qdev.size = sizeof(lan9118_state),
|
1065 | 2a424990 | Paul Brook | .qdev.reset = lan9118_reset, |
1066 | 2a424990 | Paul Brook | .qdev.props = (Property[]) { |
1067 | 2a424990 | Paul Brook | DEFINE_NIC_PROPERTIES(lan9118_state, conf), |
1068 | 2a424990 | Paul Brook | DEFINE_PROP_END_OF_LIST(), |
1069 | 2a424990 | Paul Brook | } |
1070 | 2a424990 | Paul Brook | }; |
1071 | 2a424990 | Paul Brook | |
1072 | 2a424990 | Paul Brook | static void lan9118_register_devices(void) |
1073 | 2a424990 | Paul Brook | { |
1074 | 2a424990 | Paul Brook | sysbus_register_withprop(&lan9118_info); |
1075 | 2a424990 | Paul Brook | } |
1076 | 2a424990 | Paul Brook | |
1077 | 2a424990 | Paul Brook | /* Legacy helper function. Should go away when machine config files are
|
1078 | 2a424990 | Paul Brook | implemented. */
|
1079 | 2a424990 | Paul Brook | void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
|
1080 | 2a424990 | Paul Brook | { |
1081 | 2a424990 | Paul Brook | DeviceState *dev; |
1082 | 2a424990 | Paul Brook | SysBusDevice *s; |
1083 | 2a424990 | Paul Brook | |
1084 | 2a424990 | Paul Brook | qemu_check_nic_model(nd, "lan9118");
|
1085 | 2a424990 | Paul Brook | dev = qdev_create(NULL, "lan9118"); |
1086 | 2a424990 | Paul Brook | qdev_set_nic_properties(dev, nd); |
1087 | 2a424990 | Paul Brook | qdev_init_nofail(dev); |
1088 | 2a424990 | Paul Brook | s = sysbus_from_qdev(dev); |
1089 | 2a424990 | Paul Brook | sysbus_mmio_map(s, 0, base);
|
1090 | 2a424990 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
1091 | 2a424990 | Paul Brook | } |
1092 | 2a424990 | Paul Brook | |
1093 | 2a424990 | Paul Brook | device_init(lan9118_register_devices) |