Revision 2aae2b8e target-sparc/cpu.h

b/target-sparc/cpu.h
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#define PSR_CARRY_SHIFT 20
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#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
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#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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#if !defined(TARGET_SPARC64)
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#define PSR_EF    (1<<12)
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#define PSR_PIL   0xf00
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#define PSR_S     (1<<7)
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#define PSR_PS    (1<<6)
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#define PSR_ET    (1<<5)
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#define PSR_CWP   0x1f
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#endif
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#define CC_SRC (env->cc_src)
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#define CC_SRC2 (env->cc_src2)
......
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    uint32_t wim;      /* window invalid mask */
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#endif
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    target_ulong tbr;  /* trap base register */
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#if !defined(TARGET_SPARC64)
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    int      psrs;     /* supervisor mode (extracted from PSR) */
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    int      psrps;    /* previous supervisor mode */
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#if !defined(TARGET_SPARC64)
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    int      psret;    /* enable traps */
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#endif
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    uint32_t psrpil;   /* interrupt blocking level */
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    uint32_t pil_in;   /* incoming interrupt level bitmap */
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#if !defined(TARGET_SPARC64)
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    int      psref;    /* enable fpu */
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#endif
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    target_ulong version;
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    int interrupt_index;
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    uint32_t nwindows;
......
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#define CPU_SAVE_VERSION 6
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/* MMU modes definitions */
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#if defined (TARGET_SPARC64)
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#define MMU_USER_IDX   0
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#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel
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#ifdef TARGET_SPARC64
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#define MMU_MODE2_SUFFIX _hypv
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#define MMU_MODE3_SUFFIX _nucleus
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#define MMU_MODE4_SUFFIX _user_secondary
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#define MMU_MODE5_SUFFIX _kernel_secondary
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#endif
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#define MMU_USER_SECONDARY_IDX   1
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#define MMU_MODE1_SUFFIX _user_secondary
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#define MMU_KERNEL_IDX 2
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#define MMU_MODE2_SUFFIX _kernel
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#define MMU_KERNEL_SECONDARY_IDX 3
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#define MMU_MODE3_SUFFIX _kernel_secondary
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#define MMU_NUCLEUS_IDX 4
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#define MMU_MODE4_SUFFIX _nucleus
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#define MMU_HYPV_IDX   5
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#define MMU_MODE5_SUFFIX _hypv
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#else
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#define MMU_USER_IDX   0
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#define MMU_MODE0_SUFFIX _user
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#define MMU_KERNEL_IDX 1
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#define MMU_HYPV_IDX   2
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#ifdef TARGET_SPARC64
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#define MMU_NUCLEUS_IDX 3
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#define MMU_USER_SECONDARY_IDX   4
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#define MMU_KERNEL_SECONDARY_IDX 5
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#define MMU_MODE1_SUFFIX _kernel
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#endif
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#if defined (TARGET_SPARC64)
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static inline int cpu_has_hypervisor(CPUState *env1)
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{
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    return env1->def->features & CPU_FEATURE_HYPV;
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}
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static inline int cpu_hypervisor_mode(CPUState *env1)
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{
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    return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
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}
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static inline int cpu_supervisor_mode(CPUState *env1)
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{
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    return env1->pstate & PS_PRIV;
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}
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#endif
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static inline int cpu_mmu_index(CPUState *env1)
......
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#elif !defined(TARGET_SPARC64)
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    return env1->psrs;
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#else
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    if (!env1->psrs)
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        return MMU_USER_IDX;
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    else if ((env1->hpstate & HS_PRIV) == 0)
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        return MMU_KERNEL_IDX;
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    else
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    if (cpu_hypervisor_mode(env1)) {
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        return MMU_HYPV_IDX;
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    } else if (cpu_supervisor_mode(env1)) {
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        return MMU_KERNEL_IDX;
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    } else {
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        return MMU_USER_IDX;
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    }
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#endif
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}
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