Revision 2ac71179 hw/armv7m_nvic.c
| b/hw/armv7m_nvic.c | ||
|---|---|---|
| 102 | 102 |
|
| 103 | 103 |
irq = gic_acknowledge_irq(s->gic, 0); |
| 104 | 104 |
if (irq == 1023) |
| 105 |
cpu_abort(cpu_single_env, "Interrupt but no vector\n");
|
|
| 105 |
hw_error("Interrupt but no vector\n");
|
|
| 106 | 106 |
if (irq >= 32) |
| 107 | 107 |
irq -= 16; |
| 108 | 108 |
return irq; |
| ... | ... | |
| 221 | 221 |
return val; |
| 222 | 222 |
case 0xd28: /* Configurable Fault Status. */ |
| 223 | 223 |
/* TODO: Implement Fault Status. */ |
| 224 |
cpu_abort(cpu_single_env, |
|
| 225 |
"Not implemented: Configurable Fault Status."); |
|
| 224 |
hw_error("Not implemented: Configurable Fault Status.");
|
|
| 226 | 225 |
return 0; |
| 227 | 226 |
case 0xd2c: /* Hard Fault Status. */ |
| 228 | 227 |
case 0xd30: /* Debug Fault Status. */ |
| ... | ... | |
| 260 | 259 |
/* TODO: Implement debug registers. */ |
| 261 | 260 |
default: |
| 262 | 261 |
bad_reg: |
| 263 |
cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
|
|
| 262 |
hw_error("NVIC: Bad read offset 0x%x\n", offset);
|
|
| 264 | 263 |
} |
| 265 | 264 |
} |
| 266 | 265 |
|
| ... | ... | |
| 324 | 323 |
case 0xd0c: /* Application Interrupt/Reset Control. */ |
| 325 | 324 |
if ((value >> 16) == 0x05fa) {
|
| 326 | 325 |
if (value & 2) {
|
| 327 |
cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
|
|
| 326 |
hw_error("VECTCLRACTIVE not implemented");
|
|
| 328 | 327 |
} |
| 329 | 328 |
if (value & 5) {
|
| 330 |
cpu_abort(cpu_single_env, "System reset");
|
|
| 329 |
hw_error("System reset");
|
|
| 331 | 330 |
} |
| 332 | 331 |
} |
| 333 | 332 |
break; |
| ... | ... | |
| 362 | 361 |
goto bad_reg; |
| 363 | 362 |
default: |
| 364 | 363 |
bad_reg: |
| 365 |
cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
|
|
| 364 |
hw_error("NVIC: Bad write offset 0x%x\n", offset);
|
|
| 366 | 365 |
} |
| 367 | 366 |
} |
| 368 | 367 |
|
| ... | ... | |
| 402 | 401 |
s->gic->nvic = s; |
| 403 | 402 |
s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s); |
| 404 | 403 |
if (env->v7m.nvic) |
| 405 |
cpu_abort(env, "CPU can only have one NVIC\n");
|
|
| 404 |
hw_error("CPU can only have one NVIC\n");
|
|
| 406 | 405 |
env->v7m.nvic = s; |
| 407 | 406 |
register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
|
| 408 | 407 |
return s->gic->in; |
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