Revision 2ac71179 hw/integratorcp.c
| b/hw/integratorcp.c | ||
|---|---|---|
| 63 | 63 |
} |
| 64 | 64 |
case 6: /* CM_LMBUSCNT */ |
| 65 | 65 |
/* ??? High frequency timer. */ |
| 66 |
cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
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|
| 66 |
hw_error("integratorcm_read: CM_LMBUSCNT");
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|
| 67 | 67 |
case 7: /* CM_AUXOSC */ |
| 68 | 68 |
return s->cm_auxosc; |
| 69 | 69 |
case 8: /* CM_SDRAM */ |
| ... | ... | |
| 72 | 72 |
return s->cm_init; |
| 73 | 73 |
case 10: /* CM_REFCT */ |
| 74 | 74 |
/* ??? High frequency timer. */ |
| 75 |
cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
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|
| 75 |
hw_error("integratorcm_read: CM_REFCT");
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|
| 76 | 76 |
case 12: /* CM_FLAGS */ |
| 77 | 77 |
return s->cm_flags; |
| 78 | 78 |
case 14: /* CM_NVFLAGS */ |
| ... | ... | |
| 98 | 98 |
/* ??? Voltage control unimplemented. */ |
| 99 | 99 |
return 0; |
| 100 | 100 |
default: |
| 101 |
cpu_abort (cpu_single_env,
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|
| 102 |
"integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
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|
| 101 |
hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
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|
| 102 |
(int)offset);
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|
| 103 | 103 |
return 0; |
| 104 | 104 |
} |
| 105 | 105 |
} |
| ... | ... | |
| 117 | 117 |
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value) |
| 118 | 118 |
{
|
| 119 | 119 |
if (value & 8) {
|
| 120 |
cpu_abort(cpu_single_env, "Board reset\n");
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|
| 120 |
hw_error("Board reset\n");
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|
| 121 | 121 |
} |
| 122 | 122 |
if ((s->cm_init ^ value) & 4) {
|
| 123 | 123 |
integratorcm_do_remap(s, (value & 4) == 0); |
| ... | ... | |
| 133 | 133 |
/* ??? The CPU irq/fiq is raised when either the core module or base PIC |
| 134 | 134 |
are active. */ |
| 135 | 135 |
if (s->int_level & (s->irq_enabled | s->fiq_enabled)) |
| 136 |
cpu_abort(cpu_single_env, "Core module interrupt\n");
|
|
| 136 |
hw_error("Core module interrupt\n");
|
|
| 137 | 137 |
} |
| 138 | 138 |
|
| 139 | 139 |
static void integratorcm_write(void *opaque, target_phys_addr_t offset, |
| ... | ... | |
| 205 | 205 |
/* ??? Voltage control unimplemented. */ |
| 206 | 206 |
break; |
| 207 | 207 |
default: |
| 208 |
cpu_abort (cpu_single_env,
|
|
| 209 |
"integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
|
|
| 208 |
hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
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|
| 209 |
(int)offset);
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|
| 210 | 210 |
break; |
| 211 | 211 |
} |
| 212 | 212 |
} |
| ... | ... | |
| 401 | 401 |
case 3: /* CP_DECODE */ |
| 402 | 402 |
return 0x11; |
| 403 | 403 |
default: |
| 404 |
cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", |
|
| 405 |
(int)offset); |
|
| 404 |
hw_error("icp_control_read: Bad offset %x\n", (int)offset);
|
|
| 406 | 405 |
return 0; |
| 407 | 406 |
} |
| 408 | 407 |
} |
| ... | ... | |
| 417 | 416 |
/* Nothing interesting implemented yet. */ |
| 418 | 417 |
break; |
| 419 | 418 |
default: |
| 420 |
cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", |
|
| 421 |
(int)offset); |
|
| 419 |
hw_error("icp_control_write: Bad offset %x\n", (int)offset);
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|
| 422 | 420 |
} |
| 423 | 421 |
} |
| 424 | 422 |
static CPUReadMemoryFunc *icp_control_readfn[] = {
|
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