Revision 2ac71179 hw/mcf5206.c
| b/hw/mcf5206.c | ||
|---|---|---|
| 61 | 61 |
prescale *= 16; |
| 62 | 62 |
|
| 63 | 63 |
if (mode == 3 || mode == 0) |
| 64 |
cpu_abort(cpu_single_env, |
|
| 65 |
"m5206_timer: mode %d not implemented\n", mode); |
|
| 64 |
hw_error("m5206_timer: mode %d not implemented\n", mode);
|
|
| 66 | 65 |
if ((s->tmr & TMR_FRR) == 0) |
| 67 |
cpu_abort(cpu_single_env, |
|
| 68 |
"m5206_timer: free running mode not implemented\n"); |
|
| 66 |
hw_error("m5206_timer: free running mode not implemented\n");
|
|
| 69 | 67 |
|
| 70 | 68 |
/* Assume 66MHz system clock. */ |
| 71 | 69 |
ptimer_set_freq(s->timer, 66000000 / prescale); |
| ... | ... | |
| 296 | 294 |
case 0x170: return s->uivr[0]; |
| 297 | 295 |
case 0x1b0: return s->uivr[1]; |
| 298 | 296 |
} |
| 299 |
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
|
|
| 297 |
hw_error("Bad MBAR read offset 0x%x", (int)offset);
|
|
| 300 | 298 |
return 0; |
| 301 | 299 |
} |
| 302 | 300 |
|
| ... | ... | |
| 350 | 348 |
s->uivr[1] = value; |
| 351 | 349 |
break; |
| 352 | 350 |
default: |
| 353 |
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
|
|
| 351 |
hw_error("Bad MBAR write offset 0x%x", (int)offset);
|
|
| 354 | 352 |
break; |
| 355 | 353 |
} |
| 356 | 354 |
} |
| ... | ... | |
| 377 | 375 |
m5206_mbar_state *s = (m5206_mbar_state *)opaque; |
| 378 | 376 |
offset &= 0x3ff; |
| 379 | 377 |
if (offset > 0x200) {
|
| 380 |
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
|
|
| 378 |
hw_error("Bad MBAR read offset 0x%x", (int)offset);
|
|
| 381 | 379 |
} |
| 382 | 380 |
if (m5206_mbar_width[offset >> 2] > 1) {
|
| 383 | 381 |
uint16_t val; |
| ... | ... | |
| 396 | 394 |
int width; |
| 397 | 395 |
offset &= 0x3ff; |
| 398 | 396 |
if (offset > 0x200) {
|
| 399 |
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
|
|
| 397 |
hw_error("Bad MBAR read offset 0x%x", (int)offset);
|
|
| 400 | 398 |
} |
| 401 | 399 |
width = m5206_mbar_width[offset >> 2]; |
| 402 | 400 |
if (width > 2) {
|
| ... | ... | |
| 420 | 418 |
int width; |
| 421 | 419 |
offset &= 0x3ff; |
| 422 | 420 |
if (offset > 0x200) {
|
| 423 |
cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
|
|
| 421 |
hw_error("Bad MBAR read offset 0x%x", (int)offset);
|
|
| 424 | 422 |
} |
| 425 | 423 |
width = m5206_mbar_width[offset >> 2]; |
| 426 | 424 |
if (width < 4) {
|
| ... | ... | |
| 444 | 442 |
int width; |
| 445 | 443 |
offset &= 0x3ff; |
| 446 | 444 |
if (offset > 0x200) {
|
| 447 |
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
|
|
| 445 |
hw_error("Bad MBAR write offset 0x%x", (int)offset);
|
|
| 448 | 446 |
} |
| 449 | 447 |
width = m5206_mbar_width[offset >> 2]; |
| 450 | 448 |
if (width > 1) {
|
| ... | ... | |
| 468 | 466 |
int width; |
| 469 | 467 |
offset &= 0x3ff; |
| 470 | 468 |
if (offset > 0x200) {
|
| 471 |
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
|
|
| 469 |
hw_error("Bad MBAR write offset 0x%x", (int)offset);
|
|
| 472 | 470 |
} |
| 473 | 471 |
width = m5206_mbar_width[offset >> 2]; |
| 474 | 472 |
if (width > 2) {
|
| ... | ... | |
| 496 | 494 |
int width; |
| 497 | 495 |
offset &= 0x3ff; |
| 498 | 496 |
if (offset > 0x200) {
|
| 499 |
cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
|
|
| 497 |
hw_error("Bad MBAR write offset 0x%x", (int)offset);
|
|
| 500 | 498 |
} |
| 501 | 499 |
width = m5206_mbar_width[offset >> 2]; |
| 502 | 500 |
if (width < 4) {
|
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