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/*
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* OneNAND flash memories emulation.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "qemu-common.h" |
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#include "flash.h" |
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#include "irq.h" |
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#include "sysemu.h" |
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#include "block.h" |
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11 |
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|
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6) |
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struct onenand_s {
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uint32_t id; |
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int shift;
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target_phys_addr_t base; |
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qemu_irq intr; |
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qemu_irq rdy; |
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BlockDriverState *bdrv; |
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BlockDriverState *bdrv_cur; |
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uint8_t *image; |
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uint8_t *otp; |
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uint8_t *current; |
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ram_addr_t ram; |
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uint8_t *boot[2];
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uint8_t *data[2][2]; |
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int iomemtype;
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int cycle;
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int otpmode;
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|
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uint16_t addr[8];
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uint16_t unladdr[8];
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int bufaddr;
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int count;
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uint16_t command; |
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uint16_t config[2];
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uint16_t status; |
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uint16_t intstatus; |
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uint16_t wpstatus; |
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|
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struct ecc_state_s ecc;
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|
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int density_mask;
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int secs;
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int secs_cur;
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int blocks;
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uint8_t *blockwp; |
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}; |
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enum {
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ONEN_BUF_BLOCK = 0,
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ONEN_BUF_BLOCK2 = 1,
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ONEN_BUF_DEST_BLOCK = 2,
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ONEN_BUF_DEST_PAGE = 3,
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ONEN_BUF_PAGE = 7,
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}; |
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enum {
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ONEN_ERR_CMD = 1 << 10, |
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ONEN_ERR_ERASE = 1 << 11, |
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ONEN_ERR_PROG = 1 << 12, |
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ONEN_ERR_LOAD = 1 << 13, |
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}; |
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enum {
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ONEN_INT_RESET = 1 << 4, |
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ONEN_INT_ERASE = 1 << 5, |
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ONEN_INT_PROG = 1 << 6, |
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ONEN_INT_LOAD = 1 << 7, |
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ONEN_INT = 1 << 15, |
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}; |
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enum {
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ONEN_LOCK_LOCKTIGHTEN = 1 << 0, |
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ONEN_LOCK_LOCKED = 1 << 1, |
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ONEN_LOCK_UNLOCKED = 1 << 2, |
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}; |
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|
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void onenand_base_update(void *opaque, target_phys_addr_t new) |
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{
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struct onenand_s *s = (struct onenand_s *) opaque; |
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s->base = new; |
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/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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* write boot commands. Also take note of the BWPS bit. */
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cpu_register_physical_memory(s->base + (0x0000 << s->shift),
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0x0200 << s->shift, s->iomemtype);
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cpu_register_physical_memory(s->base + (0x0200 << s->shift),
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0xbe00 << s->shift,
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(s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
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if (s->iomemtype)
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cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
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0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift)); |
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} |
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void onenand_base_unmap(void *opaque) |
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{
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struct onenand_s *s = (struct onenand_s *) opaque; |
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cpu_register_physical_memory(s->base, |
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0x10000 << s->shift, IO_MEM_UNASSIGNED);
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} |
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static void onenand_intr_update(struct onenand_s *s) |
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{
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qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
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} |
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/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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static void onenand_reset(struct onenand_s *s, int cold) |
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{
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memset(&s->addr, 0, sizeof(s->addr)); |
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s->command = 0;
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s->count = 1;
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s->bufaddr = 0;
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s->config[0] = 0x40c0; |
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s->config[1] = 0x0000; |
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onenand_intr_update(s); |
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qemu_irq_raise(s->rdy); |
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s->status = 0x0000;
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s->intstatus = cold ? 0x8080 : 0x8010; |
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s->unladdr[0] = 0; |
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s->unladdr[1] = 0; |
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s->wpstatus = 0x0002;
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s->cycle = 0;
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s->otpmode = 0;
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s->bdrv_cur = s->bdrv; |
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s->current = s->image; |
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s->secs_cur = s->secs; |
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if (cold) {
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/* Lock the whole flash */
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memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); |
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if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0) |
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hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
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} |
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} |
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static inline int onenand_load_main(struct onenand_s *s, int sec, int secn, |
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void *dest)
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{
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if (s->bdrv_cur)
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return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(dest, s->current + (sec << 9), secn << 9); |
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return 0; |
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} |
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static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn, |
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void *src)
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{
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if (s->bdrv_cur)
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return bdrv_write(s->bdrv_cur, sec, src, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (sec << 9), src, secn << 9); |
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return 0; |
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} |
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static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn, |
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void *dest)
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{
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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else
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memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
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return 0; |
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} |
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static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn, |
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void *src)
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{
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(buf + ((sec & 31) << 4), src, secn << 4); |
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return bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0; |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(s->current + (s->secs_cur << 9) + (sec << 4), src, secn << 4); |
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return 0; |
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} |
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static inline int onenand_erase(struct onenand_s *s, int sec, int num) |
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{
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/* TODO: optimise */
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uint8_t buf[512];
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memset(buf, 0xff, sizeof(buf)); |
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for (; num > 0; num --, sec ++) { |
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if (onenand_prog_main(s, sec, 1, buf)) |
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return 1; |
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if (onenand_prog_spare(s, sec, 1, buf)) |
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return 1; |
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} |
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return 0; |
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} |
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static void onenand_command(struct onenand_s *s, int cmd) |
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{
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \ |
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9)); |
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ |
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buf += (s->bufaddr & 3) << 9; |
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ |
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buf += (s->bufaddr & 3) << 4; |
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switch (cmd) {
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case 0x00: /* Load single/multiple sector data unit into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_M() |
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if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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#if 0
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SETBUF_S()
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x13: /* Load single/multiple spare sector into buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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SETBUF_S() |
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
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|
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
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break;
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case 0x80: /* Program single/multiple sector data unit from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
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|
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SETBUF_M() |
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if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
| 299 |
|
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#if 0
|
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SETBUF_S()
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
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#endif
|
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|
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
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* then we need two split the read/write into two chunks.
|
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
|
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case 0x1a: /* Program single/multiple spare area sector from buffer */ |
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
| 314 |
|
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SETBUF_S() |
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
| 318 |
|
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
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* then we need two split the read/write into two chunks.
|
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
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break;
|
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case 0x1b: /* Copy-back program */ |
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SETBUF_S() |
| 327 |
|
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
| 329 |
if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
| 331 |
|
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SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) |
| 333 |
if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
| 335 |
|
| 336 |
/* TODO: spare areas */
|
| 337 |
|
| 338 |
s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
| 339 |
break;
|
| 340 |
|
| 341 |
case 0x23: /* Unlock NAND array block(s) */ |
| 342 |
s->intstatus |= ONEN_INT; |
| 343 |
|
| 344 |
/* XXX the previous (?) area should be locked automatically */
|
| 345 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
| 346 |
if (b >= s->blocks) {
|
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s->status |= ONEN_ERR_CMD; |
| 348 |
break;
|
| 349 |
} |
| 350 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
| 351 |
break;
|
| 352 |
|
| 353 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
| 354 |
} |
| 355 |
break;
|
| 356 |
case 0x27: /* Unlock All NAND array blocks */ |
| 357 |
s->intstatus |= ONEN_INT; |
| 358 |
|
| 359 |
for (b = 0; b < s->blocks; b ++) { |
| 360 |
if (b >= s->blocks) {
|
| 361 |
s->status |= ONEN_ERR_CMD; |
| 362 |
break;
|
| 363 |
} |
| 364 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
| 365 |
break;
|
| 366 |
|
| 367 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
| 368 |
} |
| 369 |
break;
|
| 370 |
|
| 371 |
case 0x2a: /* Lock NAND array block(s) */ |
| 372 |
s->intstatus |= ONEN_INT; |
| 373 |
|
| 374 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
| 375 |
if (b >= s->blocks) {
|
| 376 |
s->status |= ONEN_ERR_CMD; |
| 377 |
break;
|
| 378 |
} |
| 379 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
| 380 |
break;
|
| 381 |
|
| 382 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; |
| 383 |
} |
| 384 |
break;
|
| 385 |
case 0x2c: /* Lock-tight NAND array block(s) */ |
| 386 |
s->intstatus |= ONEN_INT; |
| 387 |
|
| 388 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
| 389 |
if (b >= s->blocks) {
|
| 390 |
s->status |= ONEN_ERR_CMD; |
| 391 |
break;
|
| 392 |
} |
| 393 |
if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
| 394 |
continue;
|
| 395 |
|
| 396 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; |
| 397 |
} |
| 398 |
break;
|
| 399 |
|
| 400 |
case 0x71: /* Erase-Verify-Read */ |
| 401 |
s->intstatus |= ONEN_INT; |
| 402 |
break;
|
| 403 |
case 0x95: /* Multi-block erase */ |
| 404 |
qemu_irq_pulse(s->intr); |
| 405 |
/* Fall through. */
|
| 406 |
case 0x94: /* Block erase */ |
| 407 |
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
| 408 |
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) |
| 409 |
<< (BLOCK_SHIFT - 9);
|
| 410 |
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) |
| 411 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; |
| 412 |
|
| 413 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
| 414 |
break;
|
| 415 |
case 0xb0: /* Erase suspend */ |
| 416 |
break;
|
| 417 |
case 0x30: /* Erase resume */ |
| 418 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
| 419 |
break;
|
| 420 |
|
| 421 |
case 0xf0: /* Reset NAND Flash core */ |
| 422 |
onenand_reset(s, 0);
|
| 423 |
break;
|
| 424 |
case 0xf3: /* Reset OneNAND */ |
| 425 |
onenand_reset(s, 0);
|
| 426 |
break;
|
| 427 |
|
| 428 |
case 0x65: /* OTP Access */ |
| 429 |
s->intstatus |= ONEN_INT; |
| 430 |
s->bdrv_cur = 0;
|
| 431 |
s->current = s->otp; |
| 432 |
s->secs_cur = 1 << (BLOCK_SHIFT - 9); |
| 433 |
s->addr[ONEN_BUF_BLOCK] = 0;
|
| 434 |
s->otpmode = 1;
|
| 435 |
break;
|
| 436 |
|
| 437 |
default:
|
| 438 |
s->status |= ONEN_ERR_CMD; |
| 439 |
s->intstatus |= ONEN_INT; |
| 440 |
fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
| 441 |
__FUNCTION__, cmd); |
| 442 |
} |
| 443 |
|
| 444 |
onenand_intr_update(s); |
| 445 |
} |
| 446 |
|
| 447 |
static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) |
| 448 |
{
|
| 449 |
struct onenand_s *s = (struct onenand_s *) opaque; |
| 450 |
int offset = addr >> s->shift;
|
| 451 |
|
| 452 |
switch (offset) {
|
| 453 |
case 0x0000 ... 0xc000: |
| 454 |
return lduw_le_p(s->boot[0] + addr); |
| 455 |
|
| 456 |
case 0xf000: /* Manufacturer ID */ |
| 457 |
return (s->id >> 16) & 0xff; |
| 458 |
case 0xf001: /* Device ID */ |
| 459 |
return (s->id >> 8) & 0xff; |
| 460 |
/* TODO: get the following values from a real chip! */
|
| 461 |
case 0xf002: /* Version ID */ |
| 462 |
return (s->id >> 0) & 0xff; |
| 463 |
case 0xf003: /* Data Buffer size */ |
| 464 |
return 1 << PAGE_SHIFT; |
| 465 |
case 0xf004: /* Boot Buffer size */ |
| 466 |
return 0x200; |
| 467 |
case 0xf005: /* Amount of buffers */ |
| 468 |
return 1 | (2 << 8); |
| 469 |
case 0xf006: /* Technology */ |
| 470 |
return 0; |
| 471 |
|
| 472 |
case 0xf100 ... 0xf107: /* Start addresses */ |
| 473 |
return s->addr[offset - 0xf100]; |
| 474 |
|
| 475 |
case 0xf200: /* Start buffer */ |
| 476 |
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
| 477 |
|
| 478 |
case 0xf220: /* Command */ |
| 479 |
return s->command;
|
| 480 |
case 0xf221: /* System Configuration 1 */ |
| 481 |
return s->config[0] & 0xffe0; |
| 482 |
case 0xf222: /* System Configuration 2 */ |
| 483 |
return s->config[1]; |
| 484 |
|
| 485 |
case 0xf240: /* Controller Status */ |
| 486 |
return s->status;
|
| 487 |
case 0xf241: /* Interrupt */ |
| 488 |
return s->intstatus;
|
| 489 |
case 0xf24c: /* Unlock Start Block Address */ |
| 490 |
return s->unladdr[0]; |
| 491 |
case 0xf24d: /* Unlock End Block Address */ |
| 492 |
return s->unladdr[1]; |
| 493 |
case 0xf24e: /* Write Protection Status */ |
| 494 |
return s->wpstatus;
|
| 495 |
|
| 496 |
case 0xff00: /* ECC Status */ |
| 497 |
return 0x00; |
| 498 |
case 0xff01: /* ECC Result of main area data */ |
| 499 |
case 0xff02: /* ECC Result of spare area data */ |
| 500 |
case 0xff03: /* ECC Result of main area data */ |
| 501 |
case 0xff04: /* ECC Result of spare area data */ |
| 502 |
hw_error("%s: imeplement ECC\n", __FUNCTION__);
|
| 503 |
return 0x0000; |
| 504 |
} |
| 505 |
|
| 506 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
| 507 |
__FUNCTION__, offset); |
| 508 |
return 0; |
| 509 |
} |
| 510 |
|
| 511 |
static void onenand_write(void *opaque, target_phys_addr_t addr, |
| 512 |
uint32_t value) |
| 513 |
{
|
| 514 |
struct onenand_s *s = (struct onenand_s *) opaque; |
| 515 |
int offset = addr >> s->shift;
|
| 516 |
int sec;
|
| 517 |
|
| 518 |
switch (offset) {
|
| 519 |
case 0x0000 ... 0x01ff: |
| 520 |
case 0x8000 ... 0x800f: |
| 521 |
if (s->cycle) {
|
| 522 |
s->cycle = 0;
|
| 523 |
|
| 524 |
if (value == 0x0000) { |
| 525 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
| 526 |
onenand_load_main(s, sec, |
| 527 |
1 << (PAGE_SHIFT - 9), s->data[0][0]); |
| 528 |
s->addr[ONEN_BUF_PAGE] += 4;
|
| 529 |
s->addr[ONEN_BUF_PAGE] &= 0xff;
|
| 530 |
} |
| 531 |
break;
|
| 532 |
} |
| 533 |
|
| 534 |
switch (value) {
|
| 535 |
case 0x00f0: /* Reset OneNAND */ |
| 536 |
onenand_reset(s, 0);
|
| 537 |
break;
|
| 538 |
|
| 539 |
case 0x00e0: /* Load Data into Buffer */ |
| 540 |
s->cycle = 1;
|
| 541 |
break;
|
| 542 |
|
| 543 |
case 0x0090: /* Read Identification Data */ |
| 544 |
memset(s->boot[0], 0, 3 << s->shift); |
| 545 |
s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff; |
| 546 |
s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff; |
| 547 |
s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
| 548 |
break;
|
| 549 |
|
| 550 |
default:
|
| 551 |
fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
|
| 552 |
__FUNCTION__, value); |
| 553 |
} |
| 554 |
break;
|
| 555 |
|
| 556 |
case 0xf100 ... 0xf107: /* Start addresses */ |
| 557 |
s->addr[offset - 0xf100] = value;
|
| 558 |
break;
|
| 559 |
|
| 560 |
case 0xf200: /* Start buffer */ |
| 561 |
s->bufaddr = (value >> 8) & 0xf; |
| 562 |
if (PAGE_SHIFT == 11) |
| 563 |
s->count = (value & 3) ?: 4; |
| 564 |
else if (PAGE_SHIFT == 10) |
| 565 |
s->count = (value & 1) ?: 2; |
| 566 |
break;
|
| 567 |
|
| 568 |
case 0xf220: /* Command */ |
| 569 |
if (s->intstatus & (1 << 15)) |
| 570 |
break;
|
| 571 |
s->command = value; |
| 572 |
onenand_command(s, s->command); |
| 573 |
break;
|
| 574 |
case 0xf221: /* System Configuration 1 */ |
| 575 |
s->config[0] = value;
|
| 576 |
onenand_intr_update(s); |
| 577 |
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); |
| 578 |
break;
|
| 579 |
case 0xf222: /* System Configuration 2 */ |
| 580 |
s->config[1] = value;
|
| 581 |
break;
|
| 582 |
|
| 583 |
case 0xf241: /* Interrupt */ |
| 584 |
s->intstatus &= value; |
| 585 |
if ((1 << 15) & ~s->intstatus) |
| 586 |
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | |
| 587 |
ONEN_ERR_PROG | ONEN_ERR_LOAD); |
| 588 |
onenand_intr_update(s); |
| 589 |
break;
|
| 590 |
case 0xf24c: /* Unlock Start Block Address */ |
| 591 |
s->unladdr[0] = value & (s->blocks - 1); |
| 592 |
/* For some reason we have to set the end address to by default
|
| 593 |
* be same as start because the software forgets to write anything
|
| 594 |
* in there. */
|
| 595 |
s->unladdr[1] = value & (s->blocks - 1); |
| 596 |
break;
|
| 597 |
case 0xf24d: /* Unlock End Block Address */ |
| 598 |
s->unladdr[1] = value & (s->blocks - 1); |
| 599 |
break;
|
| 600 |
|
| 601 |
default:
|
| 602 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
| 603 |
__FUNCTION__, offset); |
| 604 |
} |
| 605 |
} |
| 606 |
|
| 607 |
static CPUReadMemoryFunc *onenand_readfn[] = {
|
| 608 |
onenand_read, /* TODO */
|
| 609 |
onenand_read, |
| 610 |
onenand_read, |
| 611 |
}; |
| 612 |
|
| 613 |
static CPUWriteMemoryFunc *onenand_writefn[] = {
|
| 614 |
onenand_write, /* TODO */
|
| 615 |
onenand_write, |
| 616 |
onenand_write, |
| 617 |
}; |
| 618 |
|
| 619 |
void *onenand_init(uint32_t id, int regshift, qemu_irq irq) |
| 620 |
{
|
| 621 |
struct onenand_s *s = (struct onenand_s *) qemu_mallocz(sizeof(*s)); |
| 622 |
int bdrv_index = drive_get_index(IF_MTD, 0, 0); |
| 623 |
uint32_t size = 1 << (24 + ((id >> 12) & 7)); |
| 624 |
void *ram;
|
| 625 |
|
| 626 |
s->shift = regshift; |
| 627 |
s->intr = irq; |
| 628 |
s->rdy = 0;
|
| 629 |
s->id = id; |
| 630 |
s->blocks = size >> BLOCK_SHIFT; |
| 631 |
s->secs = size >> 9;
|
| 632 |
s->blockwp = qemu_malloc(s->blocks); |
| 633 |
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; |
| 634 |
s->iomemtype = cpu_register_io_memory(0, onenand_readfn,
|
| 635 |
onenand_writefn, s); |
| 636 |
if (bdrv_index == -1) |
| 637 |
s->image = memset(qemu_malloc(size + (size >> 5)),
|
| 638 |
0xff, size + (size >> 5)); |
| 639 |
else
|
| 640 |
s->bdrv = drives_table[bdrv_index].bdrv; |
| 641 |
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), |
| 642 |
0xff, (64 + 2) << PAGE_SHIFT); |
| 643 |
s->ram = qemu_ram_alloc(0xc000 << s->shift);
|
| 644 |
ram = qemu_get_ram_ptr(s->ram); |
| 645 |
s->boot[0] = ram + (0x0000 << s->shift); |
| 646 |
s->boot[1] = ram + (0x8000 << s->shift); |
| 647 |
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); |
| 648 |
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); |
| 649 |
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); |
| 650 |
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); |
| 651 |
|
| 652 |
onenand_reset(s, 1);
|
| 653 |
|
| 654 |
return s;
|
| 655 |
} |
| 656 |
|
| 657 |
void *onenand_raw_otp(void *opaque) |
| 658 |
{
|
| 659 |
struct onenand_s *s = (struct onenand_s *) opaque; |
| 660 |
|
| 661 |
return s->otp;
|
| 662 |
} |