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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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}
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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}
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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}
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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}
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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}
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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}
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
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                                    TCGv_i32 arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
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                                    TCGv_i64 arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
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                                       TCGv_ptr base, TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
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                                       TCGv_ptr base, TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
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                                                TCGv_i32 addr, TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I32(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
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                                                TCGv_i64 addr, TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I64(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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}
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static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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}
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static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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}
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static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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}
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static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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                                   TCGv_i32 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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}
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static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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                                   TCGv_i64 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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}
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static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4,
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                                    TCGv_i32 arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4,
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                                    TCGv_i64 arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
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                                     TCGv_i32 arg2, TCGv_i32 arg3,
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                                     TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
318 a7812ae4 pbrook
    *gen_opparam_ptr++ = arg5;
319 a7812ae4 pbrook
    *gen_opparam_ptr++ = arg6;
320 a7812ae4 pbrook
}
321 a7812ae4 pbrook
322 a9751609 Richard Henderson
static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
323 a9751609 Richard Henderson
                                     TCGv_i64 arg2, TCGv_i64 arg3,
324 a9751609 Richard Henderson
                                     TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
325 a7812ae4 pbrook
{
326 a7812ae4 pbrook
    *gen_opc_ptr++ = opc;
327 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
328 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
329 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
330 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
331 c896fe29 bellard
    *gen_opparam_ptr++ = arg5;
332 c896fe29 bellard
    *gen_opparam_ptr++ = arg6;
333 c896fe29 bellard
}
334 c896fe29 bellard
335 c896fe29 bellard
static inline void gen_set_label(int n)
336 c896fe29 bellard
{
337 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_set_label, n);
338 c896fe29 bellard
}
339 c896fe29 bellard
340 fb50d413 blueswir1
static inline void tcg_gen_br(int label)
341 fb50d413 blueswir1
{
342 fb50d413 blueswir1
    tcg_gen_op1i(INDEX_op_br, label);
343 fb50d413 blueswir1
}
344 fb50d413 blueswir1
345 a7812ae4 pbrook
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
346 c896fe29 bellard
{
347 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I32(ret, arg))
348 a7812ae4 pbrook
        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
349 c896fe29 bellard
}
350 c896fe29 bellard
351 a7812ae4 pbrook
static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
352 c896fe29 bellard
{
353 a7812ae4 pbrook
    tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
354 c896fe29 bellard
}
355 c896fe29 bellard
356 2bece2c8 Richard Henderson
/* A version of dh_sizemask from def-helper.h that doesn't rely on
357 2bece2c8 Richard Henderson
   preprocessor magic.  */
358 2bece2c8 Richard Henderson
static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
359 2bece2c8 Richard Henderson
{
360 2bece2c8 Richard Henderson
    return (is_64bit << n*2) | (is_signed << (n*2 + 1));
361 2bece2c8 Richard Henderson
}
362 2bece2c8 Richard Henderson
363 c896fe29 bellard
/* helper calls */
364 a7812ae4 pbrook
static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
365 a7812ae4 pbrook
                                   TCGArg ret, int nargs, TCGArg *args)
366 a7812ae4 pbrook
{
367 a7812ae4 pbrook
    TCGv_ptr fn;
368 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
369 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
370 a7812ae4 pbrook
                  nargs, args);
371 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
372 a7812ae4 pbrook
}
373 c896fe29 bellard
374 dbfff4de Aurelien Jarno
/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
375 dbfff4de Aurelien Jarno
   reserved for helpers in tcg-runtime.c. These helpers are all const
376 dbfff4de Aurelien Jarno
   and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
377 dbfff4de Aurelien Jarno
   TCG_CALL_PURE. This may need to be adjusted if these functions
378 dbfff4de Aurelien Jarno
   start to be used with other helpers. */
379 2bece2c8 Richard Henderson
static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
380 31d66551 Aurelien Jarno
                                    TCGv_i32 a, TCGv_i32 b)
381 31d66551 Aurelien Jarno
{
382 31d66551 Aurelien Jarno
    TCGv_ptr fn;
383 31d66551 Aurelien Jarno
    TCGArg args[2];
384 31d66551 Aurelien Jarno
    fn = tcg_const_ptr((tcg_target_long)func);
385 31d66551 Aurelien Jarno
    args[0] = GET_TCGV_I32(a);
386 31d66551 Aurelien Jarno
    args[1] = GET_TCGV_I32(b);
387 2bece2c8 Richard Henderson
    tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
388 2bece2c8 Richard Henderson
                  GET_TCGV_I32(ret), 2, args);
389 31d66551 Aurelien Jarno
    tcg_temp_free_ptr(fn);
390 31d66551 Aurelien Jarno
}
391 31d66551 Aurelien Jarno
392 2bece2c8 Richard Henderson
static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
393 a7812ae4 pbrook
                                    TCGv_i64 a, TCGv_i64 b)
394 c896fe29 bellard
{
395 a7812ae4 pbrook
    TCGv_ptr fn;
396 a7812ae4 pbrook
    TCGArg args[2];
397 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
398 a7812ae4 pbrook
    args[0] = GET_TCGV_I64(a);
399 a7812ae4 pbrook
    args[1] = GET_TCGV_I64(b);
400 2bece2c8 Richard Henderson
    tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
401 2bece2c8 Richard Henderson
                  GET_TCGV_I64(ret), 2, args);
402 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
403 f8422f52 blueswir1
}
404 f8422f52 blueswir1
405 c896fe29 bellard
/* 32 bit ops */
406 c896fe29 bellard
407 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
408 c896fe29 bellard
{
409 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
410 c896fe29 bellard
}
411 c896fe29 bellard
412 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
413 c896fe29 bellard
{
414 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
415 c896fe29 bellard
}
416 c896fe29 bellard
417 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
418 c896fe29 bellard
{
419 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
420 c896fe29 bellard
}
421 c896fe29 bellard
422 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
423 c896fe29 bellard
{
424 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
425 c896fe29 bellard
}
426 c896fe29 bellard
427 a7812ae4 pbrook
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
428 c896fe29 bellard
{
429 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
430 c896fe29 bellard
}
431 c896fe29 bellard
432 a7812ae4 pbrook
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
433 c896fe29 bellard
{
434 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
435 c896fe29 bellard
}
436 c896fe29 bellard
437 a7812ae4 pbrook
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
438 c896fe29 bellard
{
439 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
440 c896fe29 bellard
}
441 c896fe29 bellard
442 a7812ae4 pbrook
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
443 c896fe29 bellard
{
444 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
445 c896fe29 bellard
}
446 c896fe29 bellard
447 a7812ae4 pbrook
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
448 c896fe29 bellard
{
449 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
450 c896fe29 bellard
}
451 c896fe29 bellard
452 a7812ae4 pbrook
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
453 c896fe29 bellard
{
454 7089442c blueswir1
    /* some cases can be optimized here */
455 7089442c blueswir1
    if (arg2 == 0) {
456 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
457 7089442c blueswir1
    } else {
458 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
459 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
460 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
461 7089442c blueswir1
    }
462 c896fe29 bellard
}
463 c896fe29 bellard
464 a7812ae4 pbrook
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
465 c896fe29 bellard
{
466 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
467 c896fe29 bellard
}
468 c896fe29 bellard
469 a7812ae4 pbrook
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
470 0045734a aurel32
{
471 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg1);
472 0045734a aurel32
    tcg_gen_sub_i32(ret, t0, arg2);
473 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
474 0045734a aurel32
}
475 0045734a aurel32
476 a7812ae4 pbrook
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
477 c896fe29 bellard
{
478 7089442c blueswir1
    /* some cases can be optimized here */
479 7089442c blueswir1
    if (arg2 == 0) {
480 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
481 7089442c blueswir1
    } else {
482 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
483 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
484 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
485 7089442c blueswir1
    }
486 c896fe29 bellard
}
487 c896fe29 bellard
488 a7812ae4 pbrook
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
489 c896fe29 bellard
{
490 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
491 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
492 7fc81051 aurel32
    } else {
493 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
494 7fc81051 aurel32
    }
495 c896fe29 bellard
}
496 c896fe29 bellard
497 a7812ae4 pbrook
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
498 c896fe29 bellard
{
499 c896fe29 bellard
    /* some cases can be optimized here */
500 c896fe29 bellard
    if (arg2 == 0) {
501 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
502 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
503 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
504 c896fe29 bellard
    } else {
505 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
506 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
507 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
508 c896fe29 bellard
    }
509 c896fe29 bellard
}
510 c896fe29 bellard
511 a7812ae4 pbrook
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
512 c896fe29 bellard
{
513 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
514 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
515 7fc81051 aurel32
    } else {
516 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
517 7fc81051 aurel32
    }
518 c896fe29 bellard
}
519 c896fe29 bellard
520 a7812ae4 pbrook
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
521 c896fe29 bellard
{
522 c896fe29 bellard
    /* some cases can be optimized here */
523 c896fe29 bellard
    if (arg2 == 0xffffffff) {
524 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
525 c896fe29 bellard
    } else if (arg2 == 0) {
526 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
527 c896fe29 bellard
    } else {
528 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
529 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
530 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
531 c896fe29 bellard
    }
532 c896fe29 bellard
}
533 c896fe29 bellard
534 a7812ae4 pbrook
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
535 c896fe29 bellard
{
536 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
537 7fc81051 aurel32
        tcg_gen_movi_i32(ret, 0);
538 7fc81051 aurel32
    } else {
539 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
540 7fc81051 aurel32
    }
541 c896fe29 bellard
}
542 c896fe29 bellard
543 a7812ae4 pbrook
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
544 c896fe29 bellard
{
545 c896fe29 bellard
    /* some cases can be optimized here */
546 c896fe29 bellard
    if (arg2 == 0) {
547 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
548 c896fe29 bellard
    } else {
549 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
550 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
551 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
552 c896fe29 bellard
    }
553 c896fe29 bellard
}
554 c896fe29 bellard
555 a7812ae4 pbrook
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
556 c896fe29 bellard
{
557 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
558 c896fe29 bellard
}
559 c896fe29 bellard
560 a7812ae4 pbrook
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
561 c896fe29 bellard
{
562 34151a20 bellard
    if (arg2 == 0) {
563 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
564 34151a20 bellard
    } else {
565 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
566 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
567 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
568 34151a20 bellard
    }
569 c896fe29 bellard
}
570 c896fe29 bellard
571 a7812ae4 pbrook
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
572 c896fe29 bellard
{
573 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
574 c896fe29 bellard
}
575 c896fe29 bellard
576 a7812ae4 pbrook
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
577 c896fe29 bellard
{
578 34151a20 bellard
    if (arg2 == 0) {
579 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
580 34151a20 bellard
    } else {
581 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
582 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
583 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
584 34151a20 bellard
    }
585 c896fe29 bellard
}
586 c896fe29 bellard
587 a7812ae4 pbrook
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
588 c896fe29 bellard
{
589 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
590 c896fe29 bellard
}
591 c896fe29 bellard
592 a7812ae4 pbrook
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
593 c896fe29 bellard
{
594 34151a20 bellard
    if (arg2 == 0) {
595 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
596 34151a20 bellard
    } else {
597 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
598 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
599 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
600 34151a20 bellard
    }
601 c896fe29 bellard
}
602 c896fe29 bellard
603 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
604 8a56e840 Richard Henderson
                                      TCGv_i32 arg2, int label_index)
605 c896fe29 bellard
{
606 a7812ae4 pbrook
    tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
607 c896fe29 bellard
}
608 c896fe29 bellard
609 8a56e840 Richard Henderson
static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
610 8a56e840 Richard Henderson
                                       int32_t arg2, int label_index)
611 cb63669a pbrook
{
612 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
613 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
614 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
615 cb63669a pbrook
}
616 cb63669a pbrook
617 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
618 5105c556 Aurelien Jarno
                                       TCGv_i32 arg1, TCGv_i32 arg2)
619 5105c556 Aurelien Jarno
{
620 5105c556 Aurelien Jarno
    tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
621 5105c556 Aurelien Jarno
}
622 5105c556 Aurelien Jarno
623 8a56e840 Richard Henderson
static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
624 8a56e840 Richard Henderson
                                        TCGv_i32 arg1, int32_t arg2)
625 5105c556 Aurelien Jarno
{
626 5105c556 Aurelien Jarno
    TCGv_i32 t0 = tcg_const_i32(arg2);
627 5105c556 Aurelien Jarno
    tcg_gen_setcond_i32(cond, ret, arg1, t0);
628 5105c556 Aurelien Jarno
    tcg_temp_free_i32(t0);
629 5105c556 Aurelien Jarno
}
630 5105c556 Aurelien Jarno
631 a7812ae4 pbrook
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
632 c896fe29 bellard
{
633 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
634 c896fe29 bellard
}
635 c896fe29 bellard
636 a7812ae4 pbrook
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
637 f730fd27 ths
{
638 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
639 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
640 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
641 f730fd27 ths
}
642 f730fd27 ths
643 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
644 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
645 c896fe29 bellard
{
646 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
647 c896fe29 bellard
}
648 c896fe29 bellard
649 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
650 c896fe29 bellard
{
651 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
652 c896fe29 bellard
}
653 c896fe29 bellard
654 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
655 c896fe29 bellard
{
656 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
657 c896fe29 bellard
}
658 c896fe29 bellard
659 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
660 c896fe29 bellard
{
661 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
662 c896fe29 bellard
}
663 31d66551 Aurelien Jarno
#elif defined(TCG_TARGET_HAS_div2_i32)
664 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
665 c896fe29 bellard
{
666 a7812ae4 pbrook
    TCGv_i32 t0;
667 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
668 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
669 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
670 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
671 c896fe29 bellard
}
672 c896fe29 bellard
673 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
674 c896fe29 bellard
{
675 a7812ae4 pbrook
    TCGv_i32 t0;
676 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
677 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
678 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
679 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
680 c896fe29 bellard
}
681 c896fe29 bellard
682 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
683 c896fe29 bellard
{
684 a7812ae4 pbrook
    TCGv_i32 t0;
685 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
686 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
687 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
688 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
689 c896fe29 bellard
}
690 c896fe29 bellard
691 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
692 c896fe29 bellard
{
693 a7812ae4 pbrook
    TCGv_i32 t0;
694 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
695 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
696 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
697 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
698 c896fe29 bellard
}
699 31d66551 Aurelien Jarno
#else
700 31d66551 Aurelien Jarno
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
701 31d66551 Aurelien Jarno
{
702 2bece2c8 Richard Henderson
    int sizemask = 0;
703 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and signed.  */
704 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 1);
705 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 1);
706 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 1);
707 2bece2c8 Richard Henderson
708 2bece2c8 Richard Henderson
    tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
709 31d66551 Aurelien Jarno
}
710 31d66551 Aurelien Jarno
711 31d66551 Aurelien Jarno
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
712 31d66551 Aurelien Jarno
{
713 2bece2c8 Richard Henderson
    int sizemask = 0;
714 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and signed.  */
715 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 1);
716 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 1);
717 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 1);
718 2bece2c8 Richard Henderson
719 2bece2c8 Richard Henderson
    tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
720 31d66551 Aurelien Jarno
}
721 31d66551 Aurelien Jarno
722 31d66551 Aurelien Jarno
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
723 31d66551 Aurelien Jarno
{
724 2bece2c8 Richard Henderson
    int sizemask = 0;
725 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and unsigned.  */
726 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 0);
727 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 0);
728 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 0);
729 2bece2c8 Richard Henderson
730 2bece2c8 Richard Henderson
    tcg_gen_helper32(tcg_helper_divu_i32, ret, arg1, arg2, 0);
731 31d66551 Aurelien Jarno
}
732 31d66551 Aurelien Jarno
733 31d66551 Aurelien Jarno
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
734 31d66551 Aurelien Jarno
{
735 2bece2c8 Richard Henderson
    int sizemask = 0;
736 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and unsigned.  */
737 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 0);
738 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 0);
739 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 0);
740 2bece2c8 Richard Henderson
741 2bece2c8 Richard Henderson
    tcg_gen_helper32(tcg_helper_remu_i32, ret, arg1, arg2, 0);
742 31d66551 Aurelien Jarno
}
743 c896fe29 bellard
#endif
744 c896fe29 bellard
745 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
746 c896fe29 bellard
747 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
748 c896fe29 bellard
{
749 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg)) {
750 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
751 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
752 4d07272d blueswir1
    }
753 c896fe29 bellard
}
754 c896fe29 bellard
755 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
756 c896fe29 bellard
{
757 a7812ae4 pbrook
    tcg_gen_movi_i32(TCGV_LOW(ret), arg);
758 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
759 c896fe29 bellard
}
760 c896fe29 bellard
761 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
762 a7812ae4 pbrook
                                    tcg_target_long offset)
763 c896fe29 bellard
{
764 a7812ae4 pbrook
    tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
765 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
766 c896fe29 bellard
}
767 c896fe29 bellard
768 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
769 a7812ae4 pbrook
                                    tcg_target_long offset)
770 c896fe29 bellard
{
771 a7812ae4 pbrook
    tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
772 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
773 c896fe29 bellard
}
774 c896fe29 bellard
775 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
776 a7812ae4 pbrook
                                     tcg_target_long offset)
777 c896fe29 bellard
{
778 a747723b aurel32
    tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
779 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
780 c896fe29 bellard
}
781 c896fe29 bellard
782 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
783 a7812ae4 pbrook
                                     tcg_target_long offset)
784 c896fe29 bellard
{
785 a7812ae4 pbrook
    tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
786 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
787 c896fe29 bellard
}
788 c896fe29 bellard
789 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
790 a7812ae4 pbrook
                                     tcg_target_long offset)
791 c896fe29 bellard
{
792 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
793 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
794 c896fe29 bellard
}
795 c896fe29 bellard
796 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
797 a7812ae4 pbrook
                                     tcg_target_long offset)
798 c896fe29 bellard
{
799 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
800 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
801 c896fe29 bellard
}
802 c896fe29 bellard
803 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
804 a7812ae4 pbrook
                                  tcg_target_long offset)
805 c896fe29 bellard
{
806 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
807 c896fe29 bellard
       same temporary */
808 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
809 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
810 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
811 c896fe29 bellard
#else
812 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
813 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
814 c896fe29 bellard
#endif
815 c896fe29 bellard
}
816 c896fe29 bellard
817 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
818 a7812ae4 pbrook
                                   tcg_target_long offset)
819 c896fe29 bellard
{
820 a7812ae4 pbrook
    tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
821 c896fe29 bellard
}
822 c896fe29 bellard
823 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
824 a7812ae4 pbrook
                                    tcg_target_long offset)
825 c896fe29 bellard
{
826 a7812ae4 pbrook
    tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
827 c896fe29 bellard
}
828 c896fe29 bellard
829 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
830 a7812ae4 pbrook
                                    tcg_target_long offset)
831 c896fe29 bellard
{
832 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
833 c896fe29 bellard
}
834 c896fe29 bellard
835 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
836 a7812ae4 pbrook
                                  tcg_target_long offset)
837 c896fe29 bellard
{
838 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
839 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
840 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
841 c896fe29 bellard
#else
842 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
843 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
844 c896fe29 bellard
#endif
845 c896fe29 bellard
}
846 c896fe29 bellard
847 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
848 c896fe29 bellard
{
849 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
850 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
851 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
852 c896fe29 bellard
}
853 c896fe29 bellard
854 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
855 c896fe29 bellard
{
856 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
857 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
858 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
859 c896fe29 bellard
}
860 c896fe29 bellard
861 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
862 c896fe29 bellard
{
863 a7812ae4 pbrook
    tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
864 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
865 c896fe29 bellard
}
866 c896fe29 bellard
867 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
868 c896fe29 bellard
{
869 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
870 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
871 c896fe29 bellard
}
872 c896fe29 bellard
873 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
874 c896fe29 bellard
{
875 e5105083 aurel32
    tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
876 e5105083 aurel32
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
877 c896fe29 bellard
}
878 c896fe29 bellard
879 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
880 c896fe29 bellard
{
881 a7812ae4 pbrook
    tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
882 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
883 c896fe29 bellard
}
884 c896fe29 bellard
885 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
886 c896fe29 bellard
{
887 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
888 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
889 c896fe29 bellard
}
890 c896fe29 bellard
891 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
892 c896fe29 bellard
{
893 a7812ae4 pbrook
    tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
894 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
895 c896fe29 bellard
}
896 c896fe29 bellard
897 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
898 c896fe29 bellard
   specific code (x86) */
899 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
900 c896fe29 bellard
{
901 2bece2c8 Richard Henderson
    int sizemask = 0;
902 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
903 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
904 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
905 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
906 2bece2c8 Richard Henderson
907 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
908 c896fe29 bellard
}
909 c896fe29 bellard
910 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
911 c896fe29 bellard
{
912 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
913 c896fe29 bellard
}
914 c896fe29 bellard
915 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
916 c896fe29 bellard
{
917 2bece2c8 Richard Henderson
    int sizemask = 0;
918 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
919 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
920 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
921 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
922 2bece2c8 Richard Henderson
923 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
924 c896fe29 bellard
}
925 c896fe29 bellard
926 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
927 c896fe29 bellard
{
928 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
929 c896fe29 bellard
}
930 c896fe29 bellard
931 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
932 c896fe29 bellard
{
933 2bece2c8 Richard Henderson
    int sizemask = 0;
934 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
935 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
936 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
937 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
938 2bece2c8 Richard Henderson
939 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
940 c896fe29 bellard
}
941 c896fe29 bellard
942 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
943 c896fe29 bellard
{
944 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
945 c896fe29 bellard
}
946 c896fe29 bellard
947 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
948 8a56e840 Richard Henderson
                                      TCGv_i64 arg2, int label_index)
949 c896fe29 bellard
{
950 a7812ae4 pbrook
    tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
951 a7812ae4 pbrook
                      TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
952 a7812ae4 pbrook
                      TCGV_HIGH(arg2), cond, label_index);
953 c896fe29 bellard
}
954 c896fe29 bellard
955 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
956 5105c556 Aurelien Jarno
                                       TCGv_i64 arg1, TCGv_i64 arg2)
957 5105c556 Aurelien Jarno
{
958 5105c556 Aurelien Jarno
    tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
959 5105c556 Aurelien Jarno
                     TCGV_LOW(arg1), TCGV_HIGH(arg1),
960 5105c556 Aurelien Jarno
                     TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
961 5105c556 Aurelien Jarno
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
962 5105c556 Aurelien Jarno
}
963 5105c556 Aurelien Jarno
964 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
965 c896fe29 bellard
{
966 a7812ae4 pbrook
    TCGv_i64 t0;
967 a7812ae4 pbrook
    TCGv_i32 t1;
968 c896fe29 bellard
969 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
970 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
971 a7812ae4 pbrook
972 a7812ae4 pbrook
    tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
973 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_LOW(arg2));
974 a7812ae4 pbrook
975 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
976 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
977 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
978 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
979 a7812ae4 pbrook
980 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
981 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
982 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
983 c896fe29 bellard
}
984 c896fe29 bellard
985 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
986 c896fe29 bellard
{
987 2bece2c8 Richard Henderson
    int sizemask = 0;
988 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
989 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
990 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
991 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
992 2bece2c8 Richard Henderson
993 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
994 c896fe29 bellard
}
995 c896fe29 bellard
996 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
997 c896fe29 bellard
{
998 2bece2c8 Richard Henderson
    int sizemask = 0;
999 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
1000 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
1001 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1002 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1003 2bece2c8 Richard Henderson
1004 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1005 c896fe29 bellard
}
1006 c896fe29 bellard
1007 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1008 c896fe29 bellard
{
1009 2bece2c8 Richard Henderson
    int sizemask = 0;
1010 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1011 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1012 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1013 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1014 2bece2c8 Richard Henderson
1015 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1016 c896fe29 bellard
}
1017 c896fe29 bellard
1018 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1019 c896fe29 bellard
{
1020 2bece2c8 Richard Henderson
    int sizemask = 0;
1021 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1022 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1023 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1024 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1025 2bece2c8 Richard Henderson
1026 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1027 c896fe29 bellard
}
1028 c896fe29 bellard
1029 c896fe29 bellard
#else
1030 c896fe29 bellard
1031 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1032 c896fe29 bellard
{
1033 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg))
1034 a7812ae4 pbrook
        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
1035 c896fe29 bellard
}
1036 c896fe29 bellard
1037 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1038 c896fe29 bellard
{
1039 a7812ae4 pbrook
    tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
1040 c896fe29 bellard
}
1041 c896fe29 bellard
1042 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1043 ac56dd48 pbrook
                                    tcg_target_long offset)
1044 c896fe29 bellard
{
1045 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
1046 c896fe29 bellard
}
1047 c896fe29 bellard
1048 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1049 ac56dd48 pbrook
                                    tcg_target_long offset)
1050 c896fe29 bellard
{
1051 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
1052 c896fe29 bellard
}
1053 c896fe29 bellard
1054 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1055 ac56dd48 pbrook
                                     tcg_target_long offset)
1056 c896fe29 bellard
{
1057 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
1058 c896fe29 bellard
}
1059 c896fe29 bellard
1060 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1061 ac56dd48 pbrook
                                     tcg_target_long offset)
1062 c896fe29 bellard
{
1063 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
1064 c896fe29 bellard
}
1065 c896fe29 bellard
1066 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1067 ac56dd48 pbrook
                                     tcg_target_long offset)
1068 c896fe29 bellard
{
1069 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
1070 c896fe29 bellard
}
1071 c896fe29 bellard
1072 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1073 ac56dd48 pbrook
                                     tcg_target_long offset)
1074 c896fe29 bellard
{
1075 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
1076 c896fe29 bellard
}
1077 c896fe29 bellard
1078 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
1079 c896fe29 bellard
{
1080 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
1081 c896fe29 bellard
}
1082 c896fe29 bellard
1083 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1084 ac56dd48 pbrook
                                   tcg_target_long offset)
1085 c896fe29 bellard
{
1086 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
1087 c896fe29 bellard
}
1088 c896fe29 bellard
1089 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1090 ac56dd48 pbrook
                                    tcg_target_long offset)
1091 c896fe29 bellard
{
1092 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
1093 c896fe29 bellard
}
1094 c896fe29 bellard
1095 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1096 ac56dd48 pbrook
                                    tcg_target_long offset)
1097 c896fe29 bellard
{
1098 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
1099 c896fe29 bellard
}
1100 c896fe29 bellard
1101 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
1102 c896fe29 bellard
{
1103 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
1104 c896fe29 bellard
}
1105 c896fe29 bellard
1106 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1107 c896fe29 bellard
{
1108 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
1109 c896fe29 bellard
}
1110 c896fe29 bellard
1111 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1112 c896fe29 bellard
{
1113 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1114 c896fe29 bellard
}
1115 c896fe29 bellard
1116 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1117 c896fe29 bellard
{
1118 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1119 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
1120 7fc81051 aurel32
    } else {
1121 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1122 7fc81051 aurel32
    }
1123 c896fe29 bellard
}
1124 c896fe29 bellard
1125 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1126 c896fe29 bellard
{
1127 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1128 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
1129 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1130 c896fe29 bellard
}
1131 c896fe29 bellard
1132 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1133 c896fe29 bellard
{
1134 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1135 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
1136 7fc81051 aurel32
    } else {
1137 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1138 7fc81051 aurel32
    }
1139 c896fe29 bellard
}
1140 c896fe29 bellard
1141 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1142 c896fe29 bellard
{
1143 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1144 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
1145 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1146 c896fe29 bellard
}
1147 c896fe29 bellard
1148 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1149 c896fe29 bellard
{
1150 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1151 7fc81051 aurel32
        tcg_gen_movi_i64(ret, 0);
1152 7fc81051 aurel32
    } else {
1153 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1154 7fc81051 aurel32
    }
1155 c896fe29 bellard
}
1156 c896fe29 bellard
1157 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1158 c896fe29 bellard
{
1159 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1160 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
1161 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1162 c896fe29 bellard
}
1163 c896fe29 bellard
1164 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1165 c896fe29 bellard
{
1166 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1167 c896fe29 bellard
}
1168 c896fe29 bellard
1169 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1170 c896fe29 bellard
{
1171 34151a20 bellard
    if (arg2 == 0) {
1172 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1173 34151a20 bellard
    } else {
1174 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1175 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
1176 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1177 34151a20 bellard
    }
1178 c896fe29 bellard
}
1179 c896fe29 bellard
1180 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1181 c896fe29 bellard
{
1182 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1183 c896fe29 bellard
}
1184 c896fe29 bellard
1185 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1186 c896fe29 bellard
{
1187 34151a20 bellard
    if (arg2 == 0) {
1188 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1189 34151a20 bellard
    } else {
1190 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1191 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
1192 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1193 34151a20 bellard
    }
1194 c896fe29 bellard
}
1195 c896fe29 bellard
1196 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1197 c896fe29 bellard
{
1198 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1199 c896fe29 bellard
}
1200 c896fe29 bellard
1201 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1202 c896fe29 bellard
{
1203 34151a20 bellard
    if (arg2 == 0) {
1204 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1205 34151a20 bellard
    } else {
1206 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1207 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
1208 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1209 34151a20 bellard
    }
1210 c896fe29 bellard
}
1211 c896fe29 bellard
1212 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1213 8a56e840 Richard Henderson
                                      TCGv_i64 arg2, int label_index)
1214 c896fe29 bellard
{
1215 a7812ae4 pbrook
    tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1216 c896fe29 bellard
}
1217 c896fe29 bellard
1218 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1219 5105c556 Aurelien Jarno
                                       TCGv_i64 arg1, TCGv_i64 arg2)
1220 5105c556 Aurelien Jarno
{
1221 5105c556 Aurelien Jarno
    tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1222 5105c556 Aurelien Jarno
}
1223 5105c556 Aurelien Jarno
1224 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1225 c896fe29 bellard
{
1226 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1227 c896fe29 bellard
}
1228 c896fe29 bellard
1229 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
1230 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1231 c896fe29 bellard
{
1232 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1233 c896fe29 bellard
}
1234 c896fe29 bellard
1235 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1236 c896fe29 bellard
{
1237 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1238 c896fe29 bellard
}
1239 c896fe29 bellard
1240 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1241 c896fe29 bellard
{
1242 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1243 c896fe29 bellard
}
1244 c896fe29 bellard
1245 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1246 c896fe29 bellard
{
1247 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1248 c896fe29 bellard
}
1249 31d66551 Aurelien Jarno
#elif defined(TCG_TARGET_HAS_div2_i64)
1250 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1251 c896fe29 bellard
{
1252 a7812ae4 pbrook
    TCGv_i64 t0;
1253 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1254 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1255 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1256 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1257 c896fe29 bellard
}
1258 c896fe29 bellard
1259 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1260 c896fe29 bellard
{
1261 a7812ae4 pbrook
    TCGv_i64 t0;
1262 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1263 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1264 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1265 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1266 c896fe29 bellard
}
1267 c896fe29 bellard
1268 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1269 c896fe29 bellard
{
1270 a7812ae4 pbrook
    TCGv_i64 t0;
1271 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1272 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1273 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1274 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1275 c896fe29 bellard
}
1276 c896fe29 bellard
1277 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1278 c896fe29 bellard
{
1279 a7812ae4 pbrook
    TCGv_i64 t0;
1280 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1281 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1282 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1283 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1284 c896fe29 bellard
}
1285 31d66551 Aurelien Jarno
#else
1286 31d66551 Aurelien Jarno
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1287 31d66551 Aurelien Jarno
{
1288 2bece2c8 Richard Henderson
    int sizemask = 0;
1289 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
1290 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
1291 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1292 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1293 2bece2c8 Richard Henderson
1294 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1295 31d66551 Aurelien Jarno
}
1296 31d66551 Aurelien Jarno
1297 31d66551 Aurelien Jarno
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1298 31d66551 Aurelien Jarno
{
1299 2bece2c8 Richard Henderson
    int sizemask = 0;
1300 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
1301 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
1302 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1303 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1304 2bece2c8 Richard Henderson
1305 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1306 31d66551 Aurelien Jarno
}
1307 31d66551 Aurelien Jarno
1308 31d66551 Aurelien Jarno
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1309 31d66551 Aurelien Jarno
{
1310 2bece2c8 Richard Henderson
    int sizemask = 0;
1311 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1312 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1313 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1314 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1315 2bece2c8 Richard Henderson
1316 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1317 31d66551 Aurelien Jarno
}
1318 31d66551 Aurelien Jarno
1319 31d66551 Aurelien Jarno
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1320 31d66551 Aurelien Jarno
{
1321 2bece2c8 Richard Henderson
    int sizemask = 0;
1322 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1323 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1324 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1325 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1326 2bece2c8 Richard Henderson
1327 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1328 31d66551 Aurelien Jarno
}
1329 c896fe29 bellard
#endif
1330 c896fe29 bellard
1331 c896fe29 bellard
#endif
1332 c896fe29 bellard
1333 a7812ae4 pbrook
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1334 6359706f aurel32
{
1335 6359706f aurel32
    /* some cases can be optimized here */
1336 6359706f aurel32
    if (arg2 == 0) {
1337 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1338 6359706f aurel32
    } else {
1339 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1340 6359706f aurel32
        tcg_gen_add_i64(ret, arg1, t0);
1341 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1342 6359706f aurel32
    }
1343 6359706f aurel32
}
1344 6359706f aurel32
1345 a7812ae4 pbrook
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1346 0045734a aurel32
{
1347 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg1);
1348 0045734a aurel32
    tcg_gen_sub_i64(ret, t0, arg2);
1349 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1350 0045734a aurel32
}
1351 0045734a aurel32
1352 a7812ae4 pbrook
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1353 6359706f aurel32
{
1354 6359706f aurel32
    /* some cases can be optimized here */
1355 6359706f aurel32
    if (arg2 == 0) {
1356 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1357 6359706f aurel32
    } else {
1358 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1359 6359706f aurel32
        tcg_gen_sub_i64(ret, arg1, t0);
1360 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1361 6359706f aurel32
    }
1362 6359706f aurel32
}
1363 8a56e840 Richard Henderson
static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1364 8a56e840 Richard Henderson
                                       int64_t arg2, int label_index)
1365 f02bb954 aurel32
{
1366 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1367 f02bb954 aurel32
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1368 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1369 f02bb954 aurel32
}
1370 f02bb954 aurel32
1371 8a56e840 Richard Henderson
static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1372 8a56e840 Richard Henderson
                                        TCGv_i64 arg1, int64_t arg2)
1373 5105c556 Aurelien Jarno
{
1374 5105c556 Aurelien Jarno
    TCGv_i64 t0 = tcg_const_i64(arg2);
1375 5105c556 Aurelien Jarno
    tcg_gen_setcond_i64(cond, ret, arg1, t0);
1376 5105c556 Aurelien Jarno
    tcg_temp_free_i64(t0);
1377 5105c556 Aurelien Jarno
}
1378 5105c556 Aurelien Jarno
1379 a7812ae4 pbrook
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1380 f02bb954 aurel32
{
1381 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1382 f02bb954 aurel32
    tcg_gen_mul_i64(ret, arg1, t0);
1383 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1384 f02bb954 aurel32
}
1385 f02bb954 aurel32
1386 6359706f aurel32
1387 c896fe29 bellard
/***************************************/
1388 c896fe29 bellard
/* optional operations */
1389 c896fe29 bellard
1390 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1391 c896fe29 bellard
{
1392 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
1393 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1394 c896fe29 bellard
#else
1395 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
1396 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
1397 c896fe29 bellard
#endif
1398 c896fe29 bellard
}
1399 c896fe29 bellard
1400 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1401 c896fe29 bellard
{
1402 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
1403 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1404 c896fe29 bellard
#else
1405 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
1406 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
1407 c896fe29 bellard
#endif
1408 c896fe29 bellard
}
1409 c896fe29 bellard
1410 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1411 86831435 pbrook
{
1412 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i32
1413 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1414 cfc86988 Aurelien Jarno
#else
1415 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
1416 cfc86988 Aurelien Jarno
#endif
1417 86831435 pbrook
}
1418 86831435 pbrook
1419 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1420 86831435 pbrook
{
1421 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i32
1422 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1423 cfc86988 Aurelien Jarno
#else
1424 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
1425 cfc86988 Aurelien Jarno
#endif
1426 86831435 pbrook
}
1427 86831435 pbrook
1428 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1429 a7812ae4 pbrook
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1430 c896fe29 bellard
{
1431 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
1432 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1433 c896fe29 bellard
#else
1434 dfa1a3f1 aurel32
    TCGv_i32 t0 = tcg_temp_new_i32();
1435 c896fe29 bellard
    
1436 dfa1a3f1 aurel32
    tcg_gen_ext8u_i32(t0, arg);
1437 dfa1a3f1 aurel32
    tcg_gen_shli_i32(t0, t0, 8);
1438 dfa1a3f1 aurel32
    tcg_gen_shri_i32(ret, arg, 8);
1439 dfa1a3f1 aurel32
    tcg_gen_or_i32(ret, ret, t0);
1440 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1441 c896fe29 bellard
#endif
1442 c896fe29 bellard
}
1443 c896fe29 bellard
1444 66896cb8 aurel32
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1445 c896fe29 bellard
{
1446 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap32_i32
1447 66896cb8 aurel32
    tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1448 c896fe29 bellard
#else
1449 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1450 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1451 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1452 c896fe29 bellard
    
1453 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1454 c896fe29 bellard
    
1455 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1456 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1457 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1458 c896fe29 bellard
    
1459 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1460 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1461 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1462 c896fe29 bellard
    
1463 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1464 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1465 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1466 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1467 c896fe29 bellard
#endif
1468 c896fe29 bellard
}
1469 c896fe29 bellard
1470 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1471 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1472 c896fe29 bellard
{
1473 a7812ae4 pbrook
    tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1474 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1475 c896fe29 bellard
}
1476 c896fe29 bellard
1477 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1478 c896fe29 bellard
{
1479 a7812ae4 pbrook
    tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1480 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1481 c896fe29 bellard
}
1482 c896fe29 bellard
1483 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1484 c896fe29 bellard
{
1485 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1486 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1487 c896fe29 bellard
}
1488 c896fe29 bellard
1489 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1490 86831435 pbrook
{
1491 a7812ae4 pbrook
    tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1492 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1493 86831435 pbrook
}
1494 86831435 pbrook
1495 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1496 86831435 pbrook
{
1497 a7812ae4 pbrook
    tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1498 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1499 86831435 pbrook
}
1500 86831435 pbrook
1501 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1502 86831435 pbrook
{
1503 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1504 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1505 86831435 pbrook
}
1506 86831435 pbrook
1507 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1508 c896fe29 bellard
{
1509 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1510 c896fe29 bellard
}
1511 c896fe29 bellard
1512 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1513 c896fe29 bellard
{
1514 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1515 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1516 c896fe29 bellard
}
1517 c896fe29 bellard
1518 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1519 c896fe29 bellard
{
1520 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1521 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1522 c896fe29 bellard
}
1523 c896fe29 bellard
1524 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1525 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1526 9a5c57fd aurel32
{
1527 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1528 9a5c57fd aurel32
    tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1529 9a5c57fd aurel32
}
1530 9a5c57fd aurel32
1531 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1532 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1533 9a5c57fd aurel32
{
1534 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1535 9a5c57fd aurel32
    tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1536 9a5c57fd aurel32
}
1537 9a5c57fd aurel32
1538 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1539 c896fe29 bellard
{
1540 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1541 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1542 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1543 c896fe29 bellard
1544 66896cb8 aurel32
    tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1545 66896cb8 aurel32
    tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1546 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1547 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1548 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1549 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1550 c896fe29 bellard
}
1551 c896fe29 bellard
#else
1552 c896fe29 bellard
1553 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1554 c896fe29 bellard
{
1555 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1556 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1557 c896fe29 bellard
#else
1558 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1559 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1560 c896fe29 bellard
#endif
1561 c896fe29 bellard
}
1562 c896fe29 bellard
1563 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1564 c896fe29 bellard
{
1565 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1566 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1567 c896fe29 bellard
#else
1568 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1569 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1570 c896fe29 bellard
#endif
1571 c896fe29 bellard
}
1572 c896fe29 bellard
1573 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1574 c896fe29 bellard
{
1575 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1576 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1577 c896fe29 bellard
#else
1578 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1579 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1580 c896fe29 bellard
#endif
1581 c896fe29 bellard
}
1582 c896fe29 bellard
1583 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1584 86831435 pbrook
{
1585 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i64
1586 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1587 cfc86988 Aurelien Jarno
#else
1588 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1589 cfc86988 Aurelien Jarno
#endif
1590 86831435 pbrook
}
1591 86831435 pbrook
1592 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1593 86831435 pbrook
{
1594 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i64
1595 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1596 cfc86988 Aurelien Jarno
#else
1597 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1598 cfc86988 Aurelien Jarno
#endif
1599 86831435 pbrook
}
1600 86831435 pbrook
1601 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1602 86831435 pbrook
{
1603 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext32u_i64
1604 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1605 cfc86988 Aurelien Jarno
#else
1606 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1607 cfc86988 Aurelien Jarno
#endif
1608 86831435 pbrook
}
1609 86831435 pbrook
1610 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1611 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1612 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1613 c896fe29 bellard
{
1614 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1615 c896fe29 bellard
}
1616 c896fe29 bellard
1617 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1618 c896fe29 bellard
   registers */
1619 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1620 c896fe29 bellard
{
1621 cfc86988 Aurelien Jarno
    tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1622 c896fe29 bellard
}
1623 c896fe29 bellard
1624 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1625 c896fe29 bellard
   registers */
1626 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1627 c896fe29 bellard
{
1628 a7812ae4 pbrook
    tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1629 c896fe29 bellard
}
1630 c896fe29 bellard
1631 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1632 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1633 9a5c57fd aurel32
{
1634 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap16_i64
1635 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1636 9a5c57fd aurel32
#else
1637 9a5c57fd aurel32
    TCGv_i64 t0 = tcg_temp_new_i64();
1638 9a5c57fd aurel32
1639 9a5c57fd aurel32
    tcg_gen_ext8u_i64(t0, arg);
1640 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, t0, 8);
1641 9a5c57fd aurel32
    tcg_gen_shri_i64(ret, arg, 8);
1642 9a5c57fd aurel32
    tcg_gen_or_i64(ret, ret, t0);
1643 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1644 9a5c57fd aurel32
#endif
1645 9a5c57fd aurel32
}
1646 9a5c57fd aurel32
1647 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1648 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1649 9a5c57fd aurel32
{
1650 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap32_i64
1651 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1652 9a5c57fd aurel32
#else
1653 9a5c57fd aurel32
    TCGv_i64 t0, t1;
1654 9a5c57fd aurel32
    t0 = tcg_temp_new_i64();
1655 9a5c57fd aurel32
    t1 = tcg_temp_new_i64();
1656 9a5c57fd aurel32
1657 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, arg, 24);
1658 9a5c57fd aurel32
    tcg_gen_ext32u_i64(t0, t0);
1659 9a5c57fd aurel32
1660 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1661 9a5c57fd aurel32
    tcg_gen_shli_i64(t1, t1, 8);
1662 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1663 9a5c57fd aurel32
1664 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 8);
1665 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1666 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1667 9a5c57fd aurel32
1668 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 24);
1669 9a5c57fd aurel32
    tcg_gen_or_i64(ret, t0, t1);
1670 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1671 9a5c57fd aurel32
    tcg_temp_free_i64(t1);
1672 9a5c57fd aurel32
#endif
1673 9a5c57fd aurel32
}
1674 9a5c57fd aurel32
1675 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1676 c896fe29 bellard
{
1677 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap64_i64
1678 66896cb8 aurel32
    tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1679 c896fe29 bellard
#else
1680 b348113d Stefan Weil
    TCGv_i64 t0 = tcg_temp_new_i64();
1681 b348113d Stefan Weil
    TCGv_i64 t1 = tcg_temp_new_i64();
1682 c896fe29 bellard
    
1683 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1684 c896fe29 bellard
    
1685 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1686 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1687 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1688 c896fe29 bellard
    
1689 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1690 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1691 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1692 c896fe29 bellard
1693 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1694 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1695 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1696 c896fe29 bellard
1697 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1698 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1699 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1700 c896fe29 bellard
    
1701 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1702 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1703 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1704 c896fe29 bellard
1705 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1706 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1707 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1708 c896fe29 bellard
1709 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1710 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1711 b348113d Stefan Weil
    tcg_temp_free_i64(t0);
1712 b348113d Stefan Weil
    tcg_temp_free_i64(t1);
1713 c896fe29 bellard
#endif
1714 c896fe29 bellard
}
1715 c896fe29 bellard
1716 c896fe29 bellard
#endif
1717 c896fe29 bellard
1718 a7812ae4 pbrook
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1719 390efc54 pbrook
{
1720 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1721 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1722 390efc54 pbrook
#else
1723 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(0);
1724 e8996ee0 bellard
    tcg_gen_sub_i32(ret, t0, arg);
1725 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1726 390efc54 pbrook
#endif
1727 390efc54 pbrook
}
1728 390efc54 pbrook
1729 a7812ae4 pbrook
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1730 390efc54 pbrook
{
1731 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1732 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1733 390efc54 pbrook
#else
1734 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(0);
1735 e8996ee0 bellard
    tcg_gen_sub_i64(ret, t0, arg);
1736 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1737 390efc54 pbrook
#endif
1738 390efc54 pbrook
}
1739 390efc54 pbrook
1740 a7812ae4 pbrook
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1741 0b6ce4cf bellard
{
1742 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i32
1743 d2604285 aurel32
    tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1744 d2604285 aurel32
#else
1745 e8996ee0 bellard
    tcg_gen_xori_i32(ret, arg, -1);
1746 d2604285 aurel32
#endif
1747 0b6ce4cf bellard
}
1748 0b6ce4cf bellard
1749 a7812ae4 pbrook
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1750 0b6ce4cf bellard
{
1751 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i64
1752 43e860ef aurel32
    tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1753 a10f9f4f Richard Henderson
#elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32
1754 a10f9f4f Richard Henderson
    tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1755 a10f9f4f Richard Henderson
    tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1756 d2604285 aurel32
#else
1757 e8996ee0 bellard
    tcg_gen_xori_i64(ret, arg, -1);
1758 d2604285 aurel32
#endif
1759 0b6ce4cf bellard
}
1760 5ff9d6a4 bellard
1761 a7812ae4 pbrook
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1762 5ff9d6a4 bellard
{
1763 a7812ae4 pbrook
    tcg_gen_op1_i32(INDEX_op_discard, arg);
1764 5ff9d6a4 bellard
}
1765 5ff9d6a4 bellard
1766 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1767 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1768 5ff9d6a4 bellard
{
1769 a7812ae4 pbrook
    tcg_gen_discard_i32(TCGV_LOW(arg));
1770 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1771 5ff9d6a4 bellard
}
1772 5ff9d6a4 bellard
#else
1773 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1774 5ff9d6a4 bellard
{
1775 a7812ae4 pbrook
    tcg_gen_op1_i64(INDEX_op_discard, arg);
1776 5ff9d6a4 bellard
}
1777 5ff9d6a4 bellard
#endif
1778 5ff9d6a4 bellard
1779 a7812ae4 pbrook
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1780 36aa55dc pbrook
{
1781 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1782 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(dest), low);
1783 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1784 36aa55dc pbrook
#else
1785 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1786 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1787 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1788 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1789 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1790 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1791 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1792 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1793 36aa55dc pbrook
#endif
1794 36aa55dc pbrook
}
1795 36aa55dc pbrook
1796 a7812ae4 pbrook
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1797 945ca823 blueswir1
{
1798 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1799 a7812ae4 pbrook
    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1800 945ca823 blueswir1
#else
1801 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1802 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1803 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1804 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1805 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1806 945ca823 blueswir1
#endif
1807 945ca823 blueswir1
}
1808 945ca823 blueswir1
1809 a7812ae4 pbrook
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1810 f24cb33e aurel32
{
1811 241cbed4 Richard Henderson
#ifdef TCG_TARGET_HAS_andc_i32
1812 241cbed4 Richard Henderson
    tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1813 241cbed4 Richard Henderson
#else
1814 a7812ae4 pbrook
    TCGv_i32 t0;
1815 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1816 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1817 f24cb33e aurel32
    tcg_gen_and_i32(ret, arg1, t0);
1818 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1819 241cbed4 Richard Henderson
#endif
1820 f24cb33e aurel32
}
1821 f24cb33e aurel32
1822 a7812ae4 pbrook
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1823 f24cb33e aurel32
{
1824 241cbed4 Richard Henderson
#ifdef TCG_TARGET_HAS_andc_i64
1825 241cbed4 Richard Henderson
    tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1826 241cbed4 Richard Henderson
#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
1827 241cbed4 Richard Henderson
    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1828 241cbed4 Richard Henderson
    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1829 241cbed4 Richard Henderson
#else
1830 a7812ae4 pbrook
    TCGv_i64 t0;
1831 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1832 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1833 f24cb33e aurel32
    tcg_gen_and_i64(ret, arg1, t0);
1834 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1835 241cbed4 Richard Henderson
#endif
1836 f24cb33e aurel32
}
1837 f24cb33e aurel32
1838 a7812ae4 pbrook
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1839 f24cb33e aurel32
{
1840 8d625cf1 Richard Henderson
#ifdef TCG_TARGET_HAS_eqv_i32
1841 8d625cf1 Richard Henderson
    tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1842 8d625cf1 Richard Henderson
#else
1843 7fc81051 aurel32
    tcg_gen_xor_i32(ret, arg1, arg2);
1844 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1845 8d625cf1 Richard Henderson
#endif
1846 f24cb33e aurel32
}
1847 f24cb33e aurel32
1848 a7812ae4 pbrook
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1849 f24cb33e aurel32
{
1850 8d625cf1 Richard Henderson
#ifdef TCG_TARGET_HAS_eqv_i64
1851 8d625cf1 Richard Henderson
    tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1852 8d625cf1 Richard Henderson
#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32
1853 8d625cf1 Richard Henderson
    tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1854 8d625cf1 Richard Henderson
    tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1855 8d625cf1 Richard Henderson
#else
1856 7fc81051 aurel32
    tcg_gen_xor_i64(ret, arg1, arg2);
1857 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1858 8d625cf1 Richard Henderson
#endif
1859 f24cb33e aurel32
}
1860 f24cb33e aurel32
1861 a7812ae4 pbrook
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1862 f24cb33e aurel32
{
1863 9940a96b Richard Henderson
#ifdef TCG_TARGET_HAS_nand_i32
1864 9940a96b Richard Henderson
    tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1865 9940a96b Richard Henderson
#else
1866 7fc81051 aurel32
    tcg_gen_and_i32(ret, arg1, arg2);
1867 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1868 9940a96b Richard Henderson
#endif
1869 f24cb33e aurel32
}
1870 f24cb33e aurel32
1871 a7812ae4 pbrook
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1872 f24cb33e aurel32
{
1873 9940a96b Richard Henderson
#ifdef TCG_TARGET_HAS_nand_i64
1874 9940a96b Richard Henderson
    tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1875 9940a96b Richard Henderson
#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32
1876 9940a96b Richard Henderson
    tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1877 9940a96b Richard Henderson
    tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1878 9940a96b Richard Henderson
#else
1879 7fc81051 aurel32
    tcg_gen_and_i64(ret, arg1, arg2);
1880 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1881 9940a96b Richard Henderson
#endif
1882 f24cb33e aurel32
}
1883 f24cb33e aurel32
1884 a7812ae4 pbrook
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1885 f24cb33e aurel32
{
1886 32d98fbd Richard Henderson
#ifdef TCG_TARGET_HAS_nor_i32
1887 32d98fbd Richard Henderson
    tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1888 32d98fbd Richard Henderson
#else
1889 7fc81051 aurel32
    tcg_gen_or_i32(ret, arg1, arg2);
1890 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1891 32d98fbd Richard Henderson
#endif
1892 f24cb33e aurel32
}
1893 f24cb33e aurel32
1894 a7812ae4 pbrook
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1895 f24cb33e aurel32
{
1896 32d98fbd Richard Henderson
#ifdef TCG_TARGET_HAS_nor_i64
1897 32d98fbd Richard Henderson
    tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1898 32d98fbd Richard Henderson
#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32
1899 32d98fbd Richard Henderson
    tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1900 32d98fbd Richard Henderson
    tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1901 32d98fbd Richard Henderson
#else
1902 7fc81051 aurel32
    tcg_gen_or_i64(ret, arg1, arg2);
1903 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1904 32d98fbd Richard Henderson
#endif
1905 f24cb33e aurel32
}
1906 f24cb33e aurel32
1907 a7812ae4 pbrook
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1908 f24cb33e aurel32
{
1909 791d1262 Richard Henderson
#ifdef TCG_TARGET_HAS_orc_i32
1910 791d1262 Richard Henderson
    tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1911 791d1262 Richard Henderson
#else
1912 a7812ae4 pbrook
    TCGv_i32 t0;
1913 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1914 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1915 f24cb33e aurel32
    tcg_gen_or_i32(ret, arg1, t0);
1916 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1917 791d1262 Richard Henderson
#endif
1918 f24cb33e aurel32
}
1919 f24cb33e aurel32
1920 a7812ae4 pbrook
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1921 f24cb33e aurel32
{
1922 791d1262 Richard Henderson
#ifdef TCG_TARGET_HAS_orc_i64
1923 791d1262 Richard Henderson
    tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1924 791d1262 Richard Henderson
#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
1925 791d1262 Richard Henderson
    tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1926 791d1262 Richard Henderson
    tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1927 791d1262 Richard Henderson
#else
1928 a7812ae4 pbrook
    TCGv_i64 t0;
1929 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1930 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1931 f24cb33e aurel32
    tcg_gen_or_i64(ret, arg1, t0);
1932 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1933 791d1262 Richard Henderson
#endif
1934 f24cb33e aurel32
}
1935 f24cb33e aurel32
1936 a7812ae4 pbrook
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1937 15824571 aurel32
{
1938 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1939 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1940 d42f183c aurel32
#else
1941 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1942 15824571 aurel32
1943 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1944 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1945 15824571 aurel32
    tcg_gen_shl_i32(t0, arg1, arg2);
1946 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1947 15824571 aurel32
    tcg_gen_shr_i32(t1, arg1, t1);
1948 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1949 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1950 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1951 d42f183c aurel32
#endif
1952 15824571 aurel32
}
1953 15824571 aurel32
1954 a7812ae4 pbrook
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1955 15824571 aurel32
{
1956 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1957 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1958 d42f183c aurel32
#else
1959 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1960 15824571 aurel32
1961 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1962 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1963 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1964 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1965 15824571 aurel32
    tcg_gen_shr_i64(t1, arg1, t1);
1966 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1967 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1968 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1969 d42f183c aurel32
#endif
1970 15824571 aurel32
}
1971 15824571 aurel32
1972 a7812ae4 pbrook
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1973 15824571 aurel32
{
1974 15824571 aurel32
    /* some cases can be optimized here */
1975 15824571 aurel32
    if (arg2 == 0) {
1976 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1977 15824571 aurel32
    } else {
1978 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1979 d42f183c aurel32
        TCGv_i32 t0 = tcg_const_i32(arg2);
1980 d42f183c aurel32
        tcg_gen_rotl_i32(ret, arg1, t0);
1981 d42f183c aurel32
        tcg_temp_free_i32(t0);
1982 d42f183c aurel32
#else
1983 a7812ae4 pbrook
        TCGv_i32 t0, t1;
1984 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
1985 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
1986 15824571 aurel32
        tcg_gen_shli_i32(t0, arg1, arg2);
1987 15824571 aurel32
        tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1988 15824571 aurel32
        tcg_gen_or_i32(ret, t0, t1);
1989 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
1990 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
1991 d42f183c aurel32
#endif
1992 15824571 aurel32
    }
1993 15824571 aurel32
}
1994 15824571 aurel32
1995 a7812ae4 pbrook
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1996 15824571 aurel32
{
1997 15824571 aurel32
    /* some cases can be optimized here */
1998 15824571 aurel32
    if (arg2 == 0) {
1999 15824571 aurel32
        tcg_gen_mov_i64(ret, arg1);
2000 15824571 aurel32
    } else {
2001 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
2002 d42f183c aurel32
        TCGv_i64 t0 = tcg_const_i64(arg2);
2003 d42f183c aurel32
        tcg_gen_rotl_i64(ret, arg1, t0);
2004 d42f183c aurel32
        tcg_temp_free_i64(t0);
2005 d42f183c aurel32
#else
2006 a7812ae4 pbrook
        TCGv_i64 t0, t1;
2007 a7812ae4 pbrook
        t0 = tcg_temp_new_i64();
2008 a7812ae4 pbrook
        t1 = tcg_temp_new_i64();
2009 15824571 aurel32
        tcg_gen_shli_i64(t0, arg1, arg2);
2010 15824571 aurel32
        tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2011 15824571 aurel32
        tcg_gen_or_i64(ret, t0, t1);
2012 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
2013 a7812ae4 pbrook
        tcg_temp_free_i64(t1);
2014 d42f183c aurel32
#endif
2015 15824571 aurel32
    }
2016 15824571 aurel32
}
2017 15824571 aurel32
2018 a7812ae4 pbrook
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
2019 15824571 aurel32
{
2020 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
2021 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2022 d42f183c aurel32
#else
2023 a7812ae4 pbrook
    TCGv_i32 t0, t1;
2024 15824571 aurel32
2025 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
2026 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
2027 15824571 aurel32
    tcg_gen_shr_i32(t0, arg1, arg2);
2028 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
2029 15824571 aurel32
    tcg_gen_shl_i32(t1, arg1, t1);
2030 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
2031 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
2032 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
2033 d42f183c aurel32
#endif
2034 15824571 aurel32
}
2035 15824571 aurel32
2036 a7812ae4 pbrook
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2037 15824571 aurel32
{
2038 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
2039 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2040 d42f183c aurel32
#else
2041 a7812ae4 pbrook
    TCGv_i64 t0, t1;
2042 15824571 aurel32
2043 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
2044 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
2045 d9885a0b Aurelien Jarno
    tcg_gen_shr_i64(t0, arg1, arg2);
2046 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
2047 15824571 aurel32
    tcg_gen_shl_i64(t1, arg1, t1);
2048 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
2049 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
2050 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
2051 d42f183c aurel32
#endif
2052 15824571 aurel32
}
2053 15824571 aurel32
2054 a7812ae4 pbrook
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2055 15824571 aurel32
{
2056 15824571 aurel32
    /* some cases can be optimized here */
2057 15824571 aurel32
    if (arg2 == 0) {
2058 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
2059 15824571 aurel32
    } else {
2060 15824571 aurel32
        tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2061 15824571 aurel32
    }
2062 15824571 aurel32
}
2063 15824571 aurel32
2064 a7812ae4 pbrook
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2065 15824571 aurel32
{
2066 15824571 aurel32
    /* some cases can be optimized here */
2067 15824571 aurel32
    if (arg2 == 0) {
2068 de3526b2 pbrook
        tcg_gen_mov_i64(ret, arg1);
2069 15824571 aurel32
    } else {
2070 15824571 aurel32
        tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2071 15824571 aurel32
    }
2072 15824571 aurel32
}
2073 15824571 aurel32
2074 c896fe29 bellard
/***************************************/
2075 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
2076 c896fe29 bellard
   type. */
2077 c896fe29 bellard
#ifndef TARGET_LONG_BITS
2078 c896fe29 bellard
#error must include QEMU headers
2079 c896fe29 bellard
#endif
2080 c896fe29 bellard
2081 a7812ae4 pbrook
#if TARGET_LONG_BITS == 32
2082 a7812ae4 pbrook
#define TCGv TCGv_i32
2083 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i32()
2084 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i32
2085 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i32
2086 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
2087 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i32
2088 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2089 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2090 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2091 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2092 a7812ae4 pbrook
#else
2093 a7812ae4 pbrook
#define TCGv TCGv_i64
2094 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i64()
2095 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i64
2096 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i64
2097 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i64()
2098 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i64
2099 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2100 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2101 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2102 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2103 a7812ae4 pbrook
#endif
2104 a7812ae4 pbrook
2105 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
2106 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
2107 7e4597d7 bellard
{
2108 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
2109 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2110 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
2111 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
2112 7e4597d7 bellard
#else
2113 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2114 7e4597d7 bellard
#endif
2115 7e4597d7 bellard
}
2116 7e4597d7 bellard
2117 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
2118 c896fe29 bellard
{
2119 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
2120 c896fe29 bellard
}
2121 c896fe29 bellard
2122 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
2123 c896fe29 bellard
{
2124 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
2125 c896fe29 bellard
}
2126 c896fe29 bellard
2127 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
2128 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2129 c896fe29 bellard
{
2130 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2131 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2132 c896fe29 bellard
#else
2133 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2134 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2135 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2136 c896fe29 bellard
#endif
2137 c896fe29 bellard
}
2138 c896fe29 bellard
2139 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2140 c896fe29 bellard
{
2141 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2142 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2143 c896fe29 bellard
#else
2144 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2145 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2146 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2147 c896fe29 bellard
#endif
2148 c896fe29 bellard
}
2149 c896fe29 bellard
2150 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2151 c896fe29 bellard
{
2152 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2153 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2154 c896fe29 bellard
#else
2155 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2156 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2157 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2158 c896fe29 bellard
#endif
2159 c896fe29 bellard
}
2160 c896fe29 bellard
2161 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2162 c896fe29 bellard
{
2163 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2164 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2165 c896fe29 bellard
#else
2166 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2167 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2168 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2169 c896fe29 bellard
#endif
2170 c896fe29 bellard
}
2171 c896fe29 bellard
2172 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2173 c896fe29 bellard
{
2174 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2175 86feb1c8 Richard Henderson
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2176 c896fe29 bellard
#else
2177 86feb1c8 Richard Henderson
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2178 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2179 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2180 c896fe29 bellard
#endif
2181 c896fe29 bellard
}
2182 c896fe29 bellard
2183 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2184 c896fe29 bellard
{
2185 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2186 86feb1c8 Richard Henderson
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2187 c896fe29 bellard
#else
2188 86feb1c8 Richard Henderson
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2189 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2190 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2191 c896fe29 bellard
#endif
2192 c896fe29 bellard
}
2193 c896fe29 bellard
2194 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2195 c896fe29 bellard
{
2196 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2197 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2198 c896fe29 bellard
#else
2199 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2200 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2201 c896fe29 bellard
#endif
2202 c896fe29 bellard
}
2203 c896fe29 bellard
2204 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2205 c896fe29 bellard
{
2206 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2207 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2208 c896fe29 bellard
#else
2209 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2210 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2211 c896fe29 bellard
#endif
2212 c896fe29 bellard
}
2213 c896fe29 bellard
2214 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2215 c896fe29 bellard
{
2216 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2217 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2218 c896fe29 bellard
#else
2219 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2220 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2221 c896fe29 bellard
#endif
2222 c896fe29 bellard
}
2223 c896fe29 bellard
2224 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2225 c896fe29 bellard
{
2226 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2227 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2228 c896fe29 bellard
#else
2229 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2230 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2231 c896fe29 bellard
#endif
2232 c896fe29 bellard
}
2233 c896fe29 bellard
2234 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2235 c896fe29 bellard
{
2236 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2237 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2238 a7812ae4 pbrook
                     mem_index);
2239 c896fe29 bellard
#else
2240 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2241 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2242 c896fe29 bellard
#endif
2243 c896fe29 bellard
}
2244 c896fe29 bellard
2245 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
2246 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
2247 f8422f52 blueswir1
2248 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
2249 c896fe29 bellard
2250 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2251 c896fe29 bellard
{
2252 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2253 c896fe29 bellard
}
2254 c896fe29 bellard
2255 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2256 c896fe29 bellard
{
2257 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2258 c896fe29 bellard
}
2259 c896fe29 bellard
2260 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2261 c896fe29 bellard
{
2262 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2263 c896fe29 bellard
}
2264 c896fe29 bellard
2265 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2266 c896fe29 bellard
{
2267 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2268 c896fe29 bellard
}
2269 c896fe29 bellard
2270 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2271 c896fe29 bellard
{
2272 3e1dbadd Richard Henderson
#if TARGET_LONG_BITS == 32
2273 3e1dbadd Richard Henderson
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2274 3e1dbadd Richard Henderson
#else
2275 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2276 3e1dbadd Richard Henderson
#endif
2277 c896fe29 bellard
}
2278 c896fe29 bellard
2279 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2280 c896fe29 bellard
{
2281 3e1dbadd Richard Henderson
#if TARGET_LONG_BITS == 32
2282 3e1dbadd Richard Henderson
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2283 3e1dbadd Richard Henderson
#else
2284 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2285 3e1dbadd Richard Henderson
#endif
2286 c896fe29 bellard
}
2287 c896fe29 bellard
2288 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2289 c896fe29 bellard
{
2290 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2291 c896fe29 bellard
}
2292 c896fe29 bellard
2293 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2294 c896fe29 bellard
{
2295 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2296 c896fe29 bellard
}
2297 c896fe29 bellard
2298 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2299 c896fe29 bellard
{
2300 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2301 c896fe29 bellard
}
2302 c896fe29 bellard
2303 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2304 c896fe29 bellard
{
2305 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2306 c896fe29 bellard
}
2307 c896fe29 bellard
2308 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2309 c896fe29 bellard
{
2310 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2311 c896fe29 bellard
}
2312 c896fe29 bellard
2313 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
2314 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
2315 f8422f52 blueswir1
2316 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
2317 f8422f52 blueswir1
2318 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
2319 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
2320 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
2321 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2322 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2323 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2324 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2325 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2326 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2327 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
2328 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
2329 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
2330 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
2331 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
2332 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
2333 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
2334 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
2335 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
2336 10460c8a pbrook
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
2337 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
2338 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
2339 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
2340 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
2341 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
2342 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
2343 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
2344 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
2345 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
2346 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
2347 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
2348 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
2349 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
2350 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
2351 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
2352 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2353 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
2354 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2355 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
2356 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i64
2357 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i64
2358 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i64
2359 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i64
2360 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i64
2361 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
2362 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2363 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2364 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2365 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2366 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2367 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2368 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2369 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2370 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2371 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2372 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2373 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2374 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2375 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2376 911d79ba aurel32
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2377 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2378 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i64
2379 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2380 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i64
2381 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i64
2382 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i64
2383 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2384 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2385 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2386 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
2387 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
2388 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i64
2389 f8422f52 blueswir1
#else
2390 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
2391 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
2392 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2393 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2394 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2395 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2396 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2397 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2398 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
2399 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
2400 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
2401 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
2402 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
2403 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
2404 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
2405 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
2406 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
2407 0045734a aurel32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
2408 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
2409 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
2410 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
2411 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i32
2412 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i32
2413 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i32
2414 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i32
2415 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i32
2416 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i32
2417 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i32
2418 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i32
2419 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i32
2420 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
2421 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
2422 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2423 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2424 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
2425 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2426 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
2427 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
2428 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i32
2429 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i32
2430 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i32
2431 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i32
2432 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
2433 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2434 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2435 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2436 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2437 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2438 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2439 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2440 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2441 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2442 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2443 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2444 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2445 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2446 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2447 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2448 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i32
2449 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2450 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i32
2451 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i32
2452 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i32
2453 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2454 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2455 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2456 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2457 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
2458 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i32
2459 f8422f52 blueswir1
#endif
2460 6ddbc6e4 pbrook
2461 6ddbc6e4 pbrook
#if TCG_TARGET_REG_BITS == 32
2462 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i32
2463 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i32
2464 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2465 6ddbc6e4 pbrook
#else /* TCG_TARGET_REG_BITS == 32 */
2466 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i64
2467 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i64
2468 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2469 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */