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root / tcg / ppc64 @ 2bece2c8

# Date Author Comment
2bece2c8 06/16/2010 12:29 pm Richard Henderson

tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.

Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments. Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be...

e4d58b41 06/09/2010 12:18 pm Richard Henderson

tcg: Make some tcg-target.c routines static.

Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

3b6dac34 06/09/2010 12:18 pm Richard Henderson

tcg: Add TYPE parameter to tcg_out_mov.

Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"...

98926b0a 04/07/2010 01:26 am malc

tcg/ppc64: Fix typo

Signed-off-by: malc <>

355b1943 04/05/2010 02:28 am Paul Brook

Split TLB addend and target_phys_addr_t

Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t). However since the introduction of...

86feb1c8 03/27/2010 12:01 am Richard Henderson

tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.

Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with...

32d98fbd 03/26/2010 10:52 pm Richard Henderson

tcg: Allow target-specific implementation of NOR.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

9940a96b 03/26/2010 10:44 pm Richard Henderson

tcg: Allow target-specific implementation of NAND.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

8d625cf1 03/26/2010 10:42 pm Richard Henderson

tcg: Allow target-specific implementation of EQV.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

8a56e840 03/26/2010 10:29 pm Richard Henderson

tcg: Use TCGCond where appropriate.

Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

a9751609 03/26/2010 10:28 pm Richard Henderson

tcg: Name the opcode enumeration.

Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>

a63b5829 03/26/2010 09:48 pm Paolo Bonzini

remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Aurelien Jarno <>

35f6b599 03/12/2010 11:27 pm malc

tcg/ppc64: Only define addend load helpers in softmmu case

Signed-off-by: malc <>

d34f4baf 02/22/2010 08:56 pm malc

tcg/ppc64: Use C90 style comments

Signed-off-by: malc <>

36828256 02/20/2010 10:35 am Richard Henderson

tcg: Add comments for all optional instructions not implemented.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

1cd62ae9 02/07/2010 01:48 am malc

tcg/ppc64: implement setcond

Signed-off-by: malc <>

591d6f1d 12/15/2009 06:45 pm malc

tcg/ppc64: Fix loading of 32bit constants

Signed-off-by: malc <>

5d7ff5bb 12/06/2009 05:20 pm Andreas Faerber

TCG: Mac OS X support for ppc64 target

Darwin/ppc64 does not use function descriptors,
adapt prologue and tcg_out_call accordingly.
GPR2 is available for general use, so let's use it.

http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...

016b2b28 11/24/2009 08:51 pm Aurelien Jarno

tcg/ppc64,x86_64: fix constraints of op_qemu_st64

This op only takes two arguments, not two.

Signed-off-by: Aurelien Jarno <>

f6548c0a 07/18/2009 12:16 pm malc

PPC 32/64 GUEST_BASE support

Signed-off-by: malc <>

4f4a67ae 07/18/2009 12:16 pm malc

Fix LHZX opcode value

Signed-off-by: malc <>

2ffebe2d 04/11/2009 11:19 am malc

Remove reserved registers from tcg_target_reg_alloc_order

Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162

9de187a0 04/11/2009 10:39 am malc

Whack [LS]MW

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162

e63d7abd 03/08/2009 04:45 pm blueswir1

Prune unused TCG_AREGs

Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.

Signed-off-by: Stuart Brady <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162

095271d4 02/11/2009 08:54 pm malc

Add missing r24..r26 to callee save registers

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162

b1503cda 12/22/2008 10:33 pm malc

Use the ARRAY_SIZE() macro where appropriate.

Change from v1:
Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162

902b3d5c 12/10/2008 09:18 pm malc

Introduce and use cache-utils.[ch]

Thanks to Segher Boessenkool and Holis Blanchard.

AIX and Darwin cache inquiry:
http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html

Auxiliary vectors:
http://manugarg.googlepages.com/aboutelfauxiliaryvectors

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162

8421d9e5 11/12/2008 10:36 pm malc

Avoid compiler warning

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5710 c046a42c-6fe2-441c-8c8c-71466251a162

828808f5 11/11/2008 05:04 am malc

Fix alignment problem with some 64bit load/store instructions

LD/STD/LWA require displacement to be multiple of 4, provide
tcg_out_ldsta which checks the supplied displacement and falls
back on indexed variant when the check fails. All uses of
LD/STD/LWA outside of tcg_out_ldst appear to be safe....

d4a9eb1f 10/05/2008 12:59 pm blueswir1

Add some missing static and const qualifiers, reg_names only used if NDEBUG set

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162

3ee1b855 10/02/2008 11:02 pm malc

Optimize 64 bit bswap

Use rldimi instead of rldicr/or pair, saves us one instruction.
Suggested by Hollis Blanchard.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5404 c046a42c-6fe2-441c-8c8c-71466251a162

79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162

735ee40d 08/21/2008 01:39 am malc

Relax qemu_ld/st constraints for !SOFTMMU case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5034 c046a42c-6fe2-441c-8c8c-71466251a162

109719ec 08/21/2008 01:39 am malc

Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5033 c046a42c-6fe2-441c-8c8c-71466251a162

0b7c1d89 08/21/2008 01:39 am malc

Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5032 c046a42c-6fe2-441c-8c8c-71466251a162

a2a546b3 08/21/2008 01:39 am malc

Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warning

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5031 c046a42c-6fe2-441c-8c8c-71466251a162

fe6f943f 07/29/2008 02:46 am malc

Immediate versions of some operations

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4962 c046a42c-6fe2-441c-8c8c-71466251a162

000a2d86 07/29/2008 02:46 am malc

Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162

e924bbec 07/28/2008 10:42 pm malc

Set the L field of CMP[L][I] when dealing with 64 bit quantities

This (along with previous 2 commits) makes X86_64 work on ppc64 too.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4960 c046a42c-6fe2-441c-8c8c-71466251a162

880e52b8 07/28/2008 10:42 pm malc

Fix preprocessor guard condition

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4959 c046a42c-6fe2-441c-8c8c-71466251a162

95153fde 07/28/2008 10:42 pm malc

Remove leftover from previous way to load 64 bit constants

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4958 c046a42c-6fe2-441c-8c8c-71466251a162

4a40e231 07/27/2008 02:09 pm malc

Special-case some paths inside tcg_out_tlb_read

a. Use 32bit arithmetics in TARGET_LONG_BITS 32 case
b. Optimize byte access case in TARGET_LONG_BITS 64 case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4955 c046a42c-6fe2-441c-8c8c-71466251a162

301f6d90 07/27/2008 01:28 pm malc

Fix the opcode value of LWA

That should teach one to not blindly trust documentation that will
(out of the blue) use decimal and binary representation for numbers in
the same chart for no apparent reason and without any prefixes, sigh..

Unbreaks MIPS.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4954 c046a42c-6fe2-441c-8c8c-71466251a162

c070355d 07/26/2008 02:21 pm malc

Relax memory operations constraints

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4950 c046a42c-6fe2-441c-8c8c-71466251a162

b01d9fea 07/26/2008 02:21 pm malc

Fix qemu_ld64 constraint list

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4949 c046a42c-6fe2-441c-8c8c-71466251a162

e03ae7f9 07/26/2008 02:20 pm malc

Use proper offset for LR save slot

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4948 c046a42c-6fe2-441c-8c8c-71466251a162

5424fd10 07/26/2008 02:20 pm malc

Reduce amount of space reserved for tb jump

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4947 c046a42c-6fe2-441c-8c8c-71466251a162

6fc9dbcc 07/26/2008 02:20 pm malc

Fix and improve 64 bit immediate loading

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4946 c046a42c-6fe2-441c-8c8c-71466251a162

450e62e7 07/26/2008 02:20 pm malc

Fix EXTSW arguments

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4945 c046a42c-6fe2-441c-8c8c-71466251a162

e7d05e6f 07/25/2008 01:56 am malc

Use proper value for TCG_TARGET_CALL_STACK_OFFSET

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4941 c046a42c-6fe2-441c-8c8c-71466251a162

a69abbe0 07/24/2008 08:37 pm malc

Emit and use adhoc function descriptor for code_gen_prologue on PPC64

Thus avoiding fragile inline assembly hackery to call into generated
code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4939 c046a42c-6fe2-441c-8c8c-71466251a162

6926be2a 07/23/2008 11:01 pm malc

Remove neg_i32 debugging leftover

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4935 c046a42c-6fe2-441c-8c8c-71466251a162

e46b9681 07/23/2008 11:01 pm malc

Provide extNs_M instructions

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162

1d58ee9f 07/23/2008 11:01 pm malc

Remove stray "i" from mul_i64

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4933 c046a42c-6fe2-441c-8c8c-71466251a162

810260a8 07/23/2008 10:17 pm malc

Preliminary PPC64/Linux host support

ppc64.ld from Heikki Lindholm's patch
http://marc.info/?l=qemu-devel&m=114086179024634&w=2

Issues:
x86_64 tripple faults shortly after decompressing the kernel
No immediate versions of most 64 bit operations
More...
...