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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation for qemu: main translation routines.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 90dc8812 | Scott Wood | * Copyright (C) 2011 Freescale Semiconductor, Inc.
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6 | 79aceca5 | bellard | *
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7 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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8 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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10 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 79aceca5 | bellard | *
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12 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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13 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 79aceca5 | bellard | * Lesser General Public License for more details.
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16 | 79aceca5 | bellard | *
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17 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 79aceca5 | bellard | */
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20 | c6a1c22b | bellard | #include <stdarg.h> |
21 | c6a1c22b | bellard | #include <stdlib.h> |
22 | c6a1c22b | bellard | #include <stdio.h> |
23 | c6a1c22b | bellard | #include <string.h> |
24 | c6a1c22b | bellard | #include <inttypes.h> |
25 | c6a1c22b | bellard | |
26 | 79aceca5 | bellard | #include "cpu.h" |
27 | c6a1c22b | bellard | #include "exec-all.h" |
28 | 79aceca5 | bellard | #include "disas.h" |
29 | 57fec1fe | bellard | #include "tcg-op.h" |
30 | ca10f867 | aurel32 | #include "qemu-common.h" |
31 | 0cfe11ea | aurel32 | #include "host-utils.h" |
32 | 79aceca5 | bellard | |
33 | a7812ae4 | pbrook | #include "helper.h" |
34 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
35 | a7812ae4 | pbrook | #include "helper.h" |
36 | a7812ae4 | pbrook | |
37 | 8cbcb4fa | aurel32 | #define CPU_SINGLE_STEP 0x1 |
38 | 8cbcb4fa | aurel32 | #define CPU_BRANCH_STEP 0x2 |
39 | 8cbcb4fa | aurel32 | #define GDBSTUB_SINGLE_STEP 0x4 |
40 | 8cbcb4fa | aurel32 | |
41 | a750fc0b | j_mayer | /* Include definitions for instructions classes and implementations flags */
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42 | 9fddaa0c | bellard | //#define PPC_DEBUG_DISAS
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43 | 76a66253 | j_mayer | //#define DO_PPC_STATISTICS
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44 | 79aceca5 | bellard | |
45 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_DISAS
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46 | 93fcfe39 | aliguori | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
47 | d12d51d5 | aliguori | #else
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48 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
49 | d12d51d5 | aliguori | #endif
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50 | a750fc0b | j_mayer | /*****************************************************************************/
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51 | a750fc0b | j_mayer | /* Code translation helpers */
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52 | c53be334 | bellard | |
53 | f78fb44e | aurel32 | /* global register indexes */
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54 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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55 | 1d542695 | aurel32 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
56 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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57 | 1d542695 | aurel32 | + 10*4 + 22*5 /* SPE GPRh */ |
58 | f78fb44e | aurel32 | #endif
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59 | a5e26afa | aurel32 | + 10*4 + 22*5 /* FPR */ |
60 | 47e4661c | aurel32 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
61 | 47e4661c | aurel32 | + 8*5 /* CRF */]; |
62 | f78fb44e | aurel32 | static TCGv cpu_gpr[32]; |
63 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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64 | f78fb44e | aurel32 | static TCGv cpu_gprh[32]; |
65 | f78fb44e | aurel32 | #endif
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66 | a7812ae4 | pbrook | static TCGv_i64 cpu_fpr[32]; |
67 | a7812ae4 | pbrook | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; |
68 | a7812ae4 | pbrook | static TCGv_i32 cpu_crf[8]; |
69 | bd568f18 | aurel32 | static TCGv cpu_nip;
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70 | 6527f6ea | aurel32 | static TCGv cpu_msr;
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71 | cfdcd37a | aurel32 | static TCGv cpu_ctr;
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72 | cfdcd37a | aurel32 | static TCGv cpu_lr;
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73 | 3d7b417e | aurel32 | static TCGv cpu_xer;
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74 | cf360a32 | aurel32 | static TCGv cpu_reserve;
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75 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpscr;
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76 | a7859e89 | aurel32 | static TCGv_i32 cpu_access_type;
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77 | f78fb44e | aurel32 | |
78 | 2e70f6ef | pbrook | #include "gen-icount.h" |
79 | 2e70f6ef | pbrook | |
80 | 2e70f6ef | pbrook | void ppc_translate_init(void) |
81 | 2e70f6ef | pbrook | { |
82 | f78fb44e | aurel32 | int i;
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83 | f78fb44e | aurel32 | char* p;
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84 | 2dc766da | blueswir1 | size_t cpu_reg_names_size; |
85 | b2437bf2 | pbrook | static int done_init = 0; |
86 | f78fb44e | aurel32 | |
87 | 2e70f6ef | pbrook | if (done_init)
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88 | 2e70f6ef | pbrook | return;
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89 | f78fb44e | aurel32 | |
90 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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91 | a7812ae4 | pbrook | |
92 | f78fb44e | aurel32 | p = cpu_reg_names; |
93 | 2dc766da | blueswir1 | cpu_reg_names_size = sizeof(cpu_reg_names);
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94 | 47e4661c | aurel32 | |
95 | 47e4661c | aurel32 | for (i = 0; i < 8; i++) { |
96 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "crf%d", i);
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97 | a7812ae4 | pbrook | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
98 | a7812ae4 | pbrook | offsetof(CPUState, crf[i]), p); |
99 | 47e4661c | aurel32 | p += 5;
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100 | 2dc766da | blueswir1 | cpu_reg_names_size -= 5;
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101 | 47e4661c | aurel32 | } |
102 | 47e4661c | aurel32 | |
103 | f78fb44e | aurel32 | for (i = 0; i < 32; i++) { |
104 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%d", i);
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105 | a7812ae4 | pbrook | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
106 | f78fb44e | aurel32 | offsetof(CPUState, gpr[i]), p); |
107 | f78fb44e | aurel32 | p += (i < 10) ? 3 : 4; |
108 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
109 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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110 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%dH", i);
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111 | a7812ae4 | pbrook | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
112 | a7812ae4 | pbrook | offsetof(CPUState, gprh[i]), p); |
113 | f78fb44e | aurel32 | p += (i < 10) ? 4 : 5; |
114 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
115 | f78fb44e | aurel32 | #endif
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116 | 1d542695 | aurel32 | |
117 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "fp%d", i);
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118 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
119 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), p); |
120 | ec1ac72d | aurel32 | p += (i < 10) ? 4 : 5; |
121 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
122 | a5e26afa | aurel32 | |
123 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dH", i);
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124 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
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125 | fe1e5c53 | aurel32 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
126 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[0]), p);
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127 | fe1e5c53 | aurel32 | #else
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128 | a7812ae4 | pbrook | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
129 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[1]), p);
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130 | fe1e5c53 | aurel32 | #endif
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131 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
132 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
133 | ec1ac72d | aurel32 | |
134 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dL", i);
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135 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
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136 | fe1e5c53 | aurel32 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
137 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[1]), p);
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138 | fe1e5c53 | aurel32 | #else
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139 | a7812ae4 | pbrook | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
140 | fe1e5c53 | aurel32 | offsetof(CPUState, avr[i].u64[0]), p);
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141 | fe1e5c53 | aurel32 | #endif
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142 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
143 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
144 | f78fb44e | aurel32 | } |
145 | f10dc08e | aurel32 | |
146 | a7812ae4 | pbrook | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
147 | bd568f18 | aurel32 | offsetof(CPUState, nip), "nip");
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148 | bd568f18 | aurel32 | |
149 | 6527f6ea | aurel32 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
150 | 6527f6ea | aurel32 | offsetof(CPUState, msr), "msr");
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151 | 6527f6ea | aurel32 | |
152 | a7812ae4 | pbrook | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
153 | cfdcd37a | aurel32 | offsetof(CPUState, ctr), "ctr");
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154 | cfdcd37a | aurel32 | |
155 | a7812ae4 | pbrook | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
156 | cfdcd37a | aurel32 | offsetof(CPUState, lr), "lr");
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157 | cfdcd37a | aurel32 | |
158 | a7812ae4 | pbrook | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
159 | 3d7b417e | aurel32 | offsetof(CPUState, xer), "xer");
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160 | 3d7b417e | aurel32 | |
161 | cf360a32 | aurel32 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
162 | 18b21a2f | Nathan Froyd | offsetof(CPUState, reserve_addr), |
163 | 18b21a2f | Nathan Froyd | "reserve_addr");
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164 | cf360a32 | aurel32 | |
165 | a7812ae4 | pbrook | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
166 | a7812ae4 | pbrook | offsetof(CPUState, fpscr), "fpscr");
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167 | e1571908 | aurel32 | |
168 | a7859e89 | aurel32 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
169 | a7859e89 | aurel32 | offsetof(CPUState, access_type), "access_type");
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170 | a7859e89 | aurel32 | |
171 | f10dc08e | aurel32 | /* register helpers */
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172 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
173 | f10dc08e | aurel32 | #include "helper.h" |
174 | f10dc08e | aurel32 | |
175 | 2e70f6ef | pbrook | done_init = 1;
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176 | 2e70f6ef | pbrook | } |
177 | 2e70f6ef | pbrook | |
178 | 79aceca5 | bellard | /* internal defines */
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179 | 79aceca5 | bellard | typedef struct DisasContext { |
180 | 79aceca5 | bellard | struct TranslationBlock *tb;
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181 | 0fa85d43 | bellard | target_ulong nip; |
182 | 79aceca5 | bellard | uint32_t opcode; |
183 | 9a64fbe4 | bellard | uint32_t exception; |
184 | 3cc62370 | bellard | /* Routine used to access memory */
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185 | 3cc62370 | bellard | int mem_idx;
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186 | 76db3ba4 | aurel32 | int access_type;
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187 | 3cc62370 | bellard | /* Translation flags */
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188 | 76db3ba4 | aurel32 | int le_mode;
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189 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
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190 | d9bce9d9 | j_mayer | int sf_mode;
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191 | d9bce9d9 | j_mayer | #endif
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192 | 3cc62370 | bellard | int fpu_enabled;
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193 | a9d9eb8f | j_mayer | int altivec_enabled;
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194 | 0487d6a8 | j_mayer | int spe_enabled;
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195 | c227f099 | Anthony Liguori | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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196 | ea4e754f | bellard | int singlestep_enabled;
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197 | 79aceca5 | bellard | } DisasContext; |
198 | 79aceca5 | bellard | |
199 | c227f099 | Anthony Liguori | struct opc_handler_t {
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200 | 79aceca5 | bellard | /* invalid bits */
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201 | 79aceca5 | bellard | uint32_t inval; |
202 | 9a64fbe4 | bellard | /* instruction type */
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203 | 0487d6a8 | j_mayer | uint64_t type; |
204 | a5858d7a | Alexander Graf | /* extended instruction type */
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205 | a5858d7a | Alexander Graf | uint64_t type2; |
206 | 79aceca5 | bellard | /* handler */
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207 | 79aceca5 | bellard | void (*handler)(DisasContext *ctx);
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208 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
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209 | b55266b5 | blueswir1 | const char *oname; |
210 | a750fc0b | j_mayer | #endif
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211 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS)
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212 | 76a66253 | j_mayer | uint64_t count; |
213 | 76a66253 | j_mayer | #endif
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214 | 3fc6c082 | bellard | }; |
215 | 79aceca5 | bellard | |
216 | 636aa200 | Blue Swirl | static inline void gen_reset_fpstatus(void) |
217 | 7c58044c | j_mayer | { |
218 | a44d2ce1 | aurel32 | gen_helper_reset_fpstatus(); |
219 | 7c58044c | j_mayer | } |
220 | 7c58044c | j_mayer | |
221 | 636aa200 | Blue Swirl | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
222 | 7c58044c | j_mayer | { |
223 | 0f2f39c2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
224 | af12906f | aurel32 | |
225 | 7c58044c | j_mayer | if (set_fprf != 0) { |
226 | 7c58044c | j_mayer | /* This case might be optimized later */
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227 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 1);
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228 | af12906f | aurel32 | gen_helper_compute_fprf(t0, arg, t0); |
229 | a7812ae4 | pbrook | if (unlikely(set_rc)) {
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230 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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231 | a7812ae4 | pbrook | } |
232 | af12906f | aurel32 | gen_helper_float_check_status(); |
233 | 7c58044c | j_mayer | } else if (unlikely(set_rc)) { |
234 | 7c58044c | j_mayer | /* We always need to compute fpcc */
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235 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 0);
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236 | af12906f | aurel32 | gen_helper_compute_fprf(t0, arg, t0); |
237 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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238 | 7c58044c | j_mayer | } |
239 | af12906f | aurel32 | |
240 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
241 | 7c58044c | j_mayer | } |
242 | 7c58044c | j_mayer | |
243 | 636aa200 | Blue Swirl | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
244 | a7859e89 | aurel32 | { |
245 | 76db3ba4 | aurel32 | if (ctx->access_type != access_type) {
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246 | 76db3ba4 | aurel32 | tcg_gen_movi_i32(cpu_access_type, access_type); |
247 | 76db3ba4 | aurel32 | ctx->access_type = access_type; |
248 | 76db3ba4 | aurel32 | } |
249 | a7859e89 | aurel32 | } |
250 | a7859e89 | aurel32 | |
251 | 636aa200 | Blue Swirl | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
252 | d9bce9d9 | j_mayer | { |
253 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
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254 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
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255 | bd568f18 | aurel32 | tcg_gen_movi_tl(cpu_nip, nip); |
256 | d9bce9d9 | j_mayer | else
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257 | d9bce9d9 | j_mayer | #endif
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258 | bd568f18 | aurel32 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
259 | d9bce9d9 | j_mayer | } |
260 | d9bce9d9 | j_mayer | |
261 | 636aa200 | Blue Swirl | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
262 | e06fcd75 | aurel32 | { |
263 | e06fcd75 | aurel32 | TCGv_i32 t0, t1; |
264 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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265 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
266 | e06fcd75 | aurel32 | } |
267 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
268 | e06fcd75 | aurel32 | t1 = tcg_const_i32(error); |
269 | e06fcd75 | aurel32 | gen_helper_raise_exception_err(t0, t1); |
270 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
271 | e06fcd75 | aurel32 | tcg_temp_free_i32(t1); |
272 | e06fcd75 | aurel32 | ctx->exception = (excp); |
273 | e06fcd75 | aurel32 | } |
274 | e1833e1f | j_mayer | |
275 | 636aa200 | Blue Swirl | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
276 | e06fcd75 | aurel32 | { |
277 | e06fcd75 | aurel32 | TCGv_i32 t0; |
278 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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279 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
280 | e06fcd75 | aurel32 | } |
281 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
282 | e06fcd75 | aurel32 | gen_helper_raise_exception(t0); |
283 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
284 | e06fcd75 | aurel32 | ctx->exception = (excp); |
285 | e06fcd75 | aurel32 | } |
286 | e1833e1f | j_mayer | |
287 | 636aa200 | Blue Swirl | static inline void gen_debug_exception(DisasContext *ctx) |
288 | e06fcd75 | aurel32 | { |
289 | e06fcd75 | aurel32 | TCGv_i32 t0; |
290 | 5518f3a6 | blueswir1 | |
291 | 5518f3a6 | blueswir1 | if (ctx->exception != POWERPC_EXCP_BRANCH)
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292 | 5518f3a6 | blueswir1 | gen_update_nip(ctx, ctx->nip); |
293 | e06fcd75 | aurel32 | t0 = tcg_const_i32(EXCP_DEBUG); |
294 | e06fcd75 | aurel32 | gen_helper_raise_exception(t0); |
295 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
296 | e06fcd75 | aurel32 | } |
297 | 9a64fbe4 | bellard | |
298 | 636aa200 | Blue Swirl | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
299 | e06fcd75 | aurel32 | { |
300 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); |
301 | e06fcd75 | aurel32 | } |
302 | a9d9eb8f | j_mayer | |
303 | f24e5695 | bellard | /* Stop translation */
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304 | 636aa200 | Blue Swirl | static inline void gen_stop_exception(DisasContext *ctx) |
305 | 3fc6c082 | bellard | { |
306 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
307 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_STOP; |
308 | 3fc6c082 | bellard | } |
309 | 3fc6c082 | bellard | |
310 | f24e5695 | bellard | /* No need to update nip here, as execution flow will change */
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311 | 636aa200 | Blue Swirl | static inline void gen_sync_exception(DisasContext *ctx) |
312 | 2be0071f | bellard | { |
313 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_SYNC; |
314 | 2be0071f | bellard | } |
315 | 2be0071f | bellard | |
316 | 79aceca5 | bellard | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
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317 | a5858d7a | Alexander Graf | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
318 | a5858d7a | Alexander Graf | |
319 | a5858d7a | Alexander Graf | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
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320 | a5858d7a | Alexander Graf | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) |
321 | 79aceca5 | bellard | |
322 | c7697e1f | j_mayer | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
|
323 | a5858d7a | Alexander Graf | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
324 | a5858d7a | Alexander Graf | |
325 | a5858d7a | Alexander Graf | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
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326 | a5858d7a | Alexander Graf | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) |
327 | c7697e1f | j_mayer | |
328 | c227f099 | Anthony Liguori | typedef struct opcode_t { |
329 | 79aceca5 | bellard | unsigned char opc1, opc2, opc3; |
330 | 1235fc06 | ths | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
331 | 18fba28c | bellard | unsigned char pad[5]; |
332 | 18fba28c | bellard | #else
|
333 | 18fba28c | bellard | unsigned char pad[1]; |
334 | 18fba28c | bellard | #endif
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335 | c227f099 | Anthony Liguori | opc_handler_t handler; |
336 | b55266b5 | blueswir1 | const char *oname; |
337 | c227f099 | Anthony Liguori | } opcode_t; |
338 | 79aceca5 | bellard | |
339 | a750fc0b | j_mayer | /*****************************************************************************/
|
340 | 79aceca5 | bellard | /*** Instruction decoding ***/
|
341 | 79aceca5 | bellard | #define EXTRACT_HELPER(name, shift, nb) \
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342 | 636aa200 | Blue Swirl | static inline uint32_t name(uint32_t opcode) \ |
343 | 79aceca5 | bellard | { \ |
344 | 79aceca5 | bellard | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
345 | 79aceca5 | bellard | } |
346 | 79aceca5 | bellard | |
347 | 79aceca5 | bellard | #define EXTRACT_SHELPER(name, shift, nb) \
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348 | 636aa200 | Blue Swirl | static inline int32_t name(uint32_t opcode) \ |
349 | 79aceca5 | bellard | { \ |
350 | 18fba28c | bellard | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
351 | 79aceca5 | bellard | } |
352 | 79aceca5 | bellard | |
353 | 79aceca5 | bellard | /* Opcode part 1 */
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354 | 79aceca5 | bellard | EXTRACT_HELPER(opc1, 26, 6); |
355 | 79aceca5 | bellard | /* Opcode part 2 */
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356 | 79aceca5 | bellard | EXTRACT_HELPER(opc2, 1, 5); |
357 | 79aceca5 | bellard | /* Opcode part 3 */
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358 | 79aceca5 | bellard | EXTRACT_HELPER(opc3, 6, 5); |
359 | 79aceca5 | bellard | /* Update Cr0 flags */
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360 | 79aceca5 | bellard | EXTRACT_HELPER(Rc, 0, 1); |
361 | 79aceca5 | bellard | /* Destination */
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362 | 79aceca5 | bellard | EXTRACT_HELPER(rD, 21, 5); |
363 | 79aceca5 | bellard | /* Source */
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364 | 79aceca5 | bellard | EXTRACT_HELPER(rS, 21, 5); |
365 | 79aceca5 | bellard | /* First operand */
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366 | 79aceca5 | bellard | EXTRACT_HELPER(rA, 16, 5); |
367 | 79aceca5 | bellard | /* Second operand */
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368 | 79aceca5 | bellard | EXTRACT_HELPER(rB, 11, 5); |
369 | 79aceca5 | bellard | /* Third operand */
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370 | 79aceca5 | bellard | EXTRACT_HELPER(rC, 6, 5); |
371 | 79aceca5 | bellard | /*** Get CRn ***/
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372 | 79aceca5 | bellard | EXTRACT_HELPER(crfD, 23, 3); |
373 | 79aceca5 | bellard | EXTRACT_HELPER(crfS, 18, 3); |
374 | 79aceca5 | bellard | EXTRACT_HELPER(crbD, 21, 5); |
375 | 79aceca5 | bellard | EXTRACT_HELPER(crbA, 16, 5); |
376 | 79aceca5 | bellard | EXTRACT_HELPER(crbB, 11, 5); |
377 | 79aceca5 | bellard | /* SPR / TBL */
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378 | 3fc6c082 | bellard | EXTRACT_HELPER(_SPR, 11, 10); |
379 | 636aa200 | Blue Swirl | static inline uint32_t SPR(uint32_t opcode) |
380 | 3fc6c082 | bellard | { |
381 | 3fc6c082 | bellard | uint32_t sprn = _SPR(opcode); |
382 | 3fc6c082 | bellard | |
383 | 3fc6c082 | bellard | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
384 | 3fc6c082 | bellard | } |
385 | 79aceca5 | bellard | /*** Get constants ***/
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386 | 79aceca5 | bellard | EXTRACT_HELPER(IMM, 12, 8); |
387 | 79aceca5 | bellard | /* 16 bits signed immediate value */
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388 | 79aceca5 | bellard | EXTRACT_SHELPER(SIMM, 0, 16); |
389 | 79aceca5 | bellard | /* 16 bits unsigned immediate value */
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390 | 79aceca5 | bellard | EXTRACT_HELPER(UIMM, 0, 16); |
391 | 21d21583 | aurel32 | /* 5 bits signed immediate value */
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392 | 21d21583 | aurel32 | EXTRACT_HELPER(SIMM5, 16, 5); |
393 | 27a4edb3 | aurel32 | /* 5 bits signed immediate value */
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394 | 27a4edb3 | aurel32 | EXTRACT_HELPER(UIMM5, 16, 5); |
395 | 79aceca5 | bellard | /* Bit count */
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396 | 79aceca5 | bellard | EXTRACT_HELPER(NB, 11, 5); |
397 | 79aceca5 | bellard | /* Shift count */
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398 | 79aceca5 | bellard | EXTRACT_HELPER(SH, 11, 5); |
399 | cd633b10 | aurel32 | /* Vector shift count */
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400 | cd633b10 | aurel32 | EXTRACT_HELPER(VSH, 6, 4); |
401 | 79aceca5 | bellard | /* Mask start */
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402 | 79aceca5 | bellard | EXTRACT_HELPER(MB, 6, 5); |
403 | 79aceca5 | bellard | /* Mask end */
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404 | 79aceca5 | bellard | EXTRACT_HELPER(ME, 1, 5); |
405 | fb0eaffc | bellard | /* Trap operand */
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406 | fb0eaffc | bellard | EXTRACT_HELPER(TO, 21, 5); |
407 | 79aceca5 | bellard | |
408 | 79aceca5 | bellard | EXTRACT_HELPER(CRM, 12, 8); |
409 | 79aceca5 | bellard | EXTRACT_HELPER(FM, 17, 8); |
410 | 79aceca5 | bellard | EXTRACT_HELPER(SR, 16, 4); |
411 | e4bb997e | aurel32 | EXTRACT_HELPER(FPIMM, 12, 4); |
412 | fb0eaffc | bellard | |
413 | 79aceca5 | bellard | /*** Jump target decoding ***/
|
414 | 79aceca5 | bellard | /* Displacement */
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415 | 79aceca5 | bellard | EXTRACT_SHELPER(d, 0, 16); |
416 | 79aceca5 | bellard | /* Immediate address */
|
417 | 636aa200 | Blue Swirl | static inline target_ulong LI(uint32_t opcode) |
418 | 79aceca5 | bellard | { |
419 | 79aceca5 | bellard | return (opcode >> 0) & 0x03FFFFFC; |
420 | 79aceca5 | bellard | } |
421 | 79aceca5 | bellard | |
422 | 636aa200 | Blue Swirl | static inline uint32_t BD(uint32_t opcode) |
423 | 79aceca5 | bellard | { |
424 | 79aceca5 | bellard | return (opcode >> 0) & 0xFFFC; |
425 | 79aceca5 | bellard | } |
426 | 79aceca5 | bellard | |
427 | 79aceca5 | bellard | EXTRACT_HELPER(BO, 21, 5); |
428 | 79aceca5 | bellard | EXTRACT_HELPER(BI, 16, 5); |
429 | 79aceca5 | bellard | /* Absolute/relative address */
|
430 | 79aceca5 | bellard | EXTRACT_HELPER(AA, 1, 1); |
431 | 79aceca5 | bellard | /* Link */
|
432 | 79aceca5 | bellard | EXTRACT_HELPER(LK, 0, 1); |
433 | 79aceca5 | bellard | |
434 | 79aceca5 | bellard | /* Create a mask between <start> and <end> bits */
|
435 | 636aa200 | Blue Swirl | static inline target_ulong MASK(uint32_t start, uint32_t end) |
436 | 79aceca5 | bellard | { |
437 | 76a66253 | j_mayer | target_ulong ret; |
438 | 79aceca5 | bellard | |
439 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
440 | 76a66253 | j_mayer | if (likely(start == 0)) { |
441 | 6f2d8978 | j_mayer | ret = UINT64_MAX << (63 - end);
|
442 | 76a66253 | j_mayer | } else if (likely(end == 63)) { |
443 | 6f2d8978 | j_mayer | ret = UINT64_MAX >> start; |
444 | 76a66253 | j_mayer | } |
445 | 76a66253 | j_mayer | #else
|
446 | 76a66253 | j_mayer | if (likely(start == 0)) { |
447 | 6f2d8978 | j_mayer | ret = UINT32_MAX << (31 - end);
|
448 | 76a66253 | j_mayer | } else if (likely(end == 31)) { |
449 | 6f2d8978 | j_mayer | ret = UINT32_MAX >> start; |
450 | 76a66253 | j_mayer | } |
451 | 76a66253 | j_mayer | #endif
|
452 | 76a66253 | j_mayer | else {
|
453 | 76a66253 | j_mayer | ret = (((target_ulong)(-1ULL)) >> (start)) ^
|
454 | 76a66253 | j_mayer | (((target_ulong)(-1ULL) >> (end)) >> 1); |
455 | 76a66253 | j_mayer | if (unlikely(start > end))
|
456 | 76a66253 | j_mayer | return ~ret;
|
457 | 76a66253 | j_mayer | } |
458 | 79aceca5 | bellard | |
459 | 79aceca5 | bellard | return ret;
|
460 | 79aceca5 | bellard | } |
461 | 79aceca5 | bellard | |
462 | a750fc0b | j_mayer | /*****************************************************************************/
|
463 | a750fc0b | j_mayer | /* PowerPC instructions table */
|
464 | 933dc6eb | bellard | |
465 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
466 | a5858d7a | Alexander Graf | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
|
467 | 5c55ff99 | Blue Swirl | { \ |
468 | 79aceca5 | bellard | .opc1 = op1, \ |
469 | 79aceca5 | bellard | .opc2 = op2, \ |
470 | 79aceca5 | bellard | .opc3 = op3, \ |
471 | 18fba28c | bellard | .pad = { 0, }, \
|
472 | 79aceca5 | bellard | .handler = { \ |
473 | 79aceca5 | bellard | .inval = invl, \ |
474 | 9a64fbe4 | bellard | .type = _typ, \ |
475 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
476 | 79aceca5 | bellard | .handler = &gen_##name, \ |
477 | 76a66253 | j_mayer | .oname = stringify(name), \ |
478 | 79aceca5 | bellard | }, \ |
479 | 3fc6c082 | bellard | .oname = stringify(name), \ |
480 | 79aceca5 | bellard | } |
481 | a5858d7a | Alexander Graf | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
|
482 | 5c55ff99 | Blue Swirl | { \ |
483 | c7697e1f | j_mayer | .opc1 = op1, \ |
484 | c7697e1f | j_mayer | .opc2 = op2, \ |
485 | c7697e1f | j_mayer | .opc3 = op3, \ |
486 | c7697e1f | j_mayer | .pad = { 0, }, \
|
487 | c7697e1f | j_mayer | .handler = { \ |
488 | c7697e1f | j_mayer | .inval = invl, \ |
489 | c7697e1f | j_mayer | .type = _typ, \ |
490 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
491 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
492 | c7697e1f | j_mayer | .oname = onam, \ |
493 | c7697e1f | j_mayer | }, \ |
494 | c7697e1f | j_mayer | .oname = onam, \ |
495 | c7697e1f | j_mayer | } |
496 | 76a66253 | j_mayer | #else
|
497 | a5858d7a | Alexander Graf | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
|
498 | 5c55ff99 | Blue Swirl | { \ |
499 | c7697e1f | j_mayer | .opc1 = op1, \ |
500 | c7697e1f | j_mayer | .opc2 = op2, \ |
501 | c7697e1f | j_mayer | .opc3 = op3, \ |
502 | c7697e1f | j_mayer | .pad = { 0, }, \
|
503 | c7697e1f | j_mayer | .handler = { \ |
504 | c7697e1f | j_mayer | .inval = invl, \ |
505 | c7697e1f | j_mayer | .type = _typ, \ |
506 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
507 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
508 | 5c55ff99 | Blue Swirl | }, \ |
509 | 5c55ff99 | Blue Swirl | .oname = stringify(name), \ |
510 | 5c55ff99 | Blue Swirl | } |
511 | a5858d7a | Alexander Graf | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
|
512 | 5c55ff99 | Blue Swirl | { \ |
513 | 5c55ff99 | Blue Swirl | .opc1 = op1, \ |
514 | 5c55ff99 | Blue Swirl | .opc2 = op2, \ |
515 | 5c55ff99 | Blue Swirl | .opc3 = op3, \ |
516 | 5c55ff99 | Blue Swirl | .pad = { 0, }, \
|
517 | 5c55ff99 | Blue Swirl | .handler = { \ |
518 | 5c55ff99 | Blue Swirl | .inval = invl, \ |
519 | 5c55ff99 | Blue Swirl | .type = _typ, \ |
520 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
521 | 5c55ff99 | Blue Swirl | .handler = &gen_##name, \ |
522 | 5c55ff99 | Blue Swirl | }, \ |
523 | 5c55ff99 | Blue Swirl | .oname = onam, \ |
524 | 5c55ff99 | Blue Swirl | } |
525 | 5c55ff99 | Blue Swirl | #endif
|
526 | 2e610050 | Blue Swirl | |
527 | 5c55ff99 | Blue Swirl | /* SPR load/store helpers */
|
528 | 636aa200 | Blue Swirl | static inline void gen_load_spr(TCGv t, int reg) |
529 | 5c55ff99 | Blue Swirl | { |
530 | 5c55ff99 | Blue Swirl | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
531 | 5c55ff99 | Blue Swirl | } |
532 | 2e610050 | Blue Swirl | |
533 | 636aa200 | Blue Swirl | static inline void gen_store_spr(int reg, TCGv t) |
534 | 5c55ff99 | Blue Swirl | { |
535 | 5c55ff99 | Blue Swirl | tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
536 | 5c55ff99 | Blue Swirl | } |
537 | 2e610050 | Blue Swirl | |
538 | 54623277 | Blue Swirl | /* Invalid instruction */
|
539 | 99e300ef | Blue Swirl | static void gen_invalid(DisasContext *ctx) |
540 | 9a64fbe4 | bellard | { |
541 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
542 | 9a64fbe4 | bellard | } |
543 | 9a64fbe4 | bellard | |
544 | c227f099 | Anthony Liguori | static opc_handler_t invalid_handler = {
|
545 | 79aceca5 | bellard | .inval = 0xFFFFFFFF,
|
546 | 9a64fbe4 | bellard | .type = PPC_NONE, |
547 | a5858d7a | Alexander Graf | .type2 = PPC_NONE, |
548 | 79aceca5 | bellard | .handler = gen_invalid, |
549 | 79aceca5 | bellard | }; |
550 | 79aceca5 | bellard | |
551 | e1571908 | aurel32 | /*** Integer comparison ***/
|
552 | e1571908 | aurel32 | |
553 | 636aa200 | Blue Swirl | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
554 | e1571908 | aurel32 | { |
555 | e1571908 | aurel32 | int l1, l2, l3;
|
556 | e1571908 | aurel32 | |
557 | 269f3e95 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
558 | 269f3e95 | aurel32 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); |
559 | e1571908 | aurel32 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
|
560 | e1571908 | aurel32 | |
561 | e1571908 | aurel32 | l1 = gen_new_label(); |
562 | e1571908 | aurel32 | l2 = gen_new_label(); |
563 | e1571908 | aurel32 | l3 = gen_new_label(); |
564 | e1571908 | aurel32 | if (s) {
|
565 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
566 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); |
567 | e1571908 | aurel32 | } else {
|
568 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
569 | ea363694 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); |
570 | e1571908 | aurel32 | } |
571 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
|
572 | e1571908 | aurel32 | tcg_gen_br(l3); |
573 | e1571908 | aurel32 | gen_set_label(l1); |
574 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
|
575 | e1571908 | aurel32 | tcg_gen_br(l3); |
576 | e1571908 | aurel32 | gen_set_label(l2); |
577 | e1571908 | aurel32 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
|
578 | e1571908 | aurel32 | gen_set_label(l3); |
579 | e1571908 | aurel32 | } |
580 | e1571908 | aurel32 | |
581 | 636aa200 | Blue Swirl | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
582 | e1571908 | aurel32 | { |
583 | ea363694 | aurel32 | TCGv t0 = tcg_const_local_tl(arg1); |
584 | ea363694 | aurel32 | gen_op_cmp(arg0, t0, s, crf); |
585 | ea363694 | aurel32 | tcg_temp_free(t0); |
586 | e1571908 | aurel32 | } |
587 | e1571908 | aurel32 | |
588 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
589 | 636aa200 | Blue Swirl | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
590 | e1571908 | aurel32 | { |
591 | ea363694 | aurel32 | TCGv t0, t1; |
592 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
593 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
594 | e1571908 | aurel32 | if (s) {
|
595 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t0, arg0); |
596 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t1, arg1); |
597 | e1571908 | aurel32 | } else {
|
598 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t0, arg0); |
599 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t1, arg1); |
600 | e1571908 | aurel32 | } |
601 | ea363694 | aurel32 | gen_op_cmp(t0, t1, s, crf); |
602 | ea363694 | aurel32 | tcg_temp_free(t1); |
603 | ea363694 | aurel32 | tcg_temp_free(t0); |
604 | e1571908 | aurel32 | } |
605 | e1571908 | aurel32 | |
606 | 636aa200 | Blue Swirl | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
607 | e1571908 | aurel32 | { |
608 | ea363694 | aurel32 | TCGv t0 = tcg_const_local_tl(arg1); |
609 | ea363694 | aurel32 | gen_op_cmp32(arg0, t0, s, crf); |
610 | ea363694 | aurel32 | tcg_temp_free(t0); |
611 | e1571908 | aurel32 | } |
612 | e1571908 | aurel32 | #endif
|
613 | e1571908 | aurel32 | |
614 | 636aa200 | Blue Swirl | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
615 | e1571908 | aurel32 | { |
616 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
617 | e1571908 | aurel32 | if (!(ctx->sf_mode))
|
618 | e1571908 | aurel32 | gen_op_cmpi32(reg, 0, 1, 0); |
619 | e1571908 | aurel32 | else
|
620 | e1571908 | aurel32 | #endif
|
621 | e1571908 | aurel32 | gen_op_cmpi(reg, 0, 1, 0); |
622 | e1571908 | aurel32 | } |
623 | e1571908 | aurel32 | |
624 | e1571908 | aurel32 | /* cmp */
|
625 | 99e300ef | Blue Swirl | static void gen_cmp(DisasContext *ctx) |
626 | e1571908 | aurel32 | { |
627 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
628 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
629 | e1571908 | aurel32 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
630 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
631 | e1571908 | aurel32 | else
|
632 | e1571908 | aurel32 | #endif
|
633 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
634 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
635 | e1571908 | aurel32 | } |
636 | e1571908 | aurel32 | |
637 | e1571908 | aurel32 | /* cmpi */
|
638 | 99e300ef | Blue Swirl | static void gen_cmpi(DisasContext *ctx) |
639 | e1571908 | aurel32 | { |
640 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
641 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
642 | e1571908 | aurel32 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
643 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
644 | e1571908 | aurel32 | else
|
645 | e1571908 | aurel32 | #endif
|
646 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
647 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
648 | e1571908 | aurel32 | } |
649 | e1571908 | aurel32 | |
650 | e1571908 | aurel32 | /* cmpl */
|
651 | 99e300ef | Blue Swirl | static void gen_cmpl(DisasContext *ctx) |
652 | e1571908 | aurel32 | { |
653 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
654 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
655 | e1571908 | aurel32 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
656 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
657 | e1571908 | aurel32 | else
|
658 | e1571908 | aurel32 | #endif
|
659 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
660 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
661 | e1571908 | aurel32 | } |
662 | e1571908 | aurel32 | |
663 | e1571908 | aurel32 | /* cmpli */
|
664 | 99e300ef | Blue Swirl | static void gen_cmpli(DisasContext *ctx) |
665 | e1571908 | aurel32 | { |
666 | e1571908 | aurel32 | #if defined(TARGET_PPC64)
|
667 | e1571908 | aurel32 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
668 | e1571908 | aurel32 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
669 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
670 | e1571908 | aurel32 | else
|
671 | e1571908 | aurel32 | #endif
|
672 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
673 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
674 | e1571908 | aurel32 | } |
675 | e1571908 | aurel32 | |
676 | e1571908 | aurel32 | /* isel (PowerPC 2.03 specification) */
|
677 | 99e300ef | Blue Swirl | static void gen_isel(DisasContext *ctx) |
678 | e1571908 | aurel32 | { |
679 | e1571908 | aurel32 | int l1, l2;
|
680 | e1571908 | aurel32 | uint32_t bi = rC(ctx->opcode); |
681 | e1571908 | aurel32 | uint32_t mask; |
682 | a7812ae4 | pbrook | TCGv_i32 t0; |
683 | e1571908 | aurel32 | |
684 | e1571908 | aurel32 | l1 = gen_new_label(); |
685 | e1571908 | aurel32 | l2 = gen_new_label(); |
686 | e1571908 | aurel32 | |
687 | e1571908 | aurel32 | mask = 1 << (3 - (bi & 0x03)); |
688 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
689 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
|
690 | fea0c503 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
691 | e1571908 | aurel32 | if (rA(ctx->opcode) == 0) |
692 | e1571908 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
693 | e1571908 | aurel32 | else
|
694 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
695 | e1571908 | aurel32 | tcg_gen_br(l2); |
696 | e1571908 | aurel32 | gen_set_label(l1); |
697 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
698 | e1571908 | aurel32 | gen_set_label(l2); |
699 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
700 | e1571908 | aurel32 | } |
701 | e1571908 | aurel32 | |
702 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
703 | 79aceca5 | bellard | |
704 | 636aa200 | Blue Swirl | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
705 | 636aa200 | Blue Swirl | TCGv arg1, TCGv arg2, int sub)
|
706 | 74637406 | aurel32 | { |
707 | 74637406 | aurel32 | int l1;
|
708 | 74637406 | aurel32 | TCGv t0; |
709 | 79aceca5 | bellard | |
710 | 74637406 | aurel32 | l1 = gen_new_label(); |
711 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
712 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
713 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
714 | 74637406 | aurel32 | tcg_gen_xor_tl(t0, arg0, arg1); |
715 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
716 | 74637406 | aurel32 | if (!ctx->sf_mode)
|
717 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, t0); |
718 | 74637406 | aurel32 | #endif
|
719 | 74637406 | aurel32 | if (sub)
|
720 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
|
721 | 74637406 | aurel32 | else
|
722 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
723 | 74637406 | aurel32 | tcg_gen_xor_tl(t0, arg1, arg2); |
724 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
725 | 74637406 | aurel32 | if (!ctx->sf_mode)
|
726 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, t0); |
727 | 74637406 | aurel32 | #endif
|
728 | 74637406 | aurel32 | if (sub)
|
729 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
730 | 74637406 | aurel32 | else
|
731 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
|
732 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
733 | 74637406 | aurel32 | gen_set_label(l1); |
734 | 74637406 | aurel32 | tcg_temp_free(t0); |
735 | 79aceca5 | bellard | } |
736 | 79aceca5 | bellard | |
737 | 636aa200 | Blue Swirl | static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, |
738 | 636aa200 | Blue Swirl | TCGv arg2, int sub)
|
739 | 74637406 | aurel32 | { |
740 | 74637406 | aurel32 | int l1 = gen_new_label();
|
741 | d9bce9d9 | j_mayer | |
742 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
743 | 74637406 | aurel32 | if (!(ctx->sf_mode)) {
|
744 | 74637406 | aurel32 | TCGv t0, t1; |
745 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
746 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
747 | d9bce9d9 | j_mayer | |
748 | 74637406 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
749 | 74637406 | aurel32 | tcg_gen_ext32u_tl(t1, arg2); |
750 | 74637406 | aurel32 | if (sub) {
|
751 | 74637406 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); |
752 | bdc4e053 | aurel32 | } else {
|
753 | 74637406 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
754 | 74637406 | aurel32 | } |
755 | a9730017 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
756 | a9730017 | aurel32 | gen_set_label(l1); |
757 | a9730017 | aurel32 | tcg_temp_free(t0); |
758 | a9730017 | aurel32 | tcg_temp_free(t1); |
759 | 74637406 | aurel32 | } else
|
760 | 74637406 | aurel32 | #endif
|
761 | a9730017 | aurel32 | { |
762 | a9730017 | aurel32 | if (sub) {
|
763 | a9730017 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); |
764 | a9730017 | aurel32 | } else {
|
765 | a9730017 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); |
766 | a9730017 | aurel32 | } |
767 | a9730017 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
768 | a9730017 | aurel32 | gen_set_label(l1); |
769 | 74637406 | aurel32 | } |
770 | d9bce9d9 | j_mayer | } |
771 | d9bce9d9 | j_mayer | |
772 | 74637406 | aurel32 | /* Common add function */
|
773 | 636aa200 | Blue Swirl | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
774 | 636aa200 | Blue Swirl | TCGv arg2, int add_ca, int compute_ca, |
775 | 636aa200 | Blue Swirl | int compute_ov)
|
776 | 74637406 | aurel32 | { |
777 | 74637406 | aurel32 | TCGv t0, t1; |
778 | d9bce9d9 | j_mayer | |
779 | 74637406 | aurel32 | if ((!compute_ca && !compute_ov) ||
|
780 | a7812ae4 | pbrook | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
781 | 74637406 | aurel32 | t0 = ret; |
782 | 74637406 | aurel32 | } else {
|
783 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
784 | 74637406 | aurel32 | } |
785 | 79aceca5 | bellard | |
786 | 74637406 | aurel32 | if (add_ca) {
|
787 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
788 | 74637406 | aurel32 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
|
789 | 74637406 | aurel32 | tcg_gen_shri_tl(t1, t1, XER_CA); |
790 | d2e9fd8f | malc | } else {
|
791 | d2e9fd8f | malc | TCGV_UNUSED(t1); |
792 | 74637406 | aurel32 | } |
793 | 79aceca5 | bellard | |
794 | 74637406 | aurel32 | if (compute_ca && compute_ov) {
|
795 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
796 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
797 | 74637406 | aurel32 | } else if (compute_ca) { |
798 | 74637406 | aurel32 | /* Start with XER CA disabled, the most likely case */
|
799 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
800 | 74637406 | aurel32 | } else if (compute_ov) { |
801 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
802 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
803 | 74637406 | aurel32 | } |
804 | 79aceca5 | bellard | |
805 | 74637406 | aurel32 | tcg_gen_add_tl(t0, arg1, arg2); |
806 | 74637406 | aurel32 | |
807 | 74637406 | aurel32 | if (compute_ca) {
|
808 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg1, 0);
|
809 | 74637406 | aurel32 | } |
810 | 74637406 | aurel32 | if (add_ca) {
|
811 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, t1); |
812 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 0);
|
813 | 74637406 | aurel32 | tcg_temp_free(t1); |
814 | 74637406 | aurel32 | } |
815 | 74637406 | aurel32 | if (compute_ov) {
|
816 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
|
817 | 74637406 | aurel32 | } |
818 | 74637406 | aurel32 | |
819 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
820 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
821 | 74637406 | aurel32 | |
822 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
823 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
824 | 74637406 | aurel32 | tcg_temp_free(t0); |
825 | 74637406 | aurel32 | } |
826 | 39dd32ee | aurel32 | } |
827 | 74637406 | aurel32 | /* Add functions with two operands */
|
828 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
829 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
830 | 74637406 | aurel32 | { \ |
831 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
832 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
833 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
834 | 74637406 | aurel32 | } |
835 | 74637406 | aurel32 | /* Add functions with one operand and one immediate */
|
836 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
837 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
838 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
839 | 74637406 | aurel32 | { \ |
840 | 74637406 | aurel32 | TCGv t0 = tcg_const_local_tl(const_val); \ |
841 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
842 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
843 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
844 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
845 | 74637406 | aurel32 | } |
846 | 74637406 | aurel32 | |
847 | 74637406 | aurel32 | /* add add. addo addo. */
|
848 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
849 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
850 | 74637406 | aurel32 | /* addc addc. addco addco. */
|
851 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
852 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
853 | 74637406 | aurel32 | /* adde adde. addeo addeo. */
|
854 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
855 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
856 | 74637406 | aurel32 | /* addme addme. addmeo addmeo. */
|
857 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
858 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
859 | 74637406 | aurel32 | /* addze addze. addzeo addzeo.*/
|
860 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
861 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
862 | 74637406 | aurel32 | /* addi */
|
863 | 99e300ef | Blue Swirl | static void gen_addi(DisasContext *ctx) |
864 | d9bce9d9 | j_mayer | { |
865 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
866 | 74637406 | aurel32 | |
867 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
868 | 74637406 | aurel32 | /* li case */
|
869 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); |
870 | 74637406 | aurel32 | } else {
|
871 | 74637406 | aurel32 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); |
872 | 74637406 | aurel32 | } |
873 | d9bce9d9 | j_mayer | } |
874 | 74637406 | aurel32 | /* addic addic.*/
|
875 | 636aa200 | Blue Swirl | static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1, |
876 | 636aa200 | Blue Swirl | int compute_Rc0)
|
877 | d9bce9d9 | j_mayer | { |
878 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
879 | 74637406 | aurel32 | |
880 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
881 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
882 | 74637406 | aurel32 | |
883 | 74637406 | aurel32 | if (likely(simm != 0)) { |
884 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
885 | 74637406 | aurel32 | tcg_gen_addi_tl(t0, arg1, simm); |
886 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg1, 0);
|
887 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
888 | 74637406 | aurel32 | tcg_temp_free(t0); |
889 | 74637406 | aurel32 | } else {
|
890 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, arg1); |
891 | 74637406 | aurel32 | } |
892 | 74637406 | aurel32 | if (compute_Rc0) {
|
893 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
894 | 74637406 | aurel32 | } |
895 | d9bce9d9 | j_mayer | } |
896 | 99e300ef | Blue Swirl | |
897 | 99e300ef | Blue Swirl | static void gen_addic(DisasContext *ctx) |
898 | d9bce9d9 | j_mayer | { |
899 | 74637406 | aurel32 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
|
900 | d9bce9d9 | j_mayer | } |
901 | e8eaa2c0 | Blue Swirl | |
902 | e8eaa2c0 | Blue Swirl | static void gen_addic_(DisasContext *ctx) |
903 | d9bce9d9 | j_mayer | { |
904 | 74637406 | aurel32 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
|
905 | d9bce9d9 | j_mayer | } |
906 | 99e300ef | Blue Swirl | |
907 | 54623277 | Blue Swirl | /* addis */
|
908 | 99e300ef | Blue Swirl | static void gen_addis(DisasContext *ctx) |
909 | d9bce9d9 | j_mayer | { |
910 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
911 | 74637406 | aurel32 | |
912 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
913 | 74637406 | aurel32 | /* lis case */
|
914 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
|
915 | 74637406 | aurel32 | } else {
|
916 | 74637406 | aurel32 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
|
917 | 74637406 | aurel32 | } |
918 | d9bce9d9 | j_mayer | } |
919 | 74637406 | aurel32 | |
920 | 636aa200 | Blue Swirl | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
921 | 636aa200 | Blue Swirl | TCGv arg2, int sign, int compute_ov) |
922 | d9bce9d9 | j_mayer | { |
923 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
924 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
925 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
926 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); |
927 | 74637406 | aurel32 | |
928 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t0, arg1); |
929 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t1, arg2); |
930 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
|
931 | 74637406 | aurel32 | if (sign) {
|
932 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
933 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
|
934 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); |
935 | 74637406 | aurel32 | gen_set_label(l3); |
936 | 2ef1b120 | aurel32 | tcg_gen_div_i32(t0, t0, t1); |
937 | 74637406 | aurel32 | } else {
|
938 | 2ef1b120 | aurel32 | tcg_gen_divu_i32(t0, t0, t1); |
939 | 74637406 | aurel32 | } |
940 | 74637406 | aurel32 | if (compute_ov) {
|
941 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
942 | 74637406 | aurel32 | } |
943 | 74637406 | aurel32 | tcg_gen_br(l2); |
944 | 74637406 | aurel32 | gen_set_label(l1); |
945 | 74637406 | aurel32 | if (sign) {
|
946 | 2ef1b120 | aurel32 | tcg_gen_sari_i32(t0, t0, 31);
|
947 | 74637406 | aurel32 | } else {
|
948 | 74637406 | aurel32 | tcg_gen_movi_i32(t0, 0);
|
949 | 74637406 | aurel32 | } |
950 | 74637406 | aurel32 | if (compute_ov) {
|
951 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
952 | 74637406 | aurel32 | } |
953 | 74637406 | aurel32 | gen_set_label(l2); |
954 | 2ef1b120 | aurel32 | tcg_gen_extu_i32_tl(ret, t0); |
955 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
956 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
957 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
958 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
959 | d9bce9d9 | j_mayer | } |
960 | 74637406 | aurel32 | /* Div functions */
|
961 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
962 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
963 | 74637406 | aurel32 | { \ |
964 | 74637406 | aurel32 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ |
965 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
966 | 74637406 | aurel32 | sign, compute_ov); \ |
967 | 74637406 | aurel32 | } |
968 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
969 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); |
970 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); |
971 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
972 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); |
973 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); |
974 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
975 | 636aa200 | Blue Swirl | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
976 | 636aa200 | Blue Swirl | TCGv arg2, int sign, int compute_ov) |
977 | d9bce9d9 | j_mayer | { |
978 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
979 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
980 | 74637406 | aurel32 | |
981 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
|
982 | 74637406 | aurel32 | if (sign) {
|
983 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
984 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
|
985 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); |
986 | 74637406 | aurel32 | gen_set_label(l3); |
987 | 74637406 | aurel32 | tcg_gen_div_i64(ret, arg1, arg2); |
988 | 74637406 | aurel32 | } else {
|
989 | 74637406 | aurel32 | tcg_gen_divu_i64(ret, arg1, arg2); |
990 | 74637406 | aurel32 | } |
991 | 74637406 | aurel32 | if (compute_ov) {
|
992 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
993 | 74637406 | aurel32 | } |
994 | 74637406 | aurel32 | tcg_gen_br(l2); |
995 | 74637406 | aurel32 | gen_set_label(l1); |
996 | 74637406 | aurel32 | if (sign) {
|
997 | 74637406 | aurel32 | tcg_gen_sari_i64(ret, arg1, 63);
|
998 | 74637406 | aurel32 | } else {
|
999 | 74637406 | aurel32 | tcg_gen_movi_i64(ret, 0);
|
1000 | 74637406 | aurel32 | } |
1001 | 74637406 | aurel32 | if (compute_ov) {
|
1002 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
1003 | 74637406 | aurel32 | } |
1004 | 74637406 | aurel32 | gen_set_label(l2); |
1005 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1006 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
1007 | d9bce9d9 | j_mayer | } |
1008 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
1009 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1010 | 74637406 | aurel32 | { \ |
1011 | 2ef1b120 | aurel32 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1012 | 2ef1b120 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1013 | 2ef1b120 | aurel32 | sign, compute_ov); \ |
1014 | 74637406 | aurel32 | } |
1015 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
1016 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1017 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); |
1018 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
1019 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1020 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); |
1021 | d9bce9d9 | j_mayer | #endif
|
1022 | 74637406 | aurel32 | |
1023 | 74637406 | aurel32 | /* mulhw mulhw. */
|
1024 | 99e300ef | Blue Swirl | static void gen_mulhw(DisasContext *ctx) |
1025 | d9bce9d9 | j_mayer | { |
1026 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1027 | 74637406 | aurel32 | |
1028 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1029 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1030 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1031 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
1032 | 74637406 | aurel32 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
1033 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1034 | 74637406 | aurel32 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
1035 | 74637406 | aurel32 | #else
|
1036 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1037 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1038 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1039 | 74637406 | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
1040 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1041 | 74637406 | aurel32 | #endif
|
1042 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1043 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1044 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1045 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1046 | d9bce9d9 | j_mayer | } |
1047 | 99e300ef | Blue Swirl | |
1048 | 54623277 | Blue Swirl | /* mulhwu mulhwu. */
|
1049 | 99e300ef | Blue Swirl | static void gen_mulhwu(DisasContext *ctx) |
1050 | d9bce9d9 | j_mayer | { |
1051 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1052 | 74637406 | aurel32 | |
1053 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1054 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1055 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1056 | 74637406 | aurel32 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1057 | 74637406 | aurel32 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1058 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1059 | 74637406 | aurel32 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
1060 | 74637406 | aurel32 | #else
|
1061 | 74637406 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1062 | 74637406 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1063 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1064 | 74637406 | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
1065 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1066 | 74637406 | aurel32 | #endif
|
1067 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1068 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1069 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1070 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1071 | d9bce9d9 | j_mayer | } |
1072 | 99e300ef | Blue Swirl | |
1073 | 54623277 | Blue Swirl | /* mullw mullw. */
|
1074 | 99e300ef | Blue Swirl | static void gen_mullw(DisasContext *ctx) |
1075 | d9bce9d9 | j_mayer | { |
1076 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1077 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1078 | 1e4c090f | aurel32 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
1079 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1080 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1081 | d9bce9d9 | j_mayer | } |
1082 | 99e300ef | Blue Swirl | |
1083 | 54623277 | Blue Swirl | /* mullwo mullwo. */
|
1084 | 99e300ef | Blue Swirl | static void gen_mullwo(DisasContext *ctx) |
1085 | d9bce9d9 | j_mayer | { |
1086 | 74637406 | aurel32 | int l1;
|
1087 | a7812ae4 | pbrook | TCGv_i64 t0, t1; |
1088 | 74637406 | aurel32 | |
1089 | a7812ae4 | pbrook | t0 = tcg_temp_new_i64(); |
1090 | a7812ae4 | pbrook | t1 = tcg_temp_new_i64(); |
1091 | 74637406 | aurel32 | l1 = gen_new_label(); |
1092 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
1093 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1094 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1095 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1096 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1097 | 74637406 | aurel32 | #else
|
1098 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1099 | 74637406 | aurel32 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
1100 | d9bce9d9 | j_mayer | #endif
|
1101 | 74637406 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
1102 | 74637406 | aurel32 | #if defined(TARGET_PPC64)
|
1103 | 74637406 | aurel32 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); |
1104 | 74637406 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); |
1105 | 74637406 | aurel32 | #else
|
1106 | 74637406 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1107 | 74637406 | aurel32 | tcg_gen_ext32s_i64(t1, t0); |
1108 | 74637406 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
1109 | 74637406 | aurel32 | #endif
|
1110 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
1111 | 74637406 | aurel32 | gen_set_label(l1); |
1112 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
1113 | a7812ae4 | pbrook | tcg_temp_free_i64(t1); |
1114 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1115 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1116 | d9bce9d9 | j_mayer | } |
1117 | 99e300ef | Blue Swirl | |
1118 | 54623277 | Blue Swirl | /* mulli */
|
1119 | 99e300ef | Blue Swirl | static void gen_mulli(DisasContext *ctx) |
1120 | d9bce9d9 | j_mayer | { |
1121 | 74637406 | aurel32 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1122 | 74637406 | aurel32 | SIMM(ctx->opcode)); |
1123 | d9bce9d9 | j_mayer | } |
1124 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1125 | 74637406 | aurel32 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
|
1126 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1127 | 74637406 | aurel32 | { \ |
1128 | a7812ae4 | pbrook | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ |
1129 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
1130 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1131 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ |
1132 | d9bce9d9 | j_mayer | } |
1133 | 74637406 | aurel32 | /* mulhd mulhd. */
|
1134 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
|
1135 | 74637406 | aurel32 | /* mulhdu mulhdu. */
|
1136 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
|
1137 | 99e300ef | Blue Swirl | |
1138 | 54623277 | Blue Swirl | /* mulld mulld. */
|
1139 | 99e300ef | Blue Swirl | static void gen_mulld(DisasContext *ctx) |
1140 | d9bce9d9 | j_mayer | { |
1141 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1142 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1143 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1144 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1145 | d9bce9d9 | j_mayer | } |
1146 | 74637406 | aurel32 | /* mulldo mulldo. */
|
1147 | 74637406 | aurel32 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
|
1148 | d9bce9d9 | j_mayer | #endif
|
1149 | 74637406 | aurel32 | |
1150 | 74637406 | aurel32 | /* neg neg. nego nego. */
|
1151 | 636aa200 | Blue Swirl | static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
1152 | 636aa200 | Blue Swirl | int ov_check)
|
1153 | d9bce9d9 | j_mayer | { |
1154 | ec6469a3 | aurel32 | int l1 = gen_new_label();
|
1155 | ec6469a3 | aurel32 | int l2 = gen_new_label();
|
1156 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
1157 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1158 | 74637406 | aurel32 | if (ctx->sf_mode) {
|
1159 | 741a7444 | aurel32 | tcg_gen_mov_tl(t0, arg1); |
1160 | ec6469a3 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1161 | ec6469a3 | aurel32 | } else
|
1162 | ec6469a3 | aurel32 | #endif
|
1163 | ec6469a3 | aurel32 | { |
1164 | ec6469a3 | aurel32 | tcg_gen_ext32s_tl(t0, arg1); |
1165 | 74637406 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1166 | 74637406 | aurel32 | } |
1167 | 74637406 | aurel32 | tcg_gen_neg_tl(ret, arg1); |
1168 | 74637406 | aurel32 | if (ov_check) {
|
1169 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1170 | 74637406 | aurel32 | } |
1171 | 74637406 | aurel32 | tcg_gen_br(l2); |
1172 | 74637406 | aurel32 | gen_set_label(l1); |
1173 | ec6469a3 | aurel32 | tcg_gen_mov_tl(ret, t0); |
1174 | 74637406 | aurel32 | if (ov_check) {
|
1175 | 74637406 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
1176 | 74637406 | aurel32 | } |
1177 | 74637406 | aurel32 | gen_set_label(l2); |
1178 | ec6469a3 | aurel32 | tcg_temp_free(t0); |
1179 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1180 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
1181 | 74637406 | aurel32 | } |
1182 | 99e300ef | Blue Swirl | |
1183 | 99e300ef | Blue Swirl | static void gen_neg(DisasContext *ctx) |
1184 | d9bce9d9 | j_mayer | { |
1185 | ec6469a3 | aurel32 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
|
1186 | d9bce9d9 | j_mayer | } |
1187 | 99e300ef | Blue Swirl | |
1188 | 99e300ef | Blue Swirl | static void gen_nego(DisasContext *ctx) |
1189 | 79aceca5 | bellard | { |
1190 | ec6469a3 | aurel32 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
|
1191 | 79aceca5 | bellard | } |
1192 | 74637406 | aurel32 | |
1193 | 74637406 | aurel32 | /* Common subf function */
|
1194 | 636aa200 | Blue Swirl | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
1195 | 636aa200 | Blue Swirl | TCGv arg2, int add_ca, int compute_ca, |
1196 | 636aa200 | Blue Swirl | int compute_ov)
|
1197 | 79aceca5 | bellard | { |
1198 | 74637406 | aurel32 | TCGv t0, t1; |
1199 | 76a66253 | j_mayer | |
1200 | 74637406 | aurel32 | if ((!compute_ca && !compute_ov) ||
|
1201 | a7812ae4 | pbrook | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
1202 | 74637406 | aurel32 | t0 = ret; |
1203 | e864cabd | j_mayer | } else {
|
1204 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1205 | d9bce9d9 | j_mayer | } |
1206 | 76a66253 | j_mayer | |
1207 | 74637406 | aurel32 | if (add_ca) {
|
1208 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
1209 | 74637406 | aurel32 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
|
1210 | 74637406 | aurel32 | tcg_gen_shri_tl(t1, t1, XER_CA); |
1211 | d2e9fd8f | malc | } else {
|
1212 | d2e9fd8f | malc | TCGV_UNUSED(t1); |
1213 | d9bce9d9 | j_mayer | } |
1214 | 79aceca5 | bellard | |
1215 | 74637406 | aurel32 | if (compute_ca && compute_ov) {
|
1216 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
1217 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
1218 | 74637406 | aurel32 | } else if (compute_ca) { |
1219 | 74637406 | aurel32 | /* Start with XER CA disabled, the most likely case */
|
1220 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1221 | 74637406 | aurel32 | } else if (compute_ov) { |
1222 | 74637406 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
1223 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
1224 | 74637406 | aurel32 | } |
1225 | 74637406 | aurel32 | |
1226 | 74637406 | aurel32 | if (add_ca) {
|
1227 | 74637406 | aurel32 | tcg_gen_not_tl(t0, arg1); |
1228 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, arg2); |
1229 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg2, 0);
|
1230 | 74637406 | aurel32 | tcg_gen_add_tl(t0, t0, t1); |
1231 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 0);
|
1232 | 74637406 | aurel32 | tcg_temp_free(t1); |
1233 | 79aceca5 | bellard | } else {
|
1234 | 74637406 | aurel32 | tcg_gen_sub_tl(t0, arg2, arg1); |
1235 | 74637406 | aurel32 | if (compute_ca) {
|
1236 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, arg2, 1);
|
1237 | 74637406 | aurel32 | } |
1238 | 74637406 | aurel32 | } |
1239 | 74637406 | aurel32 | if (compute_ov) {
|
1240 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
|
1241 | 74637406 | aurel32 | } |
1242 | 74637406 | aurel32 | |
1243 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1244 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
1245 | 74637406 | aurel32 | |
1246 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
1247 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
1248 | 74637406 | aurel32 | tcg_temp_free(t0); |
1249 | 79aceca5 | bellard | } |
1250 | 79aceca5 | bellard | } |
1251 | 74637406 | aurel32 | /* Sub functions with Two operands functions */
|
1252 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
1253 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1254 | 74637406 | aurel32 | { \ |
1255 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1256 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1257 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
1258 | 74637406 | aurel32 | } |
1259 | 74637406 | aurel32 | /* Sub functions with one operand and one immediate */
|
1260 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
1261 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
1262 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1263 | 74637406 | aurel32 | { \ |
1264 | 74637406 | aurel32 | TCGv t0 = tcg_const_local_tl(const_val); \ |
1265 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1266 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
1267 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov); \ |
1268 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
1269 | 74637406 | aurel32 | } |
1270 | 74637406 | aurel32 | /* subf subf. subfo subfo. */
|
1271 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
1272 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
1273 | 74637406 | aurel32 | /* subfc subfc. subfco subfco. */
|
1274 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
1275 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
1276 | 74637406 | aurel32 | /* subfe subfe. subfeo subfo. */
|
1277 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
1278 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
1279 | 74637406 | aurel32 | /* subfme subfme. subfmeo subfmeo. */
|
1280 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
1281 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
1282 | 74637406 | aurel32 | /* subfze subfze. subfzeo subfzeo.*/
|
1283 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
1284 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
1285 | 99e300ef | Blue Swirl | |
1286 | 54623277 | Blue Swirl | /* subfic */
|
1287 | 99e300ef | Blue Swirl | static void gen_subfic(DisasContext *ctx) |
1288 | 79aceca5 | bellard | { |
1289 | 74637406 | aurel32 | /* Start with XER CA and OV disabled, the most likely case */
|
1290 | 74637406 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1291 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_local_new(); |
1292 | 74637406 | aurel32 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
1293 | 74637406 | aurel32 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); |
1294 | 74637406 | aurel32 | gen_op_arith_compute_ca(ctx, t0, t1, 1);
|
1295 | 74637406 | aurel32 | tcg_temp_free(t1); |
1296 | 74637406 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1297 | 74637406 | aurel32 | tcg_temp_free(t0); |
1298 | 79aceca5 | bellard | } |
1299 | 79aceca5 | bellard | |
1300 | 79aceca5 | bellard | /*** Integer logical ***/
|
1301 | 26d67362 | aurel32 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
1302 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1303 | 79aceca5 | bellard | { \ |
1304 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1305 | 26d67362 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
1306 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1307 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1308 | 79aceca5 | bellard | } |
1309 | 79aceca5 | bellard | |
1310 | 26d67362 | aurel32 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
1311 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1312 | 79aceca5 | bellard | { \ |
1313 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
1314 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1315 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1316 | 79aceca5 | bellard | } |
1317 | 79aceca5 | bellard | |
1318 | 79aceca5 | bellard | /* and & and. */
|
1319 | 26d67362 | aurel32 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
|
1320 | 79aceca5 | bellard | /* andc & andc. */
|
1321 | 26d67362 | aurel32 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
|
1322 | e8eaa2c0 | Blue Swirl | |
1323 | 54623277 | Blue Swirl | /* andi. */
|
1324 | e8eaa2c0 | Blue Swirl | static void gen_andi_(DisasContext *ctx) |
1325 | 79aceca5 | bellard | { |
1326 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1327 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1328 | 79aceca5 | bellard | } |
1329 | e8eaa2c0 | Blue Swirl | |
1330 | 54623277 | Blue Swirl | /* andis. */
|
1331 | e8eaa2c0 | Blue Swirl | static void gen_andis_(DisasContext *ctx) |
1332 | 79aceca5 | bellard | { |
1333 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
|
1334 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1335 | 79aceca5 | bellard | } |
1336 | 99e300ef | Blue Swirl | |
1337 | 54623277 | Blue Swirl | /* cntlzw */
|
1338 | 99e300ef | Blue Swirl | static void gen_cntlzw(DisasContext *ctx) |
1339 | 26d67362 | aurel32 | { |
1340 | a7812ae4 | pbrook | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1341 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1342 | 2e31f5d3 | pbrook | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1343 | 26d67362 | aurel32 | } |
1344 | 79aceca5 | bellard | /* eqv & eqv. */
|
1345 | 26d67362 | aurel32 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
|
1346 | 79aceca5 | bellard | /* extsb & extsb. */
|
1347 | 26d67362 | aurel32 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
|
1348 | 79aceca5 | bellard | /* extsh & extsh. */
|
1349 | 26d67362 | aurel32 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
|
1350 | 79aceca5 | bellard | /* nand & nand. */
|
1351 | 26d67362 | aurel32 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
|
1352 | 79aceca5 | bellard | /* nor & nor. */
|
1353 | 26d67362 | aurel32 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
|
1354 | 99e300ef | Blue Swirl | |
1355 | 54623277 | Blue Swirl | /* or & or. */
|
1356 | 99e300ef | Blue Swirl | static void gen_or(DisasContext *ctx) |
1357 | 9a64fbe4 | bellard | { |
1358 | 76a66253 | j_mayer | int rs, ra, rb;
|
1359 | 76a66253 | j_mayer | |
1360 | 76a66253 | j_mayer | rs = rS(ctx->opcode); |
1361 | 76a66253 | j_mayer | ra = rA(ctx->opcode); |
1362 | 76a66253 | j_mayer | rb = rB(ctx->opcode); |
1363 | 76a66253 | j_mayer | /* Optimisation for mr. ri case */
|
1364 | 76a66253 | j_mayer | if (rs != ra || rs != rb) {
|
1365 | 26d67362 | aurel32 | if (rs != rb)
|
1366 | 26d67362 | aurel32 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
1367 | 26d67362 | aurel32 | else
|
1368 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
1369 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1370 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
1371 | 76a66253 | j_mayer | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
1372 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
1373 | c80f84e3 | j_mayer | #if defined(TARGET_PPC64)
|
1374 | c80f84e3 | j_mayer | } else {
|
1375 | 26d67362 | aurel32 | int prio = 0; |
1376 | 26d67362 | aurel32 | |
1377 | c80f84e3 | j_mayer | switch (rs) {
|
1378 | c80f84e3 | j_mayer | case 1: |
1379 | c80f84e3 | j_mayer | /* Set process priority to low */
|
1380 | 26d67362 | aurel32 | prio = 2;
|
1381 | c80f84e3 | j_mayer | break;
|
1382 | c80f84e3 | j_mayer | case 6: |
1383 | c80f84e3 | j_mayer | /* Set process priority to medium-low */
|
1384 | 26d67362 | aurel32 | prio = 3;
|
1385 | c80f84e3 | j_mayer | break;
|
1386 | c80f84e3 | j_mayer | case 2: |
1387 | c80f84e3 | j_mayer | /* Set process priority to normal */
|
1388 | 26d67362 | aurel32 | prio = 4;
|
1389 | c80f84e3 | j_mayer | break;
|
1390 | be147d08 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
1391 | be147d08 | j_mayer | case 31: |
1392 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1393 | be147d08 | j_mayer | /* Set process priority to very low */
|
1394 | 26d67362 | aurel32 | prio = 1;
|
1395 | be147d08 | j_mayer | } |
1396 | be147d08 | j_mayer | break;
|
1397 | be147d08 | j_mayer | case 5: |
1398 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1399 | be147d08 | j_mayer | /* Set process priority to medium-hight */
|
1400 | 26d67362 | aurel32 | prio = 5;
|
1401 | be147d08 | j_mayer | } |
1402 | be147d08 | j_mayer | break;
|
1403 | be147d08 | j_mayer | case 3: |
1404 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1405 | be147d08 | j_mayer | /* Set process priority to high */
|
1406 | 26d67362 | aurel32 | prio = 6;
|
1407 | be147d08 | j_mayer | } |
1408 | be147d08 | j_mayer | break;
|
1409 | be147d08 | j_mayer | case 7: |
1410 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 1) { |
1411 | be147d08 | j_mayer | /* Set process priority to very high */
|
1412 | 26d67362 | aurel32 | prio = 7;
|
1413 | be147d08 | j_mayer | } |
1414 | be147d08 | j_mayer | break;
|
1415 | be147d08 | j_mayer | #endif
|
1416 | c80f84e3 | j_mayer | default:
|
1417 | c80f84e3 | j_mayer | /* nop */
|
1418 | c80f84e3 | j_mayer | break;
|
1419 | c80f84e3 | j_mayer | } |
1420 | 26d67362 | aurel32 | if (prio) {
|
1421 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1422 | 54cdcae6 | aurel32 | gen_load_spr(t0, SPR_PPR); |
1423 | ea363694 | aurel32 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
|
1424 | ea363694 | aurel32 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
|
1425 | 54cdcae6 | aurel32 | gen_store_spr(SPR_PPR, t0); |
1426 | ea363694 | aurel32 | tcg_temp_free(t0); |
1427 | 26d67362 | aurel32 | } |
1428 | c80f84e3 | j_mayer | #endif
|
1429 | 9a64fbe4 | bellard | } |
1430 | 9a64fbe4 | bellard | } |
1431 | 79aceca5 | bellard | /* orc & orc. */
|
1432 | 26d67362 | aurel32 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
|
1433 | 99e300ef | Blue Swirl | |
1434 | 54623277 | Blue Swirl | /* xor & xor. */
|
1435 | 99e300ef | Blue Swirl | static void gen_xor(DisasContext *ctx) |
1436 | 9a64fbe4 | bellard | { |
1437 | 9a64fbe4 | bellard | /* Optimisation for "set to zero" case */
|
1438 | 26d67362 | aurel32 | if (rS(ctx->opcode) != rB(ctx->opcode))
|
1439 | 312179c4 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1440 | 26d67362 | aurel32 | else
|
1441 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1442 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1443 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1444 | 9a64fbe4 | bellard | } |
1445 | 99e300ef | Blue Swirl | |
1446 | 54623277 | Blue Swirl | /* ori */
|
1447 | 99e300ef | Blue Swirl | static void gen_ori(DisasContext *ctx) |
1448 | 79aceca5 | bellard | { |
1449 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1450 | 79aceca5 | bellard | |
1451 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1452 | 9a64fbe4 | bellard | /* NOP */
|
1453 | 76a66253 | j_mayer | /* XXX: should handle special NOPs for POWER series */
|
1454 | 9a64fbe4 | bellard | return;
|
1455 | 76a66253 | j_mayer | } |
1456 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1457 | 79aceca5 | bellard | } |
1458 | 99e300ef | Blue Swirl | |
1459 | 54623277 | Blue Swirl | /* oris */
|
1460 | 99e300ef | Blue Swirl | static void gen_oris(DisasContext *ctx) |
1461 | 79aceca5 | bellard | { |
1462 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1463 | 79aceca5 | bellard | |
1464 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1465 | 9a64fbe4 | bellard | /* NOP */
|
1466 | 9a64fbe4 | bellard | return;
|
1467 | 76a66253 | j_mayer | } |
1468 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1469 | 79aceca5 | bellard | } |
1470 | 99e300ef | Blue Swirl | |
1471 | 54623277 | Blue Swirl | /* xori */
|
1472 | 99e300ef | Blue Swirl | static void gen_xori(DisasContext *ctx) |
1473 | 79aceca5 | bellard | { |
1474 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1475 | 9a64fbe4 | bellard | |
1476 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1477 | 9a64fbe4 | bellard | /* NOP */
|
1478 | 9a64fbe4 | bellard | return;
|
1479 | 9a64fbe4 | bellard | } |
1480 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1481 | 79aceca5 | bellard | } |
1482 | 99e300ef | Blue Swirl | |
1483 | 54623277 | Blue Swirl | /* xoris */
|
1484 | 99e300ef | Blue Swirl | static void gen_xoris(DisasContext *ctx) |
1485 | 79aceca5 | bellard | { |
1486 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1487 | 9a64fbe4 | bellard | |
1488 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1489 | 9a64fbe4 | bellard | /* NOP */
|
1490 | 9a64fbe4 | bellard | return;
|
1491 | 9a64fbe4 | bellard | } |
1492 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1493 | 79aceca5 | bellard | } |
1494 | 99e300ef | Blue Swirl | |
1495 | 54623277 | Blue Swirl | /* popcntb : PowerPC 2.03 specification */
|
1496 | 99e300ef | Blue Swirl | static void gen_popcntb(DisasContext *ctx) |
1497 | d9bce9d9 | j_mayer | { |
1498 | eaabeef2 | David Gibson | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1499 | eaabeef2 | David Gibson | } |
1500 | eaabeef2 | David Gibson | |
1501 | eaabeef2 | David Gibson | static void gen_popcntw(DisasContext *ctx) |
1502 | eaabeef2 | David Gibson | { |
1503 | eaabeef2 | David Gibson | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1504 | eaabeef2 | David Gibson | } |
1505 | eaabeef2 | David Gibson | |
1506 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1507 | eaabeef2 | David Gibson | /* popcntd: PowerPC 2.06 specification */
|
1508 | eaabeef2 | David Gibson | static void gen_popcntd(DisasContext *ctx) |
1509 | eaabeef2 | David Gibson | { |
1510 | eaabeef2 | David Gibson | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1511 | d9bce9d9 | j_mayer | } |
1512 | eaabeef2 | David Gibson | #endif
|
1513 | d9bce9d9 | j_mayer | |
1514 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1515 | d9bce9d9 | j_mayer | /* extsw & extsw. */
|
1516 | 26d67362 | aurel32 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
|
1517 | 99e300ef | Blue Swirl | |
1518 | 54623277 | Blue Swirl | /* cntlzd */
|
1519 | 99e300ef | Blue Swirl | static void gen_cntlzd(DisasContext *ctx) |
1520 | 26d67362 | aurel32 | { |
1521 | a7812ae4 | pbrook | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1522 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1523 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1524 | 26d67362 | aurel32 | } |
1525 | d9bce9d9 | j_mayer | #endif
|
1526 | d9bce9d9 | j_mayer | |
1527 | 79aceca5 | bellard | /*** Integer rotate ***/
|
1528 | 99e300ef | Blue Swirl | |
1529 | 54623277 | Blue Swirl | /* rlwimi & rlwimi. */
|
1530 | 99e300ef | Blue Swirl | static void gen_rlwimi(DisasContext *ctx) |
1531 | 79aceca5 | bellard | { |
1532 | 76a66253 | j_mayer | uint32_t mb, me, sh; |
1533 | 79aceca5 | bellard | |
1534 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1535 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1536 | 76a66253 | j_mayer | sh = SH(ctx->opcode); |
1537 | d03ef511 | aurel32 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1538 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1539 | d03ef511 | aurel32 | } else {
|
1540 | d03ef511 | aurel32 | target_ulong mask; |
1541 | a7812ae4 | pbrook | TCGv t1; |
1542 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1543 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1544 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_new_i32(); |
1545 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); |
1546 | a7812ae4 | pbrook | tcg_gen_rotli_i32(t2, t2, sh); |
1547 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(t0, t2); |
1548 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1549 | 54843a58 | aurel32 | #else
|
1550 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1551 | 54843a58 | aurel32 | #endif
|
1552 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1553 | d03ef511 | aurel32 | mb += 32;
|
1554 | d03ef511 | aurel32 | me += 32;
|
1555 | 76a66253 | j_mayer | #endif
|
1556 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1557 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1558 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1559 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1560 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1561 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1562 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1563 | d03ef511 | aurel32 | } |
1564 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1565 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1566 | 79aceca5 | bellard | } |
1567 | 99e300ef | Blue Swirl | |
1568 | 54623277 | Blue Swirl | /* rlwinm & rlwinm. */
|
1569 | 99e300ef | Blue Swirl | static void gen_rlwinm(DisasContext *ctx) |
1570 | 79aceca5 | bellard | { |
1571 | 79aceca5 | bellard | uint32_t mb, me, sh; |
1572 | 3b46e624 | ths | |
1573 | 79aceca5 | bellard | sh = SH(ctx->opcode); |
1574 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1575 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1576 | d03ef511 | aurel32 | |
1577 | d03ef511 | aurel32 | if (likely(mb == 0 && me == (31 - sh))) { |
1578 | d03ef511 | aurel32 | if (likely(sh == 0)) { |
1579 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1580 | d03ef511 | aurel32 | } else {
|
1581 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1582 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1583 | d03ef511 | aurel32 | tcg_gen_shli_tl(t0, t0, sh); |
1584 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1585 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1586 | 79aceca5 | bellard | } |
1587 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
1588 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1589 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1590 | d03ef511 | aurel32 | tcg_gen_shri_tl(t0, t0, mb); |
1591 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1592 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1593 | d03ef511 | aurel32 | } else {
|
1594 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1595 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1596 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_new_i32(); |
1597 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1598 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t1, t1, sh); |
1599 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1600 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1601 | 54843a58 | aurel32 | #else
|
1602 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1603 | 54843a58 | aurel32 | #endif
|
1604 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1605 | d03ef511 | aurel32 | mb += 32;
|
1606 | d03ef511 | aurel32 | me += 32;
|
1607 | 76a66253 | j_mayer | #endif
|
1608 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1609 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1610 | d03ef511 | aurel32 | } |
1611 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1612 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1613 | 79aceca5 | bellard | } |
1614 | 99e300ef | Blue Swirl | |
1615 | 54623277 | Blue Swirl | /* rlwnm & rlwnm. */
|
1616 | 99e300ef | Blue Swirl | static void gen_rlwnm(DisasContext *ctx) |
1617 | 79aceca5 | bellard | { |
1618 | 79aceca5 | bellard | uint32_t mb, me; |
1619 | 54843a58 | aurel32 | TCGv t0; |
1620 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1621 | a7812ae4 | pbrook | TCGv_i32 t1, t2; |
1622 | 54843a58 | aurel32 | #endif
|
1623 | 79aceca5 | bellard | |
1624 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1625 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1626 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1627 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1628 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1629 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1630 | a7812ae4 | pbrook | t2 = tcg_temp_new_i32(); |
1631 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1632 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t2, t0); |
1633 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t1, t1, t2); |
1634 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1635 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1636 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1637 | 54843a58 | aurel32 | #else
|
1638 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1639 | 54843a58 | aurel32 | #endif
|
1640 | 76a66253 | j_mayer | if (unlikely(mb != 0 || me != 31)) { |
1641 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1642 | 76a66253 | j_mayer | mb += 32;
|
1643 | 76a66253 | j_mayer | me += 32;
|
1644 | 76a66253 | j_mayer | #endif
|
1645 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1646 | d03ef511 | aurel32 | } else {
|
1647 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1648 | 79aceca5 | bellard | } |
1649 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1650 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1651 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1652 | 79aceca5 | bellard | } |
1653 | 79aceca5 | bellard | |
1654 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1655 | d9bce9d9 | j_mayer | #define GEN_PPC64_R2(name, opc1, opc2) \
|
1656 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1657 | d9bce9d9 | j_mayer | { \ |
1658 | d9bce9d9 | j_mayer | gen_##name(ctx, 0); \ |
1659 | d9bce9d9 | j_mayer | } \ |
1660 | e8eaa2c0 | Blue Swirl | \ |
1661 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1662 | d9bce9d9 | j_mayer | { \ |
1663 | d9bce9d9 | j_mayer | gen_##name(ctx, 1); \ |
1664 | d9bce9d9 | j_mayer | } |
1665 | d9bce9d9 | j_mayer | #define GEN_PPC64_R4(name, opc1, opc2) \
|
1666 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1667 | d9bce9d9 | j_mayer | { \ |
1668 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 0); \ |
1669 | d9bce9d9 | j_mayer | } \ |
1670 | e8eaa2c0 | Blue Swirl | \ |
1671 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1672 | d9bce9d9 | j_mayer | { \ |
1673 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 1); \ |
1674 | d9bce9d9 | j_mayer | } \ |
1675 | e8eaa2c0 | Blue Swirl | \ |
1676 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##2)(DisasContext *ctx) \ |
1677 | d9bce9d9 | j_mayer | { \ |
1678 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 0); \ |
1679 | d9bce9d9 | j_mayer | } \ |
1680 | e8eaa2c0 | Blue Swirl | \ |
1681 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##3)(DisasContext *ctx) \ |
1682 | d9bce9d9 | j_mayer | { \ |
1683 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 1); \ |
1684 | d9bce9d9 | j_mayer | } |
1685 | 51789c41 | j_mayer | |
1686 | 636aa200 | Blue Swirl | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1687 | 636aa200 | Blue Swirl | uint32_t sh) |
1688 | 51789c41 | j_mayer | { |
1689 | d03ef511 | aurel32 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1690 | d03ef511 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1691 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { |
1692 | d03ef511 | aurel32 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); |
1693 | d03ef511 | aurel32 | } else {
|
1694 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1695 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1696 | d03ef511 | aurel32 | if (likely(mb == 0 && me == 63)) { |
1697 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1698 | d03ef511 | aurel32 | } else {
|
1699 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1700 | 51789c41 | j_mayer | } |
1701 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1702 | 51789c41 | j_mayer | } |
1703 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1704 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1705 | 51789c41 | j_mayer | } |
1706 | d9bce9d9 | j_mayer | /* rldicl - rldicl. */
|
1707 | 636aa200 | Blue Swirl | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
1708 | d9bce9d9 | j_mayer | { |
1709 | 51789c41 | j_mayer | uint32_t sh, mb; |
1710 | d9bce9d9 | j_mayer | |
1711 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1712 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1713 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63, sh);
|
1714 | d9bce9d9 | j_mayer | } |
1715 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
1716 | d9bce9d9 | j_mayer | /* rldicr - rldicr. */
|
1717 | 636aa200 | Blue Swirl | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
1718 | d9bce9d9 | j_mayer | { |
1719 | 51789c41 | j_mayer | uint32_t sh, me; |
1720 | d9bce9d9 | j_mayer | |
1721 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1722 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1723 | 51789c41 | j_mayer | gen_rldinm(ctx, 0, me, sh);
|
1724 | d9bce9d9 | j_mayer | } |
1725 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
1726 | d9bce9d9 | j_mayer | /* rldic - rldic. */
|
1727 | 636aa200 | Blue Swirl | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
1728 | d9bce9d9 | j_mayer | { |
1729 | 51789c41 | j_mayer | uint32_t sh, mb; |
1730 | d9bce9d9 | j_mayer | |
1731 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1732 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1733 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63 - sh, sh);
|
1734 | 51789c41 | j_mayer | } |
1735 | 51789c41 | j_mayer | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
1736 | 51789c41 | j_mayer | |
1737 | 636aa200 | Blue Swirl | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
1738 | 51789c41 | j_mayer | { |
1739 | 54843a58 | aurel32 | TCGv t0; |
1740 | d03ef511 | aurel32 | |
1741 | d03ef511 | aurel32 | mb = MB(ctx->opcode); |
1742 | d03ef511 | aurel32 | me = ME(ctx->opcode); |
1743 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1744 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1745 | 54843a58 | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1746 | 51789c41 | j_mayer | if (unlikely(mb != 0 || me != 63)) { |
1747 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1748 | 54843a58 | aurel32 | } else {
|
1749 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1750 | 54843a58 | aurel32 | } |
1751 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1752 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1753 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1754 | d9bce9d9 | j_mayer | } |
1755 | 51789c41 | j_mayer | |
1756 | d9bce9d9 | j_mayer | /* rldcl - rldcl. */
|
1757 | 636aa200 | Blue Swirl | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
1758 | d9bce9d9 | j_mayer | { |
1759 | 51789c41 | j_mayer | uint32_t mb; |
1760 | d9bce9d9 | j_mayer | |
1761 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1762 | 51789c41 | j_mayer | gen_rldnm(ctx, mb, 63);
|
1763 | d9bce9d9 | j_mayer | } |
1764 | 36081602 | j_mayer | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
1765 | d9bce9d9 | j_mayer | /* rldcr - rldcr. */
|
1766 | 636aa200 | Blue Swirl | static inline void gen_rldcr(DisasContext *ctx, int men) |
1767 | d9bce9d9 | j_mayer | { |
1768 | 51789c41 | j_mayer | uint32_t me; |
1769 | d9bce9d9 | j_mayer | |
1770 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1771 | 51789c41 | j_mayer | gen_rldnm(ctx, 0, me);
|
1772 | d9bce9d9 | j_mayer | } |
1773 | 36081602 | j_mayer | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
1774 | d9bce9d9 | j_mayer | /* rldimi - rldimi. */
|
1775 | 636aa200 | Blue Swirl | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
1776 | d9bce9d9 | j_mayer | { |
1777 | 271a916e | j_mayer | uint32_t sh, mb, me; |
1778 | d9bce9d9 | j_mayer | |
1779 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1780 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1781 | 271a916e | j_mayer | me = 63 - sh;
|
1782 | d03ef511 | aurel32 | if (unlikely(sh == 0 && mb == 0)) { |
1783 | d03ef511 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1784 | d03ef511 | aurel32 | } else {
|
1785 | d03ef511 | aurel32 | TCGv t0, t1; |
1786 | d03ef511 | aurel32 | target_ulong mask; |
1787 | d03ef511 | aurel32 | |
1788 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1789 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1790 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1791 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1792 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1793 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1794 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1795 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1796 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1797 | 51789c41 | j_mayer | } |
1798 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1799 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1800 | d9bce9d9 | j_mayer | } |
1801 | 36081602 | j_mayer | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
1802 | d9bce9d9 | j_mayer | #endif
|
1803 | d9bce9d9 | j_mayer | |
1804 | 79aceca5 | bellard | /*** Integer shift ***/
|
1805 | 99e300ef | Blue Swirl | |
1806 | 54623277 | Blue Swirl | /* slw & slw. */
|
1807 | 99e300ef | Blue Swirl | static void gen_slw(DisasContext *ctx) |
1808 | 26d67362 | aurel32 | { |
1809 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1810 | 26d67362 | aurel32 | |
1811 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1812 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x20 */
|
1813 | 7fd6bf7d | Aurelien Jarno | #if defined(TARGET_PPC64)
|
1814 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
|
1815 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1816 | 7fd6bf7d | Aurelien Jarno | #else
|
1817 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
|
1818 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x1f);
|
1819 | 7fd6bf7d | Aurelien Jarno | #endif
|
1820 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1821 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1822 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1823 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1824 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1825 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1826 | 7fd6bf7d | Aurelien Jarno | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1827 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1828 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1829 | 26d67362 | aurel32 | } |
1830 | 99e300ef | Blue Swirl | |
1831 | 54623277 | Blue Swirl | /* sraw & sraw. */
|
1832 | 99e300ef | Blue Swirl | static void gen_sraw(DisasContext *ctx) |
1833 | 26d67362 | aurel32 | { |
1834 | a7812ae4 | pbrook | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], |
1835 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1836 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1837 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1838 | 26d67362 | aurel32 | } |
1839 | 99e300ef | Blue Swirl | |
1840 | 54623277 | Blue Swirl | /* srawi & srawi. */
|
1841 | 99e300ef | Blue Swirl | static void gen_srawi(DisasContext *ctx) |
1842 | 79aceca5 | bellard | { |
1843 | 26d67362 | aurel32 | int sh = SH(ctx->opcode);
|
1844 | 26d67362 | aurel32 | if (sh != 0) { |
1845 | 26d67362 | aurel32 | int l1, l2;
|
1846 | fea0c503 | aurel32 | TCGv t0; |
1847 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1848 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1849 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1850 | fea0c503 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1851 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
|
1852 | fea0c503 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1853 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
1854 | 269f3e95 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
1855 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1856 | 26d67362 | aurel32 | gen_set_label(l1); |
1857 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1858 | 26d67362 | aurel32 | gen_set_label(l2); |
1859 | fea0c503 | aurel32 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1860 | fea0c503 | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); |
1861 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1862 | 26d67362 | aurel32 | } else {
|
1863 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1864 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1865 | d9bce9d9 | j_mayer | } |
1866 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1867 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1868 | 79aceca5 | bellard | } |
1869 | 99e300ef | Blue Swirl | |
1870 | 54623277 | Blue Swirl | /* srw & srw. */
|
1871 | 99e300ef | Blue Swirl | static void gen_srw(DisasContext *ctx) |
1872 | 26d67362 | aurel32 | { |
1873 | fea0c503 | aurel32 | TCGv t0, t1; |
1874 | d9bce9d9 | j_mayer | |
1875 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1876 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x20 */
|
1877 | 7fd6bf7d | Aurelien Jarno | #if defined(TARGET_PPC64)
|
1878 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
|
1879 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1880 | 7fd6bf7d | Aurelien Jarno | #else
|
1881 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
|
1882 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x1f);
|
1883 | 7fd6bf7d | Aurelien Jarno | #endif
|
1884 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1885 | 7fd6bf7d | Aurelien Jarno | tcg_gen_ext32u_tl(t0, t0); |
1886 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1887 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1888 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1889 | fea0c503 | aurel32 | tcg_temp_free(t1); |
1890 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1891 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1892 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1893 | 26d67362 | aurel32 | } |
1894 | 54623277 | Blue Swirl | |
1895 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1896 | d9bce9d9 | j_mayer | /* sld & sld. */
|
1897 | 99e300ef | Blue Swirl | static void gen_sld(DisasContext *ctx) |
1898 | 26d67362 | aurel32 | { |
1899 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1900 | 26d67362 | aurel32 | |
1901 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1902 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x40 */
|
1903 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
|
1904 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1905 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1906 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1907 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1908 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1909 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1910 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1911 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1912 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1913 | 26d67362 | aurel32 | } |
1914 | 99e300ef | Blue Swirl | |
1915 | 54623277 | Blue Swirl | /* srad & srad. */
|
1916 | 99e300ef | Blue Swirl | static void gen_srad(DisasContext *ctx) |
1917 | 26d67362 | aurel32 | { |
1918 | a7812ae4 | pbrook | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], |
1919 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1920 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1921 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1922 | 26d67362 | aurel32 | } |
1923 | d9bce9d9 | j_mayer | /* sradi & sradi. */
|
1924 | 636aa200 | Blue Swirl | static inline void gen_sradi(DisasContext *ctx, int n) |
1925 | d9bce9d9 | j_mayer | { |
1926 | 26d67362 | aurel32 | int sh = SH(ctx->opcode) + (n << 5); |
1927 | d9bce9d9 | j_mayer | if (sh != 0) { |
1928 | 26d67362 | aurel32 | int l1, l2;
|
1929 | fea0c503 | aurel32 | TCGv t0; |
1930 | 26d67362 | aurel32 | l1 = gen_new_label(); |
1931 | 26d67362 | aurel32 | l2 = gen_new_label(); |
1932 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
1933 | 26d67362 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
1934 | fea0c503 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1935 | fea0c503 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
1936 | 269f3e95 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
|
1937 | 26d67362 | aurel32 | tcg_gen_br(l2); |
1938 | 26d67362 | aurel32 | gen_set_label(l1); |
1939 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1940 | 26d67362 | aurel32 | gen_set_label(l2); |
1941 | a9730017 | aurel32 | tcg_temp_free(t0); |
1942 | 26d67362 | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1943 | 26d67362 | aurel32 | } else {
|
1944 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1945 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
1946 | d9bce9d9 | j_mayer | } |
1947 | d9bce9d9 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1948 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1949 | d9bce9d9 | j_mayer | } |
1950 | e8eaa2c0 | Blue Swirl | |
1951 | e8eaa2c0 | Blue Swirl | static void gen_sradi0(DisasContext *ctx) |
1952 | d9bce9d9 | j_mayer | { |
1953 | d9bce9d9 | j_mayer | gen_sradi(ctx, 0);
|
1954 | d9bce9d9 | j_mayer | } |
1955 | e8eaa2c0 | Blue Swirl | |
1956 | e8eaa2c0 | Blue Swirl | static void gen_sradi1(DisasContext *ctx) |
1957 | d9bce9d9 | j_mayer | { |
1958 | d9bce9d9 | j_mayer | gen_sradi(ctx, 1);
|
1959 | d9bce9d9 | j_mayer | } |
1960 | 99e300ef | Blue Swirl | |
1961 | 54623277 | Blue Swirl | /* srd & srd. */
|
1962 | 99e300ef | Blue Swirl | static void gen_srd(DisasContext *ctx) |
1963 | 26d67362 | aurel32 | { |
1964 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1965 | 26d67362 | aurel32 | |
1966 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1967 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x40 */
|
1968 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
|
1969 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1970 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1971 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1972 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1973 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1974 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1975 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1976 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1977 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1978 | 26d67362 | aurel32 | } |
1979 | d9bce9d9 | j_mayer | #endif
|
1980 | 79aceca5 | bellard | |
1981 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
1982 | 7c58044c | j_mayer | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
1983 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
1984 | 9a64fbe4 | bellard | { \ |
1985 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
1986 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
1987 | 3cc62370 | bellard | return; \
|
1988 | 3cc62370 | bellard | } \ |
1989 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
1990 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
1991 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
1992 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
1993 | af12906f | aurel32 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
1994 | 4ecc3190 | bellard | if (isfloat) { \
|
1995 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
1996 | 4ecc3190 | bellard | } \ |
1997 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
1998 | af12906f | aurel32 | Rc(ctx->opcode) != 0); \
|
1999 | 9a64fbe4 | bellard | } |
2000 | 9a64fbe4 | bellard | |
2001 | 7c58044c | j_mayer | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
2002 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
2003 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
2004 | 9a64fbe4 | bellard | |
2005 | 7c58044c | j_mayer | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
2006 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2007 | 9a64fbe4 | bellard | { \ |
2008 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2009 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2010 | 3cc62370 | bellard | return; \
|
2011 | 3cc62370 | bellard | } \ |
2012 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2013 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2014 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2015 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2016 | af12906f | aurel32 | cpu_fpr[rB(ctx->opcode)]); \ |
2017 | 4ecc3190 | bellard | if (isfloat) { \
|
2018 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
2019 | 4ecc3190 | bellard | } \ |
2020 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2021 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2022 | 9a64fbe4 | bellard | } |
2023 | 7c58044c | j_mayer | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
2024 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2025 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2026 | 9a64fbe4 | bellard | |
2027 | 7c58044c | j_mayer | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
2028 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2029 | 9a64fbe4 | bellard | { \ |
2030 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2031 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2032 | 3cc62370 | bellard | return; \
|
2033 | 3cc62370 | bellard | } \ |
2034 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2035 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2036 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2037 | af12906f | aurel32 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2038 | af12906f | aurel32 | cpu_fpr[rC(ctx->opcode)]); \ |
2039 | 4ecc3190 | bellard | if (isfloat) { \
|
2040 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
2041 | 4ecc3190 | bellard | } \ |
2042 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2043 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2044 | 9a64fbe4 | bellard | } |
2045 | 7c58044c | j_mayer | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
2046 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2047 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2048 | 9a64fbe4 | bellard | |
2049 | 7c58044c | j_mayer | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
2050 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2051 | 9a64fbe4 | bellard | { \ |
2052 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2053 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2054 | 3cc62370 | bellard | return; \
|
2055 | 3cc62370 | bellard | } \ |
2056 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2057 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2058 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2059 | af12906f | aurel32 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2060 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2061 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2062 | 79aceca5 | bellard | } |
2063 | 79aceca5 | bellard | |
2064 | 7c58044c | j_mayer | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
2065 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2066 | 9a64fbe4 | bellard | { \ |
2067 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2068 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2069 | 3cc62370 | bellard | return; \
|
2070 | 3cc62370 | bellard | } \ |
2071 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2072 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2073 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2074 | af12906f | aurel32 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2075 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2076 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2077 | 79aceca5 | bellard | } |
2078 | 79aceca5 | bellard | |
2079 | 9a64fbe4 | bellard | /* fadd - fadds */
|
2080 | 7c58044c | j_mayer | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
2081 | 4ecc3190 | bellard | /* fdiv - fdivs */
|
2082 | 7c58044c | j_mayer | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
2083 | 4ecc3190 | bellard | /* fmul - fmuls */
|
2084 | 7c58044c | j_mayer | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
2085 | 79aceca5 | bellard | |
2086 | d7e4b87e | j_mayer | /* fre */
|
2087 | 7c58044c | j_mayer | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
2088 | d7e4b87e | j_mayer | |
2089 | a750fc0b | j_mayer | /* fres */
|
2090 | 7c58044c | j_mayer | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
2091 | 79aceca5 | bellard | |
2092 | a750fc0b | j_mayer | /* frsqrte */
|
2093 | 7c58044c | j_mayer | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2094 | 7c58044c | j_mayer | |
2095 | 7c58044c | j_mayer | /* frsqrtes */
|
2096 | 99e300ef | Blue Swirl | static void gen_frsqrtes(DisasContext *ctx) |
2097 | 7c58044c | j_mayer | { |
2098 | af12906f | aurel32 | if (unlikely(!ctx->fpu_enabled)) {
|
2099 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2100 | af12906f | aurel32 | return;
|
2101 | af12906f | aurel32 | } |
2102 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2103 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2104 | af12906f | aurel32 | gen_reset_fpstatus(); |
2105 | af12906f | aurel32 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2106 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
2107 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2108 | 7c58044c | j_mayer | } |
2109 | 79aceca5 | bellard | |
2110 | a750fc0b | j_mayer | /* fsel */
|
2111 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
2112 | 4ecc3190 | bellard | /* fsub - fsubs */
|
2113 | 7c58044c | j_mayer | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
2114 | 79aceca5 | bellard | /* Optional: */
|
2115 | 99e300ef | Blue Swirl | |
2116 | 54623277 | Blue Swirl | /* fsqrt */
|
2117 | 99e300ef | Blue Swirl | static void gen_fsqrt(DisasContext *ctx) |
2118 | c7d344af | bellard | { |
2119 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2120 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2121 | c7d344af | bellard | return;
|
2122 | c7d344af | bellard | } |
2123 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2124 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2125 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2126 | af12906f | aurel32 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2127 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2128 | c7d344af | bellard | } |
2129 | 79aceca5 | bellard | |
2130 | 99e300ef | Blue Swirl | static void gen_fsqrts(DisasContext *ctx) |
2131 | 79aceca5 | bellard | { |
2132 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2133 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2134 | 3cc62370 | bellard | return;
|
2135 | 3cc62370 | bellard | } |
2136 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2137 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2138 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2139 | af12906f | aurel32 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2140 | af12906f | aurel32 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
2141 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2142 | 79aceca5 | bellard | } |
2143 | 79aceca5 | bellard | |
2144 | 79aceca5 | bellard | /*** Floating-Point multiply-and-add ***/
|
2145 | 4ecc3190 | bellard | /* fmadd - fmadds */
|
2146 | 7c58044c | j_mayer | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
2147 | 4ecc3190 | bellard | /* fmsub - fmsubs */
|
2148 | 7c58044c | j_mayer | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
2149 | 4ecc3190 | bellard | /* fnmadd - fnmadds */
|
2150 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
2151 | 4ecc3190 | bellard | /* fnmsub - fnmsubs */
|
2152 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
2153 | 79aceca5 | bellard | |
2154 | 79aceca5 | bellard | /*** Floating-Point round & convert ***/
|
2155 | 79aceca5 | bellard | /* fctiw */
|
2156 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
2157 | 79aceca5 | bellard | /* fctiwz */
|
2158 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
2159 | 79aceca5 | bellard | /* frsp */
|
2160 | 7c58044c | j_mayer | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
2161 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
2162 | 426613db | j_mayer | /* fcfid */
|
2163 | 7c58044c | j_mayer | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
2164 | 426613db | j_mayer | /* fctid */
|
2165 | 7c58044c | j_mayer | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
2166 | 426613db | j_mayer | /* fctidz */
|
2167 | 7c58044c | j_mayer | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
2168 | 426613db | j_mayer | #endif
|
2169 | 79aceca5 | bellard | |
2170 | d7e4b87e | j_mayer | /* frin */
|
2171 | 7c58044c | j_mayer | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
2172 | d7e4b87e | j_mayer | /* friz */
|
2173 | 7c58044c | j_mayer | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
2174 | d7e4b87e | j_mayer | /* frip */
|
2175 | 7c58044c | j_mayer | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
2176 | d7e4b87e | j_mayer | /* frim */
|
2177 | 7c58044c | j_mayer | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
2178 | d7e4b87e | j_mayer | |
2179 | 79aceca5 | bellard | /*** Floating-Point compare ***/
|
2180 | 99e300ef | Blue Swirl | |
2181 | 54623277 | Blue Swirl | /* fcmpo */
|
2182 | 99e300ef | Blue Swirl | static void gen_fcmpo(DisasContext *ctx) |
2183 | 79aceca5 | bellard | { |
2184 | 330c483b | aurel32 | TCGv_i32 crf; |
2185 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2186 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2187 | 3cc62370 | bellard | return;
|
2188 | 3cc62370 | bellard | } |
2189 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2190 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2191 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2192 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2193 | 9a819377 | aurel32 | gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
2194 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2195 | af12906f | aurel32 | gen_helper_float_check_status(); |
2196 | 79aceca5 | bellard | } |
2197 | 79aceca5 | bellard | |
2198 | 79aceca5 | bellard | /* fcmpu */
|
2199 | 99e300ef | Blue Swirl | static void gen_fcmpu(DisasContext *ctx) |
2200 | 79aceca5 | bellard | { |
2201 | 330c483b | aurel32 | TCGv_i32 crf; |
2202 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2203 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2204 | 3cc62370 | bellard | return;
|
2205 | 3cc62370 | bellard | } |
2206 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2207 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2208 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2209 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2210 | 9a819377 | aurel32 | gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
2211 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2212 | af12906f | aurel32 | gen_helper_float_check_status(); |
2213 | 79aceca5 | bellard | } |
2214 | 79aceca5 | bellard | |
2215 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
2216 | 9a64fbe4 | bellard | /* fabs */
|
2217 | 7c58044c | j_mayer | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
|
2218 | 7c58044c | j_mayer | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); |
2219 | 9a64fbe4 | bellard | |
2220 | 9a64fbe4 | bellard | /* fmr - fmr. */
|
2221 | 7c58044c | j_mayer | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
|
2222 | 99e300ef | Blue Swirl | static void gen_fmr(DisasContext *ctx) |
2223 | 9a64fbe4 | bellard | { |
2224 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2225 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2226 | 3cc62370 | bellard | return;
|
2227 | 3cc62370 | bellard | } |
2228 | af12906f | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2229 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2230 | 9a64fbe4 | bellard | } |
2231 | 9a64fbe4 | bellard | |
2232 | 9a64fbe4 | bellard | /* fnabs */
|
2233 | 7c58044c | j_mayer | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
|
2234 | 7c58044c | j_mayer | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); |
2235 | 9a64fbe4 | bellard | /* fneg */
|
2236 | 7c58044c | j_mayer | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
|
2237 | 7c58044c | j_mayer | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); |
2238 | 9a64fbe4 | bellard | |
2239 | 79aceca5 | bellard | /*** Floating-Point status & ctrl register ***/
|
2240 | 99e300ef | Blue Swirl | |
2241 | 54623277 | Blue Swirl | /* mcrfs */
|
2242 | 99e300ef | Blue Swirl | static void gen_mcrfs(DisasContext *ctx) |
2243 | 79aceca5 | bellard | { |
2244 | 7c58044c | j_mayer | int bfa;
|
2245 | 7c58044c | j_mayer | |
2246 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2247 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2248 | 3cc62370 | bellard | return;
|
2249 | 3cc62370 | bellard | } |
2250 | 7c58044c | j_mayer | bfa = 4 * (7 - crfS(ctx->opcode)); |
2251 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
2252 | e1571908 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
|
2253 | af12906f | aurel32 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
|
2254 | 79aceca5 | bellard | } |
2255 | 79aceca5 | bellard | |
2256 | 79aceca5 | bellard | /* mffs */
|
2257 | 99e300ef | Blue Swirl | static void gen_mffs(DisasContext *ctx) |
2258 | 79aceca5 | bellard | { |
2259 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2260 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2261 | 3cc62370 | bellard | return;
|
2262 | 3cc62370 | bellard | } |
2263 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2264 | af12906f | aurel32 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
2265 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2266 | 79aceca5 | bellard | } |
2267 | 79aceca5 | bellard | |
2268 | 79aceca5 | bellard | /* mtfsb0 */
|
2269 | 99e300ef | Blue Swirl | static void gen_mtfsb0(DisasContext *ctx) |
2270 | 79aceca5 | bellard | { |
2271 | fb0eaffc | bellard | uint8_t crb; |
2272 | 3b46e624 | ths | |
2273 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2274 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2275 | 3cc62370 | bellard | return;
|
2276 | 3cc62370 | bellard | } |
2277 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2278 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2279 | 6e35d524 | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
|
2280 | eb44b959 | aurel32 | TCGv_i32 t0; |
2281 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2282 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2283 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2284 | 6e35d524 | aurel32 | gen_helper_fpscr_clrbit(t0); |
2285 | 6e35d524 | aurel32 | tcg_temp_free_i32(t0); |
2286 | 6e35d524 | aurel32 | } |
2287 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2288 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2289 | 7c58044c | j_mayer | } |
2290 | 79aceca5 | bellard | } |
2291 | 79aceca5 | bellard | |
2292 | 79aceca5 | bellard | /* mtfsb1 */
|
2293 | 99e300ef | Blue Swirl | static void gen_mtfsb1(DisasContext *ctx) |
2294 | 79aceca5 | bellard | { |
2295 | fb0eaffc | bellard | uint8_t crb; |
2296 | 3b46e624 | ths | |
2297 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2298 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2299 | 3cc62370 | bellard | return;
|
2300 | 3cc62370 | bellard | } |
2301 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2302 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2303 | 7c58044c | j_mayer | /* XXX: we pretend we can only do IEEE floating-point computations */
|
2304 | af12906f | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
|
2305 | eb44b959 | aurel32 | TCGv_i32 t0; |
2306 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2307 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2308 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2309 | af12906f | aurel32 | gen_helper_fpscr_setbit(t0); |
2310 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2311 | af12906f | aurel32 | } |
2312 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2313 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2314 | 7c58044c | j_mayer | } |
2315 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2316 | af12906f | aurel32 | gen_helper_float_check_status(); |
2317 | 79aceca5 | bellard | } |
2318 | 79aceca5 | bellard | |
2319 | 79aceca5 | bellard | /* mtfsf */
|
2320 | 99e300ef | Blue Swirl | static void gen_mtfsf(DisasContext *ctx) |
2321 | 79aceca5 | bellard | { |
2322 | 0f2f39c2 | aurel32 | TCGv_i32 t0; |
2323 | 4911012d | blueswir1 | int L = ctx->opcode & 0x02000000; |
2324 | af12906f | aurel32 | |
2325 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2326 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2327 | 3cc62370 | bellard | return;
|
2328 | 3cc62370 | bellard | } |
2329 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2330 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2331 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2332 | 4911012d | blueswir1 | if (L)
|
2333 | 4911012d | blueswir1 | t0 = tcg_const_i32(0xff);
|
2334 | 4911012d | blueswir1 | else
|
2335 | 4911012d | blueswir1 | t0 = tcg_const_i32(FM(ctx->opcode)); |
2336 | af12906f | aurel32 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
2337 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2338 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2339 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2340 | 7c58044c | j_mayer | } |
2341 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2342 | af12906f | aurel32 | gen_helper_float_check_status(); |
2343 | 79aceca5 | bellard | } |
2344 | 79aceca5 | bellard | |
2345 | 79aceca5 | bellard | /* mtfsfi */
|
2346 | 99e300ef | Blue Swirl | static void gen_mtfsfi(DisasContext *ctx) |
2347 | 79aceca5 | bellard | { |
2348 | 7c58044c | j_mayer | int bf, sh;
|
2349 | 0f2f39c2 | aurel32 | TCGv_i64 t0; |
2350 | 0f2f39c2 | aurel32 | TCGv_i32 t1; |
2351 | 7c58044c | j_mayer | |
2352 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2353 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2354 | 3cc62370 | bellard | return;
|
2355 | 3cc62370 | bellard | } |
2356 | 7c58044c | j_mayer | bf = crbD(ctx->opcode) >> 2;
|
2357 | 7c58044c | j_mayer | sh = 7 - bf;
|
2358 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2359 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2360 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2361 | 0f2f39c2 | aurel32 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
|
2362 | af12906f | aurel32 | t1 = tcg_const_i32(1 << sh);
|
2363 | af12906f | aurel32 | gen_helper_store_fpscr(t0, t1); |
2364 | 0f2f39c2 | aurel32 | tcg_temp_free_i64(t0); |
2365 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t1); |
2366 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2367 | e1571908 | aurel32 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
|
2368 | 7c58044c | j_mayer | } |
2369 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2370 | af12906f | aurel32 | gen_helper_float_check_status(); |
2371 | 79aceca5 | bellard | } |
2372 | 79aceca5 | bellard | |
2373 | 76a66253 | j_mayer | /*** Addressing modes ***/
|
2374 | 76a66253 | j_mayer | /* Register indirect with immediate index : EA = (rA|0) + SIMM */
|
2375 | 636aa200 | Blue Swirl | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2376 | 636aa200 | Blue Swirl | target_long maskl) |
2377 | 76a66253 | j_mayer | { |
2378 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
2379 | 76a66253 | j_mayer | |
2380 | be147d08 | j_mayer | simm &= ~maskl; |
2381 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2382 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2383 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2384 | 76db3ba4 | aurel32 | tcg_gen_movi_tl(EA, (uint32_t)simm); |
2385 | 76db3ba4 | aurel32 | } else
|
2386 | 76db3ba4 | aurel32 | #endif
|
2387 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, simm); |
2388 | 76db3ba4 | aurel32 | } else if (likely(simm != 0)) { |
2389 | e2be8d8d | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
2390 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2391 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2392 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2393 | 76db3ba4 | aurel32 | } |
2394 | 76db3ba4 | aurel32 | #endif
|
2395 | 76db3ba4 | aurel32 | } else {
|
2396 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2397 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2398 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2399 | 76db3ba4 | aurel32 | } else
|
2400 | 76db3ba4 | aurel32 | #endif
|
2401 | e2be8d8d | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2402 | 76db3ba4 | aurel32 | } |
2403 | 76a66253 | j_mayer | } |
2404 | 76a66253 | j_mayer | |
2405 | 636aa200 | Blue Swirl | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
2406 | 76a66253 | j_mayer | { |
2407 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2408 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2409 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2410 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2411 | 76db3ba4 | aurel32 | } else
|
2412 | 76db3ba4 | aurel32 | #endif
|
2413 | e2be8d8d | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2414 | 76db3ba4 | aurel32 | } else {
|
2415 | e2be8d8d | aurel32 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
2416 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2417 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2418 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2419 | 76db3ba4 | aurel32 | } |
2420 | 76db3ba4 | aurel32 | #endif
|
2421 | 76db3ba4 | aurel32 | } |
2422 | 76a66253 | j_mayer | } |
2423 | 76a66253 | j_mayer | |
2424 | 636aa200 | Blue Swirl | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
2425 | 76a66253 | j_mayer | { |
2426 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2427 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, 0);
|
2428 | 76db3ba4 | aurel32 | } else {
|
2429 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2430 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2431 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2432 | 76db3ba4 | aurel32 | } else
|
2433 | 76db3ba4 | aurel32 | #endif
|
2434 | 76db3ba4 | aurel32 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2435 | 76db3ba4 | aurel32 | } |
2436 | 76db3ba4 | aurel32 | } |
2437 | 76db3ba4 | aurel32 | |
2438 | 636aa200 | Blue Swirl | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2439 | 636aa200 | Blue Swirl | target_long val) |
2440 | 76db3ba4 | aurel32 | { |
2441 | 76db3ba4 | aurel32 | tcg_gen_addi_tl(ret, arg1, val); |
2442 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2443 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
2444 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(ret, ret); |
2445 | 76db3ba4 | aurel32 | } |
2446 | 76db3ba4 | aurel32 | #endif
|
2447 | 76a66253 | j_mayer | } |
2448 | 76a66253 | j_mayer | |
2449 | 636aa200 | Blue Swirl | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
2450 | cf360a32 | aurel32 | { |
2451 | cf360a32 | aurel32 | int l1 = gen_new_label();
|
2452 | cf360a32 | aurel32 | TCGv t0 = tcg_temp_new(); |
2453 | cf360a32 | aurel32 | TCGv_i32 t1, t2; |
2454 | cf360a32 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2455 | cf360a32 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2456 | cf360a32 | aurel32 | tcg_gen_andi_tl(t0, EA, mask); |
2457 | cf360a32 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
2458 | cf360a32 | aurel32 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); |
2459 | cf360a32 | aurel32 | t2 = tcg_const_i32(0);
|
2460 | cf360a32 | aurel32 | gen_helper_raise_exception_err(t1, t2); |
2461 | cf360a32 | aurel32 | tcg_temp_free_i32(t1); |
2462 | cf360a32 | aurel32 | tcg_temp_free_i32(t2); |
2463 | cf360a32 | aurel32 | gen_set_label(l1); |
2464 | cf360a32 | aurel32 | tcg_temp_free(t0); |
2465 | cf360a32 | aurel32 | } |
2466 | cf360a32 | aurel32 | |
2467 | 7863667f | j_mayer | /*** Integer load ***/
|
2468 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2469 | 76db3ba4 | aurel32 | { |
2470 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); |
2471 | 76db3ba4 | aurel32 | } |
2472 | 76db3ba4 | aurel32 | |
2473 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2474 | 76db3ba4 | aurel32 | { |
2475 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); |
2476 | 76db3ba4 | aurel32 | } |
2477 | 76db3ba4 | aurel32 | |
2478 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2479 | 76db3ba4 | aurel32 | { |
2480 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2481 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2482 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2483 | 76db3ba4 | aurel32 | } |
2484 | b61f2753 | aurel32 | } |
2485 | b61f2753 | aurel32 | |
2486 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2487 | b61f2753 | aurel32 | { |
2488 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2489 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2490 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2491 | 76db3ba4 | aurel32 | tcg_gen_ext16s_tl(arg1, arg1); |
2492 | 76db3ba4 | aurel32 | } else {
|
2493 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); |
2494 | 76db3ba4 | aurel32 | } |
2495 | b61f2753 | aurel32 | } |
2496 | b61f2753 | aurel32 | |
2497 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2498 | b61f2753 | aurel32 | { |
2499 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2500 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2501 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2502 | 76db3ba4 | aurel32 | } |
2503 | b61f2753 | aurel32 | } |
2504 | b61f2753 | aurel32 | |
2505 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
2506 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2507 | b61f2753 | aurel32 | { |
2508 | a457e7ee | blueswir1 | if (unlikely(ctx->le_mode)) {
|
2509 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2510 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2511 | fa3966a3 | aurel32 | tcg_gen_ext32s_tl(arg1, arg1); |
2512 | b61f2753 | aurel32 | } else
|
2513 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
2514 | b61f2753 | aurel32 | } |
2515 | 76db3ba4 | aurel32 | #endif
|
2516 | b61f2753 | aurel32 | |
2517 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2518 | b61f2753 | aurel32 | { |
2519 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2520 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2521 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(arg1, arg1); |
2522 | 76db3ba4 | aurel32 | } |
2523 | b61f2753 | aurel32 | } |
2524 | b61f2753 | aurel32 | |
2525 | 636aa200 | Blue Swirl | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2526 | b61f2753 | aurel32 | { |
2527 | 76db3ba4 | aurel32 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
2528 | b61f2753 | aurel32 | } |
2529 | b61f2753 | aurel32 | |
2530 | 636aa200 | Blue Swirl | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2531 | b61f2753 | aurel32 | { |
2532 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2533 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
2534 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
2535 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
2536 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2537 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2538 | 76db3ba4 | aurel32 | } else {
|
2539 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
2540 | 76db3ba4 | aurel32 | } |
2541 | b61f2753 | aurel32 | } |
2542 | b61f2753 | aurel32 | |
2543 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2544 | b61f2753 | aurel32 | { |
2545 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2546 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
2547 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
2548 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
2549 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2550 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2551 | 76db3ba4 | aurel32 | } else {
|
2552 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
2553 | 76db3ba4 | aurel32 | } |
2554 | b61f2753 | aurel32 | } |
2555 | b61f2753 | aurel32 | |
2556 | 636aa200 | Blue Swirl | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2557 | b61f2753 | aurel32 | { |
2558 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2559 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_temp_new_i64(); |
2560 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(t0, arg1); |
2561 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
2562 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
2563 | b61f2753 | aurel32 | } else
|
2564 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
2565 | b61f2753 | aurel32 | } |
2566 | b61f2753 | aurel32 | |
2567 | 0c8aacd4 | aurel32 | #define GEN_LD(name, ldop, opc, type) \
|
2568 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2569 | 79aceca5 | bellard | { \ |
2570 | 76db3ba4 | aurel32 | TCGv EA; \ |
2571 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2572 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2573 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2574 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2575 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2576 | 79aceca5 | bellard | } |
2577 | 79aceca5 | bellard | |
2578 | 0c8aacd4 | aurel32 | #define GEN_LDU(name, ldop, opc, type) \
|
2579 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
2580 | 79aceca5 | bellard | { \ |
2581 | b61f2753 | aurel32 | TCGv EA; \ |
2582 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2583 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2584 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2585 | 9fddaa0c | bellard | return; \
|
2586 | 9a64fbe4 | bellard | } \ |
2587 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2588 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2589 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2590 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2591 | 9d53c753 | j_mayer | else \
|
2592 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2593 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2594 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2595 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2596 | 79aceca5 | bellard | } |
2597 | 79aceca5 | bellard | |
2598 | 0c8aacd4 | aurel32 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
2599 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2600 | 79aceca5 | bellard | { \ |
2601 | b61f2753 | aurel32 | TCGv EA; \ |
2602 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2603 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2604 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2605 | 9fddaa0c | bellard | return; \
|
2606 | 9a64fbe4 | bellard | } \ |
2607 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2608 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2609 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2610 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2611 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2612 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2613 | 79aceca5 | bellard | } |
2614 | 79aceca5 | bellard | |
2615 | 0c8aacd4 | aurel32 | #define GEN_LDX(name, ldop, opc2, opc3, type) \
|
2616 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2617 | 79aceca5 | bellard | { \ |
2618 | 76db3ba4 | aurel32 | TCGv EA; \ |
2619 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2620 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2621 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2622 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2623 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2624 | 79aceca5 | bellard | } |
2625 | 79aceca5 | bellard | |
2626 | 0c8aacd4 | aurel32 | #define GEN_LDS(name, ldop, op, type) \
|
2627 | 0c8aacd4 | aurel32 | GEN_LD(name, ldop, op | 0x20, type); \
|
2628 | 0c8aacd4 | aurel32 | GEN_LDU(name, ldop, op | 0x21, type); \
|
2629 | 0c8aacd4 | aurel32 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ |
2630 | 0c8aacd4 | aurel32 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
2631 | 79aceca5 | bellard | |
2632 | 79aceca5 | bellard | /* lbz lbzu lbzux lbzx */
|
2633 | 0c8aacd4 | aurel32 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
|
2634 | 79aceca5 | bellard | /* lha lhau lhaux lhax */
|
2635 | 0c8aacd4 | aurel32 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
|
2636 | 79aceca5 | bellard | /* lhz lhzu lhzux lhzx */
|
2637 | 0c8aacd4 | aurel32 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
|
2638 | 79aceca5 | bellard | /* lwz lwzu lwzux lwzx */
|
2639 | 0c8aacd4 | aurel32 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
|
2640 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2641 | d9bce9d9 | j_mayer | /* lwaux */
|
2642 | 0c8aacd4 | aurel32 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
2643 | d9bce9d9 | j_mayer | /* lwax */
|
2644 | 0c8aacd4 | aurel32 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
2645 | d9bce9d9 | j_mayer | /* ldux */
|
2646 | 0c8aacd4 | aurel32 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
2647 | d9bce9d9 | j_mayer | /* ldx */
|
2648 | 0c8aacd4 | aurel32 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
2649 | 99e300ef | Blue Swirl | |
2650 | 99e300ef | Blue Swirl | static void gen_ld(DisasContext *ctx) |
2651 | d9bce9d9 | j_mayer | { |
2652 | b61f2753 | aurel32 | TCGv EA; |
2653 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode)) {
|
2654 | d9bce9d9 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || |
2655 | d9bce9d9 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { |
2656 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2657 | d9bce9d9 | j_mayer | return;
|
2658 | d9bce9d9 | j_mayer | } |
2659 | d9bce9d9 | j_mayer | } |
2660 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2661 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2662 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2663 | d9bce9d9 | j_mayer | if (ctx->opcode & 0x02) { |
2664 | d9bce9d9 | j_mayer | /* lwa (lwau is undefined) */
|
2665 | 76db3ba4 | aurel32 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2666 | d9bce9d9 | j_mayer | } else {
|
2667 | d9bce9d9 | j_mayer | /* ld - ldu */
|
2668 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2669 | d9bce9d9 | j_mayer | } |
2670 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode))
|
2671 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2672 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2673 | d9bce9d9 | j_mayer | } |
2674 | 99e300ef | Blue Swirl | |
2675 | 54623277 | Blue Swirl | /* lq */
|
2676 | 99e300ef | Blue Swirl | static void gen_lq(DisasContext *ctx) |
2677 | be147d08 | j_mayer | { |
2678 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2679 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2680 | be147d08 | j_mayer | #else
|
2681 | be147d08 | j_mayer | int ra, rd;
|
2682 | b61f2753 | aurel32 | TCGv EA; |
2683 | be147d08 | j_mayer | |
2684 | be147d08 | j_mayer | /* Restore CPU state */
|
2685 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2686 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2687 | be147d08 | j_mayer | return;
|
2688 | be147d08 | j_mayer | } |
2689 | be147d08 | j_mayer | ra = rA(ctx->opcode); |
2690 | be147d08 | j_mayer | rd = rD(ctx->opcode); |
2691 | be147d08 | j_mayer | if (unlikely((rd & 1) || rd == ra)) { |
2692 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2693 | be147d08 | j_mayer | return;
|
2694 | be147d08 | j_mayer | } |
2695 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2696 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2697 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2698 | be147d08 | j_mayer | return;
|
2699 | be147d08 | j_mayer | } |
2700 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2701 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2702 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x0F);
|
2703 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); |
2704 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2705 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
|
2706 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2707 | be147d08 | j_mayer | #endif
|
2708 | be147d08 | j_mayer | } |
2709 | d9bce9d9 | j_mayer | #endif
|
2710 | 79aceca5 | bellard | |
2711 | 79aceca5 | bellard | /*** Integer store ***/
|
2712 | 0c8aacd4 | aurel32 | #define GEN_ST(name, stop, opc, type) \
|
2713 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2714 | 79aceca5 | bellard | { \ |
2715 | 76db3ba4 | aurel32 | TCGv EA; \ |
2716 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2717 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2718 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2719 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2720 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2721 | 79aceca5 | bellard | } |
2722 | 79aceca5 | bellard | |
2723 | 0c8aacd4 | aurel32 | #define GEN_STU(name, stop, opc, type) \
|
2724 | 99e300ef | Blue Swirl | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
2725 | 79aceca5 | bellard | { \ |
2726 | b61f2753 | aurel32 | TCGv EA; \ |
2727 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2728 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2729 | 9fddaa0c | bellard | return; \
|
2730 | 9a64fbe4 | bellard | } \ |
2731 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2732 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2733 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2734 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2735 | 9d53c753 | j_mayer | else \
|
2736 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2737 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2738 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2739 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2740 | 79aceca5 | bellard | } |
2741 | 79aceca5 | bellard | |
2742 | 0c8aacd4 | aurel32 | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
2743 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2744 | 79aceca5 | bellard | { \ |
2745 | b61f2753 | aurel32 | TCGv EA; \ |
2746 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2747 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2748 | 9fddaa0c | bellard | return; \
|
2749 | 9a64fbe4 | bellard | } \ |
2750 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2751 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2752 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2753 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2754 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2755 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2756 | 79aceca5 | bellard | } |
2757 | 79aceca5 | bellard | |
2758 | 0c8aacd4 | aurel32 | #define GEN_STX(name, stop, opc2, opc3, type) \
|
2759 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2760 | 79aceca5 | bellard | { \ |
2761 | 76db3ba4 | aurel32 | TCGv EA; \ |
2762 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2763 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2764 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2765 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2766 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2767 | 79aceca5 | bellard | } |
2768 | 79aceca5 | bellard | |
2769 | 0c8aacd4 | aurel32 | #define GEN_STS(name, stop, op, type) \
|
2770 | 0c8aacd4 | aurel32 | GEN_ST(name, stop, op | 0x20, type); \
|
2771 | 0c8aacd4 | aurel32 | GEN_STU(name, stop, op | 0x21, type); \
|
2772 | 0c8aacd4 | aurel32 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ |
2773 | 0c8aacd4 | aurel32 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
2774 | 79aceca5 | bellard | |
2775 | 79aceca5 | bellard | /* stb stbu stbux stbx */
|
2776 | 0c8aacd4 | aurel32 | GEN_STS(stb, st8, 0x06, PPC_INTEGER);
|
2777 | 79aceca5 | bellard | /* sth sthu sthux sthx */
|
2778 | 0c8aacd4 | aurel32 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
|
2779 | 79aceca5 | bellard | /* stw stwu stwux stwx */
|
2780 | 0c8aacd4 | aurel32 | GEN_STS(stw, st32, 0x04, PPC_INTEGER);
|
2781 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2782 | 0c8aacd4 | aurel32 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2783 | 0c8aacd4 | aurel32 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); |
2784 | 99e300ef | Blue Swirl | |
2785 | 99e300ef | Blue Swirl | static void gen_std(DisasContext *ctx) |
2786 | d9bce9d9 | j_mayer | { |
2787 | be147d08 | j_mayer | int rs;
|
2788 | b61f2753 | aurel32 | TCGv EA; |
2789 | be147d08 | j_mayer | |
2790 | be147d08 | j_mayer | rs = rS(ctx->opcode); |
2791 | be147d08 | j_mayer | if ((ctx->opcode & 0x3) == 0x2) { |
2792 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2793 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2794 | be147d08 | j_mayer | #else
|
2795 | be147d08 | j_mayer | /* stq */
|
2796 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2797 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2798 | be147d08 | j_mayer | return;
|
2799 | be147d08 | j_mayer | } |
2800 | be147d08 | j_mayer | if (unlikely(rs & 1)) { |
2801 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2802 | d9bce9d9 | j_mayer | return;
|
2803 | d9bce9d9 | j_mayer | } |
2804 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2805 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2806 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2807 | be147d08 | j_mayer | return;
|
2808 | be147d08 | j_mayer | } |
2809 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2810 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2811 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2812 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2813 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2814 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
|
2815 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2816 | be147d08 | j_mayer | #endif
|
2817 | be147d08 | j_mayer | } else {
|
2818 | be147d08 | j_mayer | /* std / stdu */
|
2819 | be147d08 | j_mayer | if (Rc(ctx->opcode)) {
|
2820 | be147d08 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { |
2821 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2822 | be147d08 | j_mayer | return;
|
2823 | be147d08 | j_mayer | } |
2824 | be147d08 | j_mayer | } |
2825 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2826 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2827 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2828 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2829 | be147d08 | j_mayer | if (Rc(ctx->opcode))
|
2830 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2831 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2832 | d9bce9d9 | j_mayer | } |
2833 | d9bce9d9 | j_mayer | } |
2834 | d9bce9d9 | j_mayer | #endif
|
2835 | 79aceca5 | bellard | /*** Integer load and store with byte reverse ***/
|
2836 | 79aceca5 | bellard | /* lhbrx */
|
2837 | 86178a57 | Juan Quintela | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2838 | b61f2753 | aurel32 | { |
2839 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2840 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2841 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2842 | 76db3ba4 | aurel32 | } |
2843 | b61f2753 | aurel32 | } |
2844 | 0c8aacd4 | aurel32 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
2845 | b61f2753 | aurel32 | |
2846 | 79aceca5 | bellard | /* lwbrx */
|
2847 | 86178a57 | Juan Quintela | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2848 | b61f2753 | aurel32 | { |
2849 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2850 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2851 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2852 | 76db3ba4 | aurel32 | } |
2853 | b61f2753 | aurel32 | } |
2854 | 0c8aacd4 | aurel32 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
2855 | b61f2753 | aurel32 | |
2856 | 79aceca5 | bellard | /* sthbrx */
|
2857 | 86178a57 | Juan Quintela | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2858 | b61f2753 | aurel32 | { |
2859 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2860 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
2861 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
2862 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
2863 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2864 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2865 | 76db3ba4 | aurel32 | } else {
|
2866 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
2867 | 76db3ba4 | aurel32 | } |
2868 | b61f2753 | aurel32 | } |
2869 | 0c8aacd4 | aurel32 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
2870 | b61f2753 | aurel32 | |
2871 | 79aceca5 | bellard | /* stwbrx */
|
2872 | 86178a57 | Juan Quintela | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2873 | b61f2753 | aurel32 | { |
2874 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2875 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
2876 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
2877 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
2878 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2879 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2880 | 76db3ba4 | aurel32 | } else {
|
2881 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
2882 | 76db3ba4 | aurel32 | } |
2883 | b61f2753 | aurel32 | } |
2884 | 0c8aacd4 | aurel32 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
2885 | 79aceca5 | bellard | |
2886 | 79aceca5 | bellard | /*** Integer load and store multiple ***/
|
2887 | 99e300ef | Blue Swirl | |
2888 | 54623277 | Blue Swirl | /* lmw */
|
2889 | 99e300ef | Blue Swirl | static void gen_lmw(DisasContext *ctx) |
2890 | 79aceca5 | bellard | { |
2891 | 76db3ba4 | aurel32 | TCGv t0; |
2892 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
2893 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2894 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2895 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2896 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2897 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
2898 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
2899 | ff4a62cd | aurel32 | gen_helper_lmw(t0, t1); |
2900 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
2901 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
2902 | 79aceca5 | bellard | } |
2903 | 79aceca5 | bellard | |
2904 | 79aceca5 | bellard | /* stmw */
|
2905 | 99e300ef | Blue Swirl | static void gen_stmw(DisasContext *ctx) |
2906 | 79aceca5 | bellard | { |
2907 | 76db3ba4 | aurel32 | TCGv t0; |
2908 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
2909 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2910 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2911 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2912 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2913 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rS(ctx->opcode)); |
2914 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
2915 | ff4a62cd | aurel32 | gen_helper_stmw(t0, t1); |
2916 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
2917 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
2918 | 79aceca5 | bellard | } |
2919 | 79aceca5 | bellard | |
2920 | 79aceca5 | bellard | /*** Integer load and store strings ***/
|
2921 | 54623277 | Blue Swirl | |
2922 | 79aceca5 | bellard | /* lswi */
|
2923 | 3fc6c082 | bellard | /* PowerPC32 specification says we must generate an exception if
|
2924 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
|
2925 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
|
2926 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
|
2927 | 9a64fbe4 | bellard | */
|
2928 | 99e300ef | Blue Swirl | static void gen_lswi(DisasContext *ctx) |
2929 | 79aceca5 | bellard | { |
2930 | dfbc799d | aurel32 | TCGv t0; |
2931 | dfbc799d | aurel32 | TCGv_i32 t1, t2; |
2932 | 79aceca5 | bellard | int nb = NB(ctx->opcode);
|
2933 | 79aceca5 | bellard | int start = rD(ctx->opcode);
|
2934 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
2935 | 79aceca5 | bellard | int nr;
|
2936 | 79aceca5 | bellard | |
2937 | 79aceca5 | bellard | if (nb == 0) |
2938 | 79aceca5 | bellard | nb = 32;
|
2939 | 79aceca5 | bellard | nr = nb / 4;
|
2940 | 76a66253 | j_mayer | if (unlikely(((start + nr) > 32 && |
2941 | 76a66253 | j_mayer | start <= ra && (start + nr - 32) > ra) ||
|
2942 | 76a66253 | j_mayer | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
|
2943 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
2944 | 9fddaa0c | bellard | return;
|
2945 | 297d8e62 | bellard | } |
2946 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2947 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
2948 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2949 | dfbc799d | aurel32 | t0 = tcg_temp_new(); |
2950 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
2951 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
2952 | dfbc799d | aurel32 | t2 = tcg_const_i32(start); |
2953 | dfbc799d | aurel32 | gen_helper_lsw(t0, t1, t2); |
2954 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2955 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2956 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2957 | 79aceca5 | bellard | } |
2958 | 79aceca5 | bellard | |
2959 | 79aceca5 | bellard | /* lswx */
|
2960 | 99e300ef | Blue Swirl | static void gen_lswx(DisasContext *ctx) |
2961 | 79aceca5 | bellard | { |
2962 | 76db3ba4 | aurel32 | TCGv t0; |
2963 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2, t3; |
2964 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2965 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2966 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2967 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2968 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
2969 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
2970 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rA(ctx->opcode)); |
2971 | 76db3ba4 | aurel32 | t3 = tcg_const_i32(rB(ctx->opcode)); |
2972 | dfbc799d | aurel32 | gen_helper_lswx(t0, t1, t2, t3); |
2973 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2974 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2975 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2976 | dfbc799d | aurel32 | tcg_temp_free_i32(t3); |
2977 | 79aceca5 | bellard | } |
2978 | 79aceca5 | bellard | |
2979 | 79aceca5 | bellard | /* stswi */
|
2980 | 99e300ef | Blue Swirl | static void gen_stswi(DisasContext *ctx) |
2981 | 79aceca5 | bellard | { |
2982 | 76db3ba4 | aurel32 | TCGv t0; |
2983 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
2984 | 4b3686fa | bellard | int nb = NB(ctx->opcode);
|
2985 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2986 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
2987 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
2988 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
2989 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
2990 | 4b3686fa | bellard | if (nb == 0) |
2991 | 4b3686fa | bellard | nb = 32;
|
2992 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
2993 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2994 | dfbc799d | aurel32 | gen_helper_stsw(t0, t1, t2); |
2995 | dfbc799d | aurel32 | tcg_temp_free(t0); |
2996 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
2997 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
2998 | 79aceca5 | bellard | } |
2999 | 79aceca5 | bellard | |
3000 | 79aceca5 | bellard | /* stswx */
|
3001 | 99e300ef | Blue Swirl | static void gen_stswx(DisasContext *ctx) |
3002 | 79aceca5 | bellard | { |
3003 | 76db3ba4 | aurel32 | TCGv t0; |
3004 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
3005 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
3006 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
3007 | 5fafdf24 | ths | gen_update_nip(ctx, ctx->nip - 4);
|
3008 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3009 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3010 | 76db3ba4 | aurel32 | t1 = tcg_temp_new_i32(); |
3011 | dfbc799d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3012 | dfbc799d | aurel32 | tcg_gen_andi_i32(t1, t1, 0x7F);
|
3013 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
3014 | dfbc799d | aurel32 | gen_helper_stsw(t0, t1, t2); |
3015 | dfbc799d | aurel32 | tcg_temp_free(t0); |
3016 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
3017 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
3018 | 79aceca5 | bellard | } |
3019 | 79aceca5 | bellard | |
3020 | 79aceca5 | bellard | /*** Memory synchronisation ***/
|
3021 | 79aceca5 | bellard | /* eieio */
|
3022 | 99e300ef | Blue Swirl | static void gen_eieio(DisasContext *ctx) |
3023 | 79aceca5 | bellard | { |
3024 | 79aceca5 | bellard | } |
3025 | 79aceca5 | bellard | |
3026 | 79aceca5 | bellard | /* isync */
|
3027 | 99e300ef | Blue Swirl | static void gen_isync(DisasContext *ctx) |
3028 | 79aceca5 | bellard | { |
3029 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3030 | 79aceca5 | bellard | } |
3031 | 79aceca5 | bellard | |
3032 | 111bfab3 | bellard | /* lwarx */
|
3033 | 99e300ef | Blue Swirl | static void gen_lwarx(DisasContext *ctx) |
3034 | 79aceca5 | bellard | { |
3035 | 76db3ba4 | aurel32 | TCGv t0; |
3036 | 18b21a2f | Nathan Froyd | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
3037 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3038 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3039 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3040 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
3041 | 18b21a2f | Nathan Froyd | gen_qemu_ld32u(ctx, gpr, t0); |
3042 | cf360a32 | aurel32 | tcg_gen_mov_tl(cpu_reserve, t0); |
3043 | 18b21a2f | Nathan Froyd | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
3044 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3045 | 79aceca5 | bellard | } |
3046 | 79aceca5 | bellard | |
3047 | 4425265b | Nathan Froyd | #if defined(CONFIG_USER_ONLY)
|
3048 | 4425265b | Nathan Froyd | static void gen_conditional_store (DisasContext *ctx, TCGv EA, |
3049 | 4425265b | Nathan Froyd | int reg, int size) |
3050 | 4425265b | Nathan Froyd | { |
3051 | 4425265b | Nathan Froyd | TCGv t0 = tcg_temp_new(); |
3052 | 4425265b | Nathan Froyd | uint32_t save_exception = ctx->exception; |
3053 | 4425265b | Nathan Froyd | |
3054 | 4425265b | Nathan Froyd | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea)); |
3055 | 4425265b | Nathan Froyd | tcg_gen_movi_tl(t0, (size << 5) | reg);
|
3056 | 4425265b | Nathan Froyd | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info)); |
3057 | 4425265b | Nathan Froyd | tcg_temp_free(t0); |
3058 | 4425265b | Nathan Froyd | gen_update_nip(ctx, ctx->nip-4);
|
3059 | 4425265b | Nathan Froyd | ctx->exception = POWERPC_EXCP_BRANCH; |
3060 | 4425265b | Nathan Froyd | gen_exception(ctx, POWERPC_EXCP_STCX); |
3061 | 4425265b | Nathan Froyd | ctx->exception = save_exception; |
3062 | 4425265b | Nathan Froyd | } |
3063 | 4425265b | Nathan Froyd | #endif
|
3064 | 4425265b | Nathan Froyd | |
3065 | 79aceca5 | bellard | /* stwcx. */
|
3066 | e8eaa2c0 | Blue Swirl | static void gen_stwcx_(DisasContext *ctx) |
3067 | 79aceca5 | bellard | { |
3068 | 76db3ba4 | aurel32 | TCGv t0; |
3069 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3070 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3071 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3072 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
3073 | 4425265b | Nathan Froyd | #if defined(CONFIG_USER_ONLY)
|
3074 | 4425265b | Nathan Froyd | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
|
3075 | 4425265b | Nathan Froyd | #else
|
3076 | 4425265b | Nathan Froyd | { |
3077 | 4425265b | Nathan Froyd | int l1;
|
3078 | 4425265b | Nathan Froyd | |
3079 | 4425265b | Nathan Froyd | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
3080 | 4425265b | Nathan Froyd | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
3081 | 4425265b | Nathan Froyd | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
3082 | 4425265b | Nathan Froyd | l1 = gen_new_label(); |
3083 | 4425265b | Nathan Froyd | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3084 | 4425265b | Nathan Froyd | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
3085 | 4425265b | Nathan Froyd | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
3086 | 4425265b | Nathan Froyd | gen_set_label(l1); |
3087 | 4425265b | Nathan Froyd | tcg_gen_movi_tl(cpu_reserve, -1);
|
3088 | 4425265b | Nathan Froyd | } |
3089 | 4425265b | Nathan Froyd | #endif
|
3090 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3091 | 79aceca5 | bellard | } |
3092 | 79aceca5 | bellard | |
3093 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3094 | 426613db | j_mayer | /* ldarx */
|
3095 | 99e300ef | Blue Swirl | static void gen_ldarx(DisasContext *ctx) |
3096 | 426613db | j_mayer | { |
3097 | 76db3ba4 | aurel32 | TCGv t0; |
3098 | 18b21a2f | Nathan Froyd | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
3099 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3100 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3101 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3102 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x07);
|
3103 | 18b21a2f | Nathan Froyd | gen_qemu_ld64(ctx, gpr, t0); |
3104 | cf360a32 | aurel32 | tcg_gen_mov_tl(cpu_reserve, t0); |
3105 | 18b21a2f | Nathan Froyd | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
3106 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3107 | 426613db | j_mayer | } |
3108 | 426613db | j_mayer | |
3109 | 426613db | j_mayer | /* stdcx. */
|
3110 | e8eaa2c0 | Blue Swirl | static void gen_stdcx_(DisasContext *ctx) |
3111 | 426613db | j_mayer | { |
3112 | 76db3ba4 | aurel32 | TCGv t0; |
3113 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_RES); |
3114 | 76db3ba4 | aurel32 | t0 = tcg_temp_local_new(); |
3115 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3116 | cf360a32 | aurel32 | gen_check_align(ctx, t0, 0x07);
|
3117 | 4425265b | Nathan Froyd | #if defined(CONFIG_USER_ONLY)
|
3118 | 4425265b | Nathan Froyd | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
|
3119 | 4425265b | Nathan Froyd | #else
|
3120 | 4425265b | Nathan Froyd | { |
3121 | 4425265b | Nathan Froyd | int l1;
|
3122 | 4425265b | Nathan Froyd | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
3123 | 4425265b | Nathan Froyd | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
3124 | 4425265b | Nathan Froyd | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
3125 | 4425265b | Nathan Froyd | l1 = gen_new_label(); |
3126 | 4425265b | Nathan Froyd | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3127 | 4425265b | Nathan Froyd | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
3128 | 4425265b | Nathan Froyd | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
3129 | 4425265b | Nathan Froyd | gen_set_label(l1); |
3130 | 4425265b | Nathan Froyd | tcg_gen_movi_tl(cpu_reserve, -1);
|
3131 | 4425265b | Nathan Froyd | } |
3132 | 4425265b | Nathan Froyd | #endif
|
3133 | cf360a32 | aurel32 | tcg_temp_free(t0); |
3134 | 426613db | j_mayer | } |
3135 | 426613db | j_mayer | #endif /* defined(TARGET_PPC64) */ |
3136 | 426613db | j_mayer | |
3137 | 79aceca5 | bellard | /* sync */
|
3138 | 99e300ef | Blue Swirl | static void gen_sync(DisasContext *ctx) |
3139 | 79aceca5 | bellard | { |
3140 | 79aceca5 | bellard | } |
3141 | 79aceca5 | bellard | |
3142 | 0db1b20e | j_mayer | /* wait */
|
3143 | 99e300ef | Blue Swirl | static void gen_wait(DisasContext *ctx) |
3144 | 0db1b20e | j_mayer | { |
3145 | 931ff272 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3146 | 931ff272 | aurel32 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); |
3147 | 931ff272 | aurel32 | tcg_temp_free_i32(t0); |
3148 | 0db1b20e | j_mayer | /* Stop translation, as the CPU is supposed to sleep from now */
|
3149 | e06fcd75 | aurel32 | gen_exception_err(ctx, EXCP_HLT, 1);
|
3150 | 0db1b20e | j_mayer | } |
3151 | 0db1b20e | j_mayer | |
3152 | 79aceca5 | bellard | /*** Floating-point load ***/
|
3153 | a0d7d5a7 | aurel32 | #define GEN_LDF(name, ldop, opc, type) \
|
3154 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3155 | 79aceca5 | bellard | { \ |
3156 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3157 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3158 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3159 | 4ecc3190 | bellard | return; \
|
3160 | 4ecc3190 | bellard | } \ |
3161 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3162 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3163 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3164 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3165 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3166 | 79aceca5 | bellard | } |
3167 | 79aceca5 | bellard | |
3168 | a0d7d5a7 | aurel32 | #define GEN_LDUF(name, ldop, opc, type) \
|
3169 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3170 | 79aceca5 | bellard | { \ |
3171 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3172 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3173 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3174 | 4ecc3190 | bellard | return; \
|
3175 | 4ecc3190 | bellard | } \ |
3176 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3177 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3178 | 9fddaa0c | bellard | return; \
|
3179 | 9a64fbe4 | bellard | } \ |
3180 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3181 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3182 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3183 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3184 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3185 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3186 | 79aceca5 | bellard | } |
3187 | 79aceca5 | bellard | |
3188 | a0d7d5a7 | aurel32 | #define GEN_LDUXF(name, ldop, opc, type) \
|
3189 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3190 | 79aceca5 | bellard | { \ |
3191 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3192 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3193 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3194 | 4ecc3190 | bellard | return; \
|
3195 | 4ecc3190 | bellard | } \ |
3196 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3197 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3198 | 9fddaa0c | bellard | return; \
|
3199 | 9a64fbe4 | bellard | } \ |
3200 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3201 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3202 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3203 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3204 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3205 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3206 | 79aceca5 | bellard | } |
3207 | 79aceca5 | bellard | |
3208 | a0d7d5a7 | aurel32 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
3209 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3210 | 79aceca5 | bellard | { \ |
3211 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3212 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3213 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3214 | 4ecc3190 | bellard | return; \
|
3215 | 4ecc3190 | bellard | } \ |
3216 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3217 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3218 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3219 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3220 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3221 | 79aceca5 | bellard | } |
3222 | 79aceca5 | bellard | |
3223 | a0d7d5a7 | aurel32 | #define GEN_LDFS(name, ldop, op, type) \
|
3224 | a0d7d5a7 | aurel32 | GEN_LDF(name, ldop, op | 0x20, type); \
|
3225 | a0d7d5a7 | aurel32 | GEN_LDUF(name, ldop, op | 0x21, type); \
|
3226 | a0d7d5a7 | aurel32 | GEN_LDUXF(name, ldop, op | 0x01, type); \
|
3227 | a0d7d5a7 | aurel32 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
3228 | a0d7d5a7 | aurel32 | |
3229 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3230 | a0d7d5a7 | aurel32 | { |
3231 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3232 | a0d7d5a7 | aurel32 | TCGv_i32 t1 = tcg_temp_new_i32(); |
3233 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, arg2); |
3234 | a0d7d5a7 | aurel32 | tcg_gen_trunc_tl_i32(t1, t0); |
3235 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3236 | a0d7d5a7 | aurel32 | gen_helper_float32_to_float64(arg1, t1); |
3237 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t1); |
3238 | a0d7d5a7 | aurel32 | } |
3239 | 79aceca5 | bellard | |
3240 | a0d7d5a7 | aurel32 | /* lfd lfdu lfdux lfdx */
|
3241 | a0d7d5a7 | aurel32 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
|
3242 | a0d7d5a7 | aurel32 | /* lfs lfsu lfsux lfsx */
|
3243 | a0d7d5a7 | aurel32 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
|
3244 | 79aceca5 | bellard | |
3245 | 79aceca5 | bellard | /*** Floating-point store ***/
|
3246 | a0d7d5a7 | aurel32 | #define GEN_STF(name, stop, opc, type) \
|
3247 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3248 | 79aceca5 | bellard | { \ |
3249 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3250 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3251 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3252 | 4ecc3190 | bellard | return; \
|
3253 | 4ecc3190 | bellard | } \ |
3254 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3255 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3256 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3257 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3258 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3259 | 79aceca5 | bellard | } |
3260 | 79aceca5 | bellard | |
3261 | a0d7d5a7 | aurel32 | #define GEN_STUF(name, stop, opc, type) \
|
3262 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3263 | 79aceca5 | bellard | { \ |
3264 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3265 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3266 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3267 | 4ecc3190 | bellard | return; \
|
3268 | 4ecc3190 | bellard | } \ |
3269 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3270 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3271 | 9fddaa0c | bellard | return; \
|
3272 | 9a64fbe4 | bellard | } \ |
3273 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3274 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3275 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3276 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3277 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3278 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3279 | 79aceca5 | bellard | } |
3280 | 79aceca5 | bellard | |
3281 | a0d7d5a7 | aurel32 | #define GEN_STUXF(name, stop, opc, type) \
|
3282 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3283 | 79aceca5 | bellard | { \ |
3284 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3285 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3286 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3287 | 4ecc3190 | bellard | return; \
|
3288 | 4ecc3190 | bellard | } \ |
3289 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3290 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3291 | 9fddaa0c | bellard | return; \
|
3292 | 9a64fbe4 | bellard | } \ |
3293 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3294 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3295 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3296 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3297 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3298 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3299 | 79aceca5 | bellard | } |
3300 | 79aceca5 | bellard | |
3301 | a0d7d5a7 | aurel32 | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
3302 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3303 | 79aceca5 | bellard | { \ |
3304 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3305 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3306 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3307 | 4ecc3190 | bellard | return; \
|
3308 | 4ecc3190 | bellard | } \ |
3309 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3310 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3311 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3312 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3313 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3314 | 79aceca5 | bellard | } |
3315 | 79aceca5 | bellard | |
3316 | a0d7d5a7 | aurel32 | #define GEN_STFS(name, stop, op, type) \
|
3317 | a0d7d5a7 | aurel32 | GEN_STF(name, stop, op | 0x20, type); \
|
3318 | a0d7d5a7 | aurel32 | GEN_STUF(name, stop, op | 0x21, type); \
|
3319 | a0d7d5a7 | aurel32 | GEN_STUXF(name, stop, op | 0x01, type); \
|
3320 | a0d7d5a7 | aurel32 | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
3321 | a0d7d5a7 | aurel32 | |
3322 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3323 | a0d7d5a7 | aurel32 | { |
3324 | a0d7d5a7 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3325 | a0d7d5a7 | aurel32 | TCGv t1 = tcg_temp_new(); |
3326 | a0d7d5a7 | aurel32 | gen_helper_float64_to_float32(t0, arg1); |
3327 | a0d7d5a7 | aurel32 | tcg_gen_extu_i32_tl(t1, t0); |
3328 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t0); |
3329 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t1, arg2); |
3330 | a0d7d5a7 | aurel32 | tcg_temp_free(t1); |
3331 | a0d7d5a7 | aurel32 | } |
3332 | 79aceca5 | bellard | |
3333 | 79aceca5 | bellard | /* stfd stfdu stfdux stfdx */
|
3334 | a0d7d5a7 | aurel32 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
|
3335 | 79aceca5 | bellard | /* stfs stfsu stfsux stfsx */
|
3336 | a0d7d5a7 | aurel32 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
|
3337 | 79aceca5 | bellard | |
3338 | 79aceca5 | bellard | /* Optional: */
|
3339 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3340 | a0d7d5a7 | aurel32 | { |
3341 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3342 | a0d7d5a7 | aurel32 | tcg_gen_trunc_i64_tl(t0, arg1), |
3343 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, arg2); |
3344 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3345 | a0d7d5a7 | aurel32 | } |
3346 | 79aceca5 | bellard | /* stfiwx */
|
3347 | a0d7d5a7 | aurel32 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
3348 | 79aceca5 | bellard | |
3349 | 79aceca5 | bellard | /*** Branch ***/
|
3350 | 636aa200 | Blue Swirl | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
3351 | c1942362 | bellard | { |
3352 | c1942362 | bellard | TranslationBlock *tb; |
3353 | c1942362 | bellard | tb = ctx->tb; |
3354 | a2ffb812 | aurel32 | #if defined(TARGET_PPC64)
|
3355 | a2ffb812 | aurel32 | if (!ctx->sf_mode)
|
3356 | a2ffb812 | aurel32 | dest = (uint32_t) dest; |
3357 | a2ffb812 | aurel32 | #endif
|
3358 | 57fec1fe | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
3359 | 8cbcb4fa | aurel32 | likely(!ctx->singlestep_enabled)) { |
3360 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
3361 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3362 | 4b4a72e5 | Stefan Weil | tcg_gen_exit_tb((tcg_target_long)tb + n); |
3363 | c1942362 | bellard | } else {
|
3364 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3365 | 8cbcb4fa | aurel32 | if (unlikely(ctx->singlestep_enabled)) {
|
3366 | 8cbcb4fa | aurel32 | if ((ctx->singlestep_enabled &
|
3367 | bdc4e053 | aurel32 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
3368 | 8cbcb4fa | aurel32 | ctx->exception == POWERPC_EXCP_BRANCH) { |
3369 | 8cbcb4fa | aurel32 | target_ulong tmp = ctx->nip; |
3370 | 8cbcb4fa | aurel32 | ctx->nip = dest; |
3371 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
3372 | 8cbcb4fa | aurel32 | ctx->nip = tmp; |
3373 | 8cbcb4fa | aurel32 | } |
3374 | 8cbcb4fa | aurel32 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
3375 | e06fcd75 | aurel32 | gen_debug_exception(ctx); |
3376 | 8cbcb4fa | aurel32 | } |
3377 | 8cbcb4fa | aurel32 | } |
3378 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3379 | c1942362 | bellard | } |
3380 | c53be334 | bellard | } |
3381 | c53be334 | bellard | |
3382 | 636aa200 | Blue Swirl | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
3383 | e1833e1f | j_mayer | { |
3384 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
3385 | a2ffb812 | aurel32 | if (ctx->sf_mode == 0) |
3386 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); |
3387 | e1833e1f | j_mayer | else
|
3388 | e1833e1f | j_mayer | #endif
|
3389 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_lr, nip); |
3390 | e1833e1f | j_mayer | } |
3391 | e1833e1f | j_mayer | |
3392 | 79aceca5 | bellard | /* b ba bl bla */
|
3393 | 99e300ef | Blue Swirl | static void gen_b(DisasContext *ctx) |
3394 | 79aceca5 | bellard | { |
3395 | 76a66253 | j_mayer | target_ulong li, target; |
3396 | 38a64f9d | bellard | |
3397 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3398 | 38a64f9d | bellard | /* sign extend LI */
|
3399 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
3400 | d9bce9d9 | j_mayer | if (ctx->sf_mode)
|
3401 | d9bce9d9 | j_mayer | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; |
3402 | d9bce9d9 | j_mayer | else
|
3403 | 76a66253 | j_mayer | #endif
|
3404 | d9bce9d9 | j_mayer | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
3405 | 76a66253 | j_mayer | if (likely(AA(ctx->opcode) == 0)) |
3406 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
3407 | 79aceca5 | bellard | else
|
3408 | 9a64fbe4 | bellard | target = li; |
3409 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
3410 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3411 | c1942362 | bellard | gen_goto_tb(ctx, 0, target);
|
3412 | 79aceca5 | bellard | } |
3413 | 79aceca5 | bellard | |
3414 | e98a6e40 | bellard | #define BCOND_IM 0 |
3415 | e98a6e40 | bellard | #define BCOND_LR 1 |
3416 | e98a6e40 | bellard | #define BCOND_CTR 2 |
3417 | e98a6e40 | bellard | |
3418 | 636aa200 | Blue Swirl | static inline void gen_bcond(DisasContext *ctx, int type) |
3419 | d9bce9d9 | j_mayer | { |
3420 | d9bce9d9 | j_mayer | uint32_t bo = BO(ctx->opcode); |
3421 | 05f92404 | Blue Swirl | int l1;
|
3422 | a2ffb812 | aurel32 | TCGv target; |
3423 | e98a6e40 | bellard | |
3424 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3425 | a2ffb812 | aurel32 | if (type == BCOND_LR || type == BCOND_CTR) {
|
3426 | a7812ae4 | pbrook | target = tcg_temp_local_new(); |
3427 | a2ffb812 | aurel32 | if (type == BCOND_CTR)
|
3428 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_ctr); |
3429 | a2ffb812 | aurel32 | else
|
3430 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_lr); |
3431 | d2e9fd8f | malc | } else {
|
3432 | d2e9fd8f | malc | TCGV_UNUSED(target); |
3433 | e98a6e40 | bellard | } |
3434 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
3435 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3436 | a2ffb812 | aurel32 | l1 = gen_new_label(); |
3437 | a2ffb812 | aurel32 | if ((bo & 0x4) == 0) { |
3438 | a2ffb812 | aurel32 | /* Decrement and test CTR */
|
3439 | a7812ae4 | pbrook | TCGv temp = tcg_temp_new(); |
3440 | a2ffb812 | aurel32 | if (unlikely(type == BCOND_CTR)) {
|
3441 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3442 | a2ffb812 | aurel32 | return;
|
3443 | a2ffb812 | aurel32 | } |
3444 | a2ffb812 | aurel32 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
|
3445 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3446 | a2ffb812 | aurel32 | if (!ctx->sf_mode)
|
3447 | a2ffb812 | aurel32 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
3448 | a2ffb812 | aurel32 | else
|
3449 | d9bce9d9 | j_mayer | #endif
|
3450 | a2ffb812 | aurel32 | tcg_gen_mov_tl(temp, cpu_ctr); |
3451 | a2ffb812 | aurel32 | if (bo & 0x2) { |
3452 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
|
3453 | a2ffb812 | aurel32 | } else {
|
3454 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
3455 | e98a6e40 | bellard | } |
3456 | a7812ae4 | pbrook | tcg_temp_free(temp); |
3457 | a2ffb812 | aurel32 | } |
3458 | a2ffb812 | aurel32 | if ((bo & 0x10) == 0) { |
3459 | a2ffb812 | aurel32 | /* Test CR */
|
3460 | a2ffb812 | aurel32 | uint32_t bi = BI(ctx->opcode); |
3461 | a2ffb812 | aurel32 | uint32_t mask = 1 << (3 - (bi & 0x03)); |
3462 | a7812ae4 | pbrook | TCGv_i32 temp = tcg_temp_new_i32(); |
3463 | a2ffb812 | aurel32 | |
3464 | d9bce9d9 | j_mayer | if (bo & 0x8) { |
3465 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3466 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
|
3467 | d9bce9d9 | j_mayer | } else {
|
3468 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3469 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
|
3470 | d9bce9d9 | j_mayer | } |
3471 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
3472 | d9bce9d9 | j_mayer | } |
3473 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
3474 | a2ffb812 | aurel32 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3475 | a2ffb812 | aurel32 | if (likely(AA(ctx->opcode) == 0)) { |
3476 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); |
3477 | a2ffb812 | aurel32 | } else {
|
3478 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, li);
|
3479 | a2ffb812 | aurel32 | } |
3480 | c53be334 | bellard | gen_set_label(l1); |
3481 | c1942362 | bellard | gen_goto_tb(ctx, 1, ctx->nip);
|
3482 | e98a6e40 | bellard | } else {
|
3483 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3484 | a2ffb812 | aurel32 | if (!(ctx->sf_mode))
|
3485 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
|
3486 | a2ffb812 | aurel32 | else
|
3487 | a2ffb812 | aurel32 | #endif
|
3488 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, ~3);
|
3489 | a2ffb812 | aurel32 | tcg_gen_exit_tb(0);
|
3490 | a2ffb812 | aurel32 | gen_set_label(l1); |
3491 | a2ffb812 | aurel32 | #if defined(TARGET_PPC64)
|
3492 | a2ffb812 | aurel32 | if (!(ctx->sf_mode))
|
3493 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); |
3494 | d9bce9d9 | j_mayer | else
|
3495 | d9bce9d9 | j_mayer | #endif
|
3496 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
3497 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3498 | 08e46e54 | j_mayer | } |
3499 | e98a6e40 | bellard | } |
3500 | e98a6e40 | bellard | |
3501 | 99e300ef | Blue Swirl | static void gen_bc(DisasContext *ctx) |
3502 | 3b46e624 | ths | { |
3503 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_IM); |
3504 | e98a6e40 | bellard | } |
3505 | e98a6e40 | bellard | |
3506 | 99e300ef | Blue Swirl | static void gen_bcctr(DisasContext *ctx) |
3507 | 3b46e624 | ths | { |
3508 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_CTR); |
3509 | e98a6e40 | bellard | } |
3510 | e98a6e40 | bellard | |
3511 | 99e300ef | Blue Swirl | static void gen_bclr(DisasContext *ctx) |
3512 | 3b46e624 | ths | { |
3513 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_LR); |
3514 | e98a6e40 | bellard | } |
3515 | 79aceca5 | bellard | |
3516 | 79aceca5 | bellard | /*** Condition register logical ***/
|
3517 | e1571908 | aurel32 | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
3518 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3519 | 79aceca5 | bellard | { \ |
3520 | fc0d441e | j_mayer | uint8_t bitmask; \ |
3521 | fc0d441e | j_mayer | int sh; \
|
3522 | a7812ae4 | pbrook | TCGv_i32 t0, t1; \ |
3523 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
3524 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); \ |
3525 | fc0d441e | j_mayer | if (sh > 0) \ |
3526 | fea0c503 | aurel32 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
|
3527 | fc0d441e | j_mayer | else if (sh < 0) \ |
3528 | fea0c503 | aurel32 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
|
3529 | e1571908 | aurel32 | else \
|
3530 | fea0c503 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
|
3531 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); \ |
3532 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3533 | fc0d441e | j_mayer | if (sh > 0) \ |
3534 | fea0c503 | aurel32 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
|
3535 | fc0d441e | j_mayer | else if (sh < 0) \ |
3536 | fea0c503 | aurel32 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
|
3537 | e1571908 | aurel32 | else \
|
3538 | fea0c503 | aurel32 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
|
3539 | fea0c503 | aurel32 | tcg_op(t0, t0, t1); \ |
3540 | fc0d441e | j_mayer | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
3541 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3542 | fea0c503 | aurel32 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
|
3543 | fea0c503 | aurel32 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
|
3544 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
3545 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
3546 | 79aceca5 | bellard | } |
3547 | 79aceca5 | bellard | |
3548 | 79aceca5 | bellard | /* crand */
|
3549 | e1571908 | aurel32 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
|
3550 | 79aceca5 | bellard | /* crandc */
|
3551 | e1571908 | aurel32 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
|
3552 | 79aceca5 | bellard | /* creqv */
|
3553 | e1571908 | aurel32 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
|
3554 | 79aceca5 | bellard | /* crnand */
|
3555 | e1571908 | aurel32 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
|
3556 | 79aceca5 | bellard | /* crnor */
|
3557 | e1571908 | aurel32 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
|
3558 | 79aceca5 | bellard | /* cror */
|
3559 | e1571908 | aurel32 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
|
3560 | 79aceca5 | bellard | /* crorc */
|
3561 | e1571908 | aurel32 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
|
3562 | 79aceca5 | bellard | /* crxor */
|
3563 | e1571908 | aurel32 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
|
3564 | 99e300ef | Blue Swirl | |
3565 | 54623277 | Blue Swirl | /* mcrf */
|
3566 | 99e300ef | Blue Swirl | static void gen_mcrf(DisasContext *ctx) |
3567 | 79aceca5 | bellard | { |
3568 | 47e4661c | aurel32 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
3569 | 79aceca5 | bellard | } |
3570 | 79aceca5 | bellard | |
3571 | 79aceca5 | bellard | /*** System linkage ***/
|
3572 | 99e300ef | Blue Swirl | |
3573 | 54623277 | Blue Swirl | /* rfi (mem_idx only) */
|
3574 | 99e300ef | Blue Swirl | static void gen_rfi(DisasContext *ctx) |
3575 | 79aceca5 | bellard | { |
3576 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3577 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3578 | 9a64fbe4 | bellard | #else
|
3579 | 9a64fbe4 | bellard | /* Restore CPU state */
|
3580 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3581 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3582 | 9fddaa0c | bellard | return;
|
3583 | 9a64fbe4 | bellard | } |
3584 | d72a19f7 | aurel32 | gen_helper_rfi(); |
3585 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3586 | 9a64fbe4 | bellard | #endif
|
3587 | 79aceca5 | bellard | } |
3588 | 79aceca5 | bellard | |
3589 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3590 | 99e300ef | Blue Swirl | static void gen_rfid(DisasContext *ctx) |
3591 | 426613db | j_mayer | { |
3592 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3593 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3594 | 426613db | j_mayer | #else
|
3595 | 426613db | j_mayer | /* Restore CPU state */
|
3596 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3597 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3598 | 426613db | j_mayer | return;
|
3599 | 426613db | j_mayer | } |
3600 | d72a19f7 | aurel32 | gen_helper_rfid(); |
3601 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3602 | 426613db | j_mayer | #endif
|
3603 | 426613db | j_mayer | } |
3604 | 426613db | j_mayer | |
3605 | 99e300ef | Blue Swirl | static void gen_hrfid(DisasContext *ctx) |
3606 | be147d08 | j_mayer | { |
3607 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3608 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3609 | be147d08 | j_mayer | #else
|
3610 | be147d08 | j_mayer | /* Restore CPU state */
|
3611 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx <= 1)) { |
3612 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3613 | be147d08 | j_mayer | return;
|
3614 | be147d08 | j_mayer | } |
3615 | d72a19f7 | aurel32 | gen_helper_hrfid(); |
3616 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3617 | be147d08 | j_mayer | #endif
|
3618 | be147d08 | j_mayer | } |
3619 | be147d08 | j_mayer | #endif
|
3620 | be147d08 | j_mayer | |
3621 | 79aceca5 | bellard | /* sc */
|
3622 | 417bf010 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3623 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
|
3624 | 417bf010 | j_mayer | #else
|
3625 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
|
3626 | 417bf010 | j_mayer | #endif
|
3627 | 99e300ef | Blue Swirl | static void gen_sc(DisasContext *ctx) |
3628 | 79aceca5 | bellard | { |
3629 | e1833e1f | j_mayer | uint32_t lev; |
3630 | e1833e1f | j_mayer | |
3631 | e1833e1f | j_mayer | lev = (ctx->opcode >> 5) & 0x7F; |
3632 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
3633 | 79aceca5 | bellard | } |
3634 | 79aceca5 | bellard | |
3635 | 79aceca5 | bellard | /*** Trap ***/
|
3636 | 99e300ef | Blue Swirl | |
3637 | 54623277 | Blue Swirl | /* tw */
|
3638 | 99e300ef | Blue Swirl | static void gen_tw(DisasContext *ctx) |
3639 | 79aceca5 | bellard | { |
3640 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3641 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3642 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3643 | cab3bee2 | aurel32 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3644 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3645 | 79aceca5 | bellard | } |
3646 | 79aceca5 | bellard | |
3647 | 79aceca5 | bellard | /* twi */
|
3648 | 99e300ef | Blue Swirl | static void gen_twi(DisasContext *ctx) |
3649 | 79aceca5 | bellard | { |
3650 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3651 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3652 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3653 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3654 | cab3bee2 | aurel32 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3655 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3656 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3657 | 79aceca5 | bellard | } |
3658 | 79aceca5 | bellard | |
3659 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3660 | d9bce9d9 | j_mayer | /* td */
|
3661 | 99e300ef | Blue Swirl | static void gen_td(DisasContext *ctx) |
3662 | d9bce9d9 | j_mayer | { |
3663 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3664 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3665 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3666 | cab3bee2 | aurel32 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3667 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3668 | d9bce9d9 | j_mayer | } |
3669 | d9bce9d9 | j_mayer | |
3670 | d9bce9d9 | j_mayer | /* tdi */
|
3671 | 99e300ef | Blue Swirl | static void gen_tdi(DisasContext *ctx) |
3672 | d9bce9d9 | j_mayer | { |
3673 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3674 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3675 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3676 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3677 | cab3bee2 | aurel32 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3678 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3679 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3680 | d9bce9d9 | j_mayer | } |
3681 | d9bce9d9 | j_mayer | #endif
|
3682 | d9bce9d9 | j_mayer | |
3683 | 79aceca5 | bellard | /*** Processor control ***/
|
3684 | 99e300ef | Blue Swirl | |
3685 | 54623277 | Blue Swirl | /* mcrxr */
|
3686 | 99e300ef | Blue Swirl | static void gen_mcrxr(DisasContext *ctx) |
3687 | 79aceca5 | bellard | { |
3688 | 3d7b417e | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
3689 | 3d7b417e | aurel32 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); |
3690 | 269f3e95 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
3691 | 79aceca5 | bellard | } |
3692 | 79aceca5 | bellard | |
3693 | 0cfe11ea | aurel32 | /* mfcr mfocrf */
|
3694 | 99e300ef | Blue Swirl | static void gen_mfcr(DisasContext *ctx) |
3695 | 79aceca5 | bellard | { |
3696 | 76a66253 | j_mayer | uint32_t crm, crn; |
3697 | 3b46e624 | ths | |
3698 | 76a66253 | j_mayer | if (likely(ctx->opcode & 0x00100000)) { |
3699 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3700 | 8dd640e4 | malc | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
3701 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
3702 | e1571908 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
|
3703 | 0497d2f4 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3704 | 0497d2f4 | aurel32 | cpu_gpr[rD(ctx->opcode)], crn * 4);
|
3705 | 76a66253 | j_mayer | } |
3706 | d9bce9d9 | j_mayer | } else {
|
3707 | 651721b2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3708 | 651721b2 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[0]);
|
3709 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3710 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[1]);
|
3711 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3712 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[2]);
|
3713 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3714 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[3]);
|
3715 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3716 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[4]);
|
3717 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3718 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[5]);
|
3719 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3720 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[6]);
|
3721 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
3722 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[7]);
|
3723 | 651721b2 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
3724 | 651721b2 | aurel32 | tcg_temp_free_i32(t0); |
3725 | d9bce9d9 | j_mayer | } |
3726 | 79aceca5 | bellard | } |
3727 | 79aceca5 | bellard | |
3728 | 79aceca5 | bellard | /* mfmsr */
|
3729 | 99e300ef | Blue Swirl | static void gen_mfmsr(DisasContext *ctx) |
3730 | 79aceca5 | bellard | { |
3731 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3732 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3733 | 9a64fbe4 | bellard | #else
|
3734 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3735 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3736 | 9fddaa0c | bellard | return;
|
3737 | 9a64fbe4 | bellard | } |
3738 | 6527f6ea | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
3739 | 9a64fbe4 | bellard | #endif
|
3740 | 79aceca5 | bellard | } |
3741 | 79aceca5 | bellard | |
3742 | 7b13448f | Blue Swirl | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3743 | 3fc6c082 | bellard | { |
3744 | 7b13448f | Blue Swirl | #if 0
|
3745 | 3fc6c082 | bellard | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
|
3746 | 3fc6c082 | bellard | printf("ERROR: try to access SPR %d !\n", sprn);
|
3747 | 7b13448f | Blue Swirl | #endif
|
3748 | 3fc6c082 | bellard | } |
3749 | 3fc6c082 | bellard | #define SPR_NOACCESS (&spr_noaccess)
|
3750 | 3fc6c082 | bellard | |
3751 | 79aceca5 | bellard | /* mfspr */
|
3752 | 636aa200 | Blue Swirl | static inline void gen_op_mfspr(DisasContext *ctx) |
3753 | 79aceca5 | bellard | { |
3754 | 45d827d2 | aurel32 | void (*read_cb)(void *opaque, int gprn, int sprn); |
3755 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3756 | 79aceca5 | bellard | |
3757 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3758 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
3759 | be147d08 | j_mayer | read_cb = ctx->spr_cb[sprn].hea_read; |
3760 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
3761 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].oea_read; |
3762 | 3fc6c082 | bellard | else
|
3763 | 9a64fbe4 | bellard | #endif
|
3764 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].uea_read; |
3765 | 76a66253 | j_mayer | if (likely(read_cb != NULL)) { |
3766 | 76a66253 | j_mayer | if (likely(read_cb != SPR_NOACCESS)) {
|
3767 | 45d827d2 | aurel32 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3768 | 3fc6c082 | bellard | } else {
|
3769 | 3fc6c082 | bellard | /* Privilege exception */
|
3770 | 9fceefa7 | j_mayer | /* This is a hack to avoid warnings when running Linux:
|
3771 | 9fceefa7 | j_mayer | * this OS breaks the PowerPC virtualisation model,
|
3772 | 9fceefa7 | j_mayer | * allowing userland application to read the PVR
|
3773 | 9fceefa7 | j_mayer | */
|
3774 | 9fceefa7 | j_mayer | if (sprn != SPR_PVR) {
|
3775 | 93fcfe39 | aliguori | qemu_log("Trying to read privileged spr %d %03x at "
|
3776 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3777 | 90e189ec | Blue Swirl | printf("Trying to read privileged spr %d %03x at "
|
3778 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3779 | f24e5695 | bellard | } |
3780 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3781 | 79aceca5 | bellard | } |
3782 | 3fc6c082 | bellard | } else {
|
3783 | 3fc6c082 | bellard | /* Not defined */
|
3784 | 93fcfe39 | aliguori | qemu_log("Trying to read invalid spr %d %03x at "
|
3785 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3786 | 90e189ec | Blue Swirl | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", |
3787 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3788 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
3789 | 79aceca5 | bellard | } |
3790 | 79aceca5 | bellard | } |
3791 | 79aceca5 | bellard | |
3792 | 99e300ef | Blue Swirl | static void gen_mfspr(DisasContext *ctx) |
3793 | 79aceca5 | bellard | { |
3794 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3795 | 76a66253 | j_mayer | } |
3796 | 3fc6c082 | bellard | |
3797 | 3fc6c082 | bellard | /* mftb */
|
3798 | 99e300ef | Blue Swirl | static void gen_mftb(DisasContext *ctx) |
3799 | 3fc6c082 | bellard | { |
3800 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
3801 | 79aceca5 | bellard | } |
3802 | 79aceca5 | bellard | |
3803 | 0cfe11ea | aurel32 | /* mtcrf mtocrf*/
|
3804 | 99e300ef | Blue Swirl | static void gen_mtcrf(DisasContext *ctx) |
3805 | 79aceca5 | bellard | { |
3806 | 76a66253 | j_mayer | uint32_t crm, crn; |
3807 | 3b46e624 | ths | |
3808 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
3809 | 8dd640e4 | malc | if (likely((ctx->opcode & 0x00100000))) { |
3810 | 8dd640e4 | malc | if (crm && ((crm & (crm - 1)) == 0)) { |
3811 | 8dd640e4 | malc | TCGv_i32 temp = tcg_temp_new_i32(); |
3812 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
3813 | 8dd640e4 | malc | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
3814 | 0cfe11ea | aurel32 | tcg_gen_shri_i32(temp, temp, crn * 4);
|
3815 | 0cfe11ea | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); |
3816 | 8dd640e4 | malc | tcg_temp_free_i32(temp); |
3817 | 8dd640e4 | malc | } |
3818 | 76a66253 | j_mayer | } else {
|
3819 | 651721b2 | aurel32 | TCGv_i32 temp = tcg_temp_new_i32(); |
3820 | 651721b2 | aurel32 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
3821 | 651721b2 | aurel32 | for (crn = 0 ; crn < 8 ; crn++) { |
3822 | 651721b2 | aurel32 | if (crm & (1 << crn)) { |
3823 | 651721b2 | aurel32 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); |
3824 | 651721b2 | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); |
3825 | 651721b2 | aurel32 | } |
3826 | 651721b2 | aurel32 | } |
3827 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
3828 | 76a66253 | j_mayer | } |
3829 | 79aceca5 | bellard | } |
3830 | 79aceca5 | bellard | |
3831 | 79aceca5 | bellard | /* mtmsr */
|
3832 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3833 | 99e300ef | Blue Swirl | static void gen_mtmsrd(DisasContext *ctx) |
3834 | 426613db | j_mayer | { |
3835 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3836 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3837 | 426613db | j_mayer | #else
|
3838 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3839 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3840 | 426613db | j_mayer | return;
|
3841 | 426613db | j_mayer | } |
3842 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3843 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3844 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3845 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
3846 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
3847 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3848 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3849 | be147d08 | j_mayer | } else {
|
3850 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3851 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3852 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3853 | 056b05f8 | j_mayer | */
|
3854 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3855 | 6527f6ea | aurel32 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
3856 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3857 | be147d08 | j_mayer | /* Note that mtmsr is not always defined as context-synchronizing */
|
3858 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3859 | be147d08 | j_mayer | } |
3860 | 426613db | j_mayer | #endif
|
3861 | 426613db | j_mayer | } |
3862 | 426613db | j_mayer | #endif
|
3863 | 426613db | j_mayer | |
3864 | 99e300ef | Blue Swirl | static void gen_mtmsr(DisasContext *ctx) |
3865 | 79aceca5 | bellard | { |
3866 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3867 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3868 | 9a64fbe4 | bellard | #else
|
3869 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3870 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3871 | 9fddaa0c | bellard | return;
|
3872 | 9a64fbe4 | bellard | } |
3873 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
3874 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
3875 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3876 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
3877 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
3878 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3879 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3880 | be147d08 | j_mayer | } else {
|
3881 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
3882 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
3883 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
3884 | 056b05f8 | j_mayer | */
|
3885 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
3886 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3887 | 6527f6ea | aurel32 | if (!ctx->sf_mode) {
|
3888 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
3889 | 6527f6ea | aurel32 | TCGv t1 = tcg_temp_new(); |
3890 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
|
3891 | 6527f6ea | aurel32 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); |
3892 | 6527f6ea | aurel32 | tcg_gen_or_tl(t0, t0, t1); |
3893 | 6527f6ea | aurel32 | tcg_temp_free(t1); |
3894 | 6527f6ea | aurel32 | gen_helper_store_msr(t0); |
3895 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
3896 | 6527f6ea | aurel32 | } else
|
3897 | d9bce9d9 | j_mayer | #endif
|
3898 | 6527f6ea | aurel32 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
3899 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
3900 | 6527f6ea | aurel32 | /* Note that mtmsr is not always defined as context-synchronizing */
|
3901 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3902 | be147d08 | j_mayer | } |
3903 | 9a64fbe4 | bellard | #endif
|
3904 | 79aceca5 | bellard | } |
3905 | 79aceca5 | bellard | |
3906 | 79aceca5 | bellard | /* mtspr */
|
3907 | 99e300ef | Blue Swirl | static void gen_mtspr(DisasContext *ctx) |
3908 | 79aceca5 | bellard | { |
3909 | 45d827d2 | aurel32 | void (*write_cb)(void *opaque, int sprn, int gprn); |
3910 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
3911 | 79aceca5 | bellard | |
3912 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3913 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
3914 | be147d08 | j_mayer | write_cb = ctx->spr_cb[sprn].hea_write; |
3915 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
3916 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].oea_write; |
3917 | 3fc6c082 | bellard | else
|
3918 | 9a64fbe4 | bellard | #endif
|
3919 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].uea_write; |
3920 | 76a66253 | j_mayer | if (likely(write_cb != NULL)) { |
3921 | 76a66253 | j_mayer | if (likely(write_cb != SPR_NOACCESS)) {
|
3922 | 45d827d2 | aurel32 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3923 | 3fc6c082 | bellard | } else {
|
3924 | 3fc6c082 | bellard | /* Privilege exception */
|
3925 | 93fcfe39 | aliguori | qemu_log("Trying to write privileged spr %d %03x at "
|
3926 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3927 | 90e189ec | Blue Swirl | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
|
3928 | 90e189ec | Blue Swirl | "\n", sprn, sprn, ctx->nip);
|
3929 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
3930 | 76a66253 | j_mayer | } |
3931 | 3fc6c082 | bellard | } else {
|
3932 | 3fc6c082 | bellard | /* Not defined */
|
3933 | 93fcfe39 | aliguori | qemu_log("Trying to write invalid spr %d %03x at "
|
3934 | 90e189ec | Blue Swirl | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
|
3935 | 90e189ec | Blue Swirl | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", |
3936 | 077fc206 | j_mayer | sprn, sprn, ctx->nip); |
3937 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
3938 | 79aceca5 | bellard | } |
3939 | 79aceca5 | bellard | } |
3940 | 79aceca5 | bellard | |
3941 | 79aceca5 | bellard | /*** Cache management ***/
|
3942 | 99e300ef | Blue Swirl | |
3943 | 54623277 | Blue Swirl | /* dcbf */
|
3944 | 99e300ef | Blue Swirl | static void gen_dcbf(DisasContext *ctx) |
3945 | 79aceca5 | bellard | { |
3946 | dac454af | j_mayer | /* XXX: specification says this is treated as a load by the MMU */
|
3947 | 76db3ba4 | aurel32 | TCGv t0; |
3948 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3949 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3950 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3951 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
3952 | fea0c503 | aurel32 | tcg_temp_free(t0); |
3953 | 79aceca5 | bellard | } |
3954 | 79aceca5 | bellard | |
3955 | 79aceca5 | bellard | /* dcbi (Supervisor only) */
|
3956 | 99e300ef | Blue Swirl | static void gen_dcbi(DisasContext *ctx) |
3957 | 79aceca5 | bellard | { |
3958 | a541f297 | bellard | #if defined(CONFIG_USER_ONLY)
|
3959 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3960 | a541f297 | bellard | #else
|
3961 | b61f2753 | aurel32 | TCGv EA, val; |
3962 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3963 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3964 | 9fddaa0c | bellard | return;
|
3965 | 9a64fbe4 | bellard | } |
3966 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
3967 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3968 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
3969 | a7812ae4 | pbrook | val = tcg_temp_new(); |
3970 | 76a66253 | j_mayer | /* XXX: specification says this should be treated as a store by the MMU */
|
3971 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, val, EA); |
3972 | 76db3ba4 | aurel32 | gen_qemu_st8(ctx, val, EA); |
3973 | b61f2753 | aurel32 | tcg_temp_free(val); |
3974 | b61f2753 | aurel32 | tcg_temp_free(EA); |
3975 | a541f297 | bellard | #endif
|
3976 | 79aceca5 | bellard | } |
3977 | 79aceca5 | bellard | |
3978 | 79aceca5 | bellard | /* dcdst */
|
3979 | 99e300ef | Blue Swirl | static void gen_dcbst(DisasContext *ctx) |
3980 | 79aceca5 | bellard | { |
3981 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU */
|
3982 | 76db3ba4 | aurel32 | TCGv t0; |
3983 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
3984 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3985 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3986 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
3987 | fea0c503 | aurel32 | tcg_temp_free(t0); |
3988 | 79aceca5 | bellard | } |
3989 | 79aceca5 | bellard | |
3990 | 79aceca5 | bellard | /* dcbt */
|
3991 | 99e300ef | Blue Swirl | static void gen_dcbt(DisasContext *ctx) |
3992 | 79aceca5 | bellard | { |
3993 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
3994 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
3995 | 76a66253 | j_mayer | * but does not generate any exception
|
3996 | 76a66253 | j_mayer | */
|
3997 | 79aceca5 | bellard | } |
3998 | 79aceca5 | bellard | |
3999 | 79aceca5 | bellard | /* dcbtst */
|
4000 | 99e300ef | Blue Swirl | static void gen_dcbtst(DisasContext *ctx) |
4001 | 79aceca5 | bellard | { |
4002 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
4003 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
4004 | 76a66253 | j_mayer | * but does not generate any exception
|
4005 | 76a66253 | j_mayer | */
|
4006 | 79aceca5 | bellard | } |
4007 | 79aceca5 | bellard | |
4008 | 79aceca5 | bellard | /* dcbz */
|
4009 | 99e300ef | Blue Swirl | static void gen_dcbz(DisasContext *ctx) |
4010 | 79aceca5 | bellard | { |
4011 | 76db3ba4 | aurel32 | TCGv t0; |
4012 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4013 | 799a8c8d | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
4014 | 799a8c8d | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
4015 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4016 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4017 | 799a8c8d | aurel32 | gen_helper_dcbz(t0); |
4018 | 799a8c8d | aurel32 | tcg_temp_free(t0); |
4019 | d63001d1 | j_mayer | } |
4020 | d63001d1 | j_mayer | |
4021 | e8eaa2c0 | Blue Swirl | static void gen_dcbz_970(DisasContext *ctx) |
4022 | d63001d1 | j_mayer | { |
4023 | 76db3ba4 | aurel32 | TCGv t0; |
4024 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4025 | 799a8c8d | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
4026 | 799a8c8d | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
4027 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4028 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4029 | d63001d1 | j_mayer | if (ctx->opcode & 0x00200000) |
4030 | 799a8c8d | aurel32 | gen_helper_dcbz(t0); |
4031 | d63001d1 | j_mayer | else
|
4032 | 799a8c8d | aurel32 | gen_helper_dcbz_970(t0); |
4033 | 799a8c8d | aurel32 | tcg_temp_free(t0); |
4034 | 79aceca5 | bellard | } |
4035 | 79aceca5 | bellard | |
4036 | ae1c1a3d | aurel32 | /* dst / dstt */
|
4037 | 99e300ef | Blue Swirl | static void gen_dst(DisasContext *ctx) |
4038 | ae1c1a3d | aurel32 | { |
4039 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
4040 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
4041 | ae1c1a3d | aurel32 | } else {
|
4042 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4043 | ae1c1a3d | aurel32 | } |
4044 | ae1c1a3d | aurel32 | } |
4045 | ae1c1a3d | aurel32 | |
4046 | ae1c1a3d | aurel32 | /* dstst /dststt */
|
4047 | 99e300ef | Blue Swirl | static void gen_dstst(DisasContext *ctx) |
4048 | ae1c1a3d | aurel32 | { |
4049 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
4050 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
4051 | ae1c1a3d | aurel32 | } else {
|
4052 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4053 | ae1c1a3d | aurel32 | } |
4054 | ae1c1a3d | aurel32 | |
4055 | ae1c1a3d | aurel32 | } |
4056 | ae1c1a3d | aurel32 | |
4057 | ae1c1a3d | aurel32 | /* dss / dssall */
|
4058 | 99e300ef | Blue Swirl | static void gen_dss(DisasContext *ctx) |
4059 | ae1c1a3d | aurel32 | { |
4060 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4061 | ae1c1a3d | aurel32 | } |
4062 | ae1c1a3d | aurel32 | |
4063 | 79aceca5 | bellard | /* icbi */
|
4064 | 99e300ef | Blue Swirl | static void gen_icbi(DisasContext *ctx) |
4065 | 79aceca5 | bellard | { |
4066 | 76db3ba4 | aurel32 | TCGv t0; |
4067 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4068 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4069 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4070 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4071 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4072 | 37d269df | aurel32 | gen_helper_icbi(t0); |
4073 | 37d269df | aurel32 | tcg_temp_free(t0); |
4074 | 79aceca5 | bellard | } |
4075 | 79aceca5 | bellard | |
4076 | 79aceca5 | bellard | /* Optional: */
|
4077 | 79aceca5 | bellard | /* dcba */
|
4078 | 99e300ef | Blue Swirl | static void gen_dcba(DisasContext *ctx) |
4079 | 79aceca5 | bellard | { |
4080 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
4081 | 0db1b20e | j_mayer | /* XXX: specification say this is treated as a store by the MMU
|
4082 | 0db1b20e | j_mayer | * but does not generate any exception
|
4083 | 0db1b20e | j_mayer | */
|
4084 | 79aceca5 | bellard | } |
4085 | 79aceca5 | bellard | |
4086 | 79aceca5 | bellard | /*** Segment register manipulation ***/
|
4087 | 79aceca5 | bellard | /* Supervisor only: */
|
4088 | 99e300ef | Blue Swirl | |
4089 | 54623277 | Blue Swirl | /* mfsr */
|
4090 | 99e300ef | Blue Swirl | static void gen_mfsr(DisasContext *ctx) |
4091 | 79aceca5 | bellard | { |
4092 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4093 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4094 | 9a64fbe4 | bellard | #else
|
4095 | 74d37793 | aurel32 | TCGv t0; |
4096 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4097 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4098 | 9fddaa0c | bellard | return;
|
4099 | 9a64fbe4 | bellard | } |
4100 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4101 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4102 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4103 | 9a64fbe4 | bellard | #endif
|
4104 | 79aceca5 | bellard | } |
4105 | 79aceca5 | bellard | |
4106 | 79aceca5 | bellard | /* mfsrin */
|
4107 | 99e300ef | Blue Swirl | static void gen_mfsrin(DisasContext *ctx) |
4108 | 79aceca5 | bellard | { |
4109 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4110 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4111 | 9a64fbe4 | bellard | #else
|
4112 | 74d37793 | aurel32 | TCGv t0; |
4113 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4114 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4115 | 9fddaa0c | bellard | return;
|
4116 | 9a64fbe4 | bellard | } |
4117 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4118 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4119 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4120 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4121 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4122 | 9a64fbe4 | bellard | #endif
|
4123 | 79aceca5 | bellard | } |
4124 | 79aceca5 | bellard | |
4125 | 79aceca5 | bellard | /* mtsr */
|
4126 | 99e300ef | Blue Swirl | static void gen_mtsr(DisasContext *ctx) |
4127 | 79aceca5 | bellard | { |
4128 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4129 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4130 | 9a64fbe4 | bellard | #else
|
4131 | 74d37793 | aurel32 | TCGv t0; |
4132 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4133 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4134 | 9fddaa0c | bellard | return;
|
4135 | 9a64fbe4 | bellard | } |
4136 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4137 | 74d37793 | aurel32 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4138 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4139 | 9a64fbe4 | bellard | #endif
|
4140 | 79aceca5 | bellard | } |
4141 | 79aceca5 | bellard | |
4142 | 79aceca5 | bellard | /* mtsrin */
|
4143 | 99e300ef | Blue Swirl | static void gen_mtsrin(DisasContext *ctx) |
4144 | 79aceca5 | bellard | { |
4145 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4146 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4147 | 9a64fbe4 | bellard | #else
|
4148 | 74d37793 | aurel32 | TCGv t0; |
4149 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4150 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4151 | 9fddaa0c | bellard | return;
|
4152 | 9a64fbe4 | bellard | } |
4153 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4154 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4155 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4156 | 74d37793 | aurel32 | gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]); |
4157 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4158 | 9a64fbe4 | bellard | #endif
|
4159 | 79aceca5 | bellard | } |
4160 | 79aceca5 | bellard | |
4161 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
4162 | 12de9a39 | j_mayer | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
|
4163 | e8eaa2c0 | Blue Swirl | |
4164 | 54623277 | Blue Swirl | /* mfsr */
|
4165 | e8eaa2c0 | Blue Swirl | static void gen_mfsr_64b(DisasContext *ctx) |
4166 | 12de9a39 | j_mayer | { |
4167 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4168 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4169 | 12de9a39 | j_mayer | #else
|
4170 | 74d37793 | aurel32 | TCGv t0; |
4171 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4172 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4173 | 12de9a39 | j_mayer | return;
|
4174 | 12de9a39 | j_mayer | } |
4175 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4176 | f6b868fc | blueswir1 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4177 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4178 | 12de9a39 | j_mayer | #endif
|
4179 | 12de9a39 | j_mayer | } |
4180 | 12de9a39 | j_mayer | |
4181 | 12de9a39 | j_mayer | /* mfsrin */
|
4182 | e8eaa2c0 | Blue Swirl | static void gen_mfsrin_64b(DisasContext *ctx) |
4183 | 12de9a39 | j_mayer | { |
4184 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4185 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4186 | 12de9a39 | j_mayer | #else
|
4187 | 74d37793 | aurel32 | TCGv t0; |
4188 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4189 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4190 | 12de9a39 | j_mayer | return;
|
4191 | 12de9a39 | j_mayer | } |
4192 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4193 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4194 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4195 | f6b868fc | blueswir1 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
4196 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4197 | 12de9a39 | j_mayer | #endif
|
4198 | 12de9a39 | j_mayer | } |
4199 | 12de9a39 | j_mayer | |
4200 | 12de9a39 | j_mayer | /* mtsr */
|
4201 | e8eaa2c0 | Blue Swirl | static void gen_mtsr_64b(DisasContext *ctx) |
4202 | 12de9a39 | j_mayer | { |
4203 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4204 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4205 | 12de9a39 | j_mayer | #else
|
4206 | 74d37793 | aurel32 | TCGv t0; |
4207 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4208 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4209 | 12de9a39 | j_mayer | return;
|
4210 | 12de9a39 | j_mayer | } |
4211 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4212 | f6b868fc | blueswir1 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4213 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4214 | 12de9a39 | j_mayer | #endif
|
4215 | 12de9a39 | j_mayer | } |
4216 | 12de9a39 | j_mayer | |
4217 | 12de9a39 | j_mayer | /* mtsrin */
|
4218 | e8eaa2c0 | Blue Swirl | static void gen_mtsrin_64b(DisasContext *ctx) |
4219 | 12de9a39 | j_mayer | { |
4220 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4221 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4222 | 12de9a39 | j_mayer | #else
|
4223 | 74d37793 | aurel32 | TCGv t0; |
4224 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4225 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4226 | 12de9a39 | j_mayer | return;
|
4227 | 12de9a39 | j_mayer | } |
4228 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4229 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4230 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4231 | f6b868fc | blueswir1 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
4232 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4233 | 12de9a39 | j_mayer | #endif
|
4234 | 12de9a39 | j_mayer | } |
4235 | f6b868fc | blueswir1 | |
4236 | f6b868fc | blueswir1 | /* slbmte */
|
4237 | e8eaa2c0 | Blue Swirl | static void gen_slbmte(DisasContext *ctx) |
4238 | f6b868fc | blueswir1 | { |
4239 | f6b868fc | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4240 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4241 | f6b868fc | blueswir1 | #else
|
4242 | f6b868fc | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4243 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4244 | f6b868fc | blueswir1 | return;
|
4245 | f6b868fc | blueswir1 | } |
4246 | f6b868fc | blueswir1 | gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
4247 | f6b868fc | blueswir1 | #endif
|
4248 | f6b868fc | blueswir1 | } |
4249 | f6b868fc | blueswir1 | |
4250 | efdef95f | David Gibson | static void gen_slbmfee(DisasContext *ctx) |
4251 | efdef95f | David Gibson | { |
4252 | efdef95f | David Gibson | #if defined(CONFIG_USER_ONLY)
|
4253 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4254 | efdef95f | David Gibson | #else
|
4255 | efdef95f | David Gibson | if (unlikely(!ctx->mem_idx)) {
|
4256 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4257 | efdef95f | David Gibson | return;
|
4258 | efdef95f | David Gibson | } |
4259 | efdef95f | David Gibson | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], |
4260 | efdef95f | David Gibson | cpu_gpr[rB(ctx->opcode)]); |
4261 | efdef95f | David Gibson | #endif
|
4262 | efdef95f | David Gibson | } |
4263 | efdef95f | David Gibson | |
4264 | efdef95f | David Gibson | static void gen_slbmfev(DisasContext *ctx) |
4265 | efdef95f | David Gibson | { |
4266 | efdef95f | David Gibson | #if defined(CONFIG_USER_ONLY)
|
4267 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4268 | efdef95f | David Gibson | #else
|
4269 | efdef95f | David Gibson | if (unlikely(!ctx->mem_idx)) {
|
4270 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4271 | efdef95f | David Gibson | return;
|
4272 | efdef95f | David Gibson | } |
4273 | efdef95f | David Gibson | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], |
4274 | efdef95f | David Gibson | cpu_gpr[rB(ctx->opcode)]); |
4275 | efdef95f | David Gibson | #endif
|
4276 | efdef95f | David Gibson | } |
4277 | 12de9a39 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
4278 | 12de9a39 | j_mayer | |
4279 | 79aceca5 | bellard | /*** Lookaside buffer management ***/
|
4280 | 76db3ba4 | aurel32 | /* Optional & mem_idx only: */
|
4281 | 99e300ef | Blue Swirl | |
4282 | 54623277 | Blue Swirl | /* tlbia */
|
4283 | 99e300ef | Blue Swirl | static void gen_tlbia(DisasContext *ctx) |
4284 | 79aceca5 | bellard | { |
4285 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4286 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4287 | 9a64fbe4 | bellard | #else
|
4288 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4289 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4290 | 9fddaa0c | bellard | return;
|
4291 | 9a64fbe4 | bellard | } |
4292 | 74d37793 | aurel32 | gen_helper_tlbia(); |
4293 | 9a64fbe4 | bellard | #endif
|
4294 | 79aceca5 | bellard | } |
4295 | 79aceca5 | bellard | |
4296 | bf14b1ce | blueswir1 | /* tlbiel */
|
4297 | 99e300ef | Blue Swirl | static void gen_tlbiel(DisasContext *ctx) |
4298 | bf14b1ce | blueswir1 | { |
4299 | bf14b1ce | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4300 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4301 | bf14b1ce | blueswir1 | #else
|
4302 | bf14b1ce | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4303 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4304 | bf14b1ce | blueswir1 | return;
|
4305 | bf14b1ce | blueswir1 | } |
4306 | bf14b1ce | blueswir1 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
4307 | bf14b1ce | blueswir1 | #endif
|
4308 | bf14b1ce | blueswir1 | } |
4309 | bf14b1ce | blueswir1 | |
4310 | 79aceca5 | bellard | /* tlbie */
|
4311 | 99e300ef | Blue Swirl | static void gen_tlbie(DisasContext *ctx) |
4312 | 79aceca5 | bellard | { |
4313 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4314 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4315 | 9a64fbe4 | bellard | #else
|
4316 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4317 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4318 | 9fddaa0c | bellard | return;
|
4319 | 9a64fbe4 | bellard | } |
4320 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
4321 | 74d37793 | aurel32 | if (!ctx->sf_mode) {
|
4322 | 74d37793 | aurel32 | TCGv t0 = tcg_temp_new(); |
4323 | 74d37793 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
4324 | 74d37793 | aurel32 | gen_helper_tlbie(t0); |
4325 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4326 | 74d37793 | aurel32 | } else
|
4327 | d9bce9d9 | j_mayer | #endif
|
4328 | 74d37793 | aurel32 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
4329 | 9a64fbe4 | bellard | #endif
|
4330 | 79aceca5 | bellard | } |
4331 | 79aceca5 | bellard | |
4332 | 79aceca5 | bellard | /* tlbsync */
|
4333 | 99e300ef | Blue Swirl | static void gen_tlbsync(DisasContext *ctx) |
4334 | 79aceca5 | bellard | { |
4335 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4336 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4337 | 9a64fbe4 | bellard | #else
|
4338 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4339 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4340 | 9fddaa0c | bellard | return;
|
4341 | 9a64fbe4 | bellard | } |
4342 | 9a64fbe4 | bellard | /* This has no effect: it should ensure that all previous
|
4343 | 9a64fbe4 | bellard | * tlbie have completed
|
4344 | 9a64fbe4 | bellard | */
|
4345 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
4346 | 9a64fbe4 | bellard | #endif
|
4347 | 79aceca5 | bellard | } |
4348 | 79aceca5 | bellard | |
4349 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
4350 | 426613db | j_mayer | /* slbia */
|
4351 | 99e300ef | Blue Swirl | static void gen_slbia(DisasContext *ctx) |
4352 | 426613db | j_mayer | { |
4353 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4354 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4355 | 426613db | j_mayer | #else
|
4356 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4357 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4358 | 426613db | j_mayer | return;
|
4359 | 426613db | j_mayer | } |
4360 | 74d37793 | aurel32 | gen_helper_slbia(); |
4361 | 426613db | j_mayer | #endif
|
4362 | 426613db | j_mayer | } |
4363 | 426613db | j_mayer | |
4364 | 426613db | j_mayer | /* slbie */
|
4365 | 99e300ef | Blue Swirl | static void gen_slbie(DisasContext *ctx) |
4366 | 426613db | j_mayer | { |
4367 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4368 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4369 | 426613db | j_mayer | #else
|
4370 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4371 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4372 | 426613db | j_mayer | return;
|
4373 | 426613db | j_mayer | } |
4374 | 74d37793 | aurel32 | gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); |
4375 | 426613db | j_mayer | #endif
|
4376 | 426613db | j_mayer | } |
4377 | 426613db | j_mayer | #endif
|
4378 | 426613db | j_mayer | |
4379 | 79aceca5 | bellard | /*** External control ***/
|
4380 | 79aceca5 | bellard | /* Optional: */
|
4381 | 99e300ef | Blue Swirl | |
4382 | 54623277 | Blue Swirl | /* eciwx */
|
4383 | 99e300ef | Blue Swirl | static void gen_eciwx(DisasContext *ctx) |
4384 | 79aceca5 | bellard | { |
4385 | 76db3ba4 | aurel32 | TCGv t0; |
4386 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4387 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4388 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4389 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4390 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4391 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4392 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4393 | 76a66253 | j_mayer | } |
4394 | 76a66253 | j_mayer | |
4395 | 76a66253 | j_mayer | /* ecowx */
|
4396 | 99e300ef | Blue Swirl | static void gen_ecowx(DisasContext *ctx) |
4397 | 76a66253 | j_mayer | { |
4398 | 76db3ba4 | aurel32 | TCGv t0; |
4399 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4400 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4401 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4402 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4403 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4404 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4405 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4406 | 76a66253 | j_mayer | } |
4407 | 76a66253 | j_mayer | |
4408 | 76a66253 | j_mayer | /* PowerPC 601 specific instructions */
|
4409 | 99e300ef | Blue Swirl | |
4410 | 54623277 | Blue Swirl | /* abs - abs. */
|
4411 | 99e300ef | Blue Swirl | static void gen_abs(DisasContext *ctx) |
4412 | 76a66253 | j_mayer | { |
4413 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4414 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4415 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4416 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4417 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4418 | 22e0e173 | aurel32 | gen_set_label(l1); |
4419 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4420 | 22e0e173 | aurel32 | gen_set_label(l2); |
4421 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4422 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4423 | 76a66253 | j_mayer | } |
4424 | 76a66253 | j_mayer | |
4425 | 76a66253 | j_mayer | /* abso - abso. */
|
4426 | 99e300ef | Blue Swirl | static void gen_abso(DisasContext *ctx) |
4427 | 76a66253 | j_mayer | { |
4428 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4429 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4430 | 22e0e173 | aurel32 | int l3 = gen_new_label();
|
4431 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4432 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4433 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
|
4434 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
|
4435 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4436 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4437 | 22e0e173 | aurel32 | gen_set_label(l1); |
4438 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4439 | 22e0e173 | aurel32 | tcg_gen_br(l3); |
4440 | 22e0e173 | aurel32 | gen_set_label(l2); |
4441 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4442 | 22e0e173 | aurel32 | gen_set_label(l3); |
4443 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4444 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4445 | 76a66253 | j_mayer | } |
4446 | 76a66253 | j_mayer | |
4447 | 76a66253 | j_mayer | /* clcs */
|
4448 | 99e300ef | Blue Swirl | static void gen_clcs(DisasContext *ctx) |
4449 | 76a66253 | j_mayer | { |
4450 | 22e0e173 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
4451 | 22e0e173 | aurel32 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); |
4452 | 22e0e173 | aurel32 | tcg_temp_free_i32(t0); |
4453 | c7697e1f | j_mayer | /* Rc=1 sets CR0 to an undefined state */
|
4454 | 76a66253 | j_mayer | } |
4455 | 76a66253 | j_mayer | |
4456 | 76a66253 | j_mayer | /* div - div. */
|
4457 | 99e300ef | Blue Swirl | static void gen_div(DisasContext *ctx) |
4458 | 76a66253 | j_mayer | { |
4459 | 22e0e173 | aurel32 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4460 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4461 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4462 | 76a66253 | j_mayer | } |
4463 | 76a66253 | j_mayer | |
4464 | 76a66253 | j_mayer | /* divo - divo. */
|
4465 | 99e300ef | Blue Swirl | static void gen_divo(DisasContext *ctx) |
4466 | 76a66253 | j_mayer | { |
4467 | 22e0e173 | aurel32 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4468 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4469 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4470 | 76a66253 | j_mayer | } |
4471 | 76a66253 | j_mayer | |
4472 | 76a66253 | j_mayer | /* divs - divs. */
|
4473 | 99e300ef | Blue Swirl | static void gen_divs(DisasContext *ctx) |
4474 | 76a66253 | j_mayer | { |
4475 | 22e0e173 | aurel32 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4476 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4477 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4478 | 76a66253 | j_mayer | } |
4479 | 76a66253 | j_mayer | |
4480 | 76a66253 | j_mayer | /* divso - divso. */
|
4481 | 99e300ef | Blue Swirl | static void gen_divso(DisasContext *ctx) |
4482 | 76a66253 | j_mayer | { |
4483 | 22e0e173 | aurel32 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4484 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4485 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4486 | 76a66253 | j_mayer | } |
4487 | 76a66253 | j_mayer | |
4488 | 76a66253 | j_mayer | /* doz - doz. */
|
4489 | 99e300ef | Blue Swirl | static void gen_doz(DisasContext *ctx) |
4490 | 76a66253 | j_mayer | { |
4491 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4492 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4493 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4494 | 22e0e173 | aurel32 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4495 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4496 | 22e0e173 | aurel32 | gen_set_label(l1); |
4497 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4498 | 22e0e173 | aurel32 | gen_set_label(l2); |
4499 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4500 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4501 | 76a66253 | j_mayer | } |
4502 | 76a66253 | j_mayer | |
4503 | 76a66253 | j_mayer | /* dozo - dozo. */
|
4504 | 99e300ef | Blue Swirl | static void gen_dozo(DisasContext *ctx) |
4505 | 76a66253 | j_mayer | { |
4506 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4507 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4508 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4509 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4510 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4511 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4512 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4513 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4514 | 22e0e173 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4515 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4516 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); |
4517 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4518 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
4519 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
4520 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4521 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4522 | 22e0e173 | aurel32 | gen_set_label(l1); |
4523 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4524 | 22e0e173 | aurel32 | gen_set_label(l2); |
4525 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4526 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4527 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4528 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4529 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4530 | 76a66253 | j_mayer | } |
4531 | 76a66253 | j_mayer | |
4532 | 76a66253 | j_mayer | /* dozi */
|
4533 | 99e300ef | Blue Swirl | static void gen_dozi(DisasContext *ctx) |
4534 | 76a66253 | j_mayer | { |
4535 | 22e0e173 | aurel32 | target_long simm = SIMM(ctx->opcode); |
4536 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4537 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4538 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4539 | 22e0e173 | aurel32 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); |
4540 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4541 | 22e0e173 | aurel32 | gen_set_label(l1); |
4542 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4543 | 22e0e173 | aurel32 | gen_set_label(l2); |
4544 | 22e0e173 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
4545 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4546 | 76a66253 | j_mayer | } |
4547 | 76a66253 | j_mayer | |
4548 | 76a66253 | j_mayer | /* lscbx - lscbx. */
|
4549 | 99e300ef | Blue Swirl | static void gen_lscbx(DisasContext *ctx) |
4550 | 76a66253 | j_mayer | { |
4551 | bdb4b689 | aurel32 | TCGv t0 = tcg_temp_new(); |
4552 | bdb4b689 | aurel32 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); |
4553 | bdb4b689 | aurel32 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); |
4554 | bdb4b689 | aurel32 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); |
4555 | 76a66253 | j_mayer | |
4556 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4557 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4558 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4559 | bdb4b689 | aurel32 | gen_helper_lscbx(t0, t0, t1, t2, t3); |
4560 | bdb4b689 | aurel32 | tcg_temp_free_i32(t1); |
4561 | bdb4b689 | aurel32 | tcg_temp_free_i32(t2); |
4562 | bdb4b689 | aurel32 | tcg_temp_free_i32(t3); |
4563 | 3d7b417e | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
|
4564 | bdb4b689 | aurel32 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
4565 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4566 | bdb4b689 | aurel32 | gen_set_Rc0(ctx, t0); |
4567 | bdb4b689 | aurel32 | tcg_temp_free(t0); |
4568 | 76a66253 | j_mayer | } |
4569 | 76a66253 | j_mayer | |
4570 | 76a66253 | j_mayer | /* maskg - maskg. */
|
4571 | 99e300ef | Blue Swirl | static void gen_maskg(DisasContext *ctx) |
4572 | 76a66253 | j_mayer | { |
4573 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4574 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4575 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4576 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4577 | 22e0e173 | aurel32 | TCGv t3 = tcg_temp_new(); |
4578 | 22e0e173 | aurel32 | tcg_gen_movi_tl(t3, 0xFFFFFFFF);
|
4579 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4580 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
|
4581 | 22e0e173 | aurel32 | tcg_gen_addi_tl(t2, t0, 1);
|
4582 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t2, t3, t2); |
4583 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t3, t3, t1); |
4584 | 22e0e173 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); |
4585 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); |
4586 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4587 | 22e0e173 | aurel32 | gen_set_label(l1); |
4588 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4589 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4590 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4591 | 22e0e173 | aurel32 | tcg_temp_free(t3); |
4592 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4593 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4594 | 76a66253 | j_mayer | } |
4595 | 76a66253 | j_mayer | |
4596 | 76a66253 | j_mayer | /* maskir - maskir. */
|
4597 | 99e300ef | Blue Swirl | static void gen_maskir(DisasContext *ctx) |
4598 | 76a66253 | j_mayer | { |
4599 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4600 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4601 | 22e0e173 | aurel32 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4602 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4603 | 22e0e173 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4604 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4605 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4606 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4607 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4608 | 76a66253 | j_mayer | } |
4609 | 76a66253 | j_mayer | |
4610 | 76a66253 | j_mayer | /* mul - mul. */
|
4611 | 99e300ef | Blue Swirl | static void gen_mul(DisasContext *ctx) |
4612 | 76a66253 | j_mayer | { |
4613 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4614 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4615 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4616 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4617 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4618 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4619 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4620 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4621 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4622 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4623 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4624 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4625 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4626 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4627 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4628 | 76a66253 | j_mayer | } |
4629 | 76a66253 | j_mayer | |
4630 | 76a66253 | j_mayer | /* mulo - mulo. */
|
4631 | 99e300ef | Blue Swirl | static void gen_mulo(DisasContext *ctx) |
4632 | 76a66253 | j_mayer | { |
4633 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4634 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4635 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4636 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4637 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4638 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4639 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4640 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4641 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4642 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4643 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4644 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4645 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4646 | 22e0e173 | aurel32 | tcg_gen_ext32s_i64(t1, t0); |
4647 | 22e0e173 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
4648 | 22e0e173 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
4649 | 22e0e173 | aurel32 | gen_set_label(l1); |
4650 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4651 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4652 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4653 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4654 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4655 | 76a66253 | j_mayer | } |
4656 | 76a66253 | j_mayer | |
4657 | 76a66253 | j_mayer | /* nabs - nabs. */
|
4658 | 99e300ef | Blue Swirl | static void gen_nabs(DisasContext *ctx) |
4659 | 76a66253 | j_mayer | { |
4660 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4661 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4662 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4663 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4664 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4665 | 22e0e173 | aurel32 | gen_set_label(l1); |
4666 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4667 | 22e0e173 | aurel32 | gen_set_label(l2); |
4668 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4669 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4670 | 76a66253 | j_mayer | } |
4671 | 76a66253 | j_mayer | |
4672 | 76a66253 | j_mayer | /* nabso - nabso. */
|
4673 | 99e300ef | Blue Swirl | static void gen_nabso(DisasContext *ctx) |
4674 | 76a66253 | j_mayer | { |
4675 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4676 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4677 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4678 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4679 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4680 | 22e0e173 | aurel32 | gen_set_label(l1); |
4681 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4682 | 22e0e173 | aurel32 | gen_set_label(l2); |
4683 | 22e0e173 | aurel32 | /* nabs never overflows */
|
4684 | 22e0e173 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
4685 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4686 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4687 | 76a66253 | j_mayer | } |
4688 | 76a66253 | j_mayer | |
4689 | 76a66253 | j_mayer | /* rlmi - rlmi. */
|
4690 | 99e300ef | Blue Swirl | static void gen_rlmi(DisasContext *ctx) |
4691 | 76a66253 | j_mayer | { |
4692 | 7487953d | aurel32 | uint32_t mb = MB(ctx->opcode); |
4693 | 7487953d | aurel32 | uint32_t me = ME(ctx->opcode); |
4694 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4695 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4696 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4697 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); |
4698 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); |
4699 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
4700 | 7487953d | aurel32 | tcg_temp_free(t0); |
4701 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4702 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4703 | 76a66253 | j_mayer | } |
4704 | 76a66253 | j_mayer | |
4705 | 76a66253 | j_mayer | /* rrib - rrib. */
|
4706 | 99e300ef | Blue Swirl | static void gen_rrib(DisasContext *ctx) |
4707 | 76a66253 | j_mayer | { |
4708 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4709 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4710 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4711 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0x80000000);
|
4712 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
4713 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4714 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
4715 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); |
4716 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4717 | 7487953d | aurel32 | tcg_temp_free(t0); |
4718 | 7487953d | aurel32 | tcg_temp_free(t1); |
4719 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4720 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4721 | 76a66253 | j_mayer | } |
4722 | 76a66253 | j_mayer | |
4723 | 76a66253 | j_mayer | /* sle - sle. */
|
4724 | 99e300ef | Blue Swirl | static void gen_sle(DisasContext *ctx) |
4725 | 76a66253 | j_mayer | { |
4726 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4727 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4728 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4729 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4730 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4731 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4732 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4733 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4734 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4735 | 7487953d | aurel32 | tcg_temp_free(t0); |
4736 | 7487953d | aurel32 | tcg_temp_free(t1); |
4737 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4738 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4739 | 76a66253 | j_mayer | } |
4740 | 76a66253 | j_mayer | |
4741 | 76a66253 | j_mayer | /* sleq - sleq. */
|
4742 | 99e300ef | Blue Swirl | static void gen_sleq(DisasContext *ctx) |
4743 | 76a66253 | j_mayer | { |
4744 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4745 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4746 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
4747 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4748 | 7487953d | aurel32 | tcg_gen_movi_tl(t2, 0xFFFFFFFF);
|
4749 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, t2, t0); |
4750 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4751 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4752 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4753 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
4754 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4755 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4756 | 7487953d | aurel32 | tcg_temp_free(t0); |
4757 | 7487953d | aurel32 | tcg_temp_free(t1); |
4758 | 7487953d | aurel32 | tcg_temp_free(t2); |
4759 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4760 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4761 | 76a66253 | j_mayer | } |
4762 | 76a66253 | j_mayer | |
4763 | 76a66253 | j_mayer | /* sliq - sliq. */
|
4764 | 99e300ef | Blue Swirl | static void gen_sliq(DisasContext *ctx) |
4765 | 76a66253 | j_mayer | { |
4766 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4767 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4768 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4769 | 7487953d | aurel32 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4770 | 7487953d | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4771 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4772 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4773 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4774 | 7487953d | aurel32 | tcg_temp_free(t0); |
4775 | 7487953d | aurel32 | tcg_temp_free(t1); |
4776 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4777 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4778 | 76a66253 | j_mayer | } |
4779 | 76a66253 | j_mayer | |
4780 | 76a66253 | j_mayer | /* slliq - slliq. */
|
4781 | 99e300ef | Blue Swirl | static void gen_slliq(DisasContext *ctx) |
4782 | 76a66253 | j_mayer | { |
4783 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4784 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4785 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4786 | 7487953d | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4787 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4788 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4789 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
|
4790 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
|
4791 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4792 | 7487953d | aurel32 | tcg_temp_free(t0); |
4793 | 7487953d | aurel32 | tcg_temp_free(t1); |
4794 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4795 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4796 | 76a66253 | j_mayer | } |
4797 | 76a66253 | j_mayer | |
4798 | 76a66253 | j_mayer | /* sllq - sllq. */
|
4799 | 99e300ef | Blue Swirl | static void gen_sllq(DisasContext *ctx) |
4800 | 76a66253 | j_mayer | { |
4801 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4802 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4803 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
4804 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4805 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4806 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4807 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4808 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, t1, t2); |
4809 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4810 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
4811 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
4812 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4813 | 7487953d | aurel32 | tcg_gen_br(l2); |
4814 | 7487953d | aurel32 | gen_set_label(l1); |
4815 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4816 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
4817 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t2, t1); |
4818 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4819 | 7487953d | aurel32 | gen_set_label(l2); |
4820 | 7487953d | aurel32 | tcg_temp_free(t0); |
4821 | 7487953d | aurel32 | tcg_temp_free(t1); |
4822 | 7487953d | aurel32 | tcg_temp_free(t2); |
4823 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4824 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4825 | 76a66253 | j_mayer | } |
4826 | 76a66253 | j_mayer | |
4827 | 76a66253 | j_mayer | /* slq - slq. */
|
4828 | 99e300ef | Blue Swirl | static void gen_slq(DisasContext *ctx) |
4829 | 76a66253 | j_mayer | { |
4830 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4831 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4832 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4833 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4834 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4835 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4836 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4837 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4838 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4839 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4840 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4841 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
4842 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
4843 | 7487953d | aurel32 | gen_set_label(l1); |
4844 | 7487953d | aurel32 | tcg_temp_free(t0); |
4845 | 7487953d | aurel32 | tcg_temp_free(t1); |
4846 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4847 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4848 | 76a66253 | j_mayer | } |
4849 | 76a66253 | j_mayer | |
4850 | d9bce9d9 | j_mayer | /* sraiq - sraiq. */
|
4851 | 99e300ef | Blue Swirl | static void gen_sraiq(DisasContext *ctx) |
4852 | 76a66253 | j_mayer | { |
4853 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4854 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4855 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4856 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4857 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4858 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4859 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t1); |
4860 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4861 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
4862 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
4863 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
4864 | 7487953d | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
|
4865 | 7487953d | aurel32 | gen_set_label(l1); |
4866 | 7487953d | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
4867 | 7487953d | aurel32 | tcg_temp_free(t0); |
4868 | 7487953d | aurel32 | tcg_temp_free(t1); |
4869 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4870 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4871 | 76a66253 | j_mayer | } |
4872 | 76a66253 | j_mayer | |
4873 | 76a66253 | j_mayer | /* sraq - sraq. */
|
4874 | 99e300ef | Blue Swirl | static void gen_sraq(DisasContext *ctx) |
4875 | 76a66253 | j_mayer | { |
4876 | 7487953d | aurel32 | int l1 = gen_new_label();
|
4877 | 7487953d | aurel32 | int l2 = gen_new_label();
|
4878 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4879 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
4880 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
4881 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4882 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
4883 | 7487953d | aurel32 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); |
4884 | 7487953d | aurel32 | tcg_gen_subfi_tl(t2, 32, t2);
|
4885 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); |
4886 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t2); |
4887 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4888 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
4889 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
|
4890 | 7487953d | aurel32 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); |
4891 | 7487953d | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
|
4892 | 7487953d | aurel32 | gen_set_label(l1); |
4893 | 7487953d | aurel32 | tcg_temp_free(t0); |
4894 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); |
4895 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
|
4896 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
4897 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
|
4898 | 7487953d | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
|
4899 | 7487953d | aurel32 | gen_set_label(l2); |
4900 | 7487953d | aurel32 | tcg_temp_free(t1); |
4901 | 7487953d | aurel32 | tcg_temp_free(t2); |
4902 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4903 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4904 | 76a66253 | j_mayer | } |
4905 | 76a66253 | j_mayer | |
4906 | 76a66253 | j_mayer | /* sre - sre. */
|
4907 | 99e300ef | Blue Swirl | static void gen_sre(DisasContext *ctx) |
4908 | 76a66253 | j_mayer | { |
4909 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4910 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4911 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4912 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4913 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
4914 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
4915 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4916 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4917 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4918 | 7487953d | aurel32 | tcg_temp_free(t0); |
4919 | 7487953d | aurel32 | tcg_temp_free(t1); |
4920 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4921 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4922 | 76a66253 | j_mayer | } |
4923 | 76a66253 | j_mayer | |
4924 | 76a66253 | j_mayer | /* srea - srea. */
|
4925 | 99e300ef | Blue Swirl | static void gen_srea(DisasContext *ctx) |
4926 | 76a66253 | j_mayer | { |
4927 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4928 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4929 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4930 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
4931 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4932 | 7487953d | aurel32 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); |
4933 | 7487953d | aurel32 | tcg_temp_free(t0); |
4934 | 7487953d | aurel32 | tcg_temp_free(t1); |
4935 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4936 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4937 | 76a66253 | j_mayer | } |
4938 | 76a66253 | j_mayer | |
4939 | 76a66253 | j_mayer | /* sreq */
|
4940 | 99e300ef | Blue Swirl | static void gen_sreq(DisasContext *ctx) |
4941 | 76a66253 | j_mayer | { |
4942 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4943 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4944 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
4945 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4946 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
4947 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
4948 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
4949 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
4950 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4951 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
4952 | 7487953d | aurel32 | tcg_gen_andc_tl(t2, t2, t1); |
4953 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
4954 | 7487953d | aurel32 | tcg_temp_free(t0); |
4955 | 7487953d | aurel32 | tcg_temp_free(t1); |
4956 | 7487953d | aurel32 | tcg_temp_free(t2); |
4957 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4958 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4959 | 76a66253 | j_mayer | } |
4960 | 76a66253 | j_mayer | |
4961 | 76a66253 | j_mayer | /* sriq */
|
4962 | 99e300ef | Blue Swirl | static void gen_sriq(DisasContext *ctx) |
4963 | 76a66253 | j_mayer | { |
4964 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4965 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4966 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4967 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4968 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
4969 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
4970 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
4971 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
4972 | 7487953d | aurel32 | tcg_temp_free(t0); |
4973 | 7487953d | aurel32 | tcg_temp_free(t1); |
4974 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4975 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4976 | 76a66253 | j_mayer | } |
4977 | 76a66253 | j_mayer | |
4978 | 76a66253 | j_mayer | /* srliq */
|
4979 | 99e300ef | Blue Swirl | static void gen_srliq(DisasContext *ctx) |
4980 | 76a66253 | j_mayer | { |
4981 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
4982 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
4983 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
4984 | 7487953d | aurel32 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
4985 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
4986 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
4987 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
|
4988 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
|
4989 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4990 | 7487953d | aurel32 | tcg_temp_free(t0); |
4991 | 7487953d | aurel32 | tcg_temp_free(t1); |
4992 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4993 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4994 | 76a66253 | j_mayer | } |
4995 | 76a66253 | j_mayer | |
4996 | 76a66253 | j_mayer | /* srlq */
|
4997 | 99e300ef | Blue Swirl | static void gen_srlq(DisasContext *ctx) |
4998 | 76a66253 | j_mayer | { |
4999 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5000 | 7487953d | aurel32 | int l2 = gen_new_label();
|
5001 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
5002 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
5003 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
5004 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5005 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
5006 | 7487953d | aurel32 | tcg_gen_shr_tl(t2, t1, t2); |
5007 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5008 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
5009 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
5010 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
5011 | 7487953d | aurel32 | tcg_gen_br(l2); |
5012 | 7487953d | aurel32 | gen_set_label(l1); |
5013 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
5014 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
5015 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
5016 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
5017 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5018 | 7487953d | aurel32 | gen_set_label(l2); |
5019 | 7487953d | aurel32 | tcg_temp_free(t0); |
5020 | 7487953d | aurel32 | tcg_temp_free(t1); |
5021 | 7487953d | aurel32 | tcg_temp_free(t2); |
5022 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5023 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5024 | 76a66253 | j_mayer | } |
5025 | 76a66253 | j_mayer | |
5026 | 76a66253 | j_mayer | /* srq */
|
5027 | 99e300ef | Blue Swirl | static void gen_srq(DisasContext *ctx) |
5028 | 76a66253 | j_mayer | { |
5029 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5030 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5031 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5032 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5033 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5034 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
5035 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5036 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5037 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5038 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5039 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5040 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
5041 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
5042 | 7487953d | aurel32 | gen_set_label(l1); |
5043 | 7487953d | aurel32 | tcg_temp_free(t0); |
5044 | 7487953d | aurel32 | tcg_temp_free(t1); |
5045 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5046 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5047 | 76a66253 | j_mayer | } |
5048 | 76a66253 | j_mayer | |
5049 | 76a66253 | j_mayer | /* PowerPC 602 specific instructions */
|
5050 | 99e300ef | Blue Swirl | |
5051 | 54623277 | Blue Swirl | /* dsa */
|
5052 | 99e300ef | Blue Swirl | static void gen_dsa(DisasContext *ctx) |
5053 | 76a66253 | j_mayer | { |
5054 | 76a66253 | j_mayer | /* XXX: TODO */
|
5055 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5056 | 76a66253 | j_mayer | } |
5057 | 76a66253 | j_mayer | |
5058 | 76a66253 | j_mayer | /* esa */
|
5059 | 99e300ef | Blue Swirl | static void gen_esa(DisasContext *ctx) |
5060 | 76a66253 | j_mayer | { |
5061 | 76a66253 | j_mayer | /* XXX: TODO */
|
5062 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5063 | 76a66253 | j_mayer | } |
5064 | 76a66253 | j_mayer | |
5065 | 76a66253 | j_mayer | /* mfrom */
|
5066 | 99e300ef | Blue Swirl | static void gen_mfrom(DisasContext *ctx) |
5067 | 76a66253 | j_mayer | { |
5068 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5069 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5070 | 76a66253 | j_mayer | #else
|
5071 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5072 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5073 | 76a66253 | j_mayer | return;
|
5074 | 76a66253 | j_mayer | } |
5075 | cf02a65c | aurel32 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5076 | 76a66253 | j_mayer | #endif
|
5077 | 76a66253 | j_mayer | } |
5078 | 76a66253 | j_mayer | |
5079 | 76a66253 | j_mayer | /* 602 - 603 - G2 TLB management */
|
5080 | e8eaa2c0 | Blue Swirl | |
5081 | 54623277 | Blue Swirl | /* tlbld */
|
5082 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_6xx(DisasContext *ctx) |
5083 | 76a66253 | j_mayer | { |
5084 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5085 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5086 | 76a66253 | j_mayer | #else
|
5087 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5088 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5089 | 76a66253 | j_mayer | return;
|
5090 | 76a66253 | j_mayer | } |
5091 | 74d37793 | aurel32 | gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
5092 | 76a66253 | j_mayer | #endif
|
5093 | 76a66253 | j_mayer | } |
5094 | 76a66253 | j_mayer | |
5095 | 76a66253 | j_mayer | /* tlbli */
|
5096 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_6xx(DisasContext *ctx) |
5097 | 76a66253 | j_mayer | { |
5098 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5099 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5100 | 76a66253 | j_mayer | #else
|
5101 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5102 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5103 | 76a66253 | j_mayer | return;
|
5104 | 76a66253 | j_mayer | } |
5105 | 74d37793 | aurel32 | gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
5106 | 76a66253 | j_mayer | #endif
|
5107 | 76a66253 | j_mayer | } |
5108 | 76a66253 | j_mayer | |
5109 | 7dbe11ac | j_mayer | /* 74xx TLB management */
|
5110 | e8eaa2c0 | Blue Swirl | |
5111 | 54623277 | Blue Swirl | /* tlbld */
|
5112 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_74xx(DisasContext *ctx) |
5113 | 7dbe11ac | j_mayer | { |
5114 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5115 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5116 | 7dbe11ac | j_mayer | #else
|
5117 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5118 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5119 | 7dbe11ac | j_mayer | return;
|
5120 | 7dbe11ac | j_mayer | } |
5121 | 74d37793 | aurel32 | gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
5122 | 7dbe11ac | j_mayer | #endif
|
5123 | 7dbe11ac | j_mayer | } |
5124 | 7dbe11ac | j_mayer | |
5125 | 7dbe11ac | j_mayer | /* tlbli */
|
5126 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_74xx(DisasContext *ctx) |
5127 | 7dbe11ac | j_mayer | { |
5128 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5129 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5130 | 7dbe11ac | j_mayer | #else
|
5131 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5132 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5133 | 7dbe11ac | j_mayer | return;
|
5134 | 7dbe11ac | j_mayer | } |
5135 | 74d37793 | aurel32 | gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
5136 | 7dbe11ac | j_mayer | #endif
|
5137 | 7dbe11ac | j_mayer | } |
5138 | 7dbe11ac | j_mayer | |
5139 | 76a66253 | j_mayer | /* POWER instructions not in PowerPC 601 */
|
5140 | 99e300ef | Blue Swirl | |
5141 | 54623277 | Blue Swirl | /* clf */
|
5142 | 99e300ef | Blue Swirl | static void gen_clf(DisasContext *ctx) |
5143 | 76a66253 | j_mayer | { |
5144 | 76a66253 | j_mayer | /* Cache line flush: implemented as no-op */
|
5145 | 76a66253 | j_mayer | } |
5146 | 76a66253 | j_mayer | |
5147 | 76a66253 | j_mayer | /* cli */
|
5148 | 99e300ef | Blue Swirl | static void gen_cli(DisasContext *ctx) |
5149 | 76a66253 | j_mayer | { |
5150 | 7f75ffd3 | blueswir1 | /* Cache line invalidate: privileged and treated as no-op */
|
5151 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5152 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5153 | 76a66253 | j_mayer | #else
|
5154 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5155 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5156 | 76a66253 | j_mayer | return;
|
5157 | 76a66253 | j_mayer | } |
5158 | 76a66253 | j_mayer | #endif
|
5159 | 76a66253 | j_mayer | } |
5160 | 76a66253 | j_mayer | |
5161 | 76a66253 | j_mayer | /* dclst */
|
5162 | 99e300ef | Blue Swirl | static void gen_dclst(DisasContext *ctx) |
5163 | 76a66253 | j_mayer | { |
5164 | 76a66253 | j_mayer | /* Data cache line store: treated as no-op */
|
5165 | 76a66253 | j_mayer | } |
5166 | 76a66253 | j_mayer | |
5167 | 99e300ef | Blue Swirl | static void gen_mfsri(DisasContext *ctx) |
5168 | 76a66253 | j_mayer | { |
5169 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5170 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5171 | 76a66253 | j_mayer | #else
|
5172 | 74d37793 | aurel32 | int ra = rA(ctx->opcode);
|
5173 | 74d37793 | aurel32 | int rd = rD(ctx->opcode);
|
5174 | 74d37793 | aurel32 | TCGv t0; |
5175 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5176 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5177 | 76a66253 | j_mayer | return;
|
5178 | 76a66253 | j_mayer | } |
5179 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5180 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5181 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, t0, 28);
|
5182 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
5183 | 74d37793 | aurel32 | gen_helper_load_sr(cpu_gpr[rd], t0); |
5184 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5185 | 76a66253 | j_mayer | if (ra != 0 && ra != rd) |
5186 | 74d37793 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
5187 | 76a66253 | j_mayer | #endif
|
5188 | 76a66253 | j_mayer | } |
5189 | 76a66253 | j_mayer | |
5190 | 99e300ef | Blue Swirl | static void gen_rac(DisasContext *ctx) |
5191 | 76a66253 | j_mayer | { |
5192 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5193 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5194 | 76a66253 | j_mayer | #else
|
5195 | 22e0e173 | aurel32 | TCGv t0; |
5196 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5197 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5198 | 76a66253 | j_mayer | return;
|
5199 | 76a66253 | j_mayer | } |
5200 | 22e0e173 | aurel32 | t0 = tcg_temp_new(); |
5201 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5202 | 22e0e173 | aurel32 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); |
5203 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
5204 | 76a66253 | j_mayer | #endif
|
5205 | 76a66253 | j_mayer | } |
5206 | 76a66253 | j_mayer | |
5207 | 99e300ef | Blue Swirl | static void gen_rfsvc(DisasContext *ctx) |
5208 | 76a66253 | j_mayer | { |
5209 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5210 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5211 | 76a66253 | j_mayer | #else
|
5212 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5213 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5214 | 76a66253 | j_mayer | return;
|
5215 | 76a66253 | j_mayer | } |
5216 | d72a19f7 | aurel32 | gen_helper_rfsvc(); |
5217 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5218 | 76a66253 | j_mayer | #endif
|
5219 | 76a66253 | j_mayer | } |
5220 | 76a66253 | j_mayer | |
5221 | 76a66253 | j_mayer | /* svc is not implemented for now */
|
5222 | 76a66253 | j_mayer | |
5223 | 76a66253 | j_mayer | /* POWER2 specific instructions */
|
5224 | 76a66253 | j_mayer | /* Quad manipulation (load/store two floats at a time) */
|
5225 | 76a66253 | j_mayer | |
5226 | 76a66253 | j_mayer | /* lfq */
|
5227 | 99e300ef | Blue Swirl | static void gen_lfq(DisasContext *ctx) |
5228 | 76a66253 | j_mayer | { |
5229 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5230 | 76db3ba4 | aurel32 | TCGv t0; |
5231 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5232 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5233 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5234 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5235 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5236 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5237 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5238 | 76a66253 | j_mayer | } |
5239 | 76a66253 | j_mayer | |
5240 | 76a66253 | j_mayer | /* lfqu */
|
5241 | 99e300ef | Blue Swirl | static void gen_lfqu(DisasContext *ctx) |
5242 | 76a66253 | j_mayer | { |
5243 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5244 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5245 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5246 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5247 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5248 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5249 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5250 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5251 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5252 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5253 | 76a66253 | j_mayer | if (ra != 0) |
5254 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5255 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5256 | 01a4afeb | aurel32 | tcg_temp_free(t1); |
5257 | 76a66253 | j_mayer | } |
5258 | 76a66253 | j_mayer | |
5259 | 76a66253 | j_mayer | /* lfqux */
|
5260 | 99e300ef | Blue Swirl | static void gen_lfqux(DisasContext *ctx) |
5261 | 76a66253 | j_mayer | { |
5262 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5263 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5264 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5265 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5266 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5267 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5268 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5269 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5270 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5271 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5272 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5273 | 76a66253 | j_mayer | if (ra != 0) |
5274 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5275 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5276 | 76a66253 | j_mayer | } |
5277 | 76a66253 | j_mayer | |
5278 | 76a66253 | j_mayer | /* lfqx */
|
5279 | 99e300ef | Blue Swirl | static void gen_lfqx(DisasContext *ctx) |
5280 | 76a66253 | j_mayer | { |
5281 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5282 | 76db3ba4 | aurel32 | TCGv t0; |
5283 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5284 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5285 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5286 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5287 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5288 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5289 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5290 | 76a66253 | j_mayer | } |
5291 | 76a66253 | j_mayer | |
5292 | 76a66253 | j_mayer | /* stfq */
|
5293 | 99e300ef | Blue Swirl | static void gen_stfq(DisasContext *ctx) |
5294 | 76a66253 | j_mayer | { |
5295 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5296 | 76db3ba4 | aurel32 | TCGv t0; |
5297 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5298 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5299 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5300 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5301 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5302 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5303 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5304 | 76a66253 | j_mayer | } |
5305 | 76a66253 | j_mayer | |
5306 | 76a66253 | j_mayer | /* stfqu */
|
5307 | 99e300ef | Blue Swirl | static void gen_stfqu(DisasContext *ctx) |
5308 | 76a66253 | j_mayer | { |
5309 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5310 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5311 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5312 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5313 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5314 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5315 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5316 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5317 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5318 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5319 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5320 | 76a66253 | j_mayer | if (ra != 0) |
5321 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5322 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5323 | 76a66253 | j_mayer | } |
5324 | 76a66253 | j_mayer | |
5325 | 76a66253 | j_mayer | /* stfqux */
|
5326 | 99e300ef | Blue Swirl | static void gen_stfqux(DisasContext *ctx) |
5327 | 76a66253 | j_mayer | { |
5328 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5329 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5330 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5331 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5332 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5333 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5334 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5335 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5336 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5337 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5338 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5339 | 76a66253 | j_mayer | if (ra != 0) |
5340 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5341 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5342 | 76a66253 | j_mayer | } |
5343 | 76a66253 | j_mayer | |
5344 | 76a66253 | j_mayer | /* stfqx */
|
5345 | 99e300ef | Blue Swirl | static void gen_stfqx(DisasContext *ctx) |
5346 | 76a66253 | j_mayer | { |
5347 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5348 | 76db3ba4 | aurel32 | TCGv t0; |
5349 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5350 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5351 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5352 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5353 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5354 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5355 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5356 | 76a66253 | j_mayer | } |
5357 | 76a66253 | j_mayer | |
5358 | 76a66253 | j_mayer | /* BookE specific instructions */
|
5359 | 99e300ef | Blue Swirl | |
5360 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
5361 | 99e300ef | Blue Swirl | static void gen_mfapidi(DisasContext *ctx) |
5362 | 76a66253 | j_mayer | { |
5363 | 76a66253 | j_mayer | /* XXX: TODO */
|
5364 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5365 | 76a66253 | j_mayer | } |
5366 | 76a66253 | j_mayer | |
5367 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5368 | 99e300ef | Blue Swirl | static void gen_tlbiva(DisasContext *ctx) |
5369 | 76a66253 | j_mayer | { |
5370 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5371 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5372 | 76a66253 | j_mayer | #else
|
5373 | 74d37793 | aurel32 | TCGv t0; |
5374 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5375 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5376 | 76a66253 | j_mayer | return;
|
5377 | 76a66253 | j_mayer | } |
5378 | ec72e276 | aurel32 | t0 = tcg_temp_new(); |
5379 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5380 | 74d37793 | aurel32 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
5381 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5382 | 76a66253 | j_mayer | #endif
|
5383 | 76a66253 | j_mayer | } |
5384 | 76a66253 | j_mayer | |
5385 | 76a66253 | j_mayer | /* All 405 MAC instructions are translated here */
|
5386 | 636aa200 | Blue Swirl | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5387 | 636aa200 | Blue Swirl | int ra, int rb, int rt, int Rc) |
5388 | 76a66253 | j_mayer | { |
5389 | 182608d4 | aurel32 | TCGv t0, t1; |
5390 | 182608d4 | aurel32 | |
5391 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
5392 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
5393 | 182608d4 | aurel32 | |
5394 | 76a66253 | j_mayer | switch (opc3 & 0x0D) { |
5395 | 76a66253 | j_mayer | case 0x05: |
5396 | 76a66253 | j_mayer | /* macchw - macchw. - macchwo - macchwo. */
|
5397 | 76a66253 | j_mayer | /* macchws - macchws. - macchwso - macchwso. */
|
5398 | 76a66253 | j_mayer | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
|
5399 | 76a66253 | j_mayer | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
|
5400 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5401 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5402 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5403 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5404 | 76a66253 | j_mayer | break;
|
5405 | 76a66253 | j_mayer | case 0x04: |
5406 | 76a66253 | j_mayer | /* macchwu - macchwu. - macchwuo - macchwuo. */
|
5407 | 76a66253 | j_mayer | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
|
5408 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5409 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5410 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5411 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5412 | 76a66253 | j_mayer | break;
|
5413 | 76a66253 | j_mayer | case 0x01: |
5414 | 76a66253 | j_mayer | /* machhw - machhw. - machhwo - machhwo. */
|
5415 | 76a66253 | j_mayer | /* machhws - machhws. - machhwso - machhwso. */
|
5416 | 76a66253 | j_mayer | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
|
5417 | 76a66253 | j_mayer | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
|
5418 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5419 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
|
5420 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, t0); |
5421 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5422 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5423 | 76a66253 | j_mayer | break;
|
5424 | 76a66253 | j_mayer | case 0x00: |
5425 | 76a66253 | j_mayer | /* machhwu - machhwu. - machhwuo - machhwuo. */
|
5426 | 76a66253 | j_mayer | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
|
5427 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5428 | 182608d4 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
|
5429 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, t0); |
5430 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5431 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5432 | 76a66253 | j_mayer | break;
|
5433 | 76a66253 | j_mayer | case 0x0D: |
5434 | 76a66253 | j_mayer | /* maclhw - maclhw. - maclhwo - maclhwo. */
|
5435 | 76a66253 | j_mayer | /* maclhws - maclhws. - maclhwso - maclhwso. */
|
5436 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
|
5437 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
|
5438 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5439 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5440 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); |
5441 | 76a66253 | j_mayer | break;
|
5442 | 76a66253 | j_mayer | case 0x0C: |
5443 | 76a66253 | j_mayer | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
|
5444 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
|
5445 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5446 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5447 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); |
5448 | 76a66253 | j_mayer | break;
|
5449 | 76a66253 | j_mayer | } |
5450 | 76a66253 | j_mayer | if (opc2 & 0x04) { |
5451 | 182608d4 | aurel32 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */
|
5452 | 182608d4 | aurel32 | tcg_gen_mul_tl(t1, t0, t1); |
5453 | 182608d4 | aurel32 | if (opc2 & 0x02) { |
5454 | 182608d4 | aurel32 | /* nmultiply-and-accumulate (0x0E) */
|
5455 | 182608d4 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); |
5456 | 182608d4 | aurel32 | } else {
|
5457 | 182608d4 | aurel32 | /* multiply-and-accumulate (0x0C) */
|
5458 | 182608d4 | aurel32 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); |
5459 | 182608d4 | aurel32 | } |
5460 | 182608d4 | aurel32 | |
5461 | 182608d4 | aurel32 | if (opc3 & 0x12) { |
5462 | 182608d4 | aurel32 | /* Check overflow and/or saturate */
|
5463 | 182608d4 | aurel32 | int l1 = gen_new_label();
|
5464 | 182608d4 | aurel32 | |
5465 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5466 | 182608d4 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
5467 | 182608d4 | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
|
5468 | 182608d4 | aurel32 | } |
5469 | 182608d4 | aurel32 | if (opc3 & 0x01) { |
5470 | 182608d4 | aurel32 | /* Signed */
|
5471 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); |
5472 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
|
5473 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); |
5474 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
|
5475 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5476 | 182608d4 | aurel32 | /* Saturate */
|
5477 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
|
5478 | 182608d4 | aurel32 | tcg_gen_xori_tl(t0, t0, 0x7fffffff);
|
5479 | 182608d4 | aurel32 | } |
5480 | 182608d4 | aurel32 | } else {
|
5481 | 182608d4 | aurel32 | /* Unsigned */
|
5482 | 182608d4 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
5483 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5484 | 182608d4 | aurel32 | /* Saturate */
|
5485 | 182608d4 | aurel32 | tcg_gen_movi_tl(t0, UINT32_MAX); |
5486 | 182608d4 | aurel32 | } |
5487 | 182608d4 | aurel32 | } |
5488 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5489 | 182608d4 | aurel32 | /* Check overflow */
|
5490 | 182608d4 | aurel32 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
5491 | 182608d4 | aurel32 | } |
5492 | 182608d4 | aurel32 | gen_set_label(l1); |
5493 | 182608d4 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rt], t0); |
5494 | 182608d4 | aurel32 | } |
5495 | 182608d4 | aurel32 | } else {
|
5496 | 182608d4 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); |
5497 | 76a66253 | j_mayer | } |
5498 | 182608d4 | aurel32 | tcg_temp_free(t0); |
5499 | 182608d4 | aurel32 | tcg_temp_free(t1); |
5500 | 76a66253 | j_mayer | if (unlikely(Rc) != 0) { |
5501 | 76a66253 | j_mayer | /* Update Rc0 */
|
5502 | 182608d4 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
5503 | 76a66253 | j_mayer | } |
5504 | 76a66253 | j_mayer | } |
5505 | 76a66253 | j_mayer | |
5506 | a750fc0b | j_mayer | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
5507 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
5508 | 76a66253 | j_mayer | { \ |
5509 | 76a66253 | j_mayer | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
5510 | 76a66253 | j_mayer | rD(ctx->opcode), Rc(ctx->opcode)); \ |
5511 | 76a66253 | j_mayer | } |
5512 | 76a66253 | j_mayer | |
5513 | 76a66253 | j_mayer | /* macchw - macchw. */
|
5514 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
5515 | 76a66253 | j_mayer | /* macchwo - macchwo. */
|
5516 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
5517 | 76a66253 | j_mayer | /* macchws - macchws. */
|
5518 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
5519 | 76a66253 | j_mayer | /* macchwso - macchwso. */
|
5520 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
5521 | 76a66253 | j_mayer | /* macchwsu - macchwsu. */
|
5522 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
5523 | 76a66253 | j_mayer | /* macchwsuo - macchwsuo. */
|
5524 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
5525 | 76a66253 | j_mayer | /* macchwu - macchwu. */
|
5526 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
5527 | 76a66253 | j_mayer | /* macchwuo - macchwuo. */
|
5528 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
5529 | 76a66253 | j_mayer | /* machhw - machhw. */
|
5530 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
5531 | 76a66253 | j_mayer | /* machhwo - machhwo. */
|
5532 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
5533 | 76a66253 | j_mayer | /* machhws - machhws. */
|
5534 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
5535 | 76a66253 | j_mayer | /* machhwso - machhwso. */
|
5536 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
5537 | 76a66253 | j_mayer | /* machhwsu - machhwsu. */
|
5538 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
5539 | 76a66253 | j_mayer | /* machhwsuo - machhwsuo. */
|
5540 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
5541 | 76a66253 | j_mayer | /* machhwu - machhwu. */
|
5542 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
5543 | 76a66253 | j_mayer | /* machhwuo - machhwuo. */
|
5544 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
5545 | 76a66253 | j_mayer | /* maclhw - maclhw. */
|
5546 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
5547 | 76a66253 | j_mayer | /* maclhwo - maclhwo. */
|
5548 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
5549 | 76a66253 | j_mayer | /* maclhws - maclhws. */
|
5550 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
5551 | 76a66253 | j_mayer | /* maclhwso - maclhwso. */
|
5552 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
5553 | 76a66253 | j_mayer | /* maclhwu - maclhwu. */
|
5554 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
5555 | 76a66253 | j_mayer | /* maclhwuo - maclhwuo. */
|
5556 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
5557 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. */
|
5558 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
5559 | 76a66253 | j_mayer | /* maclhwsuo - maclhwsuo. */
|
5560 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
5561 | 76a66253 | j_mayer | /* nmacchw - nmacchw. */
|
5562 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
5563 | 76a66253 | j_mayer | /* nmacchwo - nmacchwo. */
|
5564 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
5565 | 76a66253 | j_mayer | /* nmacchws - nmacchws. */
|
5566 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
5567 | 76a66253 | j_mayer | /* nmacchwso - nmacchwso. */
|
5568 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
5569 | 76a66253 | j_mayer | /* nmachhw - nmachhw. */
|
5570 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
5571 | 76a66253 | j_mayer | /* nmachhwo - nmachhwo. */
|
5572 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
5573 | 76a66253 | j_mayer | /* nmachhws - nmachhws. */
|
5574 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
5575 | 76a66253 | j_mayer | /* nmachhwso - nmachhwso. */
|
5576 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
5577 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. */
|
5578 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
5579 | 76a66253 | j_mayer | /* nmaclhwo - nmaclhwo. */
|
5580 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
5581 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. */
|
5582 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
5583 | 76a66253 | j_mayer | /* nmaclhwso - nmaclhwso. */
|
5584 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
5585 | 76a66253 | j_mayer | |
5586 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5587 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
5588 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5589 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
5590 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5591 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
5592 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5593 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
5594 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5595 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
5596 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5597 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
5598 | 76a66253 | j_mayer | |
5599 | 76a66253 | j_mayer | /* mfdcr */
|
5600 | 99e300ef | Blue Swirl | static void gen_mfdcr(DisasContext *ctx) |
5601 | 76a66253 | j_mayer | { |
5602 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5603 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5604 | 76a66253 | j_mayer | #else
|
5605 | 06dca6a7 | aurel32 | TCGv dcrn; |
5606 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5607 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5608 | 76a66253 | j_mayer | return;
|
5609 | 76a66253 | j_mayer | } |
5610 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5611 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5612 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5613 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn); |
5614 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5615 | 76a66253 | j_mayer | #endif
|
5616 | 76a66253 | j_mayer | } |
5617 | 76a66253 | j_mayer | |
5618 | 76a66253 | j_mayer | /* mtdcr */
|
5619 | 99e300ef | Blue Swirl | static void gen_mtdcr(DisasContext *ctx) |
5620 | 76a66253 | j_mayer | { |
5621 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5622 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5623 | 76a66253 | j_mayer | #else
|
5624 | 06dca6a7 | aurel32 | TCGv dcrn; |
5625 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5626 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5627 | 76a66253 | j_mayer | return;
|
5628 | 76a66253 | j_mayer | } |
5629 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5630 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5631 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5632 | 06dca6a7 | aurel32 | gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]); |
5633 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5634 | a42bd6cc | j_mayer | #endif
|
5635 | a42bd6cc | j_mayer | } |
5636 | a42bd6cc | j_mayer | |
5637 | a42bd6cc | j_mayer | /* mfdcrx */
|
5638 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5639 | 99e300ef | Blue Swirl | static void gen_mfdcrx(DisasContext *ctx) |
5640 | a42bd6cc | j_mayer | { |
5641 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5642 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5643 | a42bd6cc | j_mayer | #else
|
5644 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5645 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5646 | a42bd6cc | j_mayer | return;
|
5647 | a42bd6cc | j_mayer | } |
5648 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5649 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5650 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5651 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5652 | a42bd6cc | j_mayer | #endif
|
5653 | a42bd6cc | j_mayer | } |
5654 | a42bd6cc | j_mayer | |
5655 | a42bd6cc | j_mayer | /* mtdcrx */
|
5656 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5657 | 99e300ef | Blue Swirl | static void gen_mtdcrx(DisasContext *ctx) |
5658 | a42bd6cc | j_mayer | { |
5659 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5660 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5661 | a42bd6cc | j_mayer | #else
|
5662 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5663 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5664 | a42bd6cc | j_mayer | return;
|
5665 | a42bd6cc | j_mayer | } |
5666 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5667 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5668 | 06dca6a7 | aurel32 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5669 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5670 | 76a66253 | j_mayer | #endif
|
5671 | 76a66253 | j_mayer | } |
5672 | 76a66253 | j_mayer | |
5673 | a750fc0b | j_mayer | /* mfdcrux (PPC 460) : user-mode access to DCR */
|
5674 | 99e300ef | Blue Swirl | static void gen_mfdcrux(DisasContext *ctx) |
5675 | a750fc0b | j_mayer | { |
5676 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5677 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5678 | 06dca6a7 | aurel32 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5679 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5680 | a750fc0b | j_mayer | } |
5681 | a750fc0b | j_mayer | |
5682 | a750fc0b | j_mayer | /* mtdcrux (PPC 460) : user-mode access to DCR */
|
5683 | 99e300ef | Blue Swirl | static void gen_mtdcrux(DisasContext *ctx) |
5684 | a750fc0b | j_mayer | { |
5685 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5686 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5687 | 06dca6a7 | aurel32 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5688 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5689 | a750fc0b | j_mayer | } |
5690 | a750fc0b | j_mayer | |
5691 | 76a66253 | j_mayer | /* dccci */
|
5692 | 99e300ef | Blue Swirl | static void gen_dccci(DisasContext *ctx) |
5693 | 76a66253 | j_mayer | { |
5694 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5695 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5696 | 76a66253 | j_mayer | #else
|
5697 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5698 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5699 | 76a66253 | j_mayer | return;
|
5700 | 76a66253 | j_mayer | } |
5701 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5702 | 76a66253 | j_mayer | #endif
|
5703 | 76a66253 | j_mayer | } |
5704 | 76a66253 | j_mayer | |
5705 | 76a66253 | j_mayer | /* dcread */
|
5706 | 99e300ef | Blue Swirl | static void gen_dcread(DisasContext *ctx) |
5707 | 76a66253 | j_mayer | { |
5708 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5709 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5710 | 76a66253 | j_mayer | #else
|
5711 | b61f2753 | aurel32 | TCGv EA, val; |
5712 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5713 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5714 | 76a66253 | j_mayer | return;
|
5715 | 76a66253 | j_mayer | } |
5716 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
5717 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
5718 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
5719 | a7812ae4 | pbrook | val = tcg_temp_new(); |
5720 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, val, EA); |
5721 | b61f2753 | aurel32 | tcg_temp_free(val); |
5722 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
5723 | b61f2753 | aurel32 | tcg_temp_free(EA); |
5724 | 76a66253 | j_mayer | #endif
|
5725 | 76a66253 | j_mayer | } |
5726 | 76a66253 | j_mayer | |
5727 | 76a66253 | j_mayer | /* icbt */
|
5728 | e8eaa2c0 | Blue Swirl | static void gen_icbt_40x(DisasContext *ctx) |
5729 | 76a66253 | j_mayer | { |
5730 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5731 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
5732 | 76a66253 | j_mayer | * but does not generate any exception
|
5733 | 76a66253 | j_mayer | */
|
5734 | 76a66253 | j_mayer | } |
5735 | 76a66253 | j_mayer | |
5736 | 76a66253 | j_mayer | /* iccci */
|
5737 | 99e300ef | Blue Swirl | static void gen_iccci(DisasContext *ctx) |
5738 | 76a66253 | j_mayer | { |
5739 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5740 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5741 | 76a66253 | j_mayer | #else
|
5742 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5743 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5744 | 76a66253 | j_mayer | return;
|
5745 | 76a66253 | j_mayer | } |
5746 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5747 | 76a66253 | j_mayer | #endif
|
5748 | 76a66253 | j_mayer | } |
5749 | 76a66253 | j_mayer | |
5750 | 76a66253 | j_mayer | /* icread */
|
5751 | 99e300ef | Blue Swirl | static void gen_icread(DisasContext *ctx) |
5752 | 76a66253 | j_mayer | { |
5753 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5754 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5755 | 76a66253 | j_mayer | #else
|
5756 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5757 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5758 | 76a66253 | j_mayer | return;
|
5759 | 76a66253 | j_mayer | } |
5760 | 76a66253 | j_mayer | /* interpreted as no-op */
|
5761 | 76a66253 | j_mayer | #endif
|
5762 | 76a66253 | j_mayer | } |
5763 | 76a66253 | j_mayer | |
5764 | 76db3ba4 | aurel32 | /* rfci (mem_idx only) */
|
5765 | e8eaa2c0 | Blue Swirl | static void gen_rfci_40x(DisasContext *ctx) |
5766 | a42bd6cc | j_mayer | { |
5767 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5768 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5769 | a42bd6cc | j_mayer | #else
|
5770 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5771 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5772 | a42bd6cc | j_mayer | return;
|
5773 | a42bd6cc | j_mayer | } |
5774 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5775 | d72a19f7 | aurel32 | gen_helper_40x_rfci(); |
5776 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5777 | a42bd6cc | j_mayer | #endif
|
5778 | a42bd6cc | j_mayer | } |
5779 | a42bd6cc | j_mayer | |
5780 | 99e300ef | Blue Swirl | static void gen_rfci(DisasContext *ctx) |
5781 | a42bd6cc | j_mayer | { |
5782 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5783 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5784 | a42bd6cc | j_mayer | #else
|
5785 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5786 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5787 | a42bd6cc | j_mayer | return;
|
5788 | a42bd6cc | j_mayer | } |
5789 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5790 | d72a19f7 | aurel32 | gen_helper_rfci(); |
5791 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5792 | a42bd6cc | j_mayer | #endif
|
5793 | a42bd6cc | j_mayer | } |
5794 | a42bd6cc | j_mayer | |
5795 | a42bd6cc | j_mayer | /* BookE specific */
|
5796 | 99e300ef | Blue Swirl | |
5797 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
5798 | 99e300ef | Blue Swirl | static void gen_rfdi(DisasContext *ctx) |
5799 | 76a66253 | j_mayer | { |
5800 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5801 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5802 | 76a66253 | j_mayer | #else
|
5803 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5804 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5805 | 76a66253 | j_mayer | return;
|
5806 | 76a66253 | j_mayer | } |
5807 | 76a66253 | j_mayer | /* Restore CPU state */
|
5808 | d72a19f7 | aurel32 | gen_helper_rfdi(); |
5809 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5810 | 76a66253 | j_mayer | #endif
|
5811 | 76a66253 | j_mayer | } |
5812 | 76a66253 | j_mayer | |
5813 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5814 | 99e300ef | Blue Swirl | static void gen_rfmci(DisasContext *ctx) |
5815 | a42bd6cc | j_mayer | { |
5816 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5817 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5818 | a42bd6cc | j_mayer | #else
|
5819 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5820 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5821 | a42bd6cc | j_mayer | return;
|
5822 | a42bd6cc | j_mayer | } |
5823 | a42bd6cc | j_mayer | /* Restore CPU state */
|
5824 | d72a19f7 | aurel32 | gen_helper_rfmci(); |
5825 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5826 | a42bd6cc | j_mayer | #endif
|
5827 | a42bd6cc | j_mayer | } |
5828 | 5eb7995e | j_mayer | |
5829 | d9bce9d9 | j_mayer | /* TLB management - PowerPC 405 implementation */
|
5830 | e8eaa2c0 | Blue Swirl | |
5831 | 54623277 | Blue Swirl | /* tlbre */
|
5832 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_40x(DisasContext *ctx) |
5833 | 76a66253 | j_mayer | { |
5834 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5835 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5836 | 76a66253 | j_mayer | #else
|
5837 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5838 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5839 | 76a66253 | j_mayer | return;
|
5840 | 76a66253 | j_mayer | } |
5841 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5842 | 76a66253 | j_mayer | case 0: |
5843 | 74d37793 | aurel32 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5844 | 76a66253 | j_mayer | break;
|
5845 | 76a66253 | j_mayer | case 1: |
5846 | 74d37793 | aurel32 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5847 | 76a66253 | j_mayer | break;
|
5848 | 76a66253 | j_mayer | default:
|
5849 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5850 | 76a66253 | j_mayer | break;
|
5851 | 9a64fbe4 | bellard | } |
5852 | 76a66253 | j_mayer | #endif
|
5853 | 76a66253 | j_mayer | } |
5854 | 76a66253 | j_mayer | |
5855 | d9bce9d9 | j_mayer | /* tlbsx - tlbsx. */
|
5856 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_40x(DisasContext *ctx) |
5857 | 76a66253 | j_mayer | { |
5858 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5859 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5860 | 76a66253 | j_mayer | #else
|
5861 | 74d37793 | aurel32 | TCGv t0; |
5862 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5863 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5864 | 76a66253 | j_mayer | return;
|
5865 | 76a66253 | j_mayer | } |
5866 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5867 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5868 | 74d37793 | aurel32 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5869 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5870 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
5871 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
5872 | 74d37793 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
5873 | 74d37793 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
5874 | 74d37793 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
5875 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
5876 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
5877 | 74d37793 | aurel32 | gen_set_label(l1); |
5878 | 74d37793 | aurel32 | } |
5879 | 76a66253 | j_mayer | #endif
|
5880 | 79aceca5 | bellard | } |
5881 | 79aceca5 | bellard | |
5882 | 76a66253 | j_mayer | /* tlbwe */
|
5883 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_40x(DisasContext *ctx) |
5884 | 79aceca5 | bellard | { |
5885 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5886 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5887 | 76a66253 | j_mayer | #else
|
5888 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5889 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5890 | 76a66253 | j_mayer | return;
|
5891 | 76a66253 | j_mayer | } |
5892 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
5893 | 76a66253 | j_mayer | case 0: |
5894 | 74d37793 | aurel32 | gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5895 | 76a66253 | j_mayer | break;
|
5896 | 76a66253 | j_mayer | case 1: |
5897 | 74d37793 | aurel32 | gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5898 | 76a66253 | j_mayer | break;
|
5899 | 76a66253 | j_mayer | default:
|
5900 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5901 | 76a66253 | j_mayer | break;
|
5902 | 9a64fbe4 | bellard | } |
5903 | 76a66253 | j_mayer | #endif
|
5904 | 76a66253 | j_mayer | } |
5905 | 76a66253 | j_mayer | |
5906 | a4bb6c3e | j_mayer | /* TLB management - PowerPC 440 implementation */
|
5907 | e8eaa2c0 | Blue Swirl | |
5908 | 54623277 | Blue Swirl | /* tlbre */
|
5909 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_440(DisasContext *ctx) |
5910 | 5eb7995e | j_mayer | { |
5911 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5912 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5913 | 5eb7995e | j_mayer | #else
|
5914 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5915 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5916 | 5eb7995e | j_mayer | return;
|
5917 | 5eb7995e | j_mayer | } |
5918 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5919 | 5eb7995e | j_mayer | case 0: |
5920 | 5eb7995e | j_mayer | case 1: |
5921 | 5eb7995e | j_mayer | case 2: |
5922 | 74d37793 | aurel32 | { |
5923 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
5924 | 5823947f | Edgar E. Iglesias | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]); |
5925 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
5926 | 74d37793 | aurel32 | } |
5927 | 5eb7995e | j_mayer | break;
|
5928 | 5eb7995e | j_mayer | default:
|
5929 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5930 | 5eb7995e | j_mayer | break;
|
5931 | 5eb7995e | j_mayer | } |
5932 | 5eb7995e | j_mayer | #endif
|
5933 | 5eb7995e | j_mayer | } |
5934 | 5eb7995e | j_mayer | |
5935 | 5eb7995e | j_mayer | /* tlbsx - tlbsx. */
|
5936 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_440(DisasContext *ctx) |
5937 | 5eb7995e | j_mayer | { |
5938 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5939 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5940 | 5eb7995e | j_mayer | #else
|
5941 | 74d37793 | aurel32 | TCGv t0; |
5942 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5943 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5944 | 5eb7995e | j_mayer | return;
|
5945 | 5eb7995e | j_mayer | } |
5946 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5947 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5948 | 74d37793 | aurel32 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5949 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5950 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
5951 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
5952 | 74d37793 | aurel32 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
|
5953 | 74d37793 | aurel32 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
5954 | 74d37793 | aurel32 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
5955 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
5956 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
5957 | 74d37793 | aurel32 | gen_set_label(l1); |
5958 | 74d37793 | aurel32 | } |
5959 | 5eb7995e | j_mayer | #endif
|
5960 | 5eb7995e | j_mayer | } |
5961 | 5eb7995e | j_mayer | |
5962 | 5eb7995e | j_mayer | /* tlbwe */
|
5963 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_440(DisasContext *ctx) |
5964 | 5eb7995e | j_mayer | { |
5965 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5966 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5967 | 5eb7995e | j_mayer | #else
|
5968 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5969 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5970 | 5eb7995e | j_mayer | return;
|
5971 | 5eb7995e | j_mayer | } |
5972 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
5973 | 5eb7995e | j_mayer | case 0: |
5974 | 5eb7995e | j_mayer | case 1: |
5975 | 5eb7995e | j_mayer | case 2: |
5976 | 74d37793 | aurel32 | { |
5977 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
5978 | 74d37793 | aurel32 | gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
5979 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
5980 | 74d37793 | aurel32 | } |
5981 | 5eb7995e | j_mayer | break;
|
5982 | 5eb7995e | j_mayer | default:
|
5983 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5984 | 5eb7995e | j_mayer | break;
|
5985 | 5eb7995e | j_mayer | } |
5986 | 5eb7995e | j_mayer | #endif
|
5987 | 5eb7995e | j_mayer | } |
5988 | 5eb7995e | j_mayer | |
5989 | 01662f3e | Alexander Graf | /* TLB management - PowerPC BookE 2.06 implementation */
|
5990 | 01662f3e | Alexander Graf | |
5991 | 01662f3e | Alexander Graf | /* tlbre */
|
5992 | 01662f3e | Alexander Graf | static void gen_tlbre_booke206(DisasContext *ctx) |
5993 | 01662f3e | Alexander Graf | { |
5994 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
5995 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5996 | 01662f3e | Alexander Graf | #else
|
5997 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
5998 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5999 | 01662f3e | Alexander Graf | return;
|
6000 | 01662f3e | Alexander Graf | } |
6001 | 01662f3e | Alexander Graf | |
6002 | 01662f3e | Alexander Graf | gen_helper_booke206_tlbre(); |
6003 | 01662f3e | Alexander Graf | #endif
|
6004 | 01662f3e | Alexander Graf | } |
6005 | 01662f3e | Alexander Graf | |
6006 | 01662f3e | Alexander Graf | /* tlbsx - tlbsx. */
|
6007 | 01662f3e | Alexander Graf | static void gen_tlbsx_booke206(DisasContext *ctx) |
6008 | 01662f3e | Alexander Graf | { |
6009 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6010 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6011 | 01662f3e | Alexander Graf | #else
|
6012 | 01662f3e | Alexander Graf | TCGv t0; |
6013 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6014 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6015 | 01662f3e | Alexander Graf | return;
|
6016 | 01662f3e | Alexander Graf | } |
6017 | 01662f3e | Alexander Graf | |
6018 | 01662f3e | Alexander Graf | if (rA(ctx->opcode)) {
|
6019 | 01662f3e | Alexander Graf | t0 = tcg_temp_new(); |
6020 | 01662f3e | Alexander Graf | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); |
6021 | 01662f3e | Alexander Graf | } else {
|
6022 | 01662f3e | Alexander Graf | t0 = tcg_const_tl(0);
|
6023 | 01662f3e | Alexander Graf | } |
6024 | 01662f3e | Alexander Graf | |
6025 | 01662f3e | Alexander Graf | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); |
6026 | 01662f3e | Alexander Graf | gen_helper_booke206_tlbsx(t0); |
6027 | 01662f3e | Alexander Graf | #endif
|
6028 | 01662f3e | Alexander Graf | } |
6029 | 01662f3e | Alexander Graf | |
6030 | 01662f3e | Alexander Graf | /* tlbwe */
|
6031 | 01662f3e | Alexander Graf | static void gen_tlbwe_booke206(DisasContext *ctx) |
6032 | 01662f3e | Alexander Graf | { |
6033 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6034 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6035 | 01662f3e | Alexander Graf | #else
|
6036 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6037 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6038 | 01662f3e | Alexander Graf | return;
|
6039 | 01662f3e | Alexander Graf | } |
6040 | 01662f3e | Alexander Graf | gen_helper_booke206_tlbwe(); |
6041 | 01662f3e | Alexander Graf | #endif
|
6042 | 01662f3e | Alexander Graf | } |
6043 | 01662f3e | Alexander Graf | |
6044 | 01662f3e | Alexander Graf | static void gen_tlbivax_booke206(DisasContext *ctx) |
6045 | 01662f3e | Alexander Graf | { |
6046 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6047 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6048 | 01662f3e | Alexander Graf | #else
|
6049 | 01662f3e | Alexander Graf | TCGv t0; |
6050 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6051 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6052 | 01662f3e | Alexander Graf | return;
|
6053 | 01662f3e | Alexander Graf | } |
6054 | 01662f3e | Alexander Graf | |
6055 | 01662f3e | Alexander Graf | t0 = tcg_temp_new(); |
6056 | 01662f3e | Alexander Graf | gen_addr_reg_index(ctx, t0); |
6057 | 01662f3e | Alexander Graf | |
6058 | 01662f3e | Alexander Graf | gen_helper_booke206_tlbivax(t0); |
6059 | 01662f3e | Alexander Graf | #endif
|
6060 | 01662f3e | Alexander Graf | } |
6061 | 01662f3e | Alexander Graf | |
6062 | 01662f3e | Alexander Graf | |
6063 | 76a66253 | j_mayer | /* wrtee */
|
6064 | 99e300ef | Blue Swirl | static void gen_wrtee(DisasContext *ctx) |
6065 | 76a66253 | j_mayer | { |
6066 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6067 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6068 | 76a66253 | j_mayer | #else
|
6069 | 6527f6ea | aurel32 | TCGv t0; |
6070 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6071 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6072 | 76a66253 | j_mayer | return;
|
6073 | 76a66253 | j_mayer | } |
6074 | 6527f6ea | aurel32 | t0 = tcg_temp_new(); |
6075 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
|
6076 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
6077 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
6078 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
6079 | dee96f6c | j_mayer | /* Stop translation to have a chance to raise an exception
|
6080 | dee96f6c | j_mayer | * if we just set msr_ee to 1
|
6081 | dee96f6c | j_mayer | */
|
6082 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
6083 | 76a66253 | j_mayer | #endif
|
6084 | 76a66253 | j_mayer | } |
6085 | 76a66253 | j_mayer | |
6086 | 76a66253 | j_mayer | /* wrteei */
|
6087 | 99e300ef | Blue Swirl | static void gen_wrteei(DisasContext *ctx) |
6088 | 76a66253 | j_mayer | { |
6089 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6090 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6091 | 76a66253 | j_mayer | #else
|
6092 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6093 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6094 | 76a66253 | j_mayer | return;
|
6095 | 76a66253 | j_mayer | } |
6096 | fbe73008 | Baojun Wang | if (ctx->opcode & 0x00008000) { |
6097 | 6527f6ea | aurel32 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
|
6098 | 6527f6ea | aurel32 | /* Stop translation to have a chance to raise an exception */
|
6099 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
6100 | 6527f6ea | aurel32 | } else {
|
6101 | 1b6e5f99 | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
6102 | 6527f6ea | aurel32 | } |
6103 | 76a66253 | j_mayer | #endif
|
6104 | 76a66253 | j_mayer | } |
6105 | 76a66253 | j_mayer | |
6106 | 08e46e54 | j_mayer | /* PowerPC 440 specific instructions */
|
6107 | 99e300ef | Blue Swirl | |
6108 | 54623277 | Blue Swirl | /* dlmzb */
|
6109 | 99e300ef | Blue Swirl | static void gen_dlmzb(DisasContext *ctx) |
6110 | 76a66253 | j_mayer | { |
6111 | ef0d51af | aurel32 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
6112 | ef0d51af | aurel32 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
6113 | ef0d51af | aurel32 | cpu_gpr[rB(ctx->opcode)], t0); |
6114 | ef0d51af | aurel32 | tcg_temp_free_i32(t0); |
6115 | 76a66253 | j_mayer | } |
6116 | 76a66253 | j_mayer | |
6117 | 76a66253 | j_mayer | /* mbar replaces eieio on 440 */
|
6118 | 99e300ef | Blue Swirl | static void gen_mbar(DisasContext *ctx) |
6119 | 76a66253 | j_mayer | { |
6120 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6121 | 76a66253 | j_mayer | } |
6122 | 76a66253 | j_mayer | |
6123 | 76a66253 | j_mayer | /* msync replaces sync on 440 */
|
6124 | 99e300ef | Blue Swirl | static void gen_msync(DisasContext *ctx) |
6125 | 76a66253 | j_mayer | { |
6126 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6127 | 76a66253 | j_mayer | } |
6128 | 76a66253 | j_mayer | |
6129 | 76a66253 | j_mayer | /* icbt */
|
6130 | e8eaa2c0 | Blue Swirl | static void gen_icbt_440(DisasContext *ctx) |
6131 | 76a66253 | j_mayer | { |
6132 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6133 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
6134 | 76a66253 | j_mayer | * but does not generate any exception
|
6135 | 76a66253 | j_mayer | */
|
6136 | 79aceca5 | bellard | } |
6137 | 79aceca5 | bellard | |
6138 | a9d9eb8f | j_mayer | /*** Altivec vector extension ***/
|
6139 | a9d9eb8f | j_mayer | /* Altivec registers moves */
|
6140 | a9d9eb8f | j_mayer | |
6141 | 636aa200 | Blue Swirl | static inline TCGv_ptr gen_avr_ptr(int reg) |
6142 | 564e571a | aurel32 | { |
6143 | e4704b3b | aurel32 | TCGv_ptr r = tcg_temp_new_ptr(); |
6144 | 564e571a | aurel32 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6145 | 564e571a | aurel32 | return r;
|
6146 | 564e571a | aurel32 | } |
6147 | 564e571a | aurel32 | |
6148 | a9d9eb8f | j_mayer | #define GEN_VR_LDX(name, opc2, opc3) \
|
6149 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6150 | a9d9eb8f | j_mayer | { \ |
6151 | fe1e5c53 | aurel32 | TCGv EA; \ |
6152 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
6153 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6154 | a9d9eb8f | j_mayer | return; \
|
6155 | a9d9eb8f | j_mayer | } \ |
6156 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6157 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6158 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6159 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6160 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6161 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6162 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6163 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6164 | fe1e5c53 | aurel32 | } else { \
|
6165 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6166 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6167 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6168 | fe1e5c53 | aurel32 | } \ |
6169 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6170 | a9d9eb8f | j_mayer | } |
6171 | a9d9eb8f | j_mayer | |
6172 | a9d9eb8f | j_mayer | #define GEN_VR_STX(name, opc2, opc3) \
|
6173 | 99e300ef | Blue Swirl | static void gen_st##name(DisasContext *ctx) \ |
6174 | a9d9eb8f | j_mayer | { \ |
6175 | fe1e5c53 | aurel32 | TCGv EA; \ |
6176 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
6177 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6178 | a9d9eb8f | j_mayer | return; \
|
6179 | a9d9eb8f | j_mayer | } \ |
6180 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6181 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6182 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6183 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6184 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6185 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6186 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6187 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6188 | fe1e5c53 | aurel32 | } else { \
|
6189 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6190 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6191 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6192 | fe1e5c53 | aurel32 | } \ |
6193 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6194 | a9d9eb8f | j_mayer | } |
6195 | a9d9eb8f | j_mayer | |
6196 | cbfb6ae9 | aurel32 | #define GEN_VR_LVE(name, opc2, opc3) \
|
6197 | 99e300ef | Blue Swirl | static void gen_lve##name(DisasContext *ctx) \ |
6198 | cbfb6ae9 | aurel32 | { \ |
6199 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6200 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6201 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6202 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6203 | cbfb6ae9 | aurel32 | return; \
|
6204 | cbfb6ae9 | aurel32 | } \ |
6205 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6206 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6207 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6208 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6209 | cbfb6ae9 | aurel32 | gen_helper_lve##name (rs, EA); \ |
6210 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6211 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6212 | cbfb6ae9 | aurel32 | } |
6213 | cbfb6ae9 | aurel32 | |
6214 | cbfb6ae9 | aurel32 | #define GEN_VR_STVE(name, opc2, opc3) \
|
6215 | 99e300ef | Blue Swirl | static void gen_stve##name(DisasContext *ctx) \ |
6216 | cbfb6ae9 | aurel32 | { \ |
6217 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6218 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6219 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6220 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6221 | cbfb6ae9 | aurel32 | return; \
|
6222 | cbfb6ae9 | aurel32 | } \ |
6223 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6224 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6225 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6226 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6227 | cbfb6ae9 | aurel32 | gen_helper_stve##name (rs, EA); \ |
6228 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6229 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6230 | cbfb6ae9 | aurel32 | } |
6231 | cbfb6ae9 | aurel32 | |
6232 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvx, 0x07, 0x03); |
6233 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
|
6234 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
6235 | a9d9eb8f | j_mayer | |
6236 | cbfb6ae9 | aurel32 | GEN_VR_LVE(bx, 0x07, 0x00); |
6237 | cbfb6ae9 | aurel32 | GEN_VR_LVE(hx, 0x07, 0x01); |
6238 | cbfb6ae9 | aurel32 | GEN_VR_LVE(wx, 0x07, 0x02); |
6239 | cbfb6ae9 | aurel32 | |
6240 | fe1e5c53 | aurel32 | GEN_VR_STX(svx, 0x07, 0x07); |
6241 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
|
6242 | fe1e5c53 | aurel32 | GEN_VR_STX(svxl, 0x07, 0x0F); |
6243 | a9d9eb8f | j_mayer | |
6244 | cbfb6ae9 | aurel32 | GEN_VR_STVE(bx, 0x07, 0x04); |
6245 | cbfb6ae9 | aurel32 | GEN_VR_STVE(hx, 0x07, 0x05); |
6246 | cbfb6ae9 | aurel32 | GEN_VR_STVE(wx, 0x07, 0x06); |
6247 | cbfb6ae9 | aurel32 | |
6248 | 99e300ef | Blue Swirl | static void gen_lvsl(DisasContext *ctx) |
6249 | bf8d8ded | aurel32 | { |
6250 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6251 | bf8d8ded | aurel32 | TCGv EA; |
6252 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6253 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6254 | bf8d8ded | aurel32 | return;
|
6255 | bf8d8ded | aurel32 | } |
6256 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6257 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6258 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6259 | bf8d8ded | aurel32 | gen_helper_lvsl(rd, EA); |
6260 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6261 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6262 | bf8d8ded | aurel32 | } |
6263 | bf8d8ded | aurel32 | |
6264 | 99e300ef | Blue Swirl | static void gen_lvsr(DisasContext *ctx) |
6265 | bf8d8ded | aurel32 | { |
6266 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6267 | bf8d8ded | aurel32 | TCGv EA; |
6268 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6269 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6270 | bf8d8ded | aurel32 | return;
|
6271 | bf8d8ded | aurel32 | } |
6272 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6273 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6274 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6275 | bf8d8ded | aurel32 | gen_helper_lvsr(rd, EA); |
6276 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6277 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6278 | bf8d8ded | aurel32 | } |
6279 | bf8d8ded | aurel32 | |
6280 | 99e300ef | Blue Swirl | static void gen_mfvscr(DisasContext *ctx) |
6281 | 785f451b | aurel32 | { |
6282 | 785f451b | aurel32 | TCGv_i32 t; |
6283 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6284 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6285 | 785f451b | aurel32 | return;
|
6286 | 785f451b | aurel32 | } |
6287 | 785f451b | aurel32 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
|
6288 | 785f451b | aurel32 | t = tcg_temp_new_i32(); |
6289 | 785f451b | aurel32 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); |
6290 | 785f451b | aurel32 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
6291 | fce5ecb7 | aurel32 | tcg_temp_free_i32(t); |
6292 | 785f451b | aurel32 | } |
6293 | 785f451b | aurel32 | |
6294 | 99e300ef | Blue Swirl | static void gen_mtvscr(DisasContext *ctx) |
6295 | 785f451b | aurel32 | { |
6296 | 6e87b7c7 | aurel32 | TCGv_ptr p; |
6297 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6298 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6299 | 785f451b | aurel32 | return;
|
6300 | 785f451b | aurel32 | } |
6301 | 6e87b7c7 | aurel32 | p = gen_avr_ptr(rD(ctx->opcode)); |
6302 | 6e87b7c7 | aurel32 | gen_helper_mtvscr(p); |
6303 | 6e87b7c7 | aurel32 | tcg_temp_free_ptr(p); |
6304 | 785f451b | aurel32 | } |
6305 | 785f451b | aurel32 | |
6306 | 7a9b96cf | aurel32 | /* Logical operations */
|
6307 | 7a9b96cf | aurel32 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
6308 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6309 | 7a9b96cf | aurel32 | { \ |
6310 | 7a9b96cf | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6311 | 7a9b96cf | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6312 | 7a9b96cf | aurel32 | return; \
|
6313 | 7a9b96cf | aurel32 | } \ |
6314 | 7a9b96cf | aurel32 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ |
6315 | 7a9b96cf | aurel32 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ |
6316 | 7a9b96cf | aurel32 | } |
6317 | 7a9b96cf | aurel32 | |
6318 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); |
6319 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); |
6320 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); |
6321 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); |
6322 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); |
6323 | 7a9b96cf | aurel32 | |
6324 | 8e27dd6f | aurel32 | #define GEN_VXFORM(name, opc2, opc3) \
|
6325 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6326 | 8e27dd6f | aurel32 | { \ |
6327 | 8e27dd6f | aurel32 | TCGv_ptr ra, rb, rd; \ |
6328 | 8e27dd6f | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6329 | 8e27dd6f | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6330 | 8e27dd6f | aurel32 | return; \
|
6331 | 8e27dd6f | aurel32 | } \ |
6332 | 8e27dd6f | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6333 | 8e27dd6f | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6334 | 8e27dd6f | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6335 | 8e27dd6f | aurel32 | gen_helper_##name (rd, ra, rb); \ |
6336 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(ra); \ |
6337 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rb); \ |
6338 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rd); \ |
6339 | 8e27dd6f | aurel32 | } |
6340 | 8e27dd6f | aurel32 | |
6341 | 7872c51c | aurel32 | GEN_VXFORM(vaddubm, 0, 0); |
6342 | 7872c51c | aurel32 | GEN_VXFORM(vadduhm, 0, 1); |
6343 | 7872c51c | aurel32 | GEN_VXFORM(vadduwm, 0, 2); |
6344 | 7872c51c | aurel32 | GEN_VXFORM(vsububm, 0, 16); |
6345 | 7872c51c | aurel32 | GEN_VXFORM(vsubuhm, 0, 17); |
6346 | 7872c51c | aurel32 | GEN_VXFORM(vsubuwm, 0, 18); |
6347 | e4039339 | aurel32 | GEN_VXFORM(vmaxub, 1, 0); |
6348 | e4039339 | aurel32 | GEN_VXFORM(vmaxuh, 1, 1); |
6349 | e4039339 | aurel32 | GEN_VXFORM(vmaxuw, 1, 2); |
6350 | e4039339 | aurel32 | GEN_VXFORM(vmaxsb, 1, 4); |
6351 | e4039339 | aurel32 | GEN_VXFORM(vmaxsh, 1, 5); |
6352 | e4039339 | aurel32 | GEN_VXFORM(vmaxsw, 1, 6); |
6353 | e4039339 | aurel32 | GEN_VXFORM(vminub, 1, 8); |
6354 | e4039339 | aurel32 | GEN_VXFORM(vminuh, 1, 9); |
6355 | e4039339 | aurel32 | GEN_VXFORM(vminuw, 1, 10); |
6356 | e4039339 | aurel32 | GEN_VXFORM(vminsb, 1, 12); |
6357 | e4039339 | aurel32 | GEN_VXFORM(vminsh, 1, 13); |
6358 | e4039339 | aurel32 | GEN_VXFORM(vminsw, 1, 14); |
6359 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgub, 1, 16); |
6360 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguh, 1, 17); |
6361 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguw, 1, 18); |
6362 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsb, 1, 20); |
6363 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsh, 1, 21); |
6364 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsw, 1, 22); |
6365 | 3b430048 | aurel32 | GEN_VXFORM(vmrghb, 6, 0); |
6366 | 3b430048 | aurel32 | GEN_VXFORM(vmrghh, 6, 1); |
6367 | 3b430048 | aurel32 | GEN_VXFORM(vmrghw, 6, 2); |
6368 | 3b430048 | aurel32 | GEN_VXFORM(vmrglb, 6, 4); |
6369 | 3b430048 | aurel32 | GEN_VXFORM(vmrglh, 6, 5); |
6370 | 3b430048 | aurel32 | GEN_VXFORM(vmrglw, 6, 6); |
6371 | 2c277908 | aurel32 | GEN_VXFORM(vmuloub, 4, 0); |
6372 | 2c277908 | aurel32 | GEN_VXFORM(vmulouh, 4, 1); |
6373 | 2c277908 | aurel32 | GEN_VXFORM(vmulosb, 4, 4); |
6374 | 2c277908 | aurel32 | GEN_VXFORM(vmulosh, 4, 5); |
6375 | 2c277908 | aurel32 | GEN_VXFORM(vmuleub, 4, 8); |
6376 | 2c277908 | aurel32 | GEN_VXFORM(vmuleuh, 4, 9); |
6377 | 2c277908 | aurel32 | GEN_VXFORM(vmulesb, 4, 12); |
6378 | 2c277908 | aurel32 | GEN_VXFORM(vmulesh, 4, 13); |
6379 | d79f0809 | aurel32 | GEN_VXFORM(vslb, 2, 4); |
6380 | d79f0809 | aurel32 | GEN_VXFORM(vslh, 2, 5); |
6381 | d79f0809 | aurel32 | GEN_VXFORM(vslw, 2, 6); |
6382 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrb, 2, 8); |
6383 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrh, 2, 9); |
6384 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrw, 2, 10); |
6385 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrab, 2, 12); |
6386 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrah, 2, 13); |
6387 | 07ef34c3 | aurel32 | GEN_VXFORM(vsraw, 2, 14); |
6388 | 7b239bec | aurel32 | GEN_VXFORM(vslo, 6, 16); |
6389 | 7b239bec | aurel32 | GEN_VXFORM(vsro, 6, 17); |
6390 | e343da72 | aurel32 | GEN_VXFORM(vaddcuw, 0, 6); |
6391 | e343da72 | aurel32 | GEN_VXFORM(vsubcuw, 0, 22); |
6392 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddubs, 0, 8); |
6393 | 5ab09f33 | aurel32 | GEN_VXFORM(vadduhs, 0, 9); |
6394 | 5ab09f33 | aurel32 | GEN_VXFORM(vadduws, 0, 10); |
6395 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddsbs, 0, 12); |
6396 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddshs, 0, 13); |
6397 | 5ab09f33 | aurel32 | GEN_VXFORM(vaddsws, 0, 14); |
6398 | 5ab09f33 | aurel32 | GEN_VXFORM(vsububs, 0, 24); |
6399 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubuhs, 0, 25); |
6400 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubuws, 0, 26); |
6401 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubsbs, 0, 28); |
6402 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubshs, 0, 29); |
6403 | 5ab09f33 | aurel32 | GEN_VXFORM(vsubsws, 0, 30); |
6404 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlb, 2, 0); |
6405 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlh, 2, 1); |
6406 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlw, 2, 2); |
6407 | d9430add | aurel32 | GEN_VXFORM(vsl, 2, 7); |
6408 | d9430add | aurel32 | GEN_VXFORM(vsr, 2, 11); |
6409 | 5335a145 | aurel32 | GEN_VXFORM(vpkuhum, 7, 0); |
6410 | 5335a145 | aurel32 | GEN_VXFORM(vpkuwum, 7, 1); |
6411 | 5335a145 | aurel32 | GEN_VXFORM(vpkuhus, 7, 2); |
6412 | 5335a145 | aurel32 | GEN_VXFORM(vpkuwus, 7, 3); |
6413 | 5335a145 | aurel32 | GEN_VXFORM(vpkshus, 7, 4); |
6414 | 5335a145 | aurel32 | GEN_VXFORM(vpkswus, 7, 5); |
6415 | 5335a145 | aurel32 | GEN_VXFORM(vpkshss, 7, 6); |
6416 | 5335a145 | aurel32 | GEN_VXFORM(vpkswss, 7, 7); |
6417 | 1dd9ffb9 | aurel32 | GEN_VXFORM(vpkpx, 7, 12); |
6418 | 8142cddd | aurel32 | GEN_VXFORM(vsum4ubs, 4, 24); |
6419 | 8142cddd | aurel32 | GEN_VXFORM(vsum4sbs, 4, 28); |
6420 | 8142cddd | aurel32 | GEN_VXFORM(vsum4shs, 4, 25); |
6421 | 8142cddd | aurel32 | GEN_VXFORM(vsum2sws, 4, 26); |
6422 | 8142cddd | aurel32 | GEN_VXFORM(vsumsws, 4, 30); |
6423 | 56fdd213 | aurel32 | GEN_VXFORM(vaddfp, 5, 0); |
6424 | 56fdd213 | aurel32 | GEN_VXFORM(vsubfp, 5, 1); |
6425 | 1536ff64 | aurel32 | GEN_VXFORM(vmaxfp, 5, 16); |
6426 | 1536ff64 | aurel32 | GEN_VXFORM(vminfp, 5, 17); |
6427 | fab3cbe9 | aurel32 | |
6428 | 0cbcd906 | aurel32 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
6429 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6430 | 0cbcd906 | aurel32 | { \ |
6431 | 0cbcd906 | aurel32 | TCGv_ptr ra, rb, rd; \ |
6432 | 0cbcd906 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6433 | 0cbcd906 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6434 | 0cbcd906 | aurel32 | return; \
|
6435 | 0cbcd906 | aurel32 | } \ |
6436 | 0cbcd906 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6437 | 0cbcd906 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6438 | 0cbcd906 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6439 | 0cbcd906 | aurel32 | gen_helper_##opname (rd, ra, rb); \ |
6440 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(ra); \ |
6441 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rb); \ |
6442 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rd); \ |
6443 | 0cbcd906 | aurel32 | } |
6444 | 0cbcd906 | aurel32 | |
6445 | 0cbcd906 | aurel32 | #define GEN_VXRFORM(name, opc2, opc3) \
|
6446 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
6447 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
6448 | 0cbcd906 | aurel32 | |
6449 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequb, 3, 0) |
6450 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequh, 3, 1) |
6451 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequw, 3, 2) |
6452 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
6453 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsh, 3, 13) |
6454 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsw, 3, 14) |
6455 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtub, 3, 8) |
6456 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuh, 3, 9) |
6457 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuw, 3, 10) |
6458 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6459 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgefp, 3, 7) |
6460 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgtfp, 3, 11) |
6461 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpbfp, 3, 15) |
6462 | 1add6e23 | aurel32 | |
6463 | c026766b | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6464 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6465 | c026766b | aurel32 | { \ |
6466 | c026766b | aurel32 | TCGv_ptr rd; \ |
6467 | c026766b | aurel32 | TCGv_i32 simm; \ |
6468 | c026766b | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6469 | c026766b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6470 | c026766b | aurel32 | return; \
|
6471 | c026766b | aurel32 | } \ |
6472 | c026766b | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6473 | c026766b | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6474 | c026766b | aurel32 | gen_helper_##name (rd, simm); \ |
6475 | c026766b | aurel32 | tcg_temp_free_i32(simm); \ |
6476 | c026766b | aurel32 | tcg_temp_free_ptr(rd); \ |
6477 | c026766b | aurel32 | } |
6478 | c026766b | aurel32 | |
6479 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisb, 6, 12); |
6480 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltish, 6, 13); |
6481 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisw, 6, 14); |
6482 | c026766b | aurel32 | |
6483 | de5f2484 | aurel32 | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
6484 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6485 | de5f2484 | aurel32 | { \ |
6486 | de5f2484 | aurel32 | TCGv_ptr rb, rd; \ |
6487 | de5f2484 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6488 | de5f2484 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6489 | de5f2484 | aurel32 | return; \
|
6490 | de5f2484 | aurel32 | } \ |
6491 | de5f2484 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6492 | de5f2484 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6493 | de5f2484 | aurel32 | gen_helper_##name (rd, rb); \ |
6494 | de5f2484 | aurel32 | tcg_temp_free_ptr(rb); \ |
6495 | de5f2484 | aurel32 | tcg_temp_free_ptr(rd); \ |
6496 | de5f2484 | aurel32 | } |
6497 | de5f2484 | aurel32 | |
6498 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6499 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsh, 7, 9); |
6500 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
6501 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsh, 7, 11); |
6502 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6503 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupklpx, 7, 15); |
6504 | bdfbac35 | aurel32 | GEN_VXFORM_NOA(vrefp, 5, 4); |
6505 | 071fc3b1 | aurel32 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5); |
6506 | 0bffbc6c | Aurelien Jarno | GEN_VXFORM_NOA(vexptefp, 5, 6); |
6507 | b580763f | aurel32 | GEN_VXFORM_NOA(vlogefp, 5, 7); |
6508 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfim, 5, 8); |
6509 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfin, 5, 9); |
6510 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfip, 5, 10); |
6511 | f6b19645 | aurel32 | GEN_VXFORM_NOA(vrfiz, 5, 11); |
6512 | 79f85c3a | aurel32 | |
6513 | 21d21583 | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6514 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6515 | 21d21583 | aurel32 | { \ |
6516 | 21d21583 | aurel32 | TCGv_ptr rd; \ |
6517 | 21d21583 | aurel32 | TCGv_i32 simm; \ |
6518 | 21d21583 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6519 | 21d21583 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6520 | 21d21583 | aurel32 | return; \
|
6521 | 21d21583 | aurel32 | } \ |
6522 | 21d21583 | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6523 | 21d21583 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6524 | 21d21583 | aurel32 | gen_helper_##name (rd, simm); \ |
6525 | 21d21583 | aurel32 | tcg_temp_free_i32(simm); \ |
6526 | 21d21583 | aurel32 | tcg_temp_free_ptr(rd); \ |
6527 | 21d21583 | aurel32 | } |
6528 | 21d21583 | aurel32 | |
6529 | 27a4edb3 | aurel32 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
6530 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6531 | 27a4edb3 | aurel32 | { \ |
6532 | 27a4edb3 | aurel32 | TCGv_ptr rb, rd; \ |
6533 | 27a4edb3 | aurel32 | TCGv_i32 uimm; \ |
6534 | 27a4edb3 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6535 | 27a4edb3 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6536 | 27a4edb3 | aurel32 | return; \
|
6537 | 27a4edb3 | aurel32 | } \ |
6538 | 27a4edb3 | aurel32 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ |
6539 | 27a4edb3 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6540 | 27a4edb3 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6541 | 27a4edb3 | aurel32 | gen_helper_##name (rd, rb, uimm); \ |
6542 | 27a4edb3 | aurel32 | tcg_temp_free_i32(uimm); \ |
6543 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rb); \ |
6544 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rd); \ |
6545 | 27a4edb3 | aurel32 | } |
6546 | 27a4edb3 | aurel32 | |
6547 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6548 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vsplth, 6, 9); |
6549 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltw, 6, 10); |
6550 | e140632e | aurel32 | GEN_VXFORM_UIMM(vcfux, 5, 12); |
6551 | e140632e | aurel32 | GEN_VXFORM_UIMM(vcfsx, 5, 13); |
6552 | 875b31db | aurel32 | GEN_VXFORM_UIMM(vctuxs, 5, 14); |
6553 | 875b31db | aurel32 | GEN_VXFORM_UIMM(vctsxs, 5, 15); |
6554 | e4e6bee7 | aurel32 | |
6555 | 99e300ef | Blue Swirl | static void gen_vsldoi(DisasContext *ctx) |
6556 | cd633b10 | aurel32 | { |
6557 | cd633b10 | aurel32 | TCGv_ptr ra, rb, rd; |
6558 | fce5ecb7 | aurel32 | TCGv_i32 sh; |
6559 | cd633b10 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6560 | cd633b10 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6561 | cd633b10 | aurel32 | return;
|
6562 | cd633b10 | aurel32 | } |
6563 | cd633b10 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
6564 | cd633b10 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
6565 | cd633b10 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6566 | cd633b10 | aurel32 | sh = tcg_const_i32(VSH(ctx->opcode)); |
6567 | cd633b10 | aurel32 | gen_helper_vsldoi (rd, ra, rb, sh); |
6568 | cd633b10 | aurel32 | tcg_temp_free_ptr(ra); |
6569 | cd633b10 | aurel32 | tcg_temp_free_ptr(rb); |
6570 | cd633b10 | aurel32 | tcg_temp_free_ptr(rd); |
6571 | fce5ecb7 | aurel32 | tcg_temp_free_i32(sh); |
6572 | cd633b10 | aurel32 | } |
6573 | cd633b10 | aurel32 | |
6574 | 707cec33 | aurel32 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
6575 | 99e300ef | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
6576 | 707cec33 | aurel32 | { \ |
6577 | 707cec33 | aurel32 | TCGv_ptr ra, rb, rc, rd; \ |
6578 | 707cec33 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6579 | 707cec33 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6580 | 707cec33 | aurel32 | return; \
|
6581 | 707cec33 | aurel32 | } \ |
6582 | 707cec33 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6583 | 707cec33 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6584 | 707cec33 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); \ |
6585 | 707cec33 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6586 | 707cec33 | aurel32 | if (Rc(ctx->opcode)) { \
|
6587 | 707cec33 | aurel32 | gen_helper_##name1 (rd, ra, rb, rc); \ |
6588 | 707cec33 | aurel32 | } else { \
|
6589 | 707cec33 | aurel32 | gen_helper_##name0 (rd, ra, rb, rc); \ |
6590 | 707cec33 | aurel32 | } \ |
6591 | 707cec33 | aurel32 | tcg_temp_free_ptr(ra); \ |
6592 | 707cec33 | aurel32 | tcg_temp_free_ptr(rb); \ |
6593 | 707cec33 | aurel32 | tcg_temp_free_ptr(rc); \ |
6594 | 707cec33 | aurel32 | tcg_temp_free_ptr(rd); \ |
6595 | 707cec33 | aurel32 | } |
6596 | 707cec33 | aurel32 | |
6597 | b161ae27 | aurel32 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
|
6598 | b161ae27 | aurel32 | |
6599 | 99e300ef | Blue Swirl | static void gen_vmladduhm(DisasContext *ctx) |
6600 | bcd2ee23 | aurel32 | { |
6601 | bcd2ee23 | aurel32 | TCGv_ptr ra, rb, rc, rd; |
6602 | bcd2ee23 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6603 | bcd2ee23 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6604 | bcd2ee23 | aurel32 | return;
|
6605 | bcd2ee23 | aurel32 | } |
6606 | bcd2ee23 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
6607 | bcd2ee23 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
6608 | bcd2ee23 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); |
6609 | bcd2ee23 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6610 | bcd2ee23 | aurel32 | gen_helper_vmladduhm(rd, ra, rb, rc); |
6611 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(ra); |
6612 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rb); |
6613 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rc); |
6614 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rd); |
6615 | bcd2ee23 | aurel32 | } |
6616 | bcd2ee23 | aurel32 | |
6617 | b04ae981 | aurel32 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
|
6618 | 4d9903b6 | aurel32 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
|
6619 | eae07261 | aurel32 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
|
6620 | d1258698 | aurel32 | GEN_VAFORM_PAIRED(vsel, vperm, 21)
|
6621 | 35cf7c7e | aurel32 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
|
6622 | b04ae981 | aurel32 | |
6623 | 0487d6a8 | j_mayer | /*** SPE extension ***/
|
6624 | 0487d6a8 | j_mayer | /* Register moves */
|
6625 | 3cd7d1dd | j_mayer | |
6626 | a0e13900 | Fabien Chouteau | |
6627 | a0e13900 | Fabien Chouteau | static inline void gen_evmra(DisasContext *ctx) |
6628 | a0e13900 | Fabien Chouteau | { |
6629 | a0e13900 | Fabien Chouteau | |
6630 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
6631 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
6632 | a0e13900 | Fabien Chouteau | return;
|
6633 | a0e13900 | Fabien Chouteau | } |
6634 | a0e13900 | Fabien Chouteau | |
6635 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
6636 | a0e13900 | Fabien Chouteau | /* rD := rA */
|
6637 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
6638 | a0e13900 | Fabien Chouteau | |
6639 | a0e13900 | Fabien Chouteau | /* spe_acc := rA */
|
6640 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], |
6641 | a0e13900 | Fabien Chouteau | cpu_env, |
6642 | a0e13900 | Fabien Chouteau | offsetof(CPUState, spe_acc)); |
6643 | a0e13900 | Fabien Chouteau | #else
|
6644 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp = tcg_temp_new_i64(); |
6645 | a0e13900 | Fabien Chouteau | |
6646 | a0e13900 | Fabien Chouteau | /* tmp := rA_lo + rA_hi << 32 */
|
6647 | a0e13900 | Fabien Chouteau | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6648 | a0e13900 | Fabien Chouteau | |
6649 | a0e13900 | Fabien Chouteau | /* spe_acc := tmp */
|
6650 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
6651 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
6652 | a0e13900 | Fabien Chouteau | |
6653 | a0e13900 | Fabien Chouteau | /* rD := rA */
|
6654 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
6655 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6656 | a0e13900 | Fabien Chouteau | #endif
|
6657 | a0e13900 | Fabien Chouteau | } |
6658 | a0e13900 | Fabien Chouteau | |
6659 | 636aa200 | Blue Swirl | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
6660 | 636aa200 | Blue Swirl | { |
6661 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
6662 | f78fb44e | aurel32 | tcg_gen_mov_i64(t, cpu_gpr[reg]); |
6663 | f78fb44e | aurel32 | #else
|
6664 | 36aa55dc | pbrook | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
6665 | 3cd7d1dd | j_mayer | #endif
|
6666 | f78fb44e | aurel32 | } |
6667 | 3cd7d1dd | j_mayer | |
6668 | 636aa200 | Blue Swirl | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
6669 | 636aa200 | Blue Swirl | { |
6670 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
6671 | f78fb44e | aurel32 | tcg_gen_mov_i64(cpu_gpr[reg], t); |
6672 | f78fb44e | aurel32 | #else
|
6673 | a7812ae4 | pbrook | TCGv_i64 tmp = tcg_temp_new_i64(); |
6674 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
6675 | f78fb44e | aurel32 | tcg_gen_shri_i64(tmp, t, 32);
|
6676 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
6677 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp); |
6678 | 3cd7d1dd | j_mayer | #endif
|
6679 | f78fb44e | aurel32 | } |
6680 | 3cd7d1dd | j_mayer | |
6681 | 0487d6a8 | j_mayer | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
6682 | 99e300ef | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
6683 | 0487d6a8 | j_mayer | { \ |
6684 | 0487d6a8 | j_mayer | if (Rc(ctx->opcode)) \
|
6685 | 0487d6a8 | j_mayer | gen_##name1(ctx); \ |
6686 | 0487d6a8 | j_mayer | else \
|
6687 | 0487d6a8 | j_mayer | gen_##name0(ctx); \ |
6688 | 0487d6a8 | j_mayer | } |
6689 | 0487d6a8 | j_mayer | |
6690 | 0487d6a8 | j_mayer | /* Handler for undefined SPE opcodes */
|
6691 | 636aa200 | Blue Swirl | static inline void gen_speundef(DisasContext *ctx) |
6692 | 0487d6a8 | j_mayer | { |
6693 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6694 | 0487d6a8 | j_mayer | } |
6695 | 0487d6a8 | j_mayer | |
6696 | 57951c27 | aurel32 | /* SPE logic */
|
6697 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6698 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
6699 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6700 | 0487d6a8 | j_mayer | { \ |
6701 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6702 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6703 | 0487d6a8 | j_mayer | return; \
|
6704 | 0487d6a8 | j_mayer | } \ |
6705 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6706 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6707 | 57951c27 | aurel32 | } |
6708 | 57951c27 | aurel32 | #else
|
6709 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
6710 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6711 | 57951c27 | aurel32 | { \ |
6712 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6713 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6714 | 57951c27 | aurel32 | return; \
|
6715 | 57951c27 | aurel32 | } \ |
6716 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6717 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6718 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6719 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
6720 | 0487d6a8 | j_mayer | } |
6721 | 57951c27 | aurel32 | #endif
|
6722 | 57951c27 | aurel32 | |
6723 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); |
6724 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); |
6725 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); |
6726 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); |
6727 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); |
6728 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); |
6729 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); |
6730 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); |
6731 | 0487d6a8 | j_mayer | |
6732 | 57951c27 | aurel32 | /* SPE logic immediate */
|
6733 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6734 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
6735 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6736 | 3d3a6a0a | aurel32 | { \ |
6737 | 3d3a6a0a | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6738 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6739 | 3d3a6a0a | aurel32 | return; \
|
6740 | 3d3a6a0a | aurel32 | } \ |
6741 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6742 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6743 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6744 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6745 | 57951c27 | aurel32 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
6746 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6747 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6748 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6749 | 57951c27 | aurel32 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6750 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6751 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6752 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6753 | 3d3a6a0a | aurel32 | } |
6754 | 57951c27 | aurel32 | #else
|
6755 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
6756 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6757 | 0487d6a8 | j_mayer | { \ |
6758 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6759 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6760 | 0487d6a8 | j_mayer | return; \
|
6761 | 0487d6a8 | j_mayer | } \ |
6762 | 57951c27 | aurel32 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6763 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
6764 | 57951c27 | aurel32 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6765 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
6766 | 0487d6a8 | j_mayer | } |
6767 | 57951c27 | aurel32 | #endif
|
6768 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
6769 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); |
6770 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); |
6771 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); |
6772 | 0487d6a8 | j_mayer | |
6773 | 57951c27 | aurel32 | /* SPE arithmetic */
|
6774 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6775 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
6776 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6777 | 0487d6a8 | j_mayer | { \ |
6778 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6779 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6780 | 0487d6a8 | j_mayer | return; \
|
6781 | 0487d6a8 | j_mayer | } \ |
6782 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6783 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6784 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6785 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6786 | 57951c27 | aurel32 | tcg_op(t0, t0); \ |
6787 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
6788 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6789 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
6790 | 57951c27 | aurel32 | tcg_op(t1, t1); \ |
6791 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6792 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6793 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6794 | 0487d6a8 | j_mayer | } |
6795 | 57951c27 | aurel32 | #else
|
6796 | a7812ae4 | pbrook | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
6797 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6798 | 57951c27 | aurel32 | { \ |
6799 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6800 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6801 | 57951c27 | aurel32 | return; \
|
6802 | 57951c27 | aurel32 | } \ |
6803 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
6804 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ |
6805 | 57951c27 | aurel32 | } |
6806 | 57951c27 | aurel32 | #endif
|
6807 | 0487d6a8 | j_mayer | |
6808 | 636aa200 | Blue Swirl | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
6809 | 57951c27 | aurel32 | { |
6810 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
6811 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
6812 | 0487d6a8 | j_mayer | |
6813 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
|
6814 | 57951c27 | aurel32 | tcg_gen_neg_i32(ret, arg1); |
6815 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6816 | 57951c27 | aurel32 | gen_set_label(l1); |
6817 | a7812ae4 | pbrook | tcg_gen_mov_i32(ret, arg1); |
6818 | 57951c27 | aurel32 | gen_set_label(l2); |
6819 | 57951c27 | aurel32 | } |
6820 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); |
6821 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); |
6822 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); |
6823 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); |
6824 | 636aa200 | Blue Swirl | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
6825 | 0487d6a8 | j_mayer | { |
6826 | 57951c27 | aurel32 | tcg_gen_addi_i32(ret, arg1, 0x8000);
|
6827 | 57951c27 | aurel32 | tcg_gen_ext16u_i32(ret, ret); |
6828 | 57951c27 | aurel32 | } |
6829 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); |
6830 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
6831 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); |
6832 | 0487d6a8 | j_mayer | |
6833 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6834 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
6835 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6836 | 0487d6a8 | j_mayer | { \ |
6837 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6838 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6839 | 0487d6a8 | j_mayer | return; \
|
6840 | 0487d6a8 | j_mayer | } \ |
6841 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6842 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6843 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ |
6844 | 501e23c4 | aurel32 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
6845 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6846 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ |
6847 | 57951c27 | aurel32 | tcg_op(t0, t0, t2); \ |
6848 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
|
6849 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t3); \ |
6850 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
|
6851 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, t3); \ |
6852 | a7812ae4 | pbrook | tcg_temp_free_i64(t3); \ |
6853 | 57951c27 | aurel32 | tcg_op(t1, t1, t2); \ |
6854 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); \ |
6855 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6856 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6857 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6858 | 0487d6a8 | j_mayer | } |
6859 | 57951c27 | aurel32 | #else
|
6860 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
6861 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6862 | 0487d6a8 | j_mayer | { \ |
6863 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
6864 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6865 | 0487d6a8 | j_mayer | return; \
|
6866 | 0487d6a8 | j_mayer | } \ |
6867 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6868 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
6869 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
6870 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
6871 | 0487d6a8 | j_mayer | } |
6872 | 57951c27 | aurel32 | #endif
|
6873 | 0487d6a8 | j_mayer | |
6874 | 636aa200 | Blue Swirl | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6875 | 57951c27 | aurel32 | { |
6876 | a7812ae4 | pbrook | TCGv_i32 t0; |
6877 | 57951c27 | aurel32 | int l1, l2;
|
6878 | 0487d6a8 | j_mayer | |
6879 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6880 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6881 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6882 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6883 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6884 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6885 | 57951c27 | aurel32 | tcg_gen_shr_i32(ret, arg1, t0); |
6886 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6887 | 57951c27 | aurel32 | gen_set_label(l1); |
6888 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6889 | 0aef4261 | Aurelien Jarno | gen_set_label(l2); |
6890 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6891 | 57951c27 | aurel32 | } |
6892 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); |
6893 | 636aa200 | Blue Swirl | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6894 | 57951c27 | aurel32 | { |
6895 | a7812ae4 | pbrook | TCGv_i32 t0; |
6896 | 57951c27 | aurel32 | int l1, l2;
|
6897 | 57951c27 | aurel32 | |
6898 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6899 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6900 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6901 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6902 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6903 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6904 | 57951c27 | aurel32 | tcg_gen_sar_i32(ret, arg1, t0); |
6905 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6906 | 57951c27 | aurel32 | gen_set_label(l1); |
6907 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6908 | 0aef4261 | Aurelien Jarno | gen_set_label(l2); |
6909 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6910 | 57951c27 | aurel32 | } |
6911 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); |
6912 | 636aa200 | Blue Swirl | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6913 | 57951c27 | aurel32 | { |
6914 | a7812ae4 | pbrook | TCGv_i32 t0; |
6915 | 57951c27 | aurel32 | int l1, l2;
|
6916 | 57951c27 | aurel32 | |
6917 | 57951c27 | aurel32 | l1 = gen_new_label(); |
6918 | 57951c27 | aurel32 | l2 = gen_new_label(); |
6919 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
6920 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
6921 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
6922 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
6923 | 57951c27 | aurel32 | tcg_gen_shl_i32(ret, arg1, t0); |
6924 | 57951c27 | aurel32 | tcg_gen_br(l2); |
6925 | 57951c27 | aurel32 | gen_set_label(l1); |
6926 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
6927 | e29ef9fa | Aurelien Jarno | gen_set_label(l2); |
6928 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6929 | 57951c27 | aurel32 | } |
6930 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); |
6931 | 636aa200 | Blue Swirl | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6932 | 57951c27 | aurel32 | { |
6933 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_new_i32(); |
6934 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x1F);
|
6935 | 57951c27 | aurel32 | tcg_gen_rotl_i32(ret, arg1, t0); |
6936 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
6937 | 57951c27 | aurel32 | } |
6938 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); |
6939 | 636aa200 | Blue Swirl | static inline void gen_evmergehi(DisasContext *ctx) |
6940 | 57951c27 | aurel32 | { |
6941 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
6942 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
6943 | 57951c27 | aurel32 | return;
|
6944 | 57951c27 | aurel32 | } |
6945 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6946 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
6947 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
6948 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
6949 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
6950 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
6951 | 57951c27 | aurel32 | tcg_temp_free(t0); |
6952 | 57951c27 | aurel32 | tcg_temp_free(t1); |
6953 | 57951c27 | aurel32 | #else
|
6954 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
6955 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6956 | 57951c27 | aurel32 | #endif
|
6957 | 57951c27 | aurel32 | } |
6958 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); |
6959 | 636aa200 | Blue Swirl | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
6960 | 0487d6a8 | j_mayer | { |
6961 | 57951c27 | aurel32 | tcg_gen_sub_i32(ret, arg2, arg1); |
6962 | 57951c27 | aurel32 | } |
6963 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); |
6964 | 0487d6a8 | j_mayer | |
6965 | 57951c27 | aurel32 | /* SPE arithmetic immediate */
|
6966 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
6967 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
6968 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6969 | 57951c27 | aurel32 | { \ |
6970 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6971 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6972 | 57951c27 | aurel32 | return; \
|
6973 | 57951c27 | aurel32 | } \ |
6974 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6975 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
6976 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
6977 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
6978 | 57951c27 | aurel32 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
6979 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
6980 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
6981 | e06fcd75 | aurel32 | tcg_temp_free_i64(t2); \ |
6982 | 57951c27 | aurel32 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
6983 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
6984 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
6985 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
6986 | 57951c27 | aurel32 | } |
6987 | 57951c27 | aurel32 | #else
|
6988 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
6989 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
6990 | 57951c27 | aurel32 | { \ |
6991 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
6992 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6993 | 57951c27 | aurel32 | return; \
|
6994 | 57951c27 | aurel32 | } \ |
6995 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
6996 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
6997 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ |
6998 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
6999 | 57951c27 | aurel32 | } |
7000 | 57951c27 | aurel32 | #endif
|
7001 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
7002 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); |
7003 | 57951c27 | aurel32 | |
7004 | 57951c27 | aurel32 | /* SPE comparison */
|
7005 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7006 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
7007 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7008 | 57951c27 | aurel32 | { \ |
7009 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7010 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7011 | 57951c27 | aurel32 | return; \
|
7012 | 57951c27 | aurel32 | } \ |
7013 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
7014 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
7015 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
7016 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
7017 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7018 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
7019 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
7020 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7021 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
7022 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ |
7023 | a7812ae4 | pbrook | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
|
7024 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
7025 | 57951c27 | aurel32 | gen_set_label(l1); \ |
7026 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
7027 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
7028 | 57951c27 | aurel32 | gen_set_label(l2); \ |
7029 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
7030 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, t2); \ |
7031 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
7032 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
7033 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
7034 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7035 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
7036 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
7037 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
7038 | 57951c27 | aurel32 | gen_set_label(l3); \ |
7039 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
7040 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
7041 | 57951c27 | aurel32 | gen_set_label(l4); \ |
7042 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
7043 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
7044 | 57951c27 | aurel32 | } |
7045 | 57951c27 | aurel32 | #else
|
7046 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
7047 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7048 | 57951c27 | aurel32 | { \ |
7049 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7050 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7051 | 57951c27 | aurel32 | return; \
|
7052 | 57951c27 | aurel32 | } \ |
7053 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
7054 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
7055 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
7056 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
7057 | 57951c27 | aurel32 | \ |
7058 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ |
7059 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)], l1); \ |
7060 | 57951c27 | aurel32 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
|
7061 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
7062 | 57951c27 | aurel32 | gen_set_label(l1); \ |
7063 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
7064 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
7065 | 57951c27 | aurel32 | gen_set_label(l2); \ |
7066 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
7067 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)], l3); \ |
7068 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
7069 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
7070 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
7071 | 57951c27 | aurel32 | gen_set_label(l3); \ |
7072 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
7073 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
7074 | 57951c27 | aurel32 | gen_set_label(l4); \ |
7075 | 57951c27 | aurel32 | } |
7076 | 57951c27 | aurel32 | #endif
|
7077 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
7078 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); |
7079 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); |
7080 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); |
7081 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); |
7082 | 57951c27 | aurel32 | |
7083 | 57951c27 | aurel32 | /* SPE misc */
|
7084 | 636aa200 | Blue Swirl | static inline void gen_brinc(DisasContext *ctx) |
7085 | 57951c27 | aurel32 | { |
7086 | 57951c27 | aurel32 | /* Note: brinc is usable even if SPE is disabled */
|
7087 | a7812ae4 | pbrook | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7088 | a7812ae4 | pbrook | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7089 | 0487d6a8 | j_mayer | } |
7090 | 636aa200 | Blue Swirl | static inline void gen_evmergelo(DisasContext *ctx) |
7091 | 57951c27 | aurel32 | { |
7092 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7093 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7094 | 57951c27 | aurel32 | return;
|
7095 | 57951c27 | aurel32 | } |
7096 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7097 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
7098 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
7099 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
7100 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
7101 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
7102 | 57951c27 | aurel32 | tcg_temp_free(t0); |
7103 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7104 | 57951c27 | aurel32 | #else
|
7105 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7106 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7107 | 57951c27 | aurel32 | #endif
|
7108 | 57951c27 | aurel32 | } |
7109 | 636aa200 | Blue Swirl | static inline void gen_evmergehilo(DisasContext *ctx) |
7110 | 57951c27 | aurel32 | { |
7111 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7112 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7113 | 57951c27 | aurel32 | return;
|
7114 | 57951c27 | aurel32 | } |
7115 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7116 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
7117 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
7118 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
7119 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
7120 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
7121 | 57951c27 | aurel32 | tcg_temp_free(t0); |
7122 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7123 | 57951c27 | aurel32 | #else
|
7124 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7125 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
7126 | 57951c27 | aurel32 | #endif
|
7127 | 57951c27 | aurel32 | } |
7128 | 636aa200 | Blue Swirl | static inline void gen_evmergelohi(DisasContext *ctx) |
7129 | 57951c27 | aurel32 | { |
7130 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
7131 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
7132 | 57951c27 | aurel32 | return;
|
7133 | 57951c27 | aurel32 | } |
7134 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7135 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
7136 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
7137 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
7138 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
7139 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
7140 | 57951c27 | aurel32 | tcg_temp_free(t0); |
7141 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7142 | 57951c27 | aurel32 | #else
|
7143 | 33890b3e | Nathan Froyd | if (rD(ctx->opcode) == rA(ctx->opcode)) {
|
7144 | 33890b3e | Nathan Froyd | TCGv_i32 tmp = tcg_temp_new_i32(); |
7145 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); |
7146 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
7147 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); |
7148 | 33890b3e | Nathan Froyd | tcg_temp_free_i32(tmp); |
7149 | 33890b3e | Nathan Froyd | } else {
|
7150 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
7151 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7152 | 33890b3e | Nathan Froyd | } |
7153 | 57951c27 | aurel32 | #endif
|
7154 | 57951c27 | aurel32 | } |
7155 | 636aa200 | Blue Swirl | static inline void gen_evsplati(DisasContext *ctx) |
7156 | 57951c27 | aurel32 | { |
7157 | ae01847f | Nathan Froyd | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
7158 | 0487d6a8 | j_mayer | |
7159 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7160 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
7161 | 57951c27 | aurel32 | #else
|
7162 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
7163 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
7164 | 57951c27 | aurel32 | #endif
|
7165 | 57951c27 | aurel32 | } |
7166 | 636aa200 | Blue Swirl | static inline void gen_evsplatfi(DisasContext *ctx) |
7167 | 0487d6a8 | j_mayer | { |
7168 | ae01847f | Nathan Froyd | uint64_t imm = rA(ctx->opcode) << 27;
|
7169 | 0487d6a8 | j_mayer | |
7170 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7171 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
7172 | 57951c27 | aurel32 | #else
|
7173 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
7174 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
7175 | 57951c27 | aurel32 | #endif
|
7176 | 0487d6a8 | j_mayer | } |
7177 | 0487d6a8 | j_mayer | |
7178 | 636aa200 | Blue Swirl | static inline void gen_evsel(DisasContext *ctx) |
7179 | 57951c27 | aurel32 | { |
7180 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
7181 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
7182 | 57951c27 | aurel32 | int l3 = gen_new_label();
|
7183 | 57951c27 | aurel32 | int l4 = gen_new_label();
|
7184 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
7185 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7186 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_local_new(); |
7187 | a7812ae4 | pbrook | TCGv t2 = tcg_temp_local_new(); |
7188 | 57951c27 | aurel32 | #endif
|
7189 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
7190 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
7191 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7192 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
7193 | 57951c27 | aurel32 | #else
|
7194 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
7195 | 57951c27 | aurel32 | #endif
|
7196 | 57951c27 | aurel32 | tcg_gen_br(l2); |
7197 | 57951c27 | aurel32 | gen_set_label(l1); |
7198 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7199 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
7200 | 57951c27 | aurel32 | #else
|
7201 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
7202 | 57951c27 | aurel32 | #endif
|
7203 | 57951c27 | aurel32 | gen_set_label(l2); |
7204 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); |
7205 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
|
7206 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7207 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
7208 | 57951c27 | aurel32 | #else
|
7209 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7210 | 57951c27 | aurel32 | #endif
|
7211 | 57951c27 | aurel32 | tcg_gen_br(l4); |
7212 | 57951c27 | aurel32 | gen_set_label(l3); |
7213 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7214 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
7215 | 57951c27 | aurel32 | #else
|
7216 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
7217 | 57951c27 | aurel32 | #endif
|
7218 | 57951c27 | aurel32 | gen_set_label(l4); |
7219 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
7220 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7221 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); |
7222 | 57951c27 | aurel32 | tcg_temp_free(t1); |
7223 | 57951c27 | aurel32 | tcg_temp_free(t2); |
7224 | 57951c27 | aurel32 | #endif
|
7225 | 57951c27 | aurel32 | } |
7226 | e8eaa2c0 | Blue Swirl | |
7227 | e8eaa2c0 | Blue Swirl | static void gen_evsel0(DisasContext *ctx) |
7228 | 57951c27 | aurel32 | { |
7229 | 57951c27 | aurel32 | gen_evsel(ctx); |
7230 | 57951c27 | aurel32 | } |
7231 | e8eaa2c0 | Blue Swirl | |
7232 | e8eaa2c0 | Blue Swirl | static void gen_evsel1(DisasContext *ctx) |
7233 | 57951c27 | aurel32 | { |
7234 | 57951c27 | aurel32 | gen_evsel(ctx); |
7235 | 57951c27 | aurel32 | } |
7236 | e8eaa2c0 | Blue Swirl | |
7237 | e8eaa2c0 | Blue Swirl | static void gen_evsel2(DisasContext *ctx) |
7238 | 57951c27 | aurel32 | { |
7239 | 57951c27 | aurel32 | gen_evsel(ctx); |
7240 | 57951c27 | aurel32 | } |
7241 | e8eaa2c0 | Blue Swirl | |
7242 | e8eaa2c0 | Blue Swirl | static void gen_evsel3(DisasContext *ctx) |
7243 | 57951c27 | aurel32 | { |
7244 | 57951c27 | aurel32 | gen_evsel(ctx); |
7245 | 57951c27 | aurel32 | } |
7246 | 0487d6a8 | j_mayer | |
7247 | a0e13900 | Fabien Chouteau | /* Multiply */
|
7248 | a0e13900 | Fabien Chouteau | |
7249 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumi(DisasContext *ctx) |
7250 | a0e13900 | Fabien Chouteau | { |
7251 | a0e13900 | Fabien Chouteau | TCGv_i64 t0, t1; |
7252 | a0e13900 | Fabien Chouteau | |
7253 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7254 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7255 | a0e13900 | Fabien Chouteau | return;
|
7256 | a0e13900 | Fabien Chouteau | } |
7257 | a0e13900 | Fabien Chouteau | |
7258 | a0e13900 | Fabien Chouteau | t0 = tcg_temp_new_i64(); |
7259 | a0e13900 | Fabien Chouteau | t1 = tcg_temp_new_i64(); |
7260 | a0e13900 | Fabien Chouteau | |
7261 | a0e13900 | Fabien Chouteau | /* t0 := rA; t1 := rB */
|
7262 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
7263 | a0e13900 | Fabien Chouteau | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
7264 | a0e13900 | Fabien Chouteau | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
7265 | a0e13900 | Fabien Chouteau | #else
|
7266 | a0e13900 | Fabien Chouteau | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
7267 | a0e13900 | Fabien Chouteau | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
7268 | a0e13900 | Fabien Chouteau | #endif
|
7269 | a0e13900 | Fabien Chouteau | |
7270 | a0e13900 | Fabien Chouteau | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
|
7271 | a0e13900 | Fabien Chouteau | |
7272 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
|
7273 | a0e13900 | Fabien Chouteau | |
7274 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t0); |
7275 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t1); |
7276 | a0e13900 | Fabien Chouteau | } |
7277 | a0e13900 | Fabien Chouteau | |
7278 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumia(DisasContext *ctx) |
7279 | a0e13900 | Fabien Chouteau | { |
7280 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
7281 | a0e13900 | Fabien Chouteau | |
7282 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7283 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7284 | a0e13900 | Fabien Chouteau | return;
|
7285 | a0e13900 | Fabien Chouteau | } |
7286 | a0e13900 | Fabien Chouteau | |
7287 | a0e13900 | Fabien Chouteau | gen_evmwumi(ctx); /* rD := rA * rB */
|
7288 | a0e13900 | Fabien Chouteau | |
7289 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7290 | a0e13900 | Fabien Chouteau | |
7291 | a0e13900 | Fabien Chouteau | /* acc := rD */
|
7292 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7293 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
7294 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7295 | a0e13900 | Fabien Chouteau | } |
7296 | a0e13900 | Fabien Chouteau | |
7297 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumiaa(DisasContext *ctx) |
7298 | a0e13900 | Fabien Chouteau | { |
7299 | a0e13900 | Fabien Chouteau | TCGv_i64 acc; |
7300 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
7301 | a0e13900 | Fabien Chouteau | |
7302 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7303 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7304 | a0e13900 | Fabien Chouteau | return;
|
7305 | a0e13900 | Fabien Chouteau | } |
7306 | a0e13900 | Fabien Chouteau | |
7307 | a0e13900 | Fabien Chouteau | gen_evmwumi(ctx); /* rD := rA * rB */
|
7308 | a0e13900 | Fabien Chouteau | |
7309 | a0e13900 | Fabien Chouteau | acc = tcg_temp_new_i64(); |
7310 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7311 | a0e13900 | Fabien Chouteau | |
7312 | a0e13900 | Fabien Chouteau | /* tmp := rD */
|
7313 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7314 | a0e13900 | Fabien Chouteau | |
7315 | a0e13900 | Fabien Chouteau | /* Load acc */
|
7316 | a0e13900 | Fabien Chouteau | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7317 | a0e13900 | Fabien Chouteau | |
7318 | a0e13900 | Fabien Chouteau | /* acc := tmp + acc */
|
7319 | a0e13900 | Fabien Chouteau | tcg_gen_add_i64(acc, acc, tmp); |
7320 | a0e13900 | Fabien Chouteau | |
7321 | a0e13900 | Fabien Chouteau | /* Store acc */
|
7322 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7323 | a0e13900 | Fabien Chouteau | |
7324 | a0e13900 | Fabien Chouteau | /* rD := acc */
|
7325 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), acc); |
7326 | a0e13900 | Fabien Chouteau | |
7327 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(acc); |
7328 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7329 | a0e13900 | Fabien Chouteau | } |
7330 | a0e13900 | Fabien Chouteau | |
7331 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmi(DisasContext *ctx) |
7332 | a0e13900 | Fabien Chouteau | { |
7333 | a0e13900 | Fabien Chouteau | TCGv_i64 t0, t1; |
7334 | a0e13900 | Fabien Chouteau | |
7335 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7336 | a0e13900 | Fabien Chouteau | gen_exception(ctx, POWERPC_EXCP_APU); |
7337 | a0e13900 | Fabien Chouteau | return;
|
7338 | a0e13900 | Fabien Chouteau | } |
7339 | a0e13900 | Fabien Chouteau | |
7340 | a0e13900 | Fabien Chouteau | t0 = tcg_temp_new_i64(); |
7341 | a0e13900 | Fabien Chouteau | t1 = tcg_temp_new_i64(); |
7342 | a0e13900 | Fabien Chouteau | |
7343 | a0e13900 | Fabien Chouteau | /* t0 := rA; t1 := rB */
|
7344 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
7345 | a0e13900 | Fabien Chouteau | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
7346 | a0e13900 | Fabien Chouteau | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
7347 | a0e13900 | Fabien Chouteau | #else
|
7348 | a0e13900 | Fabien Chouteau | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
7349 | a0e13900 | Fabien Chouteau | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
7350 | a0e13900 | Fabien Chouteau | #endif
|
7351 | a0e13900 | Fabien Chouteau | |
7352 | a0e13900 | Fabien Chouteau | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
|
7353 | a0e13900 | Fabien Chouteau | |
7354 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
|
7355 | a0e13900 | Fabien Chouteau | |
7356 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t0); |
7357 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t1); |
7358 | a0e13900 | Fabien Chouteau | } |
7359 | a0e13900 | Fabien Chouteau | |
7360 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmia(DisasContext *ctx) |
7361 | a0e13900 | Fabien Chouteau | { |
7362 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
7363 | a0e13900 | Fabien Chouteau | |
7364 | a0e13900 | Fabien Chouteau | gen_evmwsmi(ctx); /* rD := rA * rB */
|
7365 | a0e13900 | Fabien Chouteau | |
7366 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7367 | a0e13900 | Fabien Chouteau | |
7368 | a0e13900 | Fabien Chouteau | /* acc := rD */
|
7369 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7370 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
7371 | a0e13900 | Fabien Chouteau | |
7372 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7373 | a0e13900 | Fabien Chouteau | } |
7374 | a0e13900 | Fabien Chouteau | |
7375 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmiaa(DisasContext *ctx) |
7376 | a0e13900 | Fabien Chouteau | { |
7377 | a0e13900 | Fabien Chouteau | TCGv_i64 acc = tcg_temp_new_i64(); |
7378 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp = tcg_temp_new_i64(); |
7379 | a0e13900 | Fabien Chouteau | |
7380 | a0e13900 | Fabien Chouteau | gen_evmwsmi(ctx); /* rD := rA * rB */
|
7381 | a0e13900 | Fabien Chouteau | |
7382 | a0e13900 | Fabien Chouteau | acc = tcg_temp_new_i64(); |
7383 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
7384 | a0e13900 | Fabien Chouteau | |
7385 | a0e13900 | Fabien Chouteau | /* tmp := rD */
|
7386 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
7387 | a0e13900 | Fabien Chouteau | |
7388 | a0e13900 | Fabien Chouteau | /* Load acc */
|
7389 | a0e13900 | Fabien Chouteau | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7390 | a0e13900 | Fabien Chouteau | |
7391 | a0e13900 | Fabien Chouteau | /* acc := tmp + acc */
|
7392 | a0e13900 | Fabien Chouteau | tcg_gen_add_i64(acc, acc, tmp); |
7393 | a0e13900 | Fabien Chouteau | |
7394 | a0e13900 | Fabien Chouteau | /* Store acc */
|
7395 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
7396 | a0e13900 | Fabien Chouteau | |
7397 | a0e13900 | Fabien Chouteau | /* rD := acc */
|
7398 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), acc); |
7399 | a0e13900 | Fabien Chouteau | |
7400 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(acc); |
7401 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7402 | a0e13900 | Fabien Chouteau | } |
7403 | a0e13900 | Fabien Chouteau | |
7404 | 0487d6a8 | j_mayer | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// |
7405 | 0487d6a8 | j_mayer | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); |
7406 | 0487d6a8 | j_mayer | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// |
7407 | 0487d6a8 | j_mayer | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); |
7408 | 0487d6a8 | j_mayer | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// |
7409 | 0487d6a8 | j_mayer | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// |
7410 | 0487d6a8 | j_mayer | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// |
7411 | 0487d6a8 | j_mayer | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // |
7412 | a0e13900 | Fabien Chouteau | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE); |
7413 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// |
7414 | 0487d6a8 | j_mayer | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// |
7415 | 0487d6a8 | j_mayer | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// |
7416 | 0487d6a8 | j_mayer | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// |
7417 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE); |
7418 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE); |
7419 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE); |
7420 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// |
7421 | 0487d6a8 | j_mayer | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// |
7422 | 0487d6a8 | j_mayer | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// |
7423 | 0487d6a8 | j_mayer | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); |
7424 | 0487d6a8 | j_mayer | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// |
7425 | 0487d6a8 | j_mayer | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); |
7426 | 0487d6a8 | j_mayer | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // |
7427 | 0487d6a8 | j_mayer | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); |
7428 | 0487d6a8 | j_mayer | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// |
7429 | 0487d6a8 | j_mayer | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// |
7430 | 0487d6a8 | j_mayer | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// |
7431 | 0487d6a8 | j_mayer | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// |
7432 | 0487d6a8 | j_mayer | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// |
7433 | 0487d6a8 | j_mayer | |
7434 | 6a6ae23f | aurel32 | /* SPE load and stores */
|
7435 | 636aa200 | Blue Swirl | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
7436 | 6a6ae23f | aurel32 | { |
7437 | 6a6ae23f | aurel32 | target_ulong uimm = rB(ctx->opcode); |
7438 | 6a6ae23f | aurel32 | |
7439 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
7440 | 6a6ae23f | aurel32 | tcg_gen_movi_tl(EA, uimm << sh); |
7441 | 76db3ba4 | aurel32 | } else {
|
7442 | 6a6ae23f | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
7443 | 76db3ba4 | aurel32 | #if defined(TARGET_PPC64)
|
7444 | 76db3ba4 | aurel32 | if (!ctx->sf_mode) {
|
7445 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
7446 | 76db3ba4 | aurel32 | } |
7447 | 76db3ba4 | aurel32 | #endif
|
7448 | 76db3ba4 | aurel32 | } |
7449 | 0487d6a8 | j_mayer | } |
7450 | 6a6ae23f | aurel32 | |
7451 | 636aa200 | Blue Swirl | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
7452 | 6a6ae23f | aurel32 | { |
7453 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7454 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7455 | 6a6ae23f | aurel32 | #else
|
7456 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7457 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, t0, addr); |
7458 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7459 | 6a6ae23f | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
7460 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); |
7461 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
7462 | 6a6ae23f | aurel32 | #endif
|
7463 | 0487d6a8 | j_mayer | } |
7464 | 6a6ae23f | aurel32 | |
7465 | 636aa200 | Blue Swirl | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
7466 | 6a6ae23f | aurel32 | { |
7467 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7468 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7469 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7470 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7471 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7472 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7473 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7474 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7475 | 6a6ae23f | aurel32 | #else
|
7476 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7477 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7478 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7479 | 6a6ae23f | aurel32 | #endif
|
7480 | 0487d6a8 | j_mayer | } |
7481 | 6a6ae23f | aurel32 | |
7482 | 636aa200 | Blue Swirl | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
7483 | 6a6ae23f | aurel32 | { |
7484 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7485 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7486 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7487 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7488 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7489 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7490 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7491 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7492 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7493 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7494 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7495 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7496 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7497 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7498 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7499 | 0487d6a8 | j_mayer | #else
|
7500 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7501 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7502 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7503 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7504 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7505 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7506 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7507 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7508 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7509 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7510 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7511 | 0487d6a8 | j_mayer | #endif
|
7512 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7513 | 0487d6a8 | j_mayer | } |
7514 | 0487d6a8 | j_mayer | |
7515 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
7516 | 6a6ae23f | aurel32 | { |
7517 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7518 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7519 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7520 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7521 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7522 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7523 | 6a6ae23f | aurel32 | #else
|
7524 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7525 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7526 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7527 | 6a6ae23f | aurel32 | #endif
|
7528 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7529 | 0487d6a8 | j_mayer | } |
7530 | 0487d6a8 | j_mayer | |
7531 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
7532 | 6a6ae23f | aurel32 | { |
7533 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7534 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7535 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7536 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7537 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7538 | 6a6ae23f | aurel32 | #else
|
7539 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7540 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7541 | 6a6ae23f | aurel32 | #endif
|
7542 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7543 | 0487d6a8 | j_mayer | } |
7544 | 0487d6a8 | j_mayer | |
7545 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
7546 | 6a6ae23f | aurel32 | { |
7547 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7548 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7549 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7550 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7551 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(t0, t0); |
7552 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7553 | 6a6ae23f | aurel32 | #else
|
7554 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7555 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7556 | 6a6ae23f | aurel32 | #endif
|
7557 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7558 | 6a6ae23f | aurel32 | } |
7559 | 6a6ae23f | aurel32 | |
7560 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
7561 | 6a6ae23f | aurel32 | { |
7562 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7563 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7564 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7565 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7566 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7567 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7568 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7569 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7570 | 6a6ae23f | aurel32 | #else
|
7571 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7572 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7573 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7574 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7575 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
7576 | 6a6ae23f | aurel32 | #endif
|
7577 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7578 | 6a6ae23f | aurel32 | } |
7579 | 6a6ae23f | aurel32 | |
7580 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
7581 | 6a6ae23f | aurel32 | { |
7582 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7583 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7584 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7585 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7586 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7587 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7588 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7589 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7590 | 6a6ae23f | aurel32 | #else
|
7591 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7592 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7593 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7594 | 6a6ae23f | aurel32 | #endif
|
7595 | 6a6ae23f | aurel32 | } |
7596 | 6a6ae23f | aurel32 | |
7597 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
7598 | 6a6ae23f | aurel32 | { |
7599 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7600 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7601 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7602 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7603 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7604 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
7605 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7606 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7607 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7608 | 6a6ae23f | aurel32 | #else
|
7609 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7610 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7611 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7612 | 6a6ae23f | aurel32 | #endif
|
7613 | 6a6ae23f | aurel32 | } |
7614 | 6a6ae23f | aurel32 | |
7615 | 636aa200 | Blue Swirl | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
7616 | 6a6ae23f | aurel32 | { |
7617 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7618 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
7619 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7620 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
7621 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7622 | 6a6ae23f | aurel32 | #else
|
7623 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
7624 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
7625 | 6a6ae23f | aurel32 | #endif
|
7626 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7627 | 6a6ae23f | aurel32 | } |
7628 | 6a6ae23f | aurel32 | |
7629 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
7630 | 6a6ae23f | aurel32 | { |
7631 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7632 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7633 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7634 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
7635 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
7636 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7637 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7638 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7639 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7640 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
7641 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7642 | 6a6ae23f | aurel32 | #else
|
7643 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7644 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
7645 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7646 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7647 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
7648 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
7649 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
7650 | 0487d6a8 | j_mayer | #endif
|
7651 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7652 | 6a6ae23f | aurel32 | } |
7653 | 6a6ae23f | aurel32 | |
7654 | 636aa200 | Blue Swirl | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
7655 | 6a6ae23f | aurel32 | { |
7656 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7657 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7658 | 0487d6a8 | j_mayer | #else
|
7659 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7660 | 6a6ae23f | aurel32 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); |
7661 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, t0, addr); |
7662 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
7663 | 6a6ae23f | aurel32 | #endif
|
7664 | 6a6ae23f | aurel32 | } |
7665 | 6a6ae23f | aurel32 | |
7666 | 636aa200 | Blue Swirl | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
7667 | 6a6ae23f | aurel32 | { |
7668 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
7669 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7670 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7671 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
7672 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7673 | 6a6ae23f | aurel32 | #else
|
7674 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7675 | 6a6ae23f | aurel32 | #endif
|
7676 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
7677 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7678 | 6a6ae23f | aurel32 | } |
7679 | 6a6ae23f | aurel32 | |
7680 | 636aa200 | Blue Swirl | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
7681 | 6a6ae23f | aurel32 | { |
7682 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7683 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7684 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
7685 | 6a6ae23f | aurel32 | #else
|
7686 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
7687 | 6a6ae23f | aurel32 | #endif
|
7688 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7689 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7690 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7691 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7692 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7693 | 6a6ae23f | aurel32 | #else
|
7694 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7695 | 6a6ae23f | aurel32 | #endif
|
7696 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7697 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
7698 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7699 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7700 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7701 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7702 | 6a6ae23f | aurel32 | } |
7703 | 6a6ae23f | aurel32 | |
7704 | 636aa200 | Blue Swirl | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
7705 | 6a6ae23f | aurel32 | { |
7706 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7707 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7708 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
7709 | 6a6ae23f | aurel32 | #else
|
7710 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
7711 | 6a6ae23f | aurel32 | #endif
|
7712 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7713 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7714 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
7715 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7716 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7717 | 6a6ae23f | aurel32 | } |
7718 | 6a6ae23f | aurel32 | |
7719 | 636aa200 | Blue Swirl | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
7720 | 6a6ae23f | aurel32 | { |
7721 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7722 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7723 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7724 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
7725 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7726 | 6a6ae23f | aurel32 | #else
|
7727 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7728 | 6a6ae23f | aurel32 | #endif
|
7729 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
7730 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7731 | 6a6ae23f | aurel32 | } |
7732 | 6a6ae23f | aurel32 | |
7733 | 636aa200 | Blue Swirl | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
7734 | 6a6ae23f | aurel32 | { |
7735 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
7736 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
7737 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
7738 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
7739 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
7740 | 6a6ae23f | aurel32 | #else
|
7741 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
7742 | 6a6ae23f | aurel32 | #endif
|
7743 | 6a6ae23f | aurel32 | } |
7744 | 6a6ae23f | aurel32 | |
7745 | 636aa200 | Blue Swirl | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
7746 | 6a6ae23f | aurel32 | { |
7747 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7748 | 6a6ae23f | aurel32 | } |
7749 | 6a6ae23f | aurel32 | |
7750 | 6a6ae23f | aurel32 | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
7751 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
7752 | 6a6ae23f | aurel32 | { \ |
7753 | 6a6ae23f | aurel32 | TCGv t0; \ |
7754 | 6a6ae23f | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7755 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7756 | 6a6ae23f | aurel32 | return; \
|
7757 | 6a6ae23f | aurel32 | } \ |
7758 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
7759 | 6a6ae23f | aurel32 | t0 = tcg_temp_new(); \ |
7760 | 6a6ae23f | aurel32 | if (Rc(ctx->opcode)) { \
|
7761 | 76db3ba4 | aurel32 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
7762 | 6a6ae23f | aurel32 | } else { \
|
7763 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); \ |
7764 | 6a6ae23f | aurel32 | } \ |
7765 | 6a6ae23f | aurel32 | gen_op_##name(ctx, t0); \ |
7766 | 6a6ae23f | aurel32 | tcg_temp_free(t0); \ |
7767 | 6a6ae23f | aurel32 | } |
7768 | 6a6ae23f | aurel32 | |
7769 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldd, 0x00, 3); |
7770 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldw, 0x01, 3); |
7771 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldh, 0x02, 3); |
7772 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); |
7773 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); |
7774 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); |
7775 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); |
7776 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); |
7777 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); |
7778 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); |
7779 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); |
7780 | 6a6ae23f | aurel32 | |
7781 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdd, 0x10, 3); |
7782 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdw, 0x11, 3); |
7783 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdh, 0x12, 3); |
7784 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); |
7785 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); |
7786 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); |
7787 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); |
7788 | 0487d6a8 | j_mayer | |
7789 | 0487d6a8 | j_mayer | /* Multiply and add - TODO */
|
7790 | 0487d6a8 | j_mayer | #if 0
|
7791 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
|
7792 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
|
7793 | 0487d6a8 | j_mayer | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
|
7794 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
|
7795 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
|
7796 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
|
7797 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
|
7798 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
|
7799 | 0487d6a8 | j_mayer | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
|
7800 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
|
7801 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
|
7802 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
|
7803 | 0487d6a8 | j_mayer | |
7804 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
|
7805 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
|
7806 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
|
7807 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
|
7808 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
|
7809 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
|
7810 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
|
7811 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
|
7812 | 0487d6a8 | j_mayer | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
|
7813 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
|
7814 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
|
7815 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
|
7816 | 0487d6a8 | j_mayer | |
7817 | 0487d6a8 | j_mayer | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
|
7818 | 0487d6a8 | j_mayer | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
|
7819 | 0487d6a8 | j_mayer | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
|
7820 | 0487d6a8 | j_mayer | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
|
7821 | 0487d6a8 | j_mayer | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
|
7822 | 0487d6a8 | j_mayer | |
7823 | 0487d6a8 | j_mayer | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
|
7824 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
|
7825 | 0487d6a8 | j_mayer | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
|
7826 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
|
7827 | 0487d6a8 | j_mayer | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
|
7828 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
|
7829 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
|
7830 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
|
7831 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
|
7832 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
|
7833 | 0487d6a8 | j_mayer | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
|
7834 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
|
7835 | 0487d6a8 | j_mayer | |
7836 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
|
7837 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
|
7838 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
|
7839 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
|
7840 | 0487d6a8 | j_mayer | |
7841 | 0487d6a8 | j_mayer | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
|
7842 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
|
7843 | 0487d6a8 | j_mayer | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
|
7844 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
|
7845 | 0487d6a8 | j_mayer | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
|
7846 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
|
7847 | 0487d6a8 | j_mayer | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
|
7848 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
|
7849 | 0487d6a8 | j_mayer | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
|
7850 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
|
7851 | 0487d6a8 | j_mayer | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
|
7852 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
|
7853 | 0487d6a8 | j_mayer | |
7854 | 0487d6a8 | j_mayer | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
|
7855 | 0487d6a8 | j_mayer | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
|
7856 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
|
7857 | 0487d6a8 | j_mayer | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
|
7858 | 0487d6a8 | j_mayer | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
|
7859 | 0487d6a8 | j_mayer | #endif
|
7860 | 0487d6a8 | j_mayer | |
7861 | 0487d6a8 | j_mayer | /*** SPE floating-point extension ***/
|
7862 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
7863 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
7864 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7865 | 0487d6a8 | j_mayer | { \ |
7866 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
7867 | 1c97856d | aurel32 | TCGv t1; \ |
7868 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7869 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7870 | 1c97856d | aurel32 | gen_helper_##name(t0, t0); \ |
7871 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
7872 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
7873 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7874 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7875 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7876 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
7877 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
7878 | 0487d6a8 | j_mayer | } |
7879 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
7880 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7881 | 1c97856d | aurel32 | { \ |
7882 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
7883 | 1c97856d | aurel32 | TCGv t1; \ |
7884 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7885 | 1c97856d | aurel32 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7886 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
7887 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
7888 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7889 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7890 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7891 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
7892 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
7893 | 1c97856d | aurel32 | } |
7894 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
7895 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7896 | 1c97856d | aurel32 | { \ |
7897 | 1c97856d | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); \ |
7898 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7899 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
7900 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7901 | 1c97856d | aurel32 | } |
7902 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
7903 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7904 | 1c97856d | aurel32 | { \ |
7905 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7906 | 1c97856d | aurel32 | } |
7907 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
7908 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7909 | 57951c27 | aurel32 | { \ |
7910 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
7911 | 1c97856d | aurel32 | TCGv_i64 t2; \ |
7912 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7913 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7914 | 57951c27 | aurel32 | return; \
|
7915 | 57951c27 | aurel32 | } \ |
7916 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7917 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
7918 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7919 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
7920 | 1c97856d | aurel32 | gen_helper_##name(t0, t0, t1); \ |
7921 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
7922 | 1c97856d | aurel32 | t2 = tcg_temp_new(); \ |
7923 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t2, t0); \ |
7924 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7925 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
7926 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
7927 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ |
7928 | 1c97856d | aurel32 | tcg_temp_free(t2); \ |
7929 | 57951c27 | aurel32 | } |
7930 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
7931 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7932 | 57951c27 | aurel32 | { \ |
7933 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7934 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7935 | 57951c27 | aurel32 | return; \
|
7936 | 57951c27 | aurel32 | } \ |
7937 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7938 | 1c97856d | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
7939 | 57951c27 | aurel32 | } |
7940 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
7941 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7942 | 57951c27 | aurel32 | { \ |
7943 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
7944 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7945 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7946 | 57951c27 | aurel32 | return; \
|
7947 | 57951c27 | aurel32 | } \ |
7948 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
7949 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
7950 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7951 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
7952 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
7953 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
7954 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
7955 | 1c97856d | aurel32 | } |
7956 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
7957 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7958 | 1c97856d | aurel32 | { \ |
7959 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7960 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
7961 | 1c97856d | aurel32 | return; \
|
7962 | 1c97856d | aurel32 | } \ |
7963 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
7964 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7965 | 1c97856d | aurel32 | } |
7966 | 1c97856d | aurel32 | #else
|
7967 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
7968 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7969 | 1c97856d | aurel32 | { \ |
7970 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7971 | 57951c27 | aurel32 | } |
7972 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
7973 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7974 | 1c97856d | aurel32 | { \ |
7975 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7976 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
7977 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
7978 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7979 | 1c97856d | aurel32 | } |
7980 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
7981 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7982 | 1c97856d | aurel32 | { \ |
7983 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7984 | 1c97856d | aurel32 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7985 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7986 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7987 | 1c97856d | aurel32 | } |
7988 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
7989 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7990 | 1c97856d | aurel32 | { \ |
7991 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7992 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
7993 | 1c97856d | aurel32 | gen_helper_##name(t0, t0); \ |
7994 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
7995 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
7996 | 1c97856d | aurel32 | } |
7997 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
7998 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7999 | 1c97856d | aurel32 | { \ |
8000 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8001 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
8002 | 1c97856d | aurel32 | return; \
|
8003 | 1c97856d | aurel32 | } \ |
8004 | 1c97856d | aurel32 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ |
8005 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8006 | 1c97856d | aurel32 | } |
8007 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
8008 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8009 | 1c97856d | aurel32 | { \ |
8010 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
8011 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8012 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
8013 | 1c97856d | aurel32 | return; \
|
8014 | 1c97856d | aurel32 | } \ |
8015 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
8016 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
8017 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
8018 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
8019 | 1c97856d | aurel32 | gen_helper_##name(t0, t0, t1); \ |
8020 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8021 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
8022 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
8023 | 1c97856d | aurel32 | } |
8024 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
8025 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8026 | 1c97856d | aurel32 | { \ |
8027 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8028 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
8029 | 1c97856d | aurel32 | return; \
|
8030 | 1c97856d | aurel32 | } \ |
8031 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
8032 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8033 | 1c97856d | aurel32 | } |
8034 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
8035 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8036 | 1c97856d | aurel32 | { \ |
8037 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
8038 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8039 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
8040 | 1c97856d | aurel32 | return; \
|
8041 | 1c97856d | aurel32 | } \ |
8042 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
8043 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
8044 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
8045 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
8046 | 1c97856d | aurel32 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
8047 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
8048 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
8049 | 1c97856d | aurel32 | } |
8050 | 1c97856d | aurel32 | #endif
|
8051 | 57951c27 | aurel32 | |
8052 | 0487d6a8 | j_mayer | /* Single precision floating-point vectors operations */
|
8053 | 0487d6a8 | j_mayer | /* Arithmetic */
|
8054 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8055 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); |
8056 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); |
8057 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); |
8058 | 636aa200 | Blue Swirl | static inline void gen_evfsabs(DisasContext *ctx) |
8059 | 1c97856d | aurel32 | { |
8060 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8061 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8062 | 1c97856d | aurel32 | return;
|
8063 | 1c97856d | aurel32 | } |
8064 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8065 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
|
8066 | 1c97856d | aurel32 | #else
|
8067 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
|
8068 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
8069 | 1c97856d | aurel32 | #endif
|
8070 | 1c97856d | aurel32 | } |
8071 | 636aa200 | Blue Swirl | static inline void gen_evfsnabs(DisasContext *ctx) |
8072 | 1c97856d | aurel32 | { |
8073 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8074 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8075 | 1c97856d | aurel32 | return;
|
8076 | 1c97856d | aurel32 | } |
8077 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8078 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
8079 | 1c97856d | aurel32 | #else
|
8080 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
8081 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
8082 | 1c97856d | aurel32 | #endif
|
8083 | 1c97856d | aurel32 | } |
8084 | 636aa200 | Blue Swirl | static inline void gen_evfsneg(DisasContext *ctx) |
8085 | 1c97856d | aurel32 | { |
8086 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8087 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8088 | 1c97856d | aurel32 | return;
|
8089 | 1c97856d | aurel32 | } |
8090 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8091 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
8092 | 1c97856d | aurel32 | #else
|
8093 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
8094 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
8095 | 1c97856d | aurel32 | #endif
|
8096 | 1c97856d | aurel32 | } |
8097 | 1c97856d | aurel32 | |
8098 | 0487d6a8 | j_mayer | /* Conversion */
|
8099 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8100 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); |
8101 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); |
8102 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); |
8103 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctui); |
8104 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); |
8105 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); |
8106 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); |
8107 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); |
8108 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); |
8109 | 1c97856d | aurel32 | |
8110 | 0487d6a8 | j_mayer | /* Comparison */
|
8111 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8112 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmplt); |
8113 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpeq); |
8114 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststgt); |
8115 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststlt); |
8116 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststeq); |
8117 | 0487d6a8 | j_mayer | |
8118 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
8119 | 40569b7e | aurel32 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
8120 | 40569b7e | aurel32 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // |
8121 | 40569b7e | aurel32 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // |
8122 | 40569b7e | aurel32 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
8123 | 40569b7e | aurel32 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8124 | 40569b7e | aurel32 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8125 | 40569b7e | aurel32 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8126 | 40569b7e | aurel32 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8127 | 40569b7e | aurel32 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8128 | 40569b7e | aurel32 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8129 | 40569b7e | aurel32 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8130 | 40569b7e | aurel32 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); // |
8131 | 40569b7e | aurel32 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8132 | 40569b7e | aurel32 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); // |
8133 | 0487d6a8 | j_mayer | |
8134 | 0487d6a8 | j_mayer | /* Single precision floating-point operations */
|
8135 | 0487d6a8 | j_mayer | /* Arithmetic */
|
8136 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8137 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efssub); |
8138 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); |
8139 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); |
8140 | 636aa200 | Blue Swirl | static inline void gen_efsabs(DisasContext *ctx) |
8141 | 1c97856d | aurel32 | { |
8142 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8143 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8144 | 1c97856d | aurel32 | return;
|
8145 | 1c97856d | aurel32 | } |
8146 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
|
8147 | 1c97856d | aurel32 | } |
8148 | 636aa200 | Blue Swirl | static inline void gen_efsnabs(DisasContext *ctx) |
8149 | 1c97856d | aurel32 | { |
8150 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8151 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8152 | 1c97856d | aurel32 | return;
|
8153 | 1c97856d | aurel32 | } |
8154 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
8155 | 1c97856d | aurel32 | } |
8156 | 636aa200 | Blue Swirl | static inline void gen_efsneg(DisasContext *ctx) |
8157 | 1c97856d | aurel32 | { |
8158 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8159 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8160 | 1c97856d | aurel32 | return;
|
8161 | 1c97856d | aurel32 | } |
8162 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
8163 | 1c97856d | aurel32 | } |
8164 | 1c97856d | aurel32 | |
8165 | 0487d6a8 | j_mayer | /* Conversion */
|
8166 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8167 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsi); |
8168 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfuf); |
8169 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsf); |
8170 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctui); |
8171 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsi); |
8172 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuf); |
8173 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsf); |
8174 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); |
8175 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); |
8176 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efscfd); |
8177 | 1c97856d | aurel32 | |
8178 | 0487d6a8 | j_mayer | /* Comparison */
|
8179 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8180 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmplt); |
8181 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpeq); |
8182 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststgt); |
8183 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststlt); |
8184 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststeq); |
8185 | 0487d6a8 | j_mayer | |
8186 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
8187 | 40569b7e | aurel32 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
8188 | 40569b7e | aurel32 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // |
8189 | 40569b7e | aurel32 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // |
8190 | 40569b7e | aurel32 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
8191 | 40569b7e | aurel32 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8192 | 40569b7e | aurel32 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8193 | 40569b7e | aurel32 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8194 | 40569b7e | aurel32 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8195 | 40569b7e | aurel32 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8196 | 40569b7e | aurel32 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8197 | 40569b7e | aurel32 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8198 | 40569b7e | aurel32 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); // |
8199 | 40569b7e | aurel32 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8200 | 40569b7e | aurel32 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); // |
8201 | 0487d6a8 | j_mayer | |
8202 | 0487d6a8 | j_mayer | /* Double precision floating-point operations */
|
8203 | 0487d6a8 | j_mayer | /* Arithmetic */
|
8204 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8205 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); |
8206 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); |
8207 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); |
8208 | 636aa200 | Blue Swirl | static inline void gen_efdabs(DisasContext *ctx) |
8209 | 1c97856d | aurel32 | { |
8210 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8211 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8212 | 1c97856d | aurel32 | return;
|
8213 | 1c97856d | aurel32 | } |
8214 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8215 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
|
8216 | 1c97856d | aurel32 | #else
|
8217 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8218 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
8219 | 1c97856d | aurel32 | #endif
|
8220 | 1c97856d | aurel32 | } |
8221 | 636aa200 | Blue Swirl | static inline void gen_efdnabs(DisasContext *ctx) |
8222 | 1c97856d | aurel32 | { |
8223 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8224 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8225 | 1c97856d | aurel32 | return;
|
8226 | 1c97856d | aurel32 | } |
8227 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8228 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
8229 | 1c97856d | aurel32 | #else
|
8230 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8231 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
8232 | 1c97856d | aurel32 | #endif
|
8233 | 1c97856d | aurel32 | } |
8234 | 636aa200 | Blue Swirl | static inline void gen_efdneg(DisasContext *ctx) |
8235 | 1c97856d | aurel32 | { |
8236 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8237 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_APU); |
8238 | 1c97856d | aurel32 | return;
|
8239 | 1c97856d | aurel32 | } |
8240 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8241 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
8242 | 1c97856d | aurel32 | #else
|
8243 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8244 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
8245 | 1c97856d | aurel32 | #endif
|
8246 | 1c97856d | aurel32 | } |
8247 | 1c97856d | aurel32 | |
8248 | 0487d6a8 | j_mayer | /* Conversion */
|
8249 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8250 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); |
8251 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); |
8252 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); |
8253 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctui); |
8254 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsi); |
8255 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuf); |
8256 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsf); |
8257 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); |
8258 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); |
8259 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfs); |
8260 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); |
8261 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); |
8262 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); |
8263 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); |
8264 | 0487d6a8 | j_mayer | |
8265 | 0487d6a8 | j_mayer | /* Comparison */
|
8266 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8267 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmplt); |
8268 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpeq); |
8269 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstgt); |
8270 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstlt); |
8271 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtsteq); |
8272 | 0487d6a8 | j_mayer | |
8273 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
8274 | 40569b7e | aurel32 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
8275 | 40569b7e | aurel32 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8276 | 40569b7e | aurel32 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // |
8277 | 40569b7e | aurel32 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // |
8278 | 40569b7e | aurel32 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
8279 | 40569b7e | aurel32 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8280 | 40569b7e | aurel32 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8281 | 40569b7e | aurel32 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8282 | 40569b7e | aurel32 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8283 | 40569b7e | aurel32 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8284 | 40569b7e | aurel32 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8285 | 40569b7e | aurel32 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8286 | 40569b7e | aurel32 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8287 | 40569b7e | aurel32 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // |
8288 | 40569b7e | aurel32 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8289 | 40569b7e | aurel32 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
8290 | 0487d6a8 | j_mayer | |
8291 | c227f099 | Anthony Liguori | static opcode_t opcodes[] = {
|
8292 | 5c55ff99 | Blue Swirl | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8293 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), |
8294 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
8295 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), |
8296 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
8297 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
8298 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8299 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8300 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8301 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8302 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
8303 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), |
8304 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), |
8305 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), |
8306 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8307 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8308 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), |
8309 | 5c55ff99 | Blue Swirl | #endif
|
8310 | 5c55ff99 | Blue Swirl | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), |
8311 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), |
8312 | 5c55ff99 | Blue Swirl | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8313 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8314 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8315 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), |
8316 | 5c55ff99 | Blue Swirl | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
8317 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), |
8318 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8319 | 5c55ff99 | Blue Swirl | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8320 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8321 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8322 | 5c55ff99 | Blue Swirl | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), |
8323 | eaabeef2 | David Gibson | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
8324 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8325 | eaabeef2 | David Gibson | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
8326 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
8327 | 5c55ff99 | Blue Swirl | #endif
|
8328 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8329 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8330 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8331 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), |
8332 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), |
8333 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), |
8334 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), |
8335 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8336 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), |
8337 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), |
8338 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), |
8339 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), |
8340 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), |
8341 | 5c55ff99 | Blue Swirl | #endif
|
8342 | 5c55ff99 | Blue Swirl | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), |
8343 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
8344 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
8345 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), |
8346 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), |
8347 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
8348 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
8349 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), |
8350 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), |
8351 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), |
8352 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), |
8353 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), |
8354 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8355 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), |
8356 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), |
8357 | 5c55ff99 | Blue Swirl | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), |
8358 | 5c55ff99 | Blue Swirl | #endif
|
8359 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8360 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
8361 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), |
8362 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), |
8363 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), |
8364 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), |
8365 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), |
8366 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
8367 | f844c817 | Alexander Graf | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
8368 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8369 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8370 | f844c817 | Alexander Graf | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
8371 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8372 | 5c55ff99 | Blue Swirl | #endif
|
8373 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), |
8374 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), |
8375 | 5c55ff99 | Blue Swirl | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8376 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8377 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), |
8378 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), |
8379 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
8380 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), |
8381 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8382 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), |
8383 | 5c55ff99 | Blue Swirl | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
8384 | 5c55ff99 | Blue Swirl | #endif
|
8385 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), |
8386 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
8387 | 5c55ff99 | Blue Swirl | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
8388 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8389 | 5c55ff99 | Blue Swirl | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), |
8390 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), |
8391 | 5c55ff99 | Blue Swirl | #endif
|
8392 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), |
8393 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), |
8394 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), |
8395 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), |
8396 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), |
8397 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), |
8398 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8399 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), |
8400 | 5c55ff99 | Blue Swirl | #endif
|
8401 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), |
8402 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), |
8403 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
8404 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
8405 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), |
8406 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), |
8407 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), |
8408 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), |
8409 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), |
8410 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
8411 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), |
8412 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
8413 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), |
8414 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
8415 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), |
8416 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), |
8417 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), |
8418 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), |
8419 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8420 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), |
8421 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
8422 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
8423 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), |
8424 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
8425 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
8426 | efdef95f | David Gibson | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8427 | efdef95f | David Gibson | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), |
8428 | efdef95f | David Gibson | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), |
8429 | 5c55ff99 | Blue Swirl | #endif
|
8430 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), |
8431 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), |
8432 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), |
8433 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
8434 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8435 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), |
8436 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
8437 | 5c55ff99 | Blue Swirl | #endif
|
8438 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), |
8439 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), |
8440 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), |
8441 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), |
8442 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), |
8443 | 5c55ff99 | Blue Swirl | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), |
8444 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), |
8445 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), |
8446 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), |
8447 | 5c55ff99 | Blue Swirl | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), |
8448 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), |
8449 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
8450 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), |
8451 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), |
8452 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), |
8453 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), |
8454 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), |
8455 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), |
8456 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), |
8457 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
8458 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), |
8459 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), |
8460 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), |
8461 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), |
8462 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), |
8463 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), |
8464 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), |
8465 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), |
8466 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), |
8467 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), |
8468 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), |
8469 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), |
8470 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), |
8471 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), |
8472 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), |
8473 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), |
8474 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), |
8475 | 5c55ff99 | Blue Swirl | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), |
8476 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), |
8477 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), |
8478 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), |
8479 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), |
8480 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), |
8481 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), |
8482 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), |
8483 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), |
8484 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), |
8485 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), |
8486 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), |
8487 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8488 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8489 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), |
8490 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), |
8491 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8492 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
8493 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), |
8494 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), |
8495 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), |
8496 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), |
8497 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), |
8498 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), |
8499 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), |
8500 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), |
8501 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), |
8502 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), |
8503 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), |
8504 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), |
8505 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), |
8506 | 5c55ff99 | Blue Swirl | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), |
8507 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), |
8508 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), |
8509 | 01662f3e | Alexander Graf | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
8510 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8511 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), |
8512 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), |
8513 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), |
8514 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), |
8515 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), |
8516 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), |
8517 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), |
8518 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
8519 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
8520 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, |
8521 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
8522 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, |
8523 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
8524 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, |
8525 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
8526 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
8527 | fbe73008 | Baojun Wang | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
8528 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
8529 | 01662f3e | Alexander Graf | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
8530 | 01662f3e | Alexander Graf | PPC_BOOKE, PPC2_BOOKE206), |
8531 | 01662f3e | Alexander Graf | GEN_HANDLER_E(msync, 0x1F, 0x16, 0x12, 0x03FFF801, |
8532 | 01662f3e | Alexander Graf | PPC_BOOKE, PPC2_BOOKE206), |
8533 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
8534 | 01662f3e | Alexander Graf | PPC_BOOKE, PPC2_BOOKE206), |
8535 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8536 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), |
8537 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), |
8538 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), |
8539 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), |
8540 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
8541 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), |
8542 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), |
8543 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), |
8544 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), |
8545 | 5c55ff99 | Blue Swirl | |
8546 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD
|
8547 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD_CONST
|
8548 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
8549 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), |
8550 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
8551 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
8552 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), |
8553 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
8554 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
8555 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
8556 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
8557 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
8558 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
8559 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
8560 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
8561 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
8562 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
8563 | 5c55ff99 | Blue Swirl | |
8564 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVW
|
8565 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
8566 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) |
8567 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), |
8568 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), |
8569 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), |
8570 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), |
8571 | 5c55ff99 | Blue Swirl | |
8572 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8573 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVD
|
8574 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
8575 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
8576 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), |
8577 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), |
8578 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), |
8579 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), |
8580 | 5c55ff99 | Blue Swirl | |
8581 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_MUL_HELPER
|
8582 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
|
8583 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
8584 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
|
8585 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
|
8586 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
|
8587 | 5c55ff99 | Blue Swirl | #endif
|
8588 | 5c55ff99 | Blue Swirl | |
8589 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF
|
8590 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF_CONST
|
8591 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
8592 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), |
8593 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
8594 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
8595 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), |
8596 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
8597 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
8598 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
8599 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
8600 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
8601 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
8602 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
8603 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
8604 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
8605 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
8606 | 5c55ff99 | Blue Swirl | |
8607 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL1
|
8608 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL2
|
8609 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
8610 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) |
8611 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
8612 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) |
8613 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
|
8614 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
|
8615 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
|
8616 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
|
8617 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
|
8618 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
|
8619 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
|
8620 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
|
8621 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8622 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
|
8623 | 5c55ff99 | Blue Swirl | #endif
|
8624 | 5c55ff99 | Blue Swirl | |
8625 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8626 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R2
|
8627 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R4
|
8628 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R2(name, opc1, opc2) \
|
8629 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
8630 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
8631 | 5c55ff99 | Blue Swirl | PPC_64B) |
8632 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R4(name, opc1, opc2) \
|
8633 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
8634 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
8635 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
8636 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
8637 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
8638 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
8639 | 5c55ff99 | Blue Swirl | PPC_64B) |
8640 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicl, 0x1E, 0x00), |
8641 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicr, 0x1E, 0x02), |
8642 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldic, 0x1E, 0x04), |
8643 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcl, 0x1E, 0x08), |
8644 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcr, 0x1E, 0x09), |
8645 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldimi, 0x1E, 0x06), |
8646 | 5c55ff99 | Blue Swirl | #endif
|
8647 | 5c55ff99 | Blue Swirl | |
8648 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_ACB
|
8649 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_ACB
|
8650 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AB
|
8651 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AB
|
8652 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AC
|
8653 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AC
|
8654 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_B
|
8655 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_BS
|
8656 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
8657 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) |
8658 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
8659 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ |
8660 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) |
8661 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
8662 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
8663 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
8664 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
8665 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
8666 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
8667 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
8668 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
8669 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
8670 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
8671 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
8672 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) |
8673 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
8674 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) |
8675 | 5c55ff99 | Blue Swirl | |
8676 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), |
8677 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), |
8678 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), |
8679 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), |
8680 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), |
8681 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), |
8682 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), |
8683 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), |
8684 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), |
8685 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), |
8686 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), |
8687 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), |
8688 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
8689 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
8690 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
8691 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8692 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), |
8693 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), |
8694 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), |
8695 | 5c55ff99 | Blue Swirl | #endif
|
8696 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), |
8697 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), |
8698 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), |
8699 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), |
8700 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), |
8701 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), |
8702 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), |
8703 | 5c55ff99 | Blue Swirl | |
8704 | 5c55ff99 | Blue Swirl | #undef GEN_LD
|
8705 | 5c55ff99 | Blue Swirl | #undef GEN_LDU
|
8706 | 5c55ff99 | Blue Swirl | #undef GEN_LDUX
|
8707 | 5c55ff99 | Blue Swirl | #undef GEN_LDX
|
8708 | 5c55ff99 | Blue Swirl | #undef GEN_LDS
|
8709 | 5c55ff99 | Blue Swirl | #define GEN_LD(name, ldop, opc, type) \
|
8710 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8711 | 5c55ff99 | Blue Swirl | #define GEN_LDU(name, ldop, opc, type) \
|
8712 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8713 | 5c55ff99 | Blue Swirl | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
8714 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
8715 | 5c55ff99 | Blue Swirl | #define GEN_LDX(name, ldop, opc2, opc3, type) \
|
8716 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8717 | 5c55ff99 | Blue Swirl | #define GEN_LDS(name, ldop, op, type) \
|
8718 | 5c55ff99 | Blue Swirl | GEN_LD(name, ldop, op | 0x20, type) \
|
8719 | 5c55ff99 | Blue Swirl | GEN_LDU(name, ldop, op | 0x21, type) \
|
8720 | 5c55ff99 | Blue Swirl | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ |
8721 | 5c55ff99 | Blue Swirl | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
8722 | 5c55ff99 | Blue Swirl | |
8723 | 5c55ff99 | Blue Swirl | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
|
8724 | 5c55ff99 | Blue Swirl | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
|
8725 | 5c55ff99 | Blue Swirl | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
|
8726 | 5c55ff99 | Blue Swirl | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
|
8727 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8728 | 5c55ff99 | Blue Swirl | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) |
8729 | 5c55ff99 | Blue Swirl | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) |
8730 | 5c55ff99 | Blue Swirl | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) |
8731 | 5c55ff99 | Blue Swirl | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) |
8732 | 5c55ff99 | Blue Swirl | #endif
|
8733 | 5c55ff99 | Blue Swirl | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) |
8734 | 5c55ff99 | Blue Swirl | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) |
8735 | 5c55ff99 | Blue Swirl | |
8736 | 5c55ff99 | Blue Swirl | #undef GEN_ST
|
8737 | 5c55ff99 | Blue Swirl | #undef GEN_STU
|
8738 | 5c55ff99 | Blue Swirl | #undef GEN_STUX
|
8739 | 5c55ff99 | Blue Swirl | #undef GEN_STX
|
8740 | 5c55ff99 | Blue Swirl | #undef GEN_STS
|
8741 | 5c55ff99 | Blue Swirl | #define GEN_ST(name, stop, opc, type) \
|
8742 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8743 | 5c55ff99 | Blue Swirl | #define GEN_STU(name, stop, opc, type) \
|
8744 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8745 | 5c55ff99 | Blue Swirl | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
8746 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
8747 | 5c55ff99 | Blue Swirl | #define GEN_STX(name, stop, opc2, opc3, type) \
|
8748 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8749 | 5c55ff99 | Blue Swirl | #define GEN_STS(name, stop, op, type) \
|
8750 | 5c55ff99 | Blue Swirl | GEN_ST(name, stop, op | 0x20, type) \
|
8751 | 5c55ff99 | Blue Swirl | GEN_STU(name, stop, op | 0x21, type) \
|
8752 | 5c55ff99 | Blue Swirl | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ |
8753 | 5c55ff99 | Blue Swirl | GEN_STX(name, stop, 0x17, op | 0x00, type) |
8754 | 5c55ff99 | Blue Swirl | |
8755 | 5c55ff99 | Blue Swirl | GEN_STS(stb, st8, 0x06, PPC_INTEGER)
|
8756 | 5c55ff99 | Blue Swirl | GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
|
8757 | 5c55ff99 | Blue Swirl | GEN_STS(stw, st32, 0x04, PPC_INTEGER)
|
8758 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
8759 | 5c55ff99 | Blue Swirl | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) |
8760 | 5c55ff99 | Blue Swirl | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) |
8761 | 5c55ff99 | Blue Swirl | #endif
|
8762 | 5c55ff99 | Blue Swirl | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) |
8763 | 5c55ff99 | Blue Swirl | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) |
8764 | 5c55ff99 | Blue Swirl | |
8765 | 5c55ff99 | Blue Swirl | #undef GEN_LDF
|
8766 | 5c55ff99 | Blue Swirl | #undef GEN_LDUF
|
8767 | 5c55ff99 | Blue Swirl | #undef GEN_LDUXF
|
8768 | 5c55ff99 | Blue Swirl | #undef GEN_LDXF
|
8769 | 5c55ff99 | Blue Swirl | #undef GEN_LDFS
|
8770 | 5c55ff99 | Blue Swirl | #define GEN_LDF(name, ldop, opc, type) \
|
8771 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8772 | 5c55ff99 | Blue Swirl | #define GEN_LDUF(name, ldop, opc, type) \
|
8773 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8774 | 5c55ff99 | Blue Swirl | #define GEN_LDUXF(name, ldop, opc, type) \
|
8775 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
8776 | 5c55ff99 | Blue Swirl | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
8777 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8778 | 5c55ff99 | Blue Swirl | #define GEN_LDFS(name, ldop, op, type) \
|
8779 | 5c55ff99 | Blue Swirl | GEN_LDF(name, ldop, op | 0x20, type) \
|
8780 | 5c55ff99 | Blue Swirl | GEN_LDUF(name, ldop, op | 0x21, type) \
|
8781 | 5c55ff99 | Blue Swirl | GEN_LDUXF(name, ldop, op | 0x01, type) \
|
8782 | 5c55ff99 | Blue Swirl | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
8783 | 5c55ff99 | Blue Swirl | |
8784 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
|
8785 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
|
8786 | 5c55ff99 | Blue Swirl | |
8787 | 5c55ff99 | Blue Swirl | #undef GEN_STF
|
8788 | 5c55ff99 | Blue Swirl | #undef GEN_STUF
|
8789 | 5c55ff99 | Blue Swirl | #undef GEN_STUXF
|
8790 | 5c55ff99 | Blue Swirl | #undef GEN_STXF
|
8791 | 5c55ff99 | Blue Swirl | #undef GEN_STFS
|
8792 | 5c55ff99 | Blue Swirl | #define GEN_STF(name, stop, opc, type) \
|
8793 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
8794 | 5c55ff99 | Blue Swirl | #define GEN_STUF(name, stop, opc, type) \
|
8795 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
8796 | 5c55ff99 | Blue Swirl | #define GEN_STUXF(name, stop, opc, type) \
|
8797 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
8798 | 5c55ff99 | Blue Swirl | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
8799 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
8800 | 5c55ff99 | Blue Swirl | #define GEN_STFS(name, stop, op, type) \
|
8801 | 5c55ff99 | Blue Swirl | GEN_STF(name, stop, op | 0x20, type) \
|
8802 | 5c55ff99 | Blue Swirl | GEN_STUF(name, stop, op | 0x21, type) \
|
8803 | 5c55ff99 | Blue Swirl | GEN_STUXF(name, stop, op | 0x01, type) \
|
8804 | 5c55ff99 | Blue Swirl | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
8805 | 5c55ff99 | Blue Swirl | |
8806 | 5c55ff99 | Blue Swirl | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
|
8807 | 5c55ff99 | Blue Swirl | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
|
8808 | 5c55ff99 | Blue Swirl | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) |
8809 | 5c55ff99 | Blue Swirl | |
8810 | 5c55ff99 | Blue Swirl | #undef GEN_CRLOGIC
|
8811 | 5c55ff99 | Blue Swirl | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
8812 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) |
8813 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
|
8814 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
|
8815 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
|
8816 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
|
8817 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
|
8818 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
|
8819 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
|
8820 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
|
8821 | 5c55ff99 | Blue Swirl | |
8822 | 5c55ff99 | Blue Swirl | #undef GEN_MAC_HANDLER
|
8823 | 5c55ff99 | Blue Swirl | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
8824 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) |
8825 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), |
8826 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), |
8827 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), |
8828 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), |
8829 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), |
8830 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), |
8831 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), |
8832 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), |
8833 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), |
8834 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), |
8835 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), |
8836 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), |
8837 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), |
8838 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), |
8839 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), |
8840 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), |
8841 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), |
8842 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), |
8843 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), |
8844 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), |
8845 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), |
8846 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), |
8847 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), |
8848 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), |
8849 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), |
8850 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), |
8851 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), |
8852 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), |
8853 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), |
8854 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), |
8855 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), |
8856 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), |
8857 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), |
8858 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), |
8859 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), |
8860 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), |
8861 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), |
8862 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), |
8863 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), |
8864 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), |
8865 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), |
8866 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), |
8867 | 5c55ff99 | Blue Swirl | |
8868 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LDX
|
8869 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STX
|
8870 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LVE
|
8871 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STVE
|
8872 | 5c55ff99 | Blue Swirl | #define GEN_VR_LDX(name, opc2, opc3) \
|
8873 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8874 | 5c55ff99 | Blue Swirl | #define GEN_VR_STX(name, opc2, opc3) \
|
8875 | 5c55ff99 | Blue Swirl | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8876 | 5c55ff99 | Blue Swirl | #define GEN_VR_LVE(name, opc2, opc3) \
|
8877 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8878 | 5c55ff99 | Blue Swirl | #define GEN_VR_STVE(name, opc2, opc3) \
|
8879 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
8880 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvx, 0x07, 0x03), |
8881 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvxl, 0x07, 0x0B), |
8882 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(bx, 0x07, 0x00), |
8883 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(hx, 0x07, 0x01), |
8884 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(wx, 0x07, 0x02), |
8885 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svx, 0x07, 0x07), |
8886 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svxl, 0x07, 0x0F), |
8887 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(bx, 0x07, 0x04), |
8888 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(hx, 0x07, 0x05), |
8889 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(wx, 0x07, 0x06), |
8890 | 5c55ff99 | Blue Swirl | |
8891 | 5c55ff99 | Blue Swirl | #undef GEN_VX_LOGICAL
|
8892 | 5c55ff99 | Blue Swirl | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
8893 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8894 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
8895 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), |
8896 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), |
8897 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), |
8898 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), |
8899 | 5c55ff99 | Blue Swirl | |
8900 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM
|
8901 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM(name, opc2, opc3) \
|
8902 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
8903 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubm, 0, 0), |
8904 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhm, 0, 1), |
8905 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduwm, 0, 2), |
8906 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububm, 0, 16), |
8907 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhm, 0, 17), |
8908 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuwm, 0, 18), |
8909 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxub, 1, 0), |
8910 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuh, 1, 1), |
8911 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuw, 1, 2), |
8912 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsb, 1, 4), |
8913 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsh, 1, 5), |
8914 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsw, 1, 6), |
8915 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminub, 1, 8), |
8916 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuh, 1, 9), |
8917 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuw, 1, 10), |
8918 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsb, 1, 12), |
8919 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsh, 1, 13), |
8920 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsw, 1, 14), |
8921 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgub, 1, 16), |
8922 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguh, 1, 17), |
8923 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguw, 1, 18), |
8924 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsb, 1, 20), |
8925 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsh, 1, 21), |
8926 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsw, 1, 22), |
8927 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghb, 6, 0), |
8928 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghh, 6, 1), |
8929 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghw, 6, 2), |
8930 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglb, 6, 4), |
8931 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglh, 6, 5), |
8932 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglw, 6, 6), |
8933 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuloub, 4, 0), |
8934 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulouh, 4, 1), |
8935 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosb, 4, 4), |
8936 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosh, 4, 5), |
8937 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleub, 4, 8), |
8938 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleuh, 4, 9), |
8939 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesb, 4, 12), |
8940 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesh, 4, 13), |
8941 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslb, 2, 4), |
8942 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslh, 2, 5), |
8943 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslw, 2, 6), |
8944 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrb, 2, 8), |
8945 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrh, 2, 9), |
8946 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrw, 2, 10), |
8947 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrab, 2, 12), |
8948 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrah, 2, 13), |
8949 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsraw, 2, 14), |
8950 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslo, 6, 16), |
8951 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsro, 6, 17), |
8952 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddcuw, 0, 6), |
8953 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubcuw, 0, 22), |
8954 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubs, 0, 8), |
8955 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhs, 0, 9), |
8956 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduws, 0, 10), |
8957 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsbs, 0, 12), |
8958 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddshs, 0, 13), |
8959 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsws, 0, 14), |
8960 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububs, 0, 24), |
8961 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhs, 0, 25), |
8962 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuws, 0, 26), |
8963 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsbs, 0, 28), |
8964 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubshs, 0, 29), |
8965 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsws, 0, 30), |
8966 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlb, 2, 0), |
8967 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlh, 2, 1), |
8968 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlw, 2, 2), |
8969 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsl, 2, 7), |
8970 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsr, 2, 11), |
8971 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhum, 7, 0), |
8972 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwum, 7, 1), |
8973 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhus, 7, 2), |
8974 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwus, 7, 3), |
8975 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshus, 7, 4), |
8976 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswus, 7, 5), |
8977 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshss, 7, 6), |
8978 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswss, 7, 7), |
8979 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkpx, 7, 12), |
8980 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4ubs, 4, 24), |
8981 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4sbs, 4, 28), |
8982 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4shs, 4, 25), |
8983 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum2sws, 4, 26), |
8984 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsumsws, 4, 30), |
8985 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddfp, 5, 0), |
8986 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubfp, 5, 1), |
8987 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxfp, 5, 16), |
8988 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminfp, 5, 17), |
8989 | 5c55ff99 | Blue Swirl | |
8990 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM1
|
8991 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM
|
8992 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
8993 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), |
8994 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM(name, opc2, opc3) \
|
8995 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
8996 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
8997 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequb, 3, 0) |
8998 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequh, 3, 1) |
8999 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequw, 3, 2) |
9000 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsb, 3, 12) |
9001 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsh, 3, 13) |
9002 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsw, 3, 14) |
9003 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtub, 3, 8) |
9004 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuh, 3, 9) |
9005 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuw, 3, 10) |
9006 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpeqfp, 3, 3) |
9007 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgefp, 3, 7) |
9008 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtfp, 3, 11) |
9009 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpbfp, 3, 15) |
9010 | 5c55ff99 | Blue Swirl | |
9011 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_SIMM
|
9012 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
9013 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
9014 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisb, 6, 12), |
9015 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltish, 6, 13), |
9016 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisw, 6, 14), |
9017 | 5c55ff99 | Blue Swirl | |
9018 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_NOA
|
9019 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
9020 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) |
9021 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsb, 7, 8), |
9022 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsh, 7, 9), |
9023 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsb, 7, 10), |
9024 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsh, 7, 11), |
9025 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
9026 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklpx, 7, 15), |
9027 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrefp, 5, 4), |
9028 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), |
9029 | 0bffbc6c | Aurelien Jarno | GEN_VXFORM_NOA(vexptefp, 5, 6), |
9030 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vlogefp, 5, 7), |
9031 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfim, 5, 8), |
9032 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfin, 5, 9), |
9033 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfip, 5, 10), |
9034 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfiz, 5, 11), |
9035 | 5c55ff99 | Blue Swirl | |
9036 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_UIMM
|
9037 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
9038 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
9039 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltb, 6, 8), |
9040 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vsplth, 6, 9), |
9041 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltw, 6, 10), |
9042 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfux, 5, 12), |
9043 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfsx, 5, 13), |
9044 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctuxs, 5, 14), |
9045 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctsxs, 5, 15), |
9046 | 5c55ff99 | Blue Swirl | |
9047 | 5c55ff99 | Blue Swirl | #undef GEN_VAFORM_PAIRED
|
9048 | 5c55ff99 | Blue Swirl | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
9049 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) |
9050 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
|
9051 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
|
9052 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
|
9053 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
|
9054 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vsel, vperm, 21),
|
9055 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
|
9056 | 5c55ff99 | Blue Swirl | |
9057 | 5c55ff99 | Blue Swirl | #undef GEN_SPE
|
9058 | 5c55ff99 | Blue Swirl | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
|
9059 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) |
9060 | 5c55ff99 | Blue Swirl | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE), |
9061 | 5c55ff99 | Blue Swirl | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE), |
9062 | 5c55ff99 | Blue Swirl | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE), |
9063 | 5c55ff99 | Blue Swirl | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE), |
9064 | 5c55ff99 | Blue Swirl | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE), |
9065 | 5c55ff99 | Blue Swirl | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE), |
9066 | 5c55ff99 | Blue Swirl | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE), |
9067 | 5c55ff99 | Blue Swirl | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE), |
9068 | a0e13900 | Fabien Chouteau | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE), |
9069 | 5c55ff99 | Blue Swirl | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE), |
9070 | 5c55ff99 | Blue Swirl | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE), |
9071 | 5c55ff99 | Blue Swirl | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE), |
9072 | 5c55ff99 | Blue Swirl | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE), |
9073 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE), |
9074 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE), |
9075 | a0e13900 | Fabien Chouteau | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE), |
9076 | 5c55ff99 | Blue Swirl | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE), |
9077 | 5c55ff99 | Blue Swirl | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE), |
9078 | 5c55ff99 | Blue Swirl | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE), |
9079 | 5c55ff99 | Blue Swirl | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE), |
9080 | 5c55ff99 | Blue Swirl | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE), |
9081 | 5c55ff99 | Blue Swirl | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE), |
9082 | 5c55ff99 | Blue Swirl | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE), |
9083 | 5c55ff99 | Blue Swirl | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE), |
9084 | 5c55ff99 | Blue Swirl | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE), |
9085 | 5c55ff99 | Blue Swirl | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE), |
9086 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE), |
9087 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE), |
9088 | 5c55ff99 | Blue Swirl | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE), |
9089 | 5c55ff99 | Blue Swirl | |
9090 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE), |
9091 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE), |
9092 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE), |
9093 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE), |
9094 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
9095 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
9096 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
9097 | 5c55ff99 | Blue Swirl | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
9098 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
9099 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
9100 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
9101 | 5c55ff99 | Blue Swirl | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE), |
9102 | 5c55ff99 | Blue Swirl | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
9103 | 5c55ff99 | Blue Swirl | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE), |
9104 | 5c55ff99 | Blue Swirl | |
9105 | 5c55ff99 | Blue Swirl | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE), |
9106 | 5c55ff99 | Blue Swirl | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE), |
9107 | 5c55ff99 | Blue Swirl | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE), |
9108 | 5c55ff99 | Blue Swirl | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE), |
9109 | 5c55ff99 | Blue Swirl | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9110 | 5c55ff99 | Blue Swirl | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9111 | 5c55ff99 | Blue Swirl | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9112 | 5c55ff99 | Blue Swirl | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9113 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9114 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9115 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9116 | 5c55ff99 | Blue Swirl | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE), |
9117 | 5c55ff99 | Blue Swirl | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9118 | 5c55ff99 | Blue Swirl | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE), |
9119 | 5c55ff99 | Blue Swirl | |
9120 | 5c55ff99 | Blue Swirl | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE), |
9121 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9122 | 5c55ff99 | Blue Swirl | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), |
9123 | 5c55ff99 | Blue Swirl | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), |
9124 | 5c55ff99 | Blue Swirl | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE), |
9125 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9126 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9127 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9128 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9129 | 5c55ff99 | Blue Swirl | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9130 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9131 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9132 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9133 | 5c55ff99 | Blue Swirl | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE), |
9134 | 5c55ff99 | Blue Swirl | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9135 | 5c55ff99 | Blue Swirl | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE), |
9136 | 5c55ff99 | Blue Swirl | |
9137 | 5c55ff99 | Blue Swirl | #undef GEN_SPEOP_LDST
|
9138 | 5c55ff99 | Blue Swirl | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
9139 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) |
9140 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldd, 0x00, 3), |
9141 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldw, 0x01, 3), |
9142 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldh, 0x02, 3), |
9143 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), |
9144 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), |
9145 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), |
9146 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhe, 0x08, 2), |
9147 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), |
9148 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), |
9149 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), |
9150 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), |
9151 | 5c55ff99 | Blue Swirl | |
9152 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdd, 0x10, 3), |
9153 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdw, 0x11, 3), |
9154 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdh, 0x12, 3), |
9155 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwhe, 0x18, 2), |
9156 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwho, 0x1A, 2), |
9157 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), |
9158 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), |
9159 | 5c55ff99 | Blue Swirl | }; |
9160 | 5c55ff99 | Blue Swirl | |
9161 | 3fc6c082 | bellard | #include "translate_init.c" |
9162 | 0411a972 | j_mayer | #include "helper_regs.h" |
9163 | 79aceca5 | bellard | |
9164 | 9a64fbe4 | bellard | /*****************************************************************************/
|
9165 | 3fc6c082 | bellard | /* Misc PowerPC helpers */
|
9166 | 9a78eead | Stefan Weil | void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
9167 | 36081602 | j_mayer | int flags)
|
9168 | 79aceca5 | bellard | { |
9169 | 3fc6c082 | bellard | #define RGPL 4 |
9170 | 3fc6c082 | bellard | #define RFPL 4 |
9171 | 3fc6c082 | bellard | |
9172 | 79aceca5 | bellard | int i;
|
9173 | 79aceca5 | bellard | |
9174 | 90e189ec | Blue Swirl | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9175 | 9a78eead | Stefan Weil | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
9176 | 9a78eead | Stefan Weil | env->nip, env->lr, env->ctr, env->xer); |
9177 | 90e189ec | Blue Swirl | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9178 | 90e189ec | Blue Swirl | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
|
9179 | 90e189ec | Blue Swirl | env->hflags, env->mmu_idx); |
9180 | d9bce9d9 | j_mayer | #if !defined(NO_TIMER_DUMP)
|
9181 | 9a78eead | Stefan Weil | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
9182 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
9183 | 9a78eead | Stefan Weil | " DECR %08" PRIu32
|
9184 | 76a66253 | j_mayer | #endif
|
9185 | 76a66253 | j_mayer | "\n",
|
9186 | 077fc206 | j_mayer | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
9187 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
9188 | 76a66253 | j_mayer | , cpu_ppc_load_decr(env) |
9189 | 76a66253 | j_mayer | #endif
|
9190 | 76a66253 | j_mayer | ); |
9191 | 077fc206 | j_mayer | #endif
|
9192 | 76a66253 | j_mayer | for (i = 0; i < 32; i++) { |
9193 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == 0) |
9194 | 3fc6c082 | bellard | cpu_fprintf(f, "GPR%02d", i);
|
9195 | b11ebf64 | Blue Swirl | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
|
9196 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == (RGPL - 1)) |
9197 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
9198 | 76a66253 | j_mayer | } |
9199 | 3fc6c082 | bellard | cpu_fprintf(f, "CR ");
|
9200 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) |
9201 | 7fe48483 | bellard | cpu_fprintf(f, "%01x", env->crf[i]);
|
9202 | 7fe48483 | bellard | cpu_fprintf(f, " [");
|
9203 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) { |
9204 | 76a66253 | j_mayer | char a = '-'; |
9205 | 76a66253 | j_mayer | if (env->crf[i] & 0x08) |
9206 | 76a66253 | j_mayer | a = 'L';
|
9207 | 76a66253 | j_mayer | else if (env->crf[i] & 0x04) |
9208 | 76a66253 | j_mayer | a = 'G';
|
9209 | 76a66253 | j_mayer | else if (env->crf[i] & 0x02) |
9210 | 76a66253 | j_mayer | a = 'E';
|
9211 | 7fe48483 | bellard | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
9212 | 76a66253 | j_mayer | } |
9213 | 90e189ec | Blue Swirl | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9214 | 90e189ec | Blue Swirl | env->reserve_addr); |
9215 | 3fc6c082 | bellard | for (i = 0; i < 32; i++) { |
9216 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == 0) |
9217 | 3fc6c082 | bellard | cpu_fprintf(f, "FPR%02d", i);
|
9218 | 26a76461 | bellard | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
|
9219 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == (RFPL - 1)) |
9220 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
9221 | 79aceca5 | bellard | } |
9222 | 7889270a | aurel32 | cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
|
9223 | f2e63a42 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
9224 | 90dc8812 | Scott Wood | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
9225 | 90dc8812 | Scott Wood | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", |
9226 | 90dc8812 | Scott Wood | env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
9227 | 90dc8812 | Scott Wood | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); |
9228 | 90dc8812 | Scott Wood | |
9229 | 90dc8812 | Scott Wood | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx |
9230 | 90dc8812 | Scott Wood | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", |
9231 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], |
9232 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); |
9233 | 90dc8812 | Scott Wood | |
9234 | 90dc8812 | Scott Wood | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx |
9235 | 90dc8812 | Scott Wood | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", |
9236 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], |
9237 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); |
9238 | 90dc8812 | Scott Wood | |
9239 | 90dc8812 | Scott Wood | if (env->excp_model == POWERPC_EXCP_BOOKE) {
|
9240 | 90dc8812 | Scott Wood | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx |
9241 | 90dc8812 | Scott Wood | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", |
9242 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], |
9243 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
9244 | 90dc8812 | Scott Wood | |
9245 | 90dc8812 | Scott Wood | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx |
9246 | 90dc8812 | Scott Wood | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", |
9247 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], |
9248 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); |
9249 | 90dc8812 | Scott Wood | |
9250 | 90dc8812 | Scott Wood | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx |
9251 | 90dc8812 | Scott Wood | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", |
9252 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], |
9253 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); |
9254 | 90dc8812 | Scott Wood | |
9255 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx |
9256 | 90dc8812 | Scott Wood | " EPR " TARGET_FMT_lx "\n", |
9257 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], |
9258 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_EPR]); |
9259 | 90dc8812 | Scott Wood | |
9260 | 90dc8812 | Scott Wood | /* FSL-specific */
|
9261 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx |
9262 | 90dc8812 | Scott Wood | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", |
9263 | 90dc8812 | Scott Wood | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], |
9264 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); |
9265 | 90dc8812 | Scott Wood | |
9266 | 90dc8812 | Scott Wood | /*
|
9267 | 90dc8812 | Scott Wood | * IVORs are left out as they are large and do not change often --
|
9268 | 90dc8812 | Scott Wood | * they can be read with "p $ivor0", "p $ivor1", etc.
|
9269 | 90dc8812 | Scott Wood | */
|
9270 | 90dc8812 | Scott Wood | } |
9271 | 90dc8812 | Scott Wood | |
9272 | 90dc8812 | Scott Wood | switch (env->mmu_model) {
|
9273 | 90dc8812 | Scott Wood | case POWERPC_MMU_32B:
|
9274 | 90dc8812 | Scott Wood | case POWERPC_MMU_601:
|
9275 | 90dc8812 | Scott Wood | case POWERPC_MMU_SOFT_6xx:
|
9276 | 90dc8812 | Scott Wood | case POWERPC_MMU_SOFT_74xx:
|
9277 | 90dc8812 | Scott Wood | #if defined(TARGET_PPC64)
|
9278 | 90dc8812 | Scott Wood | case POWERPC_MMU_620:
|
9279 | 90dc8812 | Scott Wood | case POWERPC_MMU_64B:
|
9280 | 90dc8812 | Scott Wood | #endif
|
9281 | 90dc8812 | Scott Wood | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); |
9282 | 90dc8812 | Scott Wood | break;
|
9283 | 01662f3e | Alexander Graf | case POWERPC_MMU_BOOKE206:
|
9284 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
9285 | 90dc8812 | Scott Wood | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", |
9286 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], |
9287 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); |
9288 | 90dc8812 | Scott Wood | |
9289 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx |
9290 | 90dc8812 | Scott Wood | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", |
9291 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], |
9292 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); |
9293 | 90dc8812 | Scott Wood | |
9294 | 90dc8812 | Scott Wood | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx |
9295 | 90dc8812 | Scott Wood | " TLB1CFG " TARGET_FMT_lx "\n", |
9296 | 90dc8812 | Scott Wood | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], |
9297 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TLB1CFG]); |
9298 | 90dc8812 | Scott Wood | break;
|
9299 | 90dc8812 | Scott Wood | default:
|
9300 | 90dc8812 | Scott Wood | break;
|
9301 | 90dc8812 | Scott Wood | } |
9302 | f2e63a42 | j_mayer | #endif
|
9303 | 79aceca5 | bellard | |
9304 | 3fc6c082 | bellard | #undef RGPL
|
9305 | 3fc6c082 | bellard | #undef RFPL
|
9306 | 79aceca5 | bellard | } |
9307 | 79aceca5 | bellard | |
9308 | 9a78eead | Stefan Weil | void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
|
9309 | 76a66253 | j_mayer | int flags)
|
9310 | 76a66253 | j_mayer | { |
9311 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
9312 | c227f099 | Anthony Liguori | opc_handler_t **t1, **t2, **t3, *handler; |
9313 | 76a66253 | j_mayer | int op1, op2, op3;
|
9314 | 76a66253 | j_mayer | |
9315 | 76a66253 | j_mayer | t1 = env->opcodes; |
9316 | 76a66253 | j_mayer | for (op1 = 0; op1 < 64; op1++) { |
9317 | 76a66253 | j_mayer | handler = t1[op1]; |
9318 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
9319 | 76a66253 | j_mayer | t2 = ind_table(handler); |
9320 | 76a66253 | j_mayer | for (op2 = 0; op2 < 32; op2++) { |
9321 | 76a66253 | j_mayer | handler = t2[op2]; |
9322 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
9323 | 76a66253 | j_mayer | t3 = ind_table(handler); |
9324 | 76a66253 | j_mayer | for (op3 = 0; op3 < 32; op3++) { |
9325 | 76a66253 | j_mayer | handler = t3[op3]; |
9326 | 76a66253 | j_mayer | if (handler->count == 0) |
9327 | 76a66253 | j_mayer | continue;
|
9328 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
|
9329 | 0bfcd599 | Blue Swirl | "%016" PRIx64 " %" PRId64 "\n", |
9330 | 76a66253 | j_mayer | op1, op2, op3, op1, (op3 << 5) | op2,
|
9331 | 76a66253 | j_mayer | handler->oname, |
9332 | 76a66253 | j_mayer | handler->count, handler->count); |
9333 | 76a66253 | j_mayer | } |
9334 | 76a66253 | j_mayer | } else {
|
9335 | 76a66253 | j_mayer | if (handler->count == 0) |
9336 | 76a66253 | j_mayer | continue;
|
9337 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
|
9338 | 0bfcd599 | Blue Swirl | "%016" PRIx64 " %" PRId64 "\n", |
9339 | 76a66253 | j_mayer | op1, op2, op1, op2, handler->oname, |
9340 | 76a66253 | j_mayer | handler->count, handler->count); |
9341 | 76a66253 | j_mayer | } |
9342 | 76a66253 | j_mayer | } |
9343 | 76a66253 | j_mayer | } else {
|
9344 | 76a66253 | j_mayer | if (handler->count == 0) |
9345 | 76a66253 | j_mayer | continue;
|
9346 | 0bfcd599 | Blue Swirl | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
|
9347 | 0bfcd599 | Blue Swirl | " %" PRId64 "\n", |
9348 | 76a66253 | j_mayer | op1, op1, handler->oname, |
9349 | 76a66253 | j_mayer | handler->count, handler->count); |
9350 | 76a66253 | j_mayer | } |
9351 | 76a66253 | j_mayer | } |
9352 | 76a66253 | j_mayer | #endif
|
9353 | 76a66253 | j_mayer | } |
9354 | 76a66253 | j_mayer | |
9355 | 9a64fbe4 | bellard | /*****************************************************************************/
|
9356 | 636aa200 | Blue Swirl | static inline void gen_intermediate_code_internal(CPUState *env, |
9357 | 636aa200 | Blue Swirl | TranslationBlock *tb, |
9358 | 636aa200 | Blue Swirl | int search_pc)
|
9359 | 79aceca5 | bellard | { |
9360 | 9fddaa0c | bellard | DisasContext ctx, *ctxp = &ctx; |
9361 | c227f099 | Anthony Liguori | opc_handler_t **table, *handler; |
9362 | 0fa85d43 | bellard | target_ulong pc_start; |
9363 | 79aceca5 | bellard | uint16_t *gen_opc_end; |
9364 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
9365 | 79aceca5 | bellard | int j, lj = -1; |
9366 | 2e70f6ef | pbrook | int num_insns;
|
9367 | 2e70f6ef | pbrook | int max_insns;
|
9368 | 79aceca5 | bellard | |
9369 | 79aceca5 | bellard | pc_start = tb->pc; |
9370 | 79aceca5 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
9371 | 046d6672 | bellard | ctx.nip = pc_start; |
9372 | 79aceca5 | bellard | ctx.tb = tb; |
9373 | e1833e1f | j_mayer | ctx.exception = POWERPC_EXCP_NONE; |
9374 | 3fc6c082 | bellard | ctx.spr_cb = env->spr_cb; |
9375 | 76db3ba4 | aurel32 | ctx.mem_idx = env->mmu_idx; |
9376 | 76db3ba4 | aurel32 | ctx.access_type = -1;
|
9377 | 76db3ba4 | aurel32 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; |
9378 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
9379 | d9bce9d9 | j_mayer | ctx.sf_mode = msr_sf; |
9380 | 9a64fbe4 | bellard | #endif
|
9381 | 3cc62370 | bellard | ctx.fpu_enabled = msr_fp; |
9382 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
|
9383 | d26bfc9a | j_mayer | ctx.spe_enabled = msr_spe; |
9384 | d26bfc9a | j_mayer | else
|
9385 | d26bfc9a | j_mayer | ctx.spe_enabled = 0;
|
9386 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
|
9387 | a9d9eb8f | j_mayer | ctx.altivec_enabled = msr_vr; |
9388 | a9d9eb8f | j_mayer | else
|
9389 | a9d9eb8f | j_mayer | ctx.altivec_enabled = 0;
|
9390 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_SE) && msr_se)
|
9391 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
9392 | d26bfc9a | j_mayer | else
|
9393 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = 0;
|
9394 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
9395 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9396 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled))
|
9397 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
9398 | 3fc6c082 | bellard | #if defined (DO_SINGLE_STEP) && 0 |
9399 | 9a64fbe4 | bellard | /* Single step trace mode */
|
9400 | 9a64fbe4 | bellard | msr_se = 1;
|
9401 | 9a64fbe4 | bellard | #endif
|
9402 | 2e70f6ef | pbrook | num_insns = 0;
|
9403 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
9404 | 2e70f6ef | pbrook | if (max_insns == 0) |
9405 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
9406 | 2e70f6ef | pbrook | |
9407 | 2e70f6ef | pbrook | gen_icount_start(); |
9408 | 9a64fbe4 | bellard | /* Set env in case of segfault during code fetch */
|
9409 | e1833e1f | j_mayer | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
|
9410 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
9411 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
9412 | a1d1bb31 | aliguori | if (bp->pc == ctx.nip) {
|
9413 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
9414 | ea4e754f | bellard | break;
|
9415 | ea4e754f | bellard | } |
9416 | ea4e754f | bellard | } |
9417 | ea4e754f | bellard | } |
9418 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
9419 | 79aceca5 | bellard | j = gen_opc_ptr - gen_opc_buf; |
9420 | 79aceca5 | bellard | if (lj < j) {
|
9421 | 79aceca5 | bellard | lj++; |
9422 | 79aceca5 | bellard | while (lj < j)
|
9423 | 79aceca5 | bellard | gen_opc_instr_start[lj++] = 0;
|
9424 | 79aceca5 | bellard | } |
9425 | af4b6c54 | aurel32 | gen_opc_pc[lj] = ctx.nip; |
9426 | af4b6c54 | aurel32 | gen_opc_instr_start[lj] = 1;
|
9427 | af4b6c54 | aurel32 | gen_opc_icount[lj] = num_insns; |
9428 | 79aceca5 | bellard | } |
9429 | d12d51d5 | aliguori | LOG_DISAS("----------------\n");
|
9430 | 90e189ec | Blue Swirl | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
9431 | d12d51d5 | aliguori | ctx.nip, ctx.mem_idx, (int)msr_ir);
|
9432 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9433 | 2e70f6ef | pbrook | gen_io_start(); |
9434 | 76db3ba4 | aurel32 | if (unlikely(ctx.le_mode)) {
|
9435 | 056401ea | j_mayer | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
9436 | 056401ea | j_mayer | } else {
|
9437 | 056401ea | j_mayer | ctx.opcode = ldl_code(ctx.nip); |
9438 | 111bfab3 | bellard | } |
9439 | d12d51d5 | aliguori | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
|
9440 | 9a64fbe4 | bellard | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
9441 | 056401ea | j_mayer | opc3(ctx.opcode), little_endian ? "little" : "big"); |
9442 | 731c54f8 | Aurelien Jarno | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
9443 | 731c54f8 | Aurelien Jarno | tcg_gen_debug_insn_start(ctx.nip); |
9444 | 046d6672 | bellard | ctx.nip += 4;
|
9445 | 3fc6c082 | bellard | table = env->opcodes; |
9446 | 2e70f6ef | pbrook | num_insns++; |
9447 | 79aceca5 | bellard | handler = table[opc1(ctx.opcode)]; |
9448 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
9449 | 79aceca5 | bellard | table = ind_table(handler); |
9450 | 79aceca5 | bellard | handler = table[opc2(ctx.opcode)]; |
9451 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
9452 | 79aceca5 | bellard | table = ind_table(handler); |
9453 | 79aceca5 | bellard | handler = table[opc3(ctx.opcode)]; |
9454 | 79aceca5 | bellard | } |
9455 | 79aceca5 | bellard | } |
9456 | 79aceca5 | bellard | /* Is opcode *REALLY* valid ? */
|
9457 | 76a66253 | j_mayer | if (unlikely(handler->handler == &gen_invalid)) {
|
9458 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
9459 | 93fcfe39 | aliguori | qemu_log("invalid/unsupported opcode: "
|
9460 | 90e189ec | Blue Swirl | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9461 | 90e189ec | Blue Swirl | opc1(ctx.opcode), opc2(ctx.opcode), |
9462 | 90e189ec | Blue Swirl | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
9463 | 4b3686fa | bellard | } |
9464 | 76a66253 | j_mayer | } else {
|
9465 | 76a66253 | j_mayer | if (unlikely((ctx.opcode & handler->inval) != 0)) { |
9466 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
9467 | 93fcfe39 | aliguori | qemu_log("invalid bits: %08x for opcode: "
|
9468 | 90e189ec | Blue Swirl | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
9469 | 90e189ec | Blue Swirl | ctx.opcode & handler->inval, opc1(ctx.opcode), |
9470 | 90e189ec | Blue Swirl | opc2(ctx.opcode), opc3(ctx.opcode), |
9471 | 90e189ec | Blue Swirl | ctx.opcode, ctx.nip - 4);
|
9472 | 76a66253 | j_mayer | } |
9473 | e06fcd75 | aurel32 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
9474 | 4b3686fa | bellard | break;
|
9475 | 79aceca5 | bellard | } |
9476 | 79aceca5 | bellard | } |
9477 | 4b3686fa | bellard | (*(handler->handler))(&ctx); |
9478 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
9479 | 76a66253 | j_mayer | handler->count++; |
9480 | 76a66253 | j_mayer | #endif
|
9481 | 9a64fbe4 | bellard | /* Check trace mode exceptions */
|
9482 | 8cbcb4fa | aurel32 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
|
9483 | 8cbcb4fa | aurel32 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
9484 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_SYSCALL && |
9485 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_TRAP && |
9486 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_BRANCH)) { |
9487 | e06fcd75 | aurel32 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
9488 | d26bfc9a | j_mayer | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
9489 | 2e70f6ef | pbrook | (env->singlestep_enabled) || |
9490 | 1b530a6d | aurel32 | singlestep || |
9491 | 2e70f6ef | pbrook | num_insns >= max_insns)) { |
9492 | d26bfc9a | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
9493 | d26bfc9a | j_mayer | * generation
|
9494 | d26bfc9a | j_mayer | */
|
9495 | 8dd4983c | bellard | break;
|
9496 | 76a66253 | j_mayer | } |
9497 | 3fc6c082 | bellard | } |
9498 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
9499 | 2e70f6ef | pbrook | gen_io_end(); |
9500 | e1833e1f | j_mayer | if (ctx.exception == POWERPC_EXCP_NONE) {
|
9501 | c1942362 | bellard | gen_goto_tb(&ctx, 0, ctx.nip);
|
9502 | e1833e1f | j_mayer | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
9503 | 8cbcb4fa | aurel32 | if (unlikely(env->singlestep_enabled)) {
|
9504 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
9505 | 8cbcb4fa | aurel32 | } |
9506 | 76a66253 | j_mayer | /* Generate the return instruction */
|
9507 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
9508 | 9a64fbe4 | bellard | } |
9509 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
9510 | 79aceca5 | bellard | *gen_opc_ptr = INDEX_op_end; |
9511 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
9512 | 9a64fbe4 | bellard | j = gen_opc_ptr - gen_opc_buf; |
9513 | 9a64fbe4 | bellard | lj++; |
9514 | 9a64fbe4 | bellard | while (lj <= j)
|
9515 | 9a64fbe4 | bellard | gen_opc_instr_start[lj++] = 0;
|
9516 | 9a64fbe4 | bellard | } else {
|
9517 | 046d6672 | bellard | tb->size = ctx.nip - pc_start; |
9518 | 2e70f6ef | pbrook | tb->icount = num_insns; |
9519 | 9a64fbe4 | bellard | } |
9520 | d9bce9d9 | j_mayer | #if defined(DEBUG_DISAS)
|
9521 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
9522 | 76a66253 | j_mayer | int flags;
|
9523 | 237c0af0 | j_mayer | flags = env->bfd_mach; |
9524 | 76db3ba4 | aurel32 | flags |= ctx.le_mode << 16;
|
9525 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
9526 | 93fcfe39 | aliguori | log_target_disas(pc_start, ctx.nip - pc_start, flags); |
9527 | 93fcfe39 | aliguori | qemu_log("\n");
|
9528 | 9fddaa0c | bellard | } |
9529 | 79aceca5 | bellard | #endif
|
9530 | 79aceca5 | bellard | } |
9531 | 79aceca5 | bellard | |
9532 | 2cfc5f17 | ths | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
9533 | 79aceca5 | bellard | { |
9534 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
9535 | 79aceca5 | bellard | } |
9536 | 79aceca5 | bellard | |
9537 | 2cfc5f17 | ths | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
9538 | 79aceca5 | bellard | { |
9539 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
9540 | 79aceca5 | bellard | } |
9541 | d2856f1a | aurel32 | |
9542 | e87b7cb0 | Stefan Weil | void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) |
9543 | d2856f1a | aurel32 | { |
9544 | d2856f1a | aurel32 | env->nip = gen_opc_pc[pc_pos]; |
9545 | d2856f1a | aurel32 | } |