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/*
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 *  PowerPC emulation cpu definitions for qemu.
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 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include "config.h"
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#include <inttypes.h>
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//#define PPC_EMULATE_32BITS_HYPV
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#if defined (TARGET_PPC64)
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/* PowerPC 64 definitions */
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#define TARGET_LONG_BITS 64
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#define TARGET_PAGE_BITS 12
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/* Note that the official physical address space bits is 62-M where M
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   is implementation dependent.  I've not looked up M for the set of
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   cpus we emulate at the system level.  */
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#define TARGET_PHYS_ADDR_SPACE_BITS 62
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/* Note that the PPC environment architecture talks about 80 bit virtual
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   addresses, with segmentation.  Obviously that's not all visible to a
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   single process, which is all we're concerned with here.  */
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#ifdef TARGET_ABI32
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#else
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# define TARGET_VIRT_ADDR_SPACE_BITS 64
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#endif
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#else /* defined (TARGET_PPC64) */
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/* PowerPC 32 definitions */
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#define TARGET_LONG_BITS 32
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#if defined(TARGET_PPCEMB)
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/* Specific definitions for PowerPC embedded */
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/* BookE have 36 bits physical address space */
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#if defined(CONFIG_USER_ONLY)
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/* It looks like a lot of Linux programs assume page size
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 * is 4kB long. This is evil, but we have to deal with it...
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 */
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#define TARGET_PAGE_BITS 12
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#else /* defined(CONFIG_USER_ONLY) */
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/* Pages can be 1 kB small */
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#define TARGET_PAGE_BITS 10
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#endif /* defined(CONFIG_USER_ONLY) */
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#else /* defined(TARGET_PPCEMB) */
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/* "standard" PowerPC 32 definitions */
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#define TARGET_PAGE_BITS 12
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#endif /* defined(TARGET_PPCEMB) */
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif /* defined (TARGET_PPC64) */
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#define CPUState struct CPUPPCState
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#include "cpu-defs.h"
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#include <setjmp.h>
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#if defined (TARGET_PPC64)
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#define ELF_MACHINE     EM_PPC64
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#else
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#define ELF_MACHINE     EM_PPC
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#endif
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/*****************************************************************************/
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/* MMU model                                                                 */
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typedef enum powerpc_mmu_t powerpc_mmu_t;
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enum powerpc_mmu_t {
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    POWERPC_MMU_UNKNOWN    = 0x00000000,
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    /* Standard 32 bits PowerPC MMU                            */
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    POWERPC_MMU_32B        = 0x00000001,
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    /* PowerPC 6xx MMU with software TLB                       */
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    POWERPC_MMU_SOFT_6xx   = 0x00000002,
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    /* PowerPC 74xx MMU with software TLB                      */
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    POWERPC_MMU_SOFT_74xx  = 0x00000003,
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    /* PowerPC 4xx MMU with software TLB                       */
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    POWERPC_MMU_SOFT_4xx   = 0x00000004,
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    /* PowerPC 4xx MMU with software TLB and zones protections */
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    POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
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    /* PowerPC MMU in real mode only                           */
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    POWERPC_MMU_REAL       = 0x00000006,
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    /* Freescale MPC8xx MMU model                              */
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    POWERPC_MMU_MPC8xx     = 0x00000007,
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    /* BookE MMU model                                         */
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    POWERPC_MMU_BOOKE      = 0x00000008,
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    /* BookE FSL MMU model                                     */
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    POWERPC_MMU_BOOKE_FSL  = 0x00000009,
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    /* PowerPC 601 MMU model (specific BATs format)            */
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    POWERPC_MMU_601        = 0x0000000A,
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#if defined(TARGET_PPC64)
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#define POWERPC_MMU_64       0x00010000
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    /* 64 bits PowerPC MMU                                     */
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    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
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    /* 620 variant (no segment exceptions)                     */
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    POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
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/* Exception model                                                           */
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typedef enum powerpc_excp_t powerpc_excp_t;
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enum powerpc_excp_t {
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    POWERPC_EXCP_UNKNOWN   = 0,
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    /* Standard PowerPC exception model */
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    POWERPC_EXCP_STD,
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    /* PowerPC 40x exception model      */
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    POWERPC_EXCP_40x,
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    /* PowerPC 601 exception model      */
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    POWERPC_EXCP_601,
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    /* PowerPC 602 exception model      */
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    POWERPC_EXCP_602,
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    /* PowerPC 603 exception model      */
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    POWERPC_EXCP_603,
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    /* PowerPC 603e exception model     */
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    POWERPC_EXCP_603E,
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    /* PowerPC G2 exception model       */
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    POWERPC_EXCP_G2,
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    /* PowerPC 604 exception model      */
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    POWERPC_EXCP_604,
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    /* PowerPC 7x0 exception model      */
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    POWERPC_EXCP_7x0,
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    /* PowerPC 7x5 exception model      */
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    POWERPC_EXCP_7x5,
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    /* PowerPC 74xx exception model     */
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    POWERPC_EXCP_74xx,
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    /* BookE exception model            */
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    POWERPC_EXCP_BOOKE,
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#if defined(TARGET_PPC64)
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    /* PowerPC 970 exception model      */
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    POWERPC_EXCP_970,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
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/* Exception vectors definitions                                             */
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enum {
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    POWERPC_EXCP_NONE    = -1,
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    /* The 64 first entries are used by the PowerPC embedded specification   */
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    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
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    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
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    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
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    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
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    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
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    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
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    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
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    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
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    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
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    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
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    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
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    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
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    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
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    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
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    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
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    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
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    /* Vectors 16 to 31 are reserved                                         */
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    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
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    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
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    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
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    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
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    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
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    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
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    /* Vectors 38 to 63 are reserved                                         */
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    /* Exceptions defined in the PowerPC server specification                */
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    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
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    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
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    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
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    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
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    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
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    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
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    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
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    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
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    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
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    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
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    /* 40x specific exceptions                                               */
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    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
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    /* 601 specific exceptions                                               */
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    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
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    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
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    /* 602 specific exceptions                                               */
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    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
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    /* 602/603 specific exceptions                                           */
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    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
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    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
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    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
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    /* Exceptions available on most PowerPC                                  */
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    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
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    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
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    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
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    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
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    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
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    /* 7xx/74xx specific exceptions                                          */
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    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
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    /* 74xx specific exceptions                                              */
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    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
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    /* 970FX specific exceptions                                             */
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    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
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    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
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    /* Freescale embeded cores specific exceptions                           */
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    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
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    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
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    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
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    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
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    /* EOL                                                                   */
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    POWERPC_EXCP_NB       = 96,
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    /* Qemu exceptions: used internally during code translation              */
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    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
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    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
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    /* Qemu exceptions: special cases we want to stop translation            */
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    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
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    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
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    POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
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};
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/* Exceptions error codes                                                    */
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enum {
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    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
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    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
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    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
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    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
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    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
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    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
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    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
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    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
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    /* FP exceptions                                                         */
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    POWERPC_EXCP_FP            = 0x10,
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    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
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    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
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    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
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    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
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    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
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    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
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    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
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    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
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    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
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    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
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    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
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    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
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    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
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    /* Invalid instruction                                                   */
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    POWERPC_EXCP_INVAL         = 0x20,
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    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
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    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
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    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
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    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
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    /* Privileged instruction                                                */
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    POWERPC_EXCP_PRIV          = 0x30,
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    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
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    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
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    /* Trap                                                                  */
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    POWERPC_EXCP_TRAP          = 0x40,
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};
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/*****************************************************************************/
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/* Input pins model                                                          */
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typedef enum powerpc_input_t powerpc_input_t;
279
enum powerpc_input_t {
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    PPC_FLAGS_INPUT_UNKNOWN = 0,
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    /* PowerPC 6xx bus                  */
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    PPC_FLAGS_INPUT_6xx,
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    /* BookE bus                        */
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    PPC_FLAGS_INPUT_BookE,
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    /* PowerPC 405 bus                  */
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    PPC_FLAGS_INPUT_405,
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    /* PowerPC 970 bus                  */
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    PPC_FLAGS_INPUT_970,
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    /* PowerPC 401 bus                  */
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    PPC_FLAGS_INPUT_401,
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    /* Freescale RCPU bus               */
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    PPC_FLAGS_INPUT_RCPU,
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};
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295
#define PPC_INPUT(env) (env->bus_model)
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/*****************************************************************************/
298
typedef struct ppc_def_t ppc_def_t;
299
typedef struct opc_handler_t opc_handler_t;
300

    
301
/*****************************************************************************/
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/* Types used to describe some PowerPC registers */
303
typedef struct CPUPPCState CPUPPCState;
304
typedef struct ppc_tb_t ppc_tb_t;
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typedef struct ppc_spr_t ppc_spr_t;
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typedef struct ppc_dcr_t ppc_dcr_t;
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typedef union ppc_avr_t ppc_avr_t;
308
typedef union ppc_tlb_t ppc_tlb_t;
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/* SPR access micro-ops generations callbacks */
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struct ppc_spr_t {
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    void (*uea_read)(void *opaque, int gpr_num, int spr_num);
313
    void (*uea_write)(void *opaque, int spr_num, int gpr_num);
314
#if !defined(CONFIG_USER_ONLY)
315
    void (*oea_read)(void *opaque, int gpr_num, int spr_num);
316
    void (*oea_write)(void *opaque, int spr_num, int gpr_num);
317
    void (*hea_read)(void *opaque, int gpr_num, int spr_num);
318
    void (*hea_write)(void *opaque, int spr_num, int gpr_num);
319
#endif
320
    const char *name;
321
};
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323
/* Altivec registers (128 bits) */
324
union ppc_avr_t {
325
    float32 f[4];
326
    uint8_t u8[16];
327
    uint16_t u16[8];
328
    uint32_t u32[4];
329
    int8_t s8[16];
330
    int16_t s16[8];
331
    int32_t s32[4];
332
    uint64_t u64[2];
333
};
334

    
335
#if !defined(CONFIG_USER_ONLY)
336
/* Software TLB cache */
337
typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
338
struct ppc6xx_tlb_t {
339
    target_ulong pte0;
340
    target_ulong pte1;
341
    target_ulong EPN;
342
};
343

    
344
typedef struct ppcemb_tlb_t ppcemb_tlb_t;
345
struct ppcemb_tlb_t {
346
    target_phys_addr_t RPN;
347
    target_ulong EPN;
348
    target_ulong PID;
349
    target_ulong size;
350
    uint32_t prot;
351
    uint32_t attr; /* Storage attributes */
352
};
353

    
354
union ppc_tlb_t {
355
    ppc6xx_tlb_t tlb6;
356
    ppcemb_tlb_t tlbe;
357
};
358
#endif
359

    
360
typedef struct ppc_slb_t ppc_slb_t;
361
struct ppc_slb_t {
362
    uint64_t tmp64;
363
    uint32_t tmp;
364
};
365

    
366
/*****************************************************************************/
367
/* Machine state register bits definition                                    */
368
#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
369
#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
370
#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
371
#define MSR_SHV  60 /* hypervisor state                               hflags */
372
#define MSR_CM   31 /* Computation mode for BookE                     hflags */
373
#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
374
#define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
375
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
376
#define MSR_VR   25 /* altivec available                            x hflags */
377
#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
378
#define MSR_AP   23 /* Access privilege state on 602                  hflags */
379
#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
380
#define MSR_KEY  19 /* key bit on 603e                                       */
381
#define MSR_POW  18 /* Power management                                      */
382
#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
383
#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
384
#define MSR_ILE  16 /* Interrupt little-endian mode                          */
385
#define MSR_EE   15 /* External interrupt enable                             */
386
#define MSR_PR   14 /* Problem state                                  hflags */
387
#define MSR_FP   13 /* Floating point available                       hflags */
388
#define MSR_ME   12 /* Machine check interrupt enable                        */
389
#define MSR_FE0  11 /* Floating point exception mode 0                hflags */
390
#define MSR_SE   10 /* Single-step trace enable                     x hflags */
391
#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
392
#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
393
#define MSR_BE   9  /* Branch trace enable                          x hflags */
394
#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
395
#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
396
#define MSR_AL   7  /* AL bit on POWER                                       */
397
#define MSR_EP   6  /* Exception prefix on 601                               */
398
#define MSR_IR   5  /* Instruction relocate                                  */
399
#define MSR_DR   4  /* Data relocate                                         */
400
#define MSR_PE   3  /* Protection enable on 403                              */
401
#define MSR_PX   2  /* Protection exclusive on 403                  x        */
402
#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
403
#define MSR_RI   1  /* Recoverable interrupt                        1        */
404
#define MSR_LE   0  /* Little-endian mode                           1 hflags */
405

    
406
#define msr_sf   ((env->msr >> MSR_SF)   & 1)
407
#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
408
#define msr_shv  ((env->msr >> MSR_SHV)  & 1)
409
#define msr_cm   ((env->msr >> MSR_CM)   & 1)
410
#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
411
#define msr_thv  ((env->msr >> MSR_THV)  & 1)
412
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
413
#define msr_vr   ((env->msr >> MSR_VR)   & 1)
414
#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
415
#define msr_ap   ((env->msr >> MSR_AP)   & 1)
416
#define msr_sa   ((env->msr >> MSR_SA)   & 1)
417
#define msr_key  ((env->msr >> MSR_KEY)  & 1)
418
#define msr_pow  ((env->msr >> MSR_POW)  & 1)
419
#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
420
#define msr_ce   ((env->msr >> MSR_CE)   & 1)
421
#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
422
#define msr_ee   ((env->msr >> MSR_EE)   & 1)
423
#define msr_pr   ((env->msr >> MSR_PR)   & 1)
424
#define msr_fp   ((env->msr >> MSR_FP)   & 1)
425
#define msr_me   ((env->msr >> MSR_ME)   & 1)
426
#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
427
#define msr_se   ((env->msr >> MSR_SE)   & 1)
428
#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
429
#define msr_uble ((env->msr >> MSR_UBLE) & 1)
430
#define msr_be   ((env->msr >> MSR_BE)   & 1)
431
#define msr_de   ((env->msr >> MSR_DE)   & 1)
432
#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
433
#define msr_al   ((env->msr >> MSR_AL)   & 1)
434
#define msr_ep   ((env->msr >> MSR_EP)   & 1)
435
#define msr_ir   ((env->msr >> MSR_IR)   & 1)
436
#define msr_dr   ((env->msr >> MSR_DR)   & 1)
437
#define msr_pe   ((env->msr >> MSR_PE)   & 1)
438
#define msr_px   ((env->msr >> MSR_PX)   & 1)
439
#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
440
#define msr_ri   ((env->msr >> MSR_RI)   & 1)
441
#define msr_le   ((env->msr >> MSR_LE)   & 1)
442
/* Hypervisor bit is more specific */
443
#if defined(TARGET_PPC64)
444
#define MSR_HVB (1ULL << MSR_SHV)
445
#define msr_hv  msr_shv
446
#else
447
#if defined(PPC_EMULATE_32BITS_HYPV)
448
#define MSR_HVB (1ULL << MSR_THV)
449
#define msr_hv  msr_thv
450
#else
451
#define MSR_HVB (0ULL)
452
#define msr_hv  (0)
453
#endif
454
#endif
455

    
456
/* Exception state register bits definition                                  */
457
#define ESR_ST    23    /* Exception was caused by a store type access.      */
458

    
459
enum {
460
    POWERPC_FLAG_NONE     = 0x00000000,
461
    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
462
    POWERPC_FLAG_SPE      = 0x00000001,
463
    POWERPC_FLAG_VRE      = 0x00000002,
464
    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
465
    POWERPC_FLAG_TGPR     = 0x00000004,
466
    POWERPC_FLAG_CE       = 0x00000008,
467
    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
468
    POWERPC_FLAG_SE       = 0x00000010,
469
    POWERPC_FLAG_DWE      = 0x00000020,
470
    POWERPC_FLAG_UBLE     = 0x00000040,
471
    /* Flag for MSR bit 9 signification (BE/DE)                              */
472
    POWERPC_FLAG_BE       = 0x00000080,
473
    POWERPC_FLAG_DE       = 0x00000100,
474
    /* Flag for MSR bit 2 signification (PX/PMM)                             */
475
    POWERPC_FLAG_PX       = 0x00000200,
476
    POWERPC_FLAG_PMM      = 0x00000400,
477
    /* Flag for special features                                             */
478
    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
479
    POWERPC_FLAG_RTC_CLK  = 0x00010000,
480
    POWERPC_FLAG_BUS_CLK  = 0x00020000,
481
};
482

    
483
/*****************************************************************************/
484
/* Floating point status and control register                                */
485
#define FPSCR_FX     31 /* Floating-point exception summary                  */
486
#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
487
#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
488
#define FPSCR_OX     28 /* Floating-point overflow exception                 */
489
#define FPSCR_UX     27 /* Floating-point underflow exception                */
490
#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
491
#define FPSCR_XX     25 /* Floating-point inexact exception                  */
492
#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
493
#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
494
#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
495
#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
496
#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
497
#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
498
#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
499
#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
500
#define FPSCR_C      16 /* Floating-point result class descriptor            */
501
#define FPSCR_FL     15 /* Floating-point less than or negative              */
502
#define FPSCR_FG     14 /* Floating-point greater than or negative           */
503
#define FPSCR_FE     13 /* Floating-point equal or zero                      */
504
#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
505
#define FPSCR_FPCC   12 /* Floating-point condition code                     */
506
#define FPSCR_FPRF   12 /* Floating-point result flags                       */
507
#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
508
#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
509
#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
510
#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
511
#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
512
#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
513
#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
514
#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
515
#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
516
#define FPSCR_RN1    1
517
#define FPSCR_RN     0  /* Floating-point rounding control                   */
518
#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
519
#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
520
#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
521
#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
522
#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
523
#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
524
#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
525
#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
526
#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
527
#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
528
#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
529
#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
530
#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
531
#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
532
#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
533
#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
534
#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
535
#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
536
#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
537
#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
538
#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
539
#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
540
#define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
541
/* Invalid operation exception summary */
542
#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
543
                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
544
                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
545
                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
546
                                  (1 << FPSCR_VXCVI)))
547
/* exception summary */
548
#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
549
/* enabled exception summary */
550
#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
551
                   0x1F)
552

    
553
/*****************************************************************************/
554
/* Vector status and control register */
555
#define VSCR_NJ                16 /* Vector non-java */
556
#define VSCR_SAT        0 /* Vector saturation */
557
#define vscr_nj                (((env->vscr) >> VSCR_NJ)        & 0x1)
558
#define vscr_sat        (((env->vscr) >> VSCR_SAT)        & 0x1)
559

    
560
/*****************************************************************************/
561
/* The whole PowerPC CPU context */
562
#define NB_MMU_MODES 3
563

    
564
struct CPUPPCState {
565
    /* First are the most commonly used resources
566
     * during translated code execution
567
     */
568
    /* general purpose registers */
569
    target_ulong gpr[32];
570
#if !defined(TARGET_PPC64)
571
    /* Storage for GPR MSB, used by the SPE extension */
572
    target_ulong gprh[32];
573
#endif
574
    /* LR */
575
    target_ulong lr;
576
    /* CTR */
577
    target_ulong ctr;
578
    /* condition register */
579
    uint32_t crf[8];
580
    /* XER */
581
    target_ulong xer;
582
    /* Reservation address */
583
    target_ulong reserve_addr;
584
    /* Reservation value */
585
    target_ulong reserve_val;
586
    /* Reservation store address */
587
    target_ulong reserve_ea;
588
    /* Reserved store source register and size */
589
    target_ulong reserve_info;
590

    
591
    /* Those ones are used in supervisor mode only */
592
    /* machine state register */
593
    target_ulong msr;
594
    /* temporary general purpose registers */
595
    target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
596

    
597
    /* Floating point execution context */
598
    float_status fp_status;
599
    /* floating point registers */
600
    float64 fpr[32];
601
    /* floating point status and control register */
602
    uint32_t fpscr;
603

    
604
    /* Next instruction pointer */
605
    target_ulong nip;
606

    
607
    int access_type; /* when a memory exception occurs, the access
608
                        type is stored here */
609

    
610
    CPU_COMMON
611

    
612
    /* MMU context - only relevant for full system emulation */
613
#if !defined(CONFIG_USER_ONLY)
614
#if defined(TARGET_PPC64)
615
    /* Address space register */
616
    target_ulong asr;
617
    /* PowerPC 64 SLB area */
618
    ppc_slb_t slb[64];
619
    int slb_nr;
620
#endif
621
    /* segment registers */
622
    target_ulong sdr1;
623
    target_ulong sr[32];
624
    /* BATs */
625
    int nb_BATs;
626
    target_ulong DBAT[2][8];
627
    target_ulong IBAT[2][8];
628
    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
629
    int nb_tlb;      /* Total number of TLB                                  */
630
    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
631
    int nb_ways;     /* Number of ways in the TLB set                        */
632
    int last_way;    /* Last used way used to allocate TLB in a LRU way      */
633
    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
634
    int nb_pids;     /* Number of available PID registers                    */
635
    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
636
    /* 403 dedicated access protection registers */
637
    target_ulong pb[4];
638
#endif
639

    
640
    /* Other registers */
641
    /* Special purpose registers */
642
    target_ulong spr[1024];
643
    ppc_spr_t spr_cb[1024];
644
    /* Altivec registers */
645
    ppc_avr_t avr[32];
646
    uint32_t vscr;
647
    /* SPE registers */
648
    uint64_t spe_acc;
649
    uint32_t spe_fscr;
650
    /* SPE and Altivec can share a status since they will never be used
651
     * simultaneously */
652
    float_status vec_status;
653

    
654
    /* Internal devices resources */
655
    /* Time base and decrementer */
656
    ppc_tb_t *tb_env;
657
    /* Device control registers */
658
    ppc_dcr_t *dcr_env;
659

    
660
    int dcache_line_size;
661
    int icache_line_size;
662

    
663
    /* Those resources are used during exception processing */
664
    /* CPU model definition */
665
    target_ulong msr_mask;
666
    powerpc_mmu_t mmu_model;
667
    powerpc_excp_t excp_model;
668
    powerpc_input_t bus_model;
669
    int bfd_mach;
670
    uint32_t flags;
671
    uint64_t insns_flags;
672

    
673
    int error_code;
674
    uint32_t pending_interrupts;
675
#if !defined(CONFIG_USER_ONLY)
676
    /* This is the IRQ controller, which is implementation dependant
677
     * and only relevant when emulating a complete machine.
678
     */
679
    uint32_t irq_input_state;
680
    void **irq_inputs;
681
    /* Exception vectors */
682
    target_ulong excp_vectors[POWERPC_EXCP_NB];
683
    target_ulong excp_prefix;
684
    target_ulong hreset_excp_prefix;
685
    target_ulong ivor_mask;
686
    target_ulong ivpr_mask;
687
    target_ulong hreset_vector;
688
#endif
689

    
690
    /* Those resources are used only during code translation */
691
    /* opcode handlers */
692
    opc_handler_t *opcodes[0x40];
693

    
694
    /* Those resources are used only in Qemu core */
695
    target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
696
    target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
697
    int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
698

    
699
    /* Power management */
700
    int power_mode;
701
    int (*check_pow)(CPUPPCState *env);
702

    
703
    /* temporary hack to handle OSI calls (only used if non NULL) */
704
    int (*osi_call)(struct CPUPPCState *env);
705

    
706
#if !defined(CONFIG_USER_ONLY)
707
    void *load_info;    /* Holds boot loading state.  */
708
#endif
709
};
710

    
711
#if !defined(CONFIG_USER_ONLY)
712
/* Context used internally during MMU translations */
713
typedef struct mmu_ctx_t mmu_ctx_t;
714
struct mmu_ctx_t {
715
    target_phys_addr_t raddr;      /* Real address              */
716
    target_phys_addr_t eaddr;      /* Effective address         */
717
    int prot;                      /* Protection bits           */
718
    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
719
    target_ulong ptem;             /* Virtual segment ID | API  */
720
    int key;                       /* Access key                */
721
    int nx;                        /* Non-execute area          */
722
};
723
#endif
724

    
725
/*****************************************************************************/
726
CPUPPCState *cpu_ppc_init (const char *cpu_model);
727
void ppc_translate_init(void);
728
int cpu_ppc_exec (CPUPPCState *s);
729
void cpu_ppc_close (CPUPPCState *s);
730
/* you can call this signal handler from your SIGBUS and SIGSEGV
731
   signal handlers to inform the virtual CPU of exceptions. non zero
732
   is returned if the signal was handled by the virtual CPU.  */
733
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
734
                            void *puc);
735
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
736
                              int mmu_idx, int is_softmmu);
737
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
738
#if !defined(CONFIG_USER_ONLY)
739
int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
740
                          int rw, int access_type);
741
#endif
742
void do_interrupt (CPUPPCState *env);
743
void ppc_hw_interrupt (CPUPPCState *env);
744

    
745
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
746

    
747
#if !defined(CONFIG_USER_ONLY)
748
void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
749
                       target_ulong pte0, target_ulong pte1);
750
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
751
void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
752
void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
753
void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
754
void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
755
void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
756
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
757
#if defined(TARGET_PPC64)
758
void ppc_store_asr (CPUPPCState *env, target_ulong value);
759
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
760
target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
761
void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
762
#endif /* defined(TARGET_PPC64) */
763
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
764
#endif /* !defined(CONFIG_USER_ONLY) */
765
void ppc_store_msr (CPUPPCState *env, target_ulong value);
766

    
767
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
768

    
769
const ppc_def_t *cpu_ppc_find_by_name (const char *name);
770
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
771

    
772
/* Time-base and decrementer management */
773
#ifndef NO_CPU_IO_DEFS
774
uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
775
uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
776
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
777
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
778
uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
779
uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
780
void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
781
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
782
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
783
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
784
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
785
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
786
uint64_t cpu_ppc_load_purr (CPUPPCState *env);
787
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
788
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
789
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
790
#if !defined(CONFIG_USER_ONLY)
791
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
792
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
793
target_ulong load_40x_pit (CPUPPCState *env);
794
void store_40x_pit (CPUPPCState *env, target_ulong val);
795
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
796
void store_40x_sler (CPUPPCState *env, uint32_t val);
797
void store_booke_tcr (CPUPPCState *env, target_ulong val);
798
void store_booke_tsr (CPUPPCState *env, target_ulong val);
799
void ppc_tlb_invalidate_all (CPUPPCState *env);
800
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
801
#if defined(TARGET_PPC64)
802
void ppc_slb_invalidate_all (CPUPPCState *env);
803
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
804
#endif
805
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
806
#endif
807
#endif
808

    
809
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
810
{
811
    uint64_t gprv;
812

    
813
    gprv = env->gpr[gprn];
814
#if !defined(TARGET_PPC64)
815
    if (env->flags & POWERPC_FLAG_SPE) {
816
        /* If the CPU implements the SPE extension, we have to get the
817
         * high bits of the GPR from the gprh storage area
818
         */
819
        gprv &= 0xFFFFFFFFULL;
820
        gprv |= (uint64_t)env->gprh[gprn] << 32;
821
    }
822
#endif
823

    
824
    return gprv;
825
}
826

    
827
/* Device control registers */
828
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
829
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
830

    
831
#define cpu_init cpu_ppc_init
832
#define cpu_exec cpu_ppc_exec
833
#define cpu_gen_code cpu_ppc_gen_code
834
#define cpu_signal_handler cpu_ppc_signal_handler
835
#define cpu_list ppc_cpu_list
836

    
837
#define CPU_SAVE_VERSION 4
838

    
839
/* MMU modes definitions */
840
#define MMU_MODE0_SUFFIX _user
841
#define MMU_MODE1_SUFFIX _kernel
842
#define MMU_MODE2_SUFFIX _hypv
843
#define MMU_USER_IDX 0
844
static inline int cpu_mmu_index (CPUState *env)
845
{
846
    return env->mmu_idx;
847
}
848

    
849
#if defined(CONFIG_USER_ONLY)
850
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
851
{
852
    if (newsp)
853
        env->gpr[1] = newsp;
854
    env->gpr[3] = 0;
855
}
856
#endif
857

    
858
#include "cpu-all.h"
859

    
860
/*****************************************************************************/
861
/* CRF definitions */
862
#define CRF_LT        3
863
#define CRF_GT        2
864
#define CRF_EQ        1
865
#define CRF_SO        0
866
#define CRF_CH        (1 << CRF_LT)
867
#define CRF_CL        (1 << CRF_GT)
868
#define CRF_CH_OR_CL  (1 << CRF_EQ)
869
#define CRF_CH_AND_CL (1 << CRF_SO)
870

    
871
/* XER definitions */
872
#define XER_SO  31
873
#define XER_OV  30
874
#define XER_CA  29
875
#define XER_CMP  8
876
#define XER_BC   0
877
#define xer_so  ((env->xer >> XER_SO)  &    1)
878
#define xer_ov  ((env->xer >> XER_OV)  &    1)
879
#define xer_ca  ((env->xer >> XER_CA)  &    1)
880
#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
881
#define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
882

    
883
/* SPR definitions */
884
#define SPR_MQ                (0x000)
885
#define SPR_XER               (0x001)
886
#define SPR_601_VRTCU         (0x004)
887
#define SPR_601_VRTCL         (0x005)
888
#define SPR_601_UDECR         (0x006)
889
#define SPR_LR                (0x008)
890
#define SPR_CTR               (0x009)
891
#define SPR_DSISR             (0x012)
892
#define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
893
#define SPR_601_RTCU          (0x014)
894
#define SPR_601_RTCL          (0x015)
895
#define SPR_DECR              (0x016)
896
#define SPR_SDR1              (0x019)
897
#define SPR_SRR0              (0x01A)
898
#define SPR_SRR1              (0x01B)
899
#define SPR_AMR               (0x01D)
900
#define SPR_BOOKE_PID         (0x030)
901
#define SPR_BOOKE_DECAR       (0x036)
902
#define SPR_BOOKE_CSRR0       (0x03A)
903
#define SPR_BOOKE_CSRR1       (0x03B)
904
#define SPR_BOOKE_DEAR        (0x03D)
905
#define SPR_BOOKE_ESR         (0x03E)
906
#define SPR_BOOKE_IVPR        (0x03F)
907
#define SPR_MPC_EIE           (0x050)
908
#define SPR_MPC_EID           (0x051)
909
#define SPR_MPC_NRI           (0x052)
910
#define SPR_CTRL              (0x088)
911
#define SPR_MPC_CMPA          (0x090)
912
#define SPR_MPC_CMPB          (0x091)
913
#define SPR_MPC_CMPC          (0x092)
914
#define SPR_MPC_CMPD          (0x093)
915
#define SPR_MPC_ECR           (0x094)
916
#define SPR_MPC_DER           (0x095)
917
#define SPR_MPC_COUNTA        (0x096)
918
#define SPR_MPC_COUNTB        (0x097)
919
#define SPR_UCTRL             (0x098)
920
#define SPR_MPC_CMPE          (0x098)
921
#define SPR_MPC_CMPF          (0x099)
922
#define SPR_MPC_CMPG          (0x09A)
923
#define SPR_MPC_CMPH          (0x09B)
924
#define SPR_MPC_LCTRL1        (0x09C)
925
#define SPR_MPC_LCTRL2        (0x09D)
926
#define SPR_MPC_ICTRL         (0x09E)
927
#define SPR_MPC_BAR           (0x09F)
928
#define SPR_VRSAVE            (0x100)
929
#define SPR_USPRG0            (0x100)
930
#define SPR_USPRG1            (0x101)
931
#define SPR_USPRG2            (0x102)
932
#define SPR_USPRG3            (0x103)
933
#define SPR_USPRG4            (0x104)
934
#define SPR_USPRG5            (0x105)
935
#define SPR_USPRG6            (0x106)
936
#define SPR_USPRG7            (0x107)
937
#define SPR_VTBL              (0x10C)
938
#define SPR_VTBU              (0x10D)
939
#define SPR_SPRG0             (0x110)
940
#define SPR_SPRG1             (0x111)
941
#define SPR_SPRG2             (0x112)
942
#define SPR_SPRG3             (0x113)
943
#define SPR_SPRG4             (0x114)
944
#define SPR_SCOMC             (0x114)
945
#define SPR_SPRG5             (0x115)
946
#define SPR_SCOMD             (0x115)
947
#define SPR_SPRG6             (0x116)
948
#define SPR_SPRG7             (0x117)
949
#define SPR_ASR               (0x118)
950
#define SPR_EAR               (0x11A)
951
#define SPR_TBL               (0x11C)
952
#define SPR_TBU               (0x11D)
953
#define SPR_TBU40             (0x11E)
954
#define SPR_SVR               (0x11E)
955
#define SPR_BOOKE_PIR         (0x11E)
956
#define SPR_PVR               (0x11F)
957
#define SPR_HSPRG0            (0x130)
958
#define SPR_BOOKE_DBSR        (0x130)
959
#define SPR_HSPRG1            (0x131)
960
#define SPR_HDSISR            (0x132)
961
#define SPR_HDAR              (0x133)
962
#define SPR_BOOKE_DBCR0       (0x134)
963
#define SPR_IBCR              (0x135)
964
#define SPR_PURR              (0x135)
965
#define SPR_BOOKE_DBCR1       (0x135)
966
#define SPR_DBCR              (0x136)
967
#define SPR_HDEC              (0x136)
968
#define SPR_BOOKE_DBCR2       (0x136)
969
#define SPR_HIOR              (0x137)
970
#define SPR_MBAR              (0x137)
971
#define SPR_RMOR              (0x138)
972
#define SPR_BOOKE_IAC1        (0x138)
973
#define SPR_HRMOR             (0x139)
974
#define SPR_BOOKE_IAC2        (0x139)
975
#define SPR_HSRR0             (0x13A)
976
#define SPR_BOOKE_IAC3        (0x13A)
977
#define SPR_HSRR1             (0x13B)
978
#define SPR_BOOKE_IAC4        (0x13B)
979
#define SPR_LPCR              (0x13C)
980
#define SPR_BOOKE_DAC1        (0x13C)
981
#define SPR_LPIDR             (0x13D)
982
#define SPR_DABR2             (0x13D)
983
#define SPR_BOOKE_DAC2        (0x13D)
984
#define SPR_BOOKE_DVC1        (0x13E)
985
#define SPR_BOOKE_DVC2        (0x13F)
986
#define SPR_BOOKE_TSR         (0x150)
987
#define SPR_BOOKE_TCR         (0x154)
988
#define SPR_BOOKE_IVOR0       (0x190)
989
#define SPR_BOOKE_IVOR1       (0x191)
990
#define SPR_BOOKE_IVOR2       (0x192)
991
#define SPR_BOOKE_IVOR3       (0x193)
992
#define SPR_BOOKE_IVOR4       (0x194)
993
#define SPR_BOOKE_IVOR5       (0x195)
994
#define SPR_BOOKE_IVOR6       (0x196)
995
#define SPR_BOOKE_IVOR7       (0x197)
996
#define SPR_BOOKE_IVOR8       (0x198)
997
#define SPR_BOOKE_IVOR9       (0x199)
998
#define SPR_BOOKE_IVOR10      (0x19A)
999
#define SPR_BOOKE_IVOR11      (0x19B)
1000
#define SPR_BOOKE_IVOR12      (0x19C)
1001
#define SPR_BOOKE_IVOR13      (0x19D)
1002
#define SPR_BOOKE_IVOR14      (0x19E)
1003
#define SPR_BOOKE_IVOR15      (0x19F)
1004
#define SPR_BOOKE_SPEFSCR     (0x200)
1005
#define SPR_Exxx_BBEAR        (0x201)
1006
#define SPR_Exxx_BBTAR        (0x202)
1007
#define SPR_Exxx_L1CFG0       (0x203)
1008
#define SPR_Exxx_NPIDR        (0x205)
1009
#define SPR_ATBL              (0x20E)
1010
#define SPR_ATBU              (0x20F)
1011
#define SPR_IBAT0U            (0x210)
1012
#define SPR_BOOKE_IVOR32      (0x210)
1013
#define SPR_RCPU_MI_GRA       (0x210)
1014
#define SPR_IBAT0L            (0x211)
1015
#define SPR_BOOKE_IVOR33      (0x211)
1016
#define SPR_IBAT1U            (0x212)
1017
#define SPR_BOOKE_IVOR34      (0x212)
1018
#define SPR_IBAT1L            (0x213)
1019
#define SPR_BOOKE_IVOR35      (0x213)
1020
#define SPR_IBAT2U            (0x214)
1021
#define SPR_BOOKE_IVOR36      (0x214)
1022
#define SPR_IBAT2L            (0x215)
1023
#define SPR_BOOKE_IVOR37      (0x215)
1024
#define SPR_IBAT3U            (0x216)
1025
#define SPR_IBAT3L            (0x217)
1026
#define SPR_DBAT0U            (0x218)
1027
#define SPR_RCPU_L2U_GRA      (0x218)
1028
#define SPR_DBAT0L            (0x219)
1029
#define SPR_DBAT1U            (0x21A)
1030
#define SPR_DBAT1L            (0x21B)
1031
#define SPR_DBAT2U            (0x21C)
1032
#define SPR_DBAT2L            (0x21D)
1033
#define SPR_DBAT3U            (0x21E)
1034
#define SPR_DBAT3L            (0x21F)
1035
#define SPR_IBAT4U            (0x230)
1036
#define SPR_RPCU_BBCMCR       (0x230)
1037
#define SPR_MPC_IC_CST        (0x230)
1038
#define SPR_Exxx_CTXCR        (0x230)
1039
#define SPR_IBAT4L            (0x231)
1040
#define SPR_MPC_IC_ADR        (0x231)
1041
#define SPR_Exxx_DBCR3        (0x231)
1042
#define SPR_IBAT5U            (0x232)
1043
#define SPR_MPC_IC_DAT        (0x232)
1044
#define SPR_Exxx_DBCNT        (0x232)
1045
#define SPR_IBAT5L            (0x233)
1046
#define SPR_IBAT6U            (0x234)
1047
#define SPR_IBAT6L            (0x235)
1048
#define SPR_IBAT7U            (0x236)
1049
#define SPR_IBAT7L            (0x237)
1050
#define SPR_DBAT4U            (0x238)
1051
#define SPR_RCPU_L2U_MCR      (0x238)
1052
#define SPR_MPC_DC_CST        (0x238)
1053
#define SPR_Exxx_ALTCTXCR     (0x238)
1054
#define SPR_DBAT4L            (0x239)
1055
#define SPR_MPC_DC_ADR        (0x239)
1056
#define SPR_DBAT5U            (0x23A)
1057
#define SPR_BOOKE_MCSRR0      (0x23A)
1058
#define SPR_MPC_DC_DAT        (0x23A)
1059
#define SPR_DBAT5L            (0x23B)
1060
#define SPR_BOOKE_MCSRR1      (0x23B)
1061
#define SPR_DBAT6U            (0x23C)
1062
#define SPR_BOOKE_MCSR        (0x23C)
1063
#define SPR_DBAT6L            (0x23D)
1064
#define SPR_Exxx_MCAR         (0x23D)
1065
#define SPR_DBAT7U            (0x23E)
1066
#define SPR_BOOKE_DSRR0       (0x23E)
1067
#define SPR_DBAT7L            (0x23F)
1068
#define SPR_BOOKE_DSRR1       (0x23F)
1069
#define SPR_BOOKE_SPRG8       (0x25C)
1070
#define SPR_BOOKE_SPRG9       (0x25D)
1071
#define SPR_BOOKE_MAS0        (0x270)
1072
#define SPR_BOOKE_MAS1        (0x271)
1073
#define SPR_BOOKE_MAS2        (0x272)
1074
#define SPR_BOOKE_MAS3        (0x273)
1075
#define SPR_BOOKE_MAS4        (0x274)
1076
#define SPR_BOOKE_MAS5        (0x275)
1077
#define SPR_BOOKE_MAS6        (0x276)
1078
#define SPR_BOOKE_PID1        (0x279)
1079
#define SPR_BOOKE_PID2        (0x27A)
1080
#define SPR_MPC_DPDR          (0x280)
1081
#define SPR_MPC_IMMR          (0x288)
1082
#define SPR_BOOKE_TLB0CFG     (0x2B0)
1083
#define SPR_BOOKE_TLB1CFG     (0x2B1)
1084
#define SPR_BOOKE_TLB2CFG     (0x2B2)
1085
#define SPR_BOOKE_TLB3CFG     (0x2B3)
1086
#define SPR_BOOKE_EPR         (0x2BE)
1087
#define SPR_PERF0             (0x300)
1088
#define SPR_RCPU_MI_RBA0      (0x300)
1089
#define SPR_MPC_MI_CTR        (0x300)
1090
#define SPR_PERF1             (0x301)
1091
#define SPR_RCPU_MI_RBA1      (0x301)
1092
#define SPR_PERF2             (0x302)
1093
#define SPR_RCPU_MI_RBA2      (0x302)
1094
#define SPR_MPC_MI_AP         (0x302)
1095
#define SPR_PERF3             (0x303)
1096
#define SPR_620_PMC1R         (0x303)
1097
#define SPR_RCPU_MI_RBA3      (0x303)
1098
#define SPR_MPC_MI_EPN        (0x303)
1099
#define SPR_PERF4             (0x304)
1100
#define SPR_620_PMC2R         (0x304)
1101
#define SPR_PERF5             (0x305)
1102
#define SPR_MPC_MI_TWC        (0x305)
1103
#define SPR_PERF6             (0x306)
1104
#define SPR_MPC_MI_RPN        (0x306)
1105
#define SPR_PERF7             (0x307)
1106
#define SPR_PERF8             (0x308)
1107
#define SPR_RCPU_L2U_RBA0     (0x308)
1108
#define SPR_MPC_MD_CTR        (0x308)
1109
#define SPR_PERF9             (0x309)
1110
#define SPR_RCPU_L2U_RBA1     (0x309)
1111
#define SPR_MPC_MD_CASID      (0x309)
1112
#define SPR_PERFA             (0x30A)
1113
#define SPR_RCPU_L2U_RBA2     (0x30A)
1114
#define SPR_MPC_MD_AP         (0x30A)
1115
#define SPR_PERFB             (0x30B)
1116
#define SPR_620_MMCR0R        (0x30B)
1117
#define SPR_RCPU_L2U_RBA3     (0x30B)
1118
#define SPR_MPC_MD_EPN        (0x30B)
1119
#define SPR_PERFC             (0x30C)
1120
#define SPR_MPC_MD_TWB        (0x30C)
1121
#define SPR_PERFD             (0x30D)
1122
#define SPR_MPC_MD_TWC        (0x30D)
1123
#define SPR_PERFE             (0x30E)
1124
#define SPR_MPC_MD_RPN        (0x30E)
1125
#define SPR_PERFF             (0x30F)
1126
#define SPR_MPC_MD_TW         (0x30F)
1127
#define SPR_UPERF0            (0x310)
1128
#define SPR_UPERF1            (0x311)
1129
#define SPR_UPERF2            (0x312)
1130
#define SPR_UPERF3            (0x313)
1131
#define SPR_620_PMC1W         (0x313)
1132
#define SPR_UPERF4            (0x314)
1133
#define SPR_620_PMC2W         (0x314)
1134
#define SPR_UPERF5            (0x315)
1135
#define SPR_UPERF6            (0x316)
1136
#define SPR_UPERF7            (0x317)
1137
#define SPR_UPERF8            (0x318)
1138
#define SPR_UPERF9            (0x319)
1139
#define SPR_UPERFA            (0x31A)
1140
#define SPR_UPERFB            (0x31B)
1141
#define SPR_620_MMCR0W        (0x31B)
1142
#define SPR_UPERFC            (0x31C)
1143
#define SPR_UPERFD            (0x31D)
1144
#define SPR_UPERFE            (0x31E)
1145
#define SPR_UPERFF            (0x31F)
1146
#define SPR_RCPU_MI_RA0       (0x320)
1147
#define SPR_MPC_MI_DBCAM      (0x320)
1148
#define SPR_RCPU_MI_RA1       (0x321)
1149
#define SPR_MPC_MI_DBRAM0     (0x321)
1150
#define SPR_RCPU_MI_RA2       (0x322)
1151
#define SPR_MPC_MI_DBRAM1     (0x322)
1152
#define SPR_RCPU_MI_RA3       (0x323)
1153
#define SPR_RCPU_L2U_RA0      (0x328)
1154
#define SPR_MPC_MD_DBCAM      (0x328)
1155
#define SPR_RCPU_L2U_RA1      (0x329)
1156
#define SPR_MPC_MD_DBRAM0     (0x329)
1157
#define SPR_RCPU_L2U_RA2      (0x32A)
1158
#define SPR_MPC_MD_DBRAM1     (0x32A)
1159
#define SPR_RCPU_L2U_RA3      (0x32B)
1160
#define SPR_440_INV0          (0x370)
1161
#define SPR_440_INV1          (0x371)
1162
#define SPR_440_INV2          (0x372)
1163
#define SPR_440_INV3          (0x373)
1164
#define SPR_440_ITV0          (0x374)
1165
#define SPR_440_ITV1          (0x375)
1166
#define SPR_440_ITV2          (0x376)
1167
#define SPR_440_ITV3          (0x377)
1168
#define SPR_440_CCR1          (0x378)
1169
#define SPR_DCRIPR            (0x37B)
1170
#define SPR_PPR               (0x380)
1171
#define SPR_750_GQR0          (0x390)
1172
#define SPR_440_DNV0          (0x390)
1173
#define SPR_750_GQR1          (0x391)
1174
#define SPR_440_DNV1          (0x391)
1175
#define SPR_750_GQR2          (0x392)
1176
#define SPR_440_DNV2          (0x392)
1177
#define SPR_750_GQR3          (0x393)
1178
#define SPR_440_DNV3          (0x393)
1179
#define SPR_750_GQR4          (0x394)
1180
#define SPR_440_DTV0          (0x394)
1181
#define SPR_750_GQR5          (0x395)
1182
#define SPR_440_DTV1          (0x395)
1183
#define SPR_750_GQR6          (0x396)
1184
#define SPR_440_DTV2          (0x396)
1185
#define SPR_750_GQR7          (0x397)
1186
#define SPR_440_DTV3          (0x397)
1187
#define SPR_750_THRM4         (0x398)
1188
#define SPR_750CL_HID2        (0x398)
1189
#define SPR_440_DVLIM         (0x398)
1190
#define SPR_750_WPAR          (0x399)
1191
#define SPR_440_IVLIM         (0x399)
1192
#define SPR_750_DMAU          (0x39A)
1193
#define SPR_750_DMAL          (0x39B)
1194
#define SPR_440_RSTCFG        (0x39B)
1195
#define SPR_BOOKE_DCDBTRL     (0x39C)
1196
#define SPR_BOOKE_DCDBTRH     (0x39D)
1197
#define SPR_BOOKE_ICDBTRL     (0x39E)
1198
#define SPR_BOOKE_ICDBTRH     (0x39F)
1199
#define SPR_UMMCR2            (0x3A0)
1200
#define SPR_UPMC5             (0x3A1)
1201
#define SPR_UPMC6             (0x3A2)
1202
#define SPR_UBAMR             (0x3A7)
1203
#define SPR_UMMCR0            (0x3A8)
1204
#define SPR_UPMC1             (0x3A9)
1205
#define SPR_UPMC2             (0x3AA)
1206
#define SPR_USIAR             (0x3AB)
1207
#define SPR_UMMCR1            (0x3AC)
1208
#define SPR_UPMC3             (0x3AD)
1209
#define SPR_UPMC4             (0x3AE)
1210
#define SPR_USDA              (0x3AF)
1211
#define SPR_40x_ZPR           (0x3B0)
1212
#define SPR_BOOKE_MAS7        (0x3B0)
1213
#define SPR_620_PMR0          (0x3B0)
1214
#define SPR_MMCR2             (0x3B0)
1215
#define SPR_PMC5              (0x3B1)
1216
#define SPR_40x_PID           (0x3B1)
1217
#define SPR_620_PMR1          (0x3B1)
1218
#define SPR_PMC6              (0x3B2)
1219
#define SPR_440_MMUCR         (0x3B2)
1220
#define SPR_620_PMR2          (0x3B2)
1221
#define SPR_4xx_CCR0          (0x3B3)
1222
#define SPR_BOOKE_EPLC        (0x3B3)
1223
#define SPR_620_PMR3          (0x3B3)
1224
#define SPR_405_IAC3          (0x3B4)
1225
#define SPR_BOOKE_EPSC        (0x3B4)
1226
#define SPR_620_PMR4          (0x3B4)
1227
#define SPR_405_IAC4          (0x3B5)
1228
#define SPR_620_PMR5          (0x3B5)
1229
#define SPR_405_DVC1          (0x3B6)
1230
#define SPR_620_PMR6          (0x3B6)
1231
#define SPR_405_DVC2          (0x3B7)
1232
#define SPR_620_PMR7          (0x3B7)
1233
#define SPR_BAMR              (0x3B7)
1234
#define SPR_MMCR0             (0x3B8)
1235
#define SPR_620_PMR8          (0x3B8)
1236
#define SPR_PMC1              (0x3B9)
1237
#define SPR_40x_SGR           (0x3B9)
1238
#define SPR_620_PMR9          (0x3B9)
1239
#define SPR_PMC2              (0x3BA)
1240
#define SPR_40x_DCWR          (0x3BA)
1241
#define SPR_620_PMRA          (0x3BA)
1242
#define SPR_SIAR              (0x3BB)
1243
#define SPR_405_SLER          (0x3BB)
1244
#define SPR_620_PMRB          (0x3BB)
1245
#define SPR_MMCR1             (0x3BC)
1246
#define SPR_405_SU0R          (0x3BC)
1247
#define SPR_620_PMRC          (0x3BC)
1248
#define SPR_401_SKR           (0x3BC)
1249
#define SPR_PMC3              (0x3BD)
1250
#define SPR_405_DBCR1         (0x3BD)
1251
#define SPR_620_PMRD          (0x3BD)
1252
#define SPR_PMC4              (0x3BE)
1253
#define SPR_620_PMRE          (0x3BE)
1254
#define SPR_SDA               (0x3BF)
1255
#define SPR_620_PMRF          (0x3BF)
1256
#define SPR_403_VTBL          (0x3CC)
1257
#define SPR_403_VTBU          (0x3CD)
1258
#define SPR_DMISS             (0x3D0)
1259
#define SPR_DCMP              (0x3D1)
1260
#define SPR_HASH1             (0x3D2)
1261
#define SPR_HASH2             (0x3D3)
1262
#define SPR_BOOKE_ICDBDR      (0x3D3)
1263
#define SPR_TLBMISS           (0x3D4)
1264
#define SPR_IMISS             (0x3D4)
1265
#define SPR_40x_ESR           (0x3D4)
1266
#define SPR_PTEHI             (0x3D5)
1267
#define SPR_ICMP              (0x3D5)
1268
#define SPR_40x_DEAR          (0x3D5)
1269
#define SPR_PTELO             (0x3D6)
1270
#define SPR_RPA               (0x3D6)
1271
#define SPR_40x_EVPR          (0x3D6)
1272
#define SPR_L3PM              (0x3D7)
1273
#define SPR_403_CDBCR         (0x3D7)
1274
#define SPR_L3ITCR0           (0x3D8)
1275
#define SPR_TCR               (0x3D8)
1276
#define SPR_40x_TSR           (0x3D8)
1277
#define SPR_IBR               (0x3DA)
1278
#define SPR_40x_TCR           (0x3DA)
1279
#define SPR_ESASRR            (0x3DB)
1280
#define SPR_40x_PIT           (0x3DB)
1281
#define SPR_403_TBL           (0x3DC)
1282
#define SPR_403_TBU           (0x3DD)
1283
#define SPR_SEBR              (0x3DE)
1284
#define SPR_40x_SRR2          (0x3DE)
1285
#define SPR_SER               (0x3DF)
1286
#define SPR_40x_SRR3          (0x3DF)
1287
#define SPR_L3OHCR            (0x3E8)
1288
#define SPR_L3ITCR1           (0x3E9)
1289
#define SPR_L3ITCR2           (0x3EA)
1290
#define SPR_L3ITCR3           (0x3EB)
1291
#define SPR_HID0              (0x3F0)
1292
#define SPR_40x_DBSR          (0x3F0)
1293
#define SPR_HID1              (0x3F1)
1294
#define SPR_IABR              (0x3F2)
1295
#define SPR_40x_DBCR0         (0x3F2)
1296
#define SPR_601_HID2          (0x3F2)
1297
#define SPR_Exxx_L1CSR0       (0x3F2)
1298
#define SPR_ICTRL             (0x3F3)
1299
#define SPR_HID2              (0x3F3)
1300
#define SPR_750CL_HID4        (0x3F3)
1301
#define SPR_Exxx_L1CSR1       (0x3F3)
1302
#define SPR_440_DBDR          (0x3F3)
1303
#define SPR_LDSTDB            (0x3F4)
1304
#define SPR_750_TDCL          (0x3F4)
1305
#define SPR_40x_IAC1          (0x3F4)
1306
#define SPR_MMUCSR0           (0x3F4)
1307
#define SPR_DABR              (0x3F5)
1308
#define DABR_MASK (~(target_ulong)0x7)
1309
#define SPR_Exxx_BUCSR        (0x3F5)
1310
#define SPR_40x_IAC2          (0x3F5)
1311
#define SPR_601_HID5          (0x3F5)
1312
#define SPR_40x_DAC1          (0x3F6)
1313
#define SPR_MSSCR0            (0x3F6)
1314
#define SPR_970_HID5          (0x3F6)
1315
#define SPR_MSSSR0            (0x3F7)
1316
#define SPR_MSSCR1            (0x3F7)
1317
#define SPR_DABRX             (0x3F7)
1318
#define SPR_40x_DAC2          (0x3F7)
1319
#define SPR_MMUCFG            (0x3F7)
1320
#define SPR_LDSTCR            (0x3F8)
1321
#define SPR_L2PMCR            (0x3F8)
1322
#define SPR_750FX_HID2        (0x3F8)
1323
#define SPR_620_BUSCSR        (0x3F8)
1324
#define SPR_Exxx_L1FINV0      (0x3F8)
1325
#define SPR_L2CR              (0x3F9)
1326
#define SPR_620_L2CR          (0x3F9)
1327
#define SPR_L3CR              (0x3FA)
1328
#define SPR_750_TDCH          (0x3FA)
1329
#define SPR_IABR2             (0x3FA)
1330
#define SPR_40x_DCCR          (0x3FA)
1331
#define SPR_620_L2SR          (0x3FA)
1332
#define SPR_ICTC              (0x3FB)
1333
#define SPR_40x_ICCR          (0x3FB)
1334
#define SPR_THRM1             (0x3FC)
1335
#define SPR_403_PBL1          (0x3FC)
1336
#define SPR_SP                (0x3FD)
1337
#define SPR_THRM2             (0x3FD)
1338
#define SPR_403_PBU1          (0x3FD)
1339
#define SPR_604_HID13         (0x3FD)
1340
#define SPR_LT                (0x3FE)
1341
#define SPR_THRM3             (0x3FE)
1342
#define SPR_RCPU_FPECR        (0x3FE)
1343
#define SPR_403_PBL2          (0x3FE)
1344
#define SPR_PIR               (0x3FF)
1345
#define SPR_403_PBU2          (0x3FF)
1346
#define SPR_601_HID15         (0x3FF)
1347
#define SPR_604_HID15         (0x3FF)
1348
#define SPR_E500_SVR          (0x3FF)
1349

    
1350
/*****************************************************************************/
1351
/* PowerPC Instructions types definitions                                    */
1352
enum {
1353
    PPC_NONE           = 0x0000000000000000ULL,
1354
    /* PowerPC base instructions set                                         */
1355
    PPC_INSNS_BASE     = 0x0000000000000001ULL,
1356
    /*   integer operations instructions                                     */
1357
#define PPC_INTEGER PPC_INSNS_BASE
1358
    /*   flow control instructions                                           */
1359
#define PPC_FLOW    PPC_INSNS_BASE
1360
    /*   virtual memory instructions                                         */
1361
#define PPC_MEM     PPC_INSNS_BASE
1362
    /*   ld/st with reservation instructions                                 */
1363
#define PPC_RES     PPC_INSNS_BASE
1364
    /*   spr/msr access instructions                                         */
1365
#define PPC_MISC    PPC_INSNS_BASE
1366
    /* Deprecated instruction sets                                           */
1367
    /*   Original POWER instruction set                                      */
1368
    PPC_POWER          = 0x0000000000000002ULL,
1369
    /*   POWER2 instruction set extension                                    */
1370
    PPC_POWER2         = 0x0000000000000004ULL,
1371
    /*   Power RTC support                                                   */
1372
    PPC_POWER_RTC      = 0x0000000000000008ULL,
1373
    /*   Power-to-PowerPC bridge (601)                                       */
1374
    PPC_POWER_BR       = 0x0000000000000010ULL,
1375
    /* 64 bits PowerPC instruction set                                       */
1376
    PPC_64B            = 0x0000000000000020ULL,
1377
    /*   New 64 bits extensions (PowerPC 2.0x)                               */
1378
    PPC_64BX           = 0x0000000000000040ULL,
1379
    /*   64 bits hypervisor extensions                                       */
1380
    PPC_64H            = 0x0000000000000080ULL,
1381
    /*   New wait instruction (PowerPC 2.0x)                                 */
1382
    PPC_WAIT           = 0x0000000000000100ULL,
1383
    /*   Time base mftb instruction                                          */
1384
    PPC_MFTB           = 0x0000000000000200ULL,
1385

    
1386
    /* Fixed-point unit extensions                                           */
1387
    /*   PowerPC 602 specific                                                */
1388
    PPC_602_SPEC       = 0x0000000000000400ULL,
1389
    /*   isel instruction                                                    */
1390
    PPC_ISEL           = 0x0000000000000800ULL,
1391
    /*   popcntb instruction                                                 */
1392
    PPC_POPCNTB        = 0x0000000000001000ULL,
1393
    /*   string load / store                                                 */
1394
    PPC_STRING         = 0x0000000000002000ULL,
1395

    
1396
    /* Floating-point unit extensions                                        */
1397
    /*   Optional floating point instructions                                */
1398
    PPC_FLOAT          = 0x0000000000010000ULL,
1399
    /* New floating-point extensions (PowerPC 2.0x)                          */
1400
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
1401
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
1402
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
1403
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
1404
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1405
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
1406
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
1407

    
1408
    /* Vector/SIMD extensions                                                */
1409
    /*   Altivec support                                                     */
1410
    PPC_ALTIVEC        = 0x0000000001000000ULL,
1411
    /*   PowerPC 2.03 SPE extension                                          */
1412
    PPC_SPE            = 0x0000000002000000ULL,
1413
    /*   PowerPC 2.03 SPE single-precision floating-point extension          */
1414
    PPC_SPE_SINGLE     = 0x0000000004000000ULL,
1415
    /*   PowerPC 2.03 SPE double-precision floating-point extension          */
1416
    PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
1417

    
1418
    /* Optional memory control instructions                                  */
1419
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
1420
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
1421
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
1422
    /*   sync instruction                                                    */
1423
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
1424
    /*   eieio instruction                                                   */
1425
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
1426

    
1427
    /* Cache control instructions                                            */
1428
    PPC_CACHE          = 0x0000000200000000ULL,
1429
    /*   icbi instruction                                                    */
1430
    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
1431
    /*   dcbz instruction with fixed cache line size                         */
1432
    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
1433
    /*   dcbz instruction with tunable cache line size                       */
1434
    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
1435
    /*   dcba instruction                                                    */
1436
    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
1437
    /*   Freescale cache locking instructions                                */
1438
    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
1439

    
1440
    /* MMU related extensions                                                */
1441
    /*   external control instructions                                       */
1442
    PPC_EXTERN         = 0x0000010000000000ULL,
1443
    /*   segment register access instructions                                */
1444
    PPC_SEGMENT        = 0x0000020000000000ULL,
1445
    /*   PowerPC 6xx TLB management instructions                             */
1446
    PPC_6xx_TLB        = 0x0000040000000000ULL,
1447
    /* PowerPC 74xx TLB management instructions                              */
1448
    PPC_74xx_TLB       = 0x0000080000000000ULL,
1449
    /*   PowerPC 40x TLB management instructions                             */
1450
    PPC_40x_TLB        = 0x0000100000000000ULL,
1451
    /*   segment register access instructions for PowerPC 64 "bridge"        */
1452
    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
1453
    /*   SLB management                                                      */
1454
    PPC_SLBI           = 0x0000400000000000ULL,
1455

    
1456
    /* Embedded PowerPC dedicated instructions                               */
1457
    PPC_WRTEE          = 0x0001000000000000ULL,
1458
    /* PowerPC 40x exception model                                           */
1459
    PPC_40x_EXCP       = 0x0002000000000000ULL,
1460
    /* PowerPC 405 Mac instructions                                          */
1461
    PPC_405_MAC        = 0x0004000000000000ULL,
1462
    /* PowerPC 440 specific instructions                                     */
1463
    PPC_440_SPEC       = 0x0008000000000000ULL,
1464
    /* BookE (embedded) PowerPC specification                                */
1465
    PPC_BOOKE          = 0x0010000000000000ULL,
1466
    /* mfapidi instruction                                                   */
1467
    PPC_MFAPIDI        = 0x0020000000000000ULL,
1468
    /* tlbiva instruction                                                    */
1469
    PPC_TLBIVA         = 0x0040000000000000ULL,
1470
    /* tlbivax instruction                                                   */
1471
    PPC_TLBIVAX        = 0x0080000000000000ULL,
1472
    /* PowerPC 4xx dedicated instructions                                    */
1473
    PPC_4xx_COMMON     = 0x0100000000000000ULL,
1474
    /* PowerPC 40x ibct instructions                                         */
1475
    PPC_40x_ICBT       = 0x0200000000000000ULL,
1476
    /* rfmci is not implemented in all BookE PowerPC                         */
1477
    PPC_RFMCI          = 0x0400000000000000ULL,
1478
    /* rfdi instruction                                                      */
1479
    PPC_RFDI           = 0x0800000000000000ULL,
1480
    /* DCR accesses                                                          */
1481
    PPC_DCR            = 0x1000000000000000ULL,
1482
    /* DCR extended accesse                                                  */
1483
    PPC_DCRX           = 0x2000000000000000ULL,
1484
    /* user-mode DCR access, implemented in PowerPC 460                      */
1485
    PPC_DCRUX          = 0x4000000000000000ULL,
1486
};
1487

    
1488
/*****************************************************************************/
1489
/* Memory access type :
1490
 * may be needed for precise access rights control and precise exceptions.
1491
 */
1492
enum {
1493
    /* 1 bit to define user level / supervisor access */
1494
    ACCESS_USER  = 0x00,
1495
    ACCESS_SUPER = 0x01,
1496
    /* Type of instruction that generated the access */
1497
    ACCESS_CODE  = 0x10, /* Code fetch access                */
1498
    ACCESS_INT   = 0x20, /* Integer load/store access        */
1499
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
1500
    ACCESS_RES   = 0x40, /* load/store with reservation      */
1501
    ACCESS_EXT   = 0x50, /* external access                  */
1502
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
1503
};
1504

    
1505
/* Hardware interruption sources:
1506
 * all those exception can be raised simulteaneously
1507
 */
1508
/* Input pins definitions */
1509
enum {
1510
    /* 6xx bus input pins */
1511
    PPC6xx_INPUT_HRESET     = 0,
1512
    PPC6xx_INPUT_SRESET     = 1,
1513
    PPC6xx_INPUT_CKSTP_IN   = 2,
1514
    PPC6xx_INPUT_MCP        = 3,
1515
    PPC6xx_INPUT_SMI        = 4,
1516
    PPC6xx_INPUT_INT        = 5,
1517
    PPC6xx_INPUT_TBEN       = 6,
1518
    PPC6xx_INPUT_WAKEUP     = 7,
1519
    PPC6xx_INPUT_NB,
1520
};
1521

    
1522
enum {
1523
    /* Embedded PowerPC input pins */
1524
    PPCBookE_INPUT_HRESET     = 0,
1525
    PPCBookE_INPUT_SRESET     = 1,
1526
    PPCBookE_INPUT_CKSTP_IN   = 2,
1527
    PPCBookE_INPUT_MCP        = 3,
1528
    PPCBookE_INPUT_SMI        = 4,
1529
    PPCBookE_INPUT_INT        = 5,
1530
    PPCBookE_INPUT_CINT       = 6,
1531
    PPCBookE_INPUT_NB,
1532
};
1533

    
1534
enum {
1535
    /* PowerPC E500 input pins */
1536
    PPCE500_INPUT_RESET_CORE = 0,
1537
    PPCE500_INPUT_MCK        = 1,
1538
    PPCE500_INPUT_CINT       = 3,
1539
    PPCE500_INPUT_INT        = 4,
1540
    PPCE500_INPUT_DEBUG      = 6,
1541
    PPCE500_INPUT_NB,
1542
};
1543

    
1544
enum {
1545
    /* PowerPC 40x input pins */
1546
    PPC40x_INPUT_RESET_CORE = 0,
1547
    PPC40x_INPUT_RESET_CHIP = 1,
1548
    PPC40x_INPUT_RESET_SYS  = 2,
1549
    PPC40x_INPUT_CINT       = 3,
1550
    PPC40x_INPUT_INT        = 4,
1551
    PPC40x_INPUT_HALT       = 5,
1552
    PPC40x_INPUT_DEBUG      = 6,
1553
    PPC40x_INPUT_NB,
1554
};
1555

    
1556
enum {
1557
    /* RCPU input pins */
1558
    PPCRCPU_INPUT_PORESET   = 0,
1559
    PPCRCPU_INPUT_HRESET    = 1,
1560
    PPCRCPU_INPUT_SRESET    = 2,
1561
    PPCRCPU_INPUT_IRQ0      = 3,
1562
    PPCRCPU_INPUT_IRQ1      = 4,
1563
    PPCRCPU_INPUT_IRQ2      = 5,
1564
    PPCRCPU_INPUT_IRQ3      = 6,
1565
    PPCRCPU_INPUT_IRQ4      = 7,
1566
    PPCRCPU_INPUT_IRQ5      = 8,
1567
    PPCRCPU_INPUT_IRQ6      = 9,
1568
    PPCRCPU_INPUT_IRQ7      = 10,
1569
    PPCRCPU_INPUT_NB,
1570
};
1571

    
1572
#if defined(TARGET_PPC64)
1573
enum {
1574
    /* PowerPC 970 input pins */
1575
    PPC970_INPUT_HRESET     = 0,
1576
    PPC970_INPUT_SRESET     = 1,
1577
    PPC970_INPUT_CKSTP      = 2,
1578
    PPC970_INPUT_TBEN       = 3,
1579
    PPC970_INPUT_MCP        = 4,
1580
    PPC970_INPUT_INT        = 5,
1581
    PPC970_INPUT_THINT      = 6,
1582
    PPC970_INPUT_NB,
1583
};
1584
#endif
1585

    
1586
/* Hardware exceptions definitions */
1587
enum {
1588
    /* External hardware exception sources */
1589
    PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
1590
    PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
1591
    PPC_INTERRUPT_MCK,            /* Machine check exception              */
1592
    PPC_INTERRUPT_EXT,            /* External interrupt                   */
1593
    PPC_INTERRUPT_SMI,            /* System management interrupt          */
1594
    PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
1595
    PPC_INTERRUPT_DEBUG,          /* External debug exception             */
1596
    PPC_INTERRUPT_THERM,          /* Thermal exception                    */
1597
    /* Internal hardware exception sources */
1598
    PPC_INTERRUPT_DECR,           /* Decrementer exception                */
1599
    PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
1600
    PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
1601
    PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
1602
    PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
1603
    PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
1604
    PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
1605
    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
1606
};
1607

    
1608
/*****************************************************************************/
1609

    
1610
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1611
                                        target_ulong *cs_base, int *flags)
1612
{
1613
    *pc = env->nip;
1614
    *cs_base = 0;
1615
    *flags = env->hflags;
1616
}
1617

    
1618
static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1619
{
1620
#if defined(TARGET_PPC64)
1621
    /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1622
       binaries on PPC64 yet. */
1623
    env->gpr[13] = newtls;
1624
#else
1625
    env->gpr[2] = newtls;
1626
#endif
1627
}
1628

    
1629
#endif /* !defined (__CPU_PPC_H__) */