Revision 2c7c13d4
b/hw/apic.c | ||
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280 | 280 |
#ifdef DEBUG_APIC |
281 | 281 |
printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
282 | 282 |
#endif |
283 |
if (!s) |
|
284 |
return; |
|
283 | 285 |
s->apicbase = (val & 0xfffff000) | |
284 | 286 |
(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
285 | 287 |
/* if disabled, cannot be enabled again */ |
... | ... | |
294 | 296 |
{ |
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APICState *s = env->apic_state; |
296 | 298 |
#ifdef DEBUG_APIC |
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printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase); |
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printf("cpu_get_apic_base: %016" PRIx64 "\n", |
|
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s ? (uint64_t)s->apicbase: 0); |
|
298 | 301 |
#endif |
299 |
return s->apicbase;
|
|
302 |
return s ? s->apicbase : 0;
|
|
300 | 303 |
} |
301 | 304 |
|
302 | 305 |
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val) |
303 | 306 |
{ |
304 | 307 |
APICState *s = env->apic_state; |
308 |
if (!s) |
|
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return; |
|
305 | 310 |
s->tpr = (val & 0x0f) << 4; |
306 | 311 |
apic_update_irq(s); |
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} |
... | ... | |
309 | 314 |
uint8_t cpu_get_apic_tpr(CPUX86State *env) |
310 | 315 |
{ |
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APICState *s = env->apic_state; |
312 |
return s->tpr >> 4;
|
|
317 |
return s ? s->tpr >> 4 : 0;
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|
313 | 318 |
} |
314 | 319 |
|
315 | 320 |
/* return -1 if no bit is set */ |
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