root / hw / omap2.c @ 2d08cc7c
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/*
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* TI OMAP processors emulation.
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*
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* Copyright (C) 2007-2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "blockdev.h" |
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#include "hw.h" |
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#include "arm-misc.h" |
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#include "omap.h" |
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#include "sysemu.h" |
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#include "qemu-timer.h" |
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#include "qemu-char.h" |
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#include "flash.h" |
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#include "soc_dma.h" |
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#include "audio/audio.h" |
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/* Enhanced Audio Controller (CODEC only) */
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struct omap_eac_s {
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qemu_irq irq; |
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|
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uint16_t sysconfig; |
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uint8_t config[4];
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uint8_t control; |
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uint8_t address; |
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uint16_t data; |
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uint8_t vtol; |
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uint8_t vtsl; |
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uint16_t mixer; |
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uint16_t gain[4];
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uint8_t att; |
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uint16_t max[7];
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|
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struct {
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qemu_irq txdrq; |
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qemu_irq rxdrq; |
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uint32_t (*txrx)(void *opaque, uint32_t, int); |
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void *opaque;
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|
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#define EAC_BUF_LEN 1024 |
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uint32_t rxbuf[EAC_BUF_LEN]; |
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int rxoff;
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int rxlen;
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int rxavail;
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uint32_t txbuf[EAC_BUF_LEN]; |
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int txlen;
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int txavail;
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int enable;
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int rate;
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uint16_t config[4];
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|
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/* These need to be moved to the actual codec */
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QEMUSoundCard card; |
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SWVoiceIn *in_voice; |
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SWVoiceOut *out_voice; |
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int hw_enable;
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} codec; |
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struct {
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uint8_t control; |
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uint16_t config; |
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} modem, bt; |
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}; |
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|
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static inline void omap_eac_interrupt_update(struct omap_eac_s *s) |
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{
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qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */ |
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} |
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|
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static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s) |
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{
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qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) && |
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((s->codec.config[1] >> 12) & 1)); /* DMAREN */ |
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} |
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|
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static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s) |
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{
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qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail && |
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((s->codec.config[1] >> 11) & 1)); /* DMAWEN */ |
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} |
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static inline void omap_eac_in_refill(struct omap_eac_s *s) |
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{
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int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2; |
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int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2; |
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int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start); |
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int recv = 1; |
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uint8_t *buf = (uint8_t *) s->codec.rxbuf + start; |
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left -= leftwrap; |
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start = 0;
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while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
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leftwrap)) > 0) { /* Be defensive */ |
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start += recv; |
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leftwrap -= recv; |
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} |
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if (recv <= 0) |
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s->codec.rxavail = 0;
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else
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s->codec.rxavail -= start >> 2;
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s->codec.rxlen += start >> 2;
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if (recv > 0 && left > 0) { |
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start = 0;
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while (left && (recv = AUD_read(s->codec.in_voice,
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(uint8_t *) s->codec.rxbuf + start, |
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left)) > 0) { /* Be defensive */ |
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start += recv; |
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left -= recv; |
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} |
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if (recv <= 0) |
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s->codec.rxavail = 0;
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else
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s->codec.rxavail -= start >> 2;
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s->codec.rxlen += start >> 2;
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} |
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} |
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static inline void omap_eac_out_empty(struct omap_eac_s *s) |
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{
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int left = s->codec.txlen << 2; |
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int start = 0; |
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int sent = 1; |
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while (left && (sent = AUD_write(s->codec.out_voice,
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(uint8_t *) s->codec.txbuf + start, |
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left)) > 0) { /* Be defensive */ |
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start += sent; |
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left -= sent; |
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} |
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if (!sent) {
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s->codec.txavail = 0;
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omap_eac_out_dmarequest_update(s); |
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} |
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if (start)
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s->codec.txlen = 0;
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} |
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static void omap_eac_in_cb(void *opaque, int avail_b) |
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{
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struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
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s->codec.rxavail = avail_b >> 2;
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omap_eac_in_refill(s); |
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/* TODO: possibly discard current buffer if overrun */
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omap_eac_in_dmarequest_update(s); |
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} |
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static void omap_eac_out_cb(void *opaque, int free_b) |
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{
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struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
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s->codec.txavail = free_b >> 2;
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if (s->codec.txlen)
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omap_eac_out_empty(s); |
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else
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omap_eac_out_dmarequest_update(s); |
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} |
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static void omap_eac_enable_update(struct omap_eac_s *s) |
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{
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s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */ |
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(s->codec.config[1] & 2) && /* AUDEN */ |
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s->codec.hw_enable; |
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} |
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static const int omap_eac_fsint[4] = { |
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8000,
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11025,
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22050,
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44100,
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}; |
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static const int omap_eac_fsint2[8] = { |
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8000,
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11025,
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22050,
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44100,
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48000,
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0, 0, 0, |
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}; |
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static const int omap_eac_fsint3[16] = { |
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8000,
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11025,
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16000,
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22050,
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24000,
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32000,
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44100,
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48000,
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0, 0, 0, 0, 0, 0, 0, 0, |
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}; |
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static void omap_eac_rate_update(struct omap_eac_s *s) |
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{
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int fsint[3]; |
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fsint[2] = (s->codec.config[3] >> 9) & 0xf; |
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fsint[1] = (s->codec.config[2] >> 0) & 0x7; |
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fsint[0] = (s->codec.config[0] >> 6) & 0x3; |
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if (fsint[2] < 0xf) |
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s->codec.rate = omap_eac_fsint3[fsint[2]];
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else if (fsint[1] < 0x7) |
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s->codec.rate = omap_eac_fsint2[fsint[1]];
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else
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s->codec.rate = omap_eac_fsint[fsint[0]];
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} |
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static void omap_eac_volume_update(struct omap_eac_s *s) |
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{
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/* TODO */
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} |
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static void omap_eac_format_update(struct omap_eac_s *s) |
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{
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struct audsettings fmt;
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/* The hardware buffers at most one sample */
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if (s->codec.rxlen)
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s->codec.rxlen = 1;
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if (s->codec.in_voice) {
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AUD_set_active_in(s->codec.in_voice, 0);
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AUD_close_in(&s->codec.card, s->codec.in_voice); |
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s->codec.in_voice = NULL;
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} |
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if (s->codec.out_voice) {
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omap_eac_out_empty(s); |
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AUD_set_active_out(s->codec.out_voice, 0);
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AUD_close_out(&s->codec.card, s->codec.out_voice); |
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s->codec.out_voice = NULL;
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s->codec.txavail = 0;
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} |
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/* Discard what couldn't be written */
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s->codec.txlen = 0;
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omap_eac_enable_update(s); |
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if (!s->codec.enable)
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return;
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omap_eac_rate_update(s); |
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fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */ |
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fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */ |
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fmt.freq = s->codec.rate; |
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/* TODO: signedness possibly depends on the CODEC hardware - or
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* does I2S specify it? */
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/* All register writes are 16 bits so we we store 16-bit samples
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* in the buffers regardless of AGCFR[B8_16] value. */
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fmt.fmt = AUD_FMT_U16; |
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s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice, |
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"eac.codec.in", s, omap_eac_in_cb, &fmt);
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s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice, |
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"eac.codec.out", s, omap_eac_out_cb, &fmt);
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omap_eac_volume_update(s); |
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AUD_set_active_in(s->codec.in_voice, 1);
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AUD_set_active_out(s->codec.out_voice, 1);
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} |
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static void omap_eac_reset(struct omap_eac_s *s) |
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{
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s->sysconfig = 0;
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s->config[0] = 0x0c; |
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s->config[1] = 0x09; |
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s->config[2] = 0xab; |
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s->config[3] = 0x03; |
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s->control = 0x00;
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s->address = 0x00;
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s->data = 0x0000;
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s->vtol = 0x00;
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s->vtsl = 0x00;
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s->mixer = 0x0000;
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s->gain[0] = 0xe7e7; |
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s->gain[1] = 0x6767; |
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s->gain[2] = 0x6767; |
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s->gain[3] = 0x6767; |
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s->att = 0xce;
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s->max[0] = 0; |
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s->max[1] = 0; |
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s->max[2] = 0; |
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s->max[3] = 0; |
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s->max[4] = 0; |
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s->max[5] = 0; |
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s->max[6] = 0; |
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|
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s->modem.control = 0x00;
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s->modem.config = 0x0000;
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s->bt.control = 0x00;
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s->bt.config = 0x0000;
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s->codec.config[0] = 0x0649; |
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s->codec.config[1] = 0x0000; |
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s->codec.config[2] = 0x0007; |
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s->codec.config[3] = 0x1ffc; |
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s->codec.rxoff = 0;
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s->codec.rxlen = 0;
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s->codec.txlen = 0;
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s->codec.rxavail = 0;
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s->codec.txavail = 0;
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omap_eac_format_update(s); |
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omap_eac_interrupt_update(s); |
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} |
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|
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static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
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uint32_t ret; |
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switch (addr) {
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case 0x000: /* CPCFR1 */ |
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return s->config[0]; |
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case 0x004: /* CPCFR2 */ |
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return s->config[1]; |
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case 0x008: /* CPCFR3 */ |
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return s->config[2]; |
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case 0x00c: /* CPCFR4 */ |
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return s->config[3]; |
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|
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case 0x010: /* CPTCTL */ |
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return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) | |
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((s->codec.txlen < s->codec.txavail) << 5);
|
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|
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case 0x014: /* CPTTADR */ |
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return s->address;
|
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case 0x018: /* CPTDATL */ |
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return s->data & 0xff; |
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case 0x01c: /* CPTDATH */ |
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return s->data >> 8; |
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case 0x020: /* CPTVSLL */ |
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return s->vtol;
|
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case 0x024: /* CPTVSLH */ |
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return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */ |
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case 0x040: /* MPCTR */ |
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return s->modem.control;
|
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case 0x044: /* MPMCCFR */ |
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return s->modem.config;
|
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case 0x060: /* BPCTR */ |
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return s->bt.control;
|
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case 0x064: /* BPMCCFR */ |
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return s->bt.config;
|
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case 0x080: /* AMSCFR */ |
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return s->mixer;
|
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case 0x084: /* AMVCTR */ |
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return s->gain[0]; |
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case 0x088: /* AM1VCTR */ |
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return s->gain[1]; |
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case 0x08c: /* AM2VCTR */ |
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return s->gain[2]; |
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case 0x090: /* AM3VCTR */ |
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return s->gain[3]; |
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case 0x094: /* ASTCTR */ |
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return s->att;
|
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case 0x098: /* APD1LCR */ |
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return s->max[0]; |
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case 0x09c: /* APD1RCR */ |
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return s->max[1]; |
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case 0x0a0: /* APD2LCR */ |
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return s->max[2]; |
| 380 |
case 0x0a4: /* APD2RCR */ |
| 381 |
return s->max[3]; |
| 382 |
case 0x0a8: /* APD3LCR */ |
| 383 |
return s->max[4]; |
| 384 |
case 0x0ac: /* APD3RCR */ |
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return s->max[5]; |
| 386 |
case 0x0b0: /* APD4R */ |
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return s->max[6]; |
| 388 |
case 0x0b4: /* ADWR */ |
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/* This should be write-only? Docs list it as read-only. */
|
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return 0x0000; |
| 391 |
case 0x0b8: /* ADRDR */ |
| 392 |
if (likely(s->codec.rxlen > 1)) { |
| 393 |
ret = s->codec.rxbuf[s->codec.rxoff ++]; |
| 394 |
s->codec.rxlen --; |
| 395 |
s->codec.rxoff &= EAC_BUF_LEN - 1;
|
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return ret;
|
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} else if (s->codec.rxlen) { |
| 398 |
ret = s->codec.rxbuf[s->codec.rxoff ++]; |
| 399 |
s->codec.rxlen --; |
| 400 |
s->codec.rxoff &= EAC_BUF_LEN - 1;
|
| 401 |
if (s->codec.rxavail)
|
| 402 |
omap_eac_in_refill(s); |
| 403 |
omap_eac_in_dmarequest_update(s); |
| 404 |
return ret;
|
| 405 |
} |
| 406 |
return 0x0000; |
| 407 |
case 0x0bc: /* AGCFR */ |
| 408 |
return s->codec.config[0]; |
| 409 |
case 0x0c0: /* AGCTR */ |
| 410 |
return s->codec.config[1] | ((s->codec.config[1] & 2) << 14); |
| 411 |
case 0x0c4: /* AGCFR2 */ |
| 412 |
return s->codec.config[2]; |
| 413 |
case 0x0c8: /* AGCFR3 */ |
| 414 |
return s->codec.config[3]; |
| 415 |
case 0x0cc: /* MBPDMACTR */ |
| 416 |
case 0x0d0: /* MPDDMARR */ |
| 417 |
case 0x0d8: /* MPUDMARR */ |
| 418 |
case 0x0e4: /* BPDDMARR */ |
| 419 |
case 0x0ec: /* BPUDMARR */ |
| 420 |
return 0x0000; |
| 421 |
|
| 422 |
case 0x100: /* VERSION_NUMBER */ |
| 423 |
return 0x0010; |
| 424 |
|
| 425 |
case 0x104: /* SYSCONFIG */ |
| 426 |
return s->sysconfig;
|
| 427 |
|
| 428 |
case 0x108: /* SYSSTATUS */ |
| 429 |
return 1 | 0xe; /* RESETDONE | stuff */ |
| 430 |
} |
| 431 |
|
| 432 |
OMAP_BAD_REG(addr); |
| 433 |
return 0; |
| 434 |
} |
| 435 |
|
| 436 |
static void omap_eac_write(void *opaque, target_phys_addr_t addr, |
| 437 |
uint32_t value) |
| 438 |
{
|
| 439 |
struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
| 440 |
|
| 441 |
switch (addr) {
|
| 442 |
case 0x098: /* APD1LCR */ |
| 443 |
case 0x09c: /* APD1RCR */ |
| 444 |
case 0x0a0: /* APD2LCR */ |
| 445 |
case 0x0a4: /* APD2RCR */ |
| 446 |
case 0x0a8: /* APD3LCR */ |
| 447 |
case 0x0ac: /* APD3RCR */ |
| 448 |
case 0x0b0: /* APD4R */ |
| 449 |
case 0x0b8: /* ADRDR */ |
| 450 |
case 0x0d0: /* MPDDMARR */ |
| 451 |
case 0x0d8: /* MPUDMARR */ |
| 452 |
case 0x0e4: /* BPDDMARR */ |
| 453 |
case 0x0ec: /* BPUDMARR */ |
| 454 |
case 0x100: /* VERSION_NUMBER */ |
| 455 |
case 0x108: /* SYSSTATUS */ |
| 456 |
OMAP_RO_REG(addr); |
| 457 |
return;
|
| 458 |
|
| 459 |
case 0x000: /* CPCFR1 */ |
| 460 |
s->config[0] = value & 0xff; |
| 461 |
omap_eac_format_update(s); |
| 462 |
break;
|
| 463 |
case 0x004: /* CPCFR2 */ |
| 464 |
s->config[1] = value & 0xff; |
| 465 |
omap_eac_format_update(s); |
| 466 |
break;
|
| 467 |
case 0x008: /* CPCFR3 */ |
| 468 |
s->config[2] = value & 0xff; |
| 469 |
omap_eac_format_update(s); |
| 470 |
break;
|
| 471 |
case 0x00c: /* CPCFR4 */ |
| 472 |
s->config[3] = value & 0xff; |
| 473 |
omap_eac_format_update(s); |
| 474 |
break;
|
| 475 |
|
| 476 |
case 0x010: /* CPTCTL */ |
| 477 |
/* Assuming TXF and TXE bits are read-only... */
|
| 478 |
s->control = value & 0x5f;
|
| 479 |
omap_eac_interrupt_update(s); |
| 480 |
break;
|
| 481 |
|
| 482 |
case 0x014: /* CPTTADR */ |
| 483 |
s->address = value & 0xff;
|
| 484 |
break;
|
| 485 |
case 0x018: /* CPTDATL */ |
| 486 |
s->data &= 0xff00;
|
| 487 |
s->data |= value & 0xff;
|
| 488 |
break;
|
| 489 |
case 0x01c: /* CPTDATH */ |
| 490 |
s->data &= 0x00ff;
|
| 491 |
s->data |= value << 8;
|
| 492 |
break;
|
| 493 |
case 0x020: /* CPTVSLL */ |
| 494 |
s->vtol = value & 0xf8;
|
| 495 |
break;
|
| 496 |
case 0x024: /* CPTVSLH */ |
| 497 |
s->vtsl = value & 0x9f;
|
| 498 |
break;
|
| 499 |
case 0x040: /* MPCTR */ |
| 500 |
s->modem.control = value & 0x8f;
|
| 501 |
break;
|
| 502 |
case 0x044: /* MPMCCFR */ |
| 503 |
s->modem.config = value & 0x7fff;
|
| 504 |
break;
|
| 505 |
case 0x060: /* BPCTR */ |
| 506 |
s->bt.control = value & 0x8f;
|
| 507 |
break;
|
| 508 |
case 0x064: /* BPMCCFR */ |
| 509 |
s->bt.config = value & 0x7fff;
|
| 510 |
break;
|
| 511 |
case 0x080: /* AMSCFR */ |
| 512 |
s->mixer = value & 0x0fff;
|
| 513 |
break;
|
| 514 |
case 0x084: /* AMVCTR */ |
| 515 |
s->gain[0] = value & 0xffff; |
| 516 |
break;
|
| 517 |
case 0x088: /* AM1VCTR */ |
| 518 |
s->gain[1] = value & 0xff7f; |
| 519 |
break;
|
| 520 |
case 0x08c: /* AM2VCTR */ |
| 521 |
s->gain[2] = value & 0xff7f; |
| 522 |
break;
|
| 523 |
case 0x090: /* AM3VCTR */ |
| 524 |
s->gain[3] = value & 0xff7f; |
| 525 |
break;
|
| 526 |
case 0x094: /* ASTCTR */ |
| 527 |
s->att = value & 0xff;
|
| 528 |
break;
|
| 529 |
|
| 530 |
case 0x0b4: /* ADWR */ |
| 531 |
s->codec.txbuf[s->codec.txlen ++] = value; |
| 532 |
if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
|
| 533 |
s->codec.txlen == s->codec.txavail)) {
|
| 534 |
if (s->codec.txavail)
|
| 535 |
omap_eac_out_empty(s); |
| 536 |
/* Discard what couldn't be written */
|
| 537 |
s->codec.txlen = 0;
|
| 538 |
} |
| 539 |
break;
|
| 540 |
|
| 541 |
case 0x0bc: /* AGCFR */ |
| 542 |
s->codec.config[0] = value & 0x07ff; |
| 543 |
omap_eac_format_update(s); |
| 544 |
break;
|
| 545 |
case 0x0c0: /* AGCTR */ |
| 546 |
s->codec.config[1] = value & 0x780f; |
| 547 |
omap_eac_format_update(s); |
| 548 |
break;
|
| 549 |
case 0x0c4: /* AGCFR2 */ |
| 550 |
s->codec.config[2] = value & 0x003f; |
| 551 |
omap_eac_format_update(s); |
| 552 |
break;
|
| 553 |
case 0x0c8: /* AGCFR3 */ |
| 554 |
s->codec.config[3] = value & 0xffff; |
| 555 |
omap_eac_format_update(s); |
| 556 |
break;
|
| 557 |
case 0x0cc: /* MBPDMACTR */ |
| 558 |
case 0x0d4: /* MPDDMAWR */ |
| 559 |
case 0x0e0: /* MPUDMAWR */ |
| 560 |
case 0x0e8: /* BPDDMAWR */ |
| 561 |
case 0x0f0: /* BPUDMAWR */ |
| 562 |
break;
|
| 563 |
|
| 564 |
case 0x104: /* SYSCONFIG */ |
| 565 |
if (value & (1 << 1)) /* SOFTRESET */ |
| 566 |
omap_eac_reset(s); |
| 567 |
s->sysconfig = value & 0x31d;
|
| 568 |
break;
|
| 569 |
|
| 570 |
default:
|
| 571 |
OMAP_BAD_REG(addr); |
| 572 |
return;
|
| 573 |
} |
| 574 |
} |
| 575 |
|
| 576 |
static CPUReadMemoryFunc * const omap_eac_readfn[] = { |
| 577 |
omap_badwidth_read16, |
| 578 |
omap_eac_read, |
| 579 |
omap_badwidth_read16, |
| 580 |
}; |
| 581 |
|
| 582 |
static CPUWriteMemoryFunc * const omap_eac_writefn[] = { |
| 583 |
omap_badwidth_write16, |
| 584 |
omap_eac_write, |
| 585 |
omap_badwidth_write16, |
| 586 |
}; |
| 587 |
|
| 588 |
struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, |
| 589 |
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
| 590 |
{
|
| 591 |
int iomemtype;
|
| 592 |
struct omap_eac_s *s = (struct omap_eac_s *) |
| 593 |
qemu_mallocz(sizeof(struct omap_eac_s)); |
| 594 |
|
| 595 |
s->irq = irq; |
| 596 |
s->codec.rxdrq = *drq ++; |
| 597 |
s->codec.txdrq = *drq; |
| 598 |
omap_eac_reset(s); |
| 599 |
|
| 600 |
AUD_register_card("OMAP EAC", &s->codec.card);
|
| 601 |
|
| 602 |
iomemtype = cpu_register_io_memory(omap_eac_readfn, |
| 603 |
omap_eac_writefn, s); |
| 604 |
omap_l4_attach(ta, 0, iomemtype);
|
| 605 |
|
| 606 |
return s;
|
| 607 |
} |
| 608 |
|
| 609 |
/* STI/XTI (emulation interface) console - reverse engineered only */
|
| 610 |
struct omap_sti_s {
|
| 611 |
qemu_irq irq; |
| 612 |
CharDriverState *chr; |
| 613 |
|
| 614 |
uint32_t sysconfig; |
| 615 |
uint32_t systest; |
| 616 |
uint32_t irqst; |
| 617 |
uint32_t irqen; |
| 618 |
uint32_t clkcontrol; |
| 619 |
uint32_t serial_config; |
| 620 |
}; |
| 621 |
|
| 622 |
#define STI_TRACE_CONSOLE_CHANNEL 239 |
| 623 |
#define STI_TRACE_CONTROL_CHANNEL 253 |
| 624 |
|
| 625 |
static inline void omap_sti_interrupt_update(struct omap_sti_s *s) |
| 626 |
{
|
| 627 |
qemu_set_irq(s->irq, s->irqst & s->irqen); |
| 628 |
} |
| 629 |
|
| 630 |
static void omap_sti_reset(struct omap_sti_s *s) |
| 631 |
{
|
| 632 |
s->sysconfig = 0;
|
| 633 |
s->irqst = 0;
|
| 634 |
s->irqen = 0;
|
| 635 |
s->clkcontrol = 0;
|
| 636 |
s->serial_config = 0;
|
| 637 |
|
| 638 |
omap_sti_interrupt_update(s); |
| 639 |
} |
| 640 |
|
| 641 |
static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) |
| 642 |
{
|
| 643 |
struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
| 644 |
|
| 645 |
switch (addr) {
|
| 646 |
case 0x00: /* STI_REVISION */ |
| 647 |
return 0x10; |
| 648 |
|
| 649 |
case 0x10: /* STI_SYSCONFIG */ |
| 650 |
return s->sysconfig;
|
| 651 |
|
| 652 |
case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
| 653 |
return 0x00; |
| 654 |
|
| 655 |
case 0x18: /* STI_IRQSTATUS */ |
| 656 |
return s->irqst;
|
| 657 |
|
| 658 |
case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
| 659 |
return s->irqen;
|
| 660 |
|
| 661 |
case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
| 662 |
case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
| 663 |
/* TODO */
|
| 664 |
return 0; |
| 665 |
|
| 666 |
case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
| 667 |
return s->clkcontrol;
|
| 668 |
|
| 669 |
case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
| 670 |
return s->serial_config;
|
| 671 |
} |
| 672 |
|
| 673 |
OMAP_BAD_REG(addr); |
| 674 |
return 0; |
| 675 |
} |
| 676 |
|
| 677 |
static void omap_sti_write(void *opaque, target_phys_addr_t addr, |
| 678 |
uint32_t value) |
| 679 |
{
|
| 680 |
struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
| 681 |
|
| 682 |
switch (addr) {
|
| 683 |
case 0x00: /* STI_REVISION */ |
| 684 |
case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
| 685 |
OMAP_RO_REG(addr); |
| 686 |
return;
|
| 687 |
|
| 688 |
case 0x10: /* STI_SYSCONFIG */ |
| 689 |
if (value & (1 << 1)) /* SOFTRESET */ |
| 690 |
omap_sti_reset(s); |
| 691 |
s->sysconfig = value & 0xfe;
|
| 692 |
break;
|
| 693 |
|
| 694 |
case 0x18: /* STI_IRQSTATUS */ |
| 695 |
s->irqst &= ~value; |
| 696 |
omap_sti_interrupt_update(s); |
| 697 |
break;
|
| 698 |
|
| 699 |
case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
| 700 |
s->irqen = value & 0xffff;
|
| 701 |
omap_sti_interrupt_update(s); |
| 702 |
break;
|
| 703 |
|
| 704 |
case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
| 705 |
s->clkcontrol = value & 0xff;
|
| 706 |
break;
|
| 707 |
|
| 708 |
case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
| 709 |
s->serial_config = value & 0xff;
|
| 710 |
break;
|
| 711 |
|
| 712 |
case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
| 713 |
case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
| 714 |
/* TODO */
|
| 715 |
return;
|
| 716 |
|
| 717 |
default:
|
| 718 |
OMAP_BAD_REG(addr); |
| 719 |
return;
|
| 720 |
} |
| 721 |
} |
| 722 |
|
| 723 |
static CPUReadMemoryFunc * const omap_sti_readfn[] = { |
| 724 |
omap_badwidth_read32, |
| 725 |
omap_badwidth_read32, |
| 726 |
omap_sti_read, |
| 727 |
}; |
| 728 |
|
| 729 |
static CPUWriteMemoryFunc * const omap_sti_writefn[] = { |
| 730 |
omap_badwidth_write32, |
| 731 |
omap_badwidth_write32, |
| 732 |
omap_sti_write, |
| 733 |
}; |
| 734 |
|
| 735 |
static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr) |
| 736 |
{
|
| 737 |
OMAP_BAD_REG(addr); |
| 738 |
return 0; |
| 739 |
} |
| 740 |
|
| 741 |
static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, |
| 742 |
uint32_t value) |
| 743 |
{
|
| 744 |
struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
| 745 |
int ch = addr >> 6; |
| 746 |
uint8_t byte = value; |
| 747 |
|
| 748 |
if (ch == STI_TRACE_CONTROL_CHANNEL) {
|
| 749 |
/* Flush channel <i>value</i>. */
|
| 750 |
qemu_chr_write(s->chr, (const uint8_t *) "\r", 1); |
| 751 |
} else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { |
| 752 |
if (value == 0xc0 || value == 0xc3) { |
| 753 |
/* Open channel <i>ch</i>. */
|
| 754 |
} else if (value == 0x00) |
| 755 |
qemu_chr_write(s->chr, (const uint8_t *) "\n", 1); |
| 756 |
else
|
| 757 |
qemu_chr_write(s->chr, &byte, 1);
|
| 758 |
} |
| 759 |
} |
| 760 |
|
| 761 |
static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = { |
| 762 |
omap_sti_fifo_read, |
| 763 |
omap_badwidth_read8, |
| 764 |
omap_badwidth_read8, |
| 765 |
}; |
| 766 |
|
| 767 |
static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = { |
| 768 |
omap_sti_fifo_write, |
| 769 |
omap_badwidth_write8, |
| 770 |
omap_badwidth_write8, |
| 771 |
}; |
| 772 |
|
| 773 |
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, |
| 774 |
target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk, |
| 775 |
CharDriverState *chr) |
| 776 |
{
|
| 777 |
int iomemtype;
|
| 778 |
struct omap_sti_s *s = (struct omap_sti_s *) |
| 779 |
qemu_mallocz(sizeof(struct omap_sti_s)); |
| 780 |
|
| 781 |
s->irq = irq; |
| 782 |
omap_sti_reset(s); |
| 783 |
|
| 784 |
s->chr = chr ?: qemu_chr_open("null", "null", NULL); |
| 785 |
|
| 786 |
iomemtype = l4_register_io_memory(omap_sti_readfn, |
| 787 |
omap_sti_writefn, s); |
| 788 |
omap_l4_attach(ta, 0, iomemtype);
|
| 789 |
|
| 790 |
iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn, |
| 791 |
omap_sti_fifo_writefn, s); |
| 792 |
cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
|
| 793 |
|
| 794 |
return s;
|
| 795 |
} |
| 796 |
|
| 797 |
/* L4 Interconnect */
|
| 798 |
struct omap_target_agent_s {
|
| 799 |
struct omap_l4_s *bus;
|
| 800 |
int regions;
|
| 801 |
struct omap_l4_region_s *start;
|
| 802 |
target_phys_addr_t base; |
| 803 |
uint32_t component; |
| 804 |
uint32_t control; |
| 805 |
uint32_t status; |
| 806 |
}; |
| 807 |
|
| 808 |
struct omap_l4_s {
|
| 809 |
target_phys_addr_t base; |
| 810 |
int ta_num;
|
| 811 |
struct omap_target_agent_s ta[0]; |
| 812 |
}; |
| 813 |
|
| 814 |
#ifdef L4_MUX_HACK
|
| 815 |
static int omap_l4_io_entries; |
| 816 |
static int omap_cpu_io_entry; |
| 817 |
static struct omap_l4_entry { |
| 818 |
CPUReadMemoryFunc * const *mem_read;
|
| 819 |
CPUWriteMemoryFunc * const *mem_write;
|
| 820 |
void *opaque;
|
| 821 |
} *omap_l4_io_entry; |
| 822 |
static CPUReadMemoryFunc * const *omap_l4_io_readb_fn; |
| 823 |
static CPUReadMemoryFunc * const *omap_l4_io_readh_fn; |
| 824 |
static CPUReadMemoryFunc * const *omap_l4_io_readw_fn; |
| 825 |
static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn; |
| 826 |
static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn; |
| 827 |
static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn; |
| 828 |
static void **omap_l4_io_opaque; |
| 829 |
|
| 830 |
int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
| 831 |
CPUWriteMemoryFunc * const *mem_write, void *opaque) |
| 832 |
{
|
| 833 |
omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read; |
| 834 |
omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write; |
| 835 |
omap_l4_io_entry[omap_l4_io_entries].opaque = opaque; |
| 836 |
|
| 837 |
return omap_l4_io_entries ++;
|
| 838 |
} |
| 839 |
|
| 840 |
static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr) |
| 841 |
{
|
| 842 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 843 |
|
| 844 |
return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
|
| 845 |
} |
| 846 |
|
| 847 |
static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr) |
| 848 |
{
|
| 849 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 850 |
|
| 851 |
return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
|
| 852 |
} |
| 853 |
|
| 854 |
static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr) |
| 855 |
{
|
| 856 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 857 |
|
| 858 |
return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
|
| 859 |
} |
| 860 |
|
| 861 |
static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, |
| 862 |
uint32_t value) |
| 863 |
{
|
| 864 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 865 |
|
| 866 |
return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
|
| 867 |
} |
| 868 |
|
| 869 |
static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, |
| 870 |
uint32_t value) |
| 871 |
{
|
| 872 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 873 |
|
| 874 |
return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
|
| 875 |
} |
| 876 |
|
| 877 |
static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr, |
| 878 |
uint32_t value) |
| 879 |
{
|
| 880 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 881 |
|
| 882 |
return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
|
| 883 |
} |
| 884 |
|
| 885 |
static CPUReadMemoryFunc * const omap_l4_io_readfn[] = { |
| 886 |
omap_l4_io_readb, |
| 887 |
omap_l4_io_readh, |
| 888 |
omap_l4_io_readw, |
| 889 |
}; |
| 890 |
|
| 891 |
static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = { |
| 892 |
omap_l4_io_writeb, |
| 893 |
omap_l4_io_writeh, |
| 894 |
omap_l4_io_writew, |
| 895 |
}; |
| 896 |
#endif
|
| 897 |
|
| 898 |
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) |
| 899 |
{
|
| 900 |
struct omap_l4_s *bus = qemu_mallocz(
|
| 901 |
sizeof(*bus) + ta_num * sizeof(*bus->ta)); |
| 902 |
|
| 903 |
bus->ta_num = ta_num; |
| 904 |
bus->base = base; |
| 905 |
|
| 906 |
#ifdef L4_MUX_HACK
|
| 907 |
omap_l4_io_entries = 1;
|
| 908 |
omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry)); |
| 909 |
|
| 910 |
omap_cpu_io_entry = |
| 911 |
cpu_register_io_memory(omap_l4_io_readfn, |
| 912 |
omap_l4_io_writefn, bus); |
| 913 |
# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE) |
| 914 |
omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 915 |
omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 916 |
omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 917 |
omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 918 |
omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 919 |
omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 920 |
omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 921 |
#endif
|
| 922 |
|
| 923 |
return bus;
|
| 924 |
} |
| 925 |
|
| 926 |
static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr) |
| 927 |
{
|
| 928 |
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
| 929 |
|
| 930 |
switch (addr) {
|
| 931 |
case 0x00: /* COMPONENT */ |
| 932 |
return s->component;
|
| 933 |
|
| 934 |
case 0x20: /* AGENT_CONTROL */ |
| 935 |
return s->control;
|
| 936 |
|
| 937 |
case 0x28: /* AGENT_STATUS */ |
| 938 |
return s->status;
|
| 939 |
} |
| 940 |
|
| 941 |
OMAP_BAD_REG(addr); |
| 942 |
return 0; |
| 943 |
} |
| 944 |
|
| 945 |
static void omap_l4ta_write(void *opaque, target_phys_addr_t addr, |
| 946 |
uint32_t value) |
| 947 |
{
|
| 948 |
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
| 949 |
|
| 950 |
switch (addr) {
|
| 951 |
case 0x00: /* COMPONENT */ |
| 952 |
case 0x28: /* AGENT_STATUS */ |
| 953 |
OMAP_RO_REG(addr); |
| 954 |
break;
|
| 955 |
|
| 956 |
case 0x20: /* AGENT_CONTROL */ |
| 957 |
s->control = value & 0x01000700;
|
| 958 |
if (value & 1) /* OCP_RESET */ |
| 959 |
s->status &= ~1; /* REQ_TIMEOUT */ |
| 960 |
break;
|
| 961 |
|
| 962 |
default:
|
| 963 |
OMAP_BAD_REG(addr); |
| 964 |
} |
| 965 |
} |
| 966 |
|
| 967 |
static CPUReadMemoryFunc * const omap_l4ta_readfn[] = { |
| 968 |
omap_badwidth_read16, |
| 969 |
omap_l4ta_read, |
| 970 |
omap_badwidth_read16, |
| 971 |
}; |
| 972 |
|
| 973 |
static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = { |
| 974 |
omap_badwidth_write32, |
| 975 |
omap_badwidth_write32, |
| 976 |
omap_l4ta_write, |
| 977 |
}; |
| 978 |
|
| 979 |
#define L4TA(n) (n)
|
| 980 |
#define L4TAO(n) ((n) + 39) |
| 981 |
|
| 982 |
static struct omap_l4_region_s { |
| 983 |
target_phys_addr_t offset; |
| 984 |
size_t size; |
| 985 |
int access;
|
| 986 |
} omap_l4_region[125] = {
|
| 987 |
[ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ |
| 988 |
[ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ |
| 989 |
[ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ |
| 990 |
[ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ |
| 991 |
[ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ |
| 992 |
[ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ |
| 993 |
[ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ |
| 994 |
[ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ |
| 995 |
[ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ |
| 996 |
[ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ |
| 997 |
[ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ |
| 998 |
[ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ |
| 999 |
[ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ |
| 1000 |
[ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ |
| 1001 |
[ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ |
| 1002 |
[ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ |
| 1003 |
[ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ |
| 1004 |
[ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ |
| 1005 |
[ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ |
| 1006 |
[ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ |
| 1007 |
[ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ |
| 1008 |
[ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ |
| 1009 |
[ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ |
| 1010 |
[ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ |
| 1011 |
[ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ |
| 1012 |
[ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ |
| 1013 |
[ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ |
| 1014 |
[ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ |
| 1015 |
[ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ |
| 1016 |
[ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ |
| 1017 |
[ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ |
| 1018 |
[ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ |
| 1019 |
[ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ |
| 1020 |
[ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ |
| 1021 |
[ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ |
| 1022 |
[ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ |
| 1023 |
[ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ |
| 1024 |
[ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ |
| 1025 |
[ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ |
| 1026 |
[ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ |
| 1027 |
[ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ |
| 1028 |
[ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ |
| 1029 |
[ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ |
| 1030 |
[ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ |
| 1031 |
[ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ |
| 1032 |
[ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ |
| 1033 |
[ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ |
| 1034 |
[ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ |
| 1035 |
[ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ |
| 1036 |
[ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ |
| 1037 |
[ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ |
| 1038 |
[ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ |
| 1039 |
[ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ |
| 1040 |
[ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ |
| 1041 |
[ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ |
| 1042 |
[ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ |
| 1043 |
[ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ |
| 1044 |
[ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ |
| 1045 |
[ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ |
| 1046 |
[ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ |
| 1047 |
[ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ |
| 1048 |
[ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ |
| 1049 |
[ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ |
| 1050 |
[ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ |
| 1051 |
[ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ |
| 1052 |
[ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ |
| 1053 |
[ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ |
| 1054 |
[ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ |
| 1055 |
[ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ |
| 1056 |
[ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ |
| 1057 |
[ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ |
| 1058 |
[ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ |
| 1059 |
[ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ |
| 1060 |
[ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ |
| 1061 |
[ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ |
| 1062 |
[ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ |
| 1063 |
[ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ |
| 1064 |
[ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ |
| 1065 |
[ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ |
| 1066 |
[ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ |
| 1067 |
[ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ |
| 1068 |
[ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ |
| 1069 |
[ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ |
| 1070 |
[ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ |
| 1071 |
[ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ |
| 1072 |
[ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ |
| 1073 |
[ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ |
| 1074 |
[ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ |
| 1075 |
[ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ |
| 1076 |
[ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ |
| 1077 |
[ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ |
| 1078 |
[ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ |
| 1079 |
[ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ |
| 1080 |
[ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ |
| 1081 |
[ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ |
| 1082 |
[ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ |
| 1083 |
[ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ |
| 1084 |
[ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ |
| 1085 |
[ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ |
| 1086 |
[ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ |
| 1087 |
[100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ |
| 1088 |
[101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ |
| 1089 |
[102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ |
| 1090 |
[103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ |
| 1091 |
[104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ |
| 1092 |
[105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ |
| 1093 |
[106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ |
| 1094 |
[107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ |
| 1095 |
[108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ |
| 1096 |
[109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ |
| 1097 |
[110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ |
| 1098 |
[111] = { 0xa0000, 0x1000, 32 }, /* RNG */ |
| 1099 |
[112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ |
| 1100 |
[113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ |
| 1101 |
[114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ |
| 1102 |
[115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ |
| 1103 |
[116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ |
| 1104 |
[117] = { 0xa6000, 0x1000, 32 }, /* AES */ |
| 1105 |
[118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ |
| 1106 |
[119] = { 0xa8000, 0x2000, 32 }, /* PKA */ |
| 1107 |
[120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ |
| 1108 |
[121] = { 0xb0000, 0x1000, 32 }, /* MG */ |
| 1109 |
[122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, |
| 1110 |
[123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ |
| 1111 |
[124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ |
| 1112 |
}; |
| 1113 |
|
| 1114 |
static struct omap_l4_agent_info_s { |
| 1115 |
int ta;
|
| 1116 |
int region;
|
| 1117 |
int regions;
|
| 1118 |
int ta_region;
|
| 1119 |
} omap_l4_agent_info[54] = {
|
| 1120 |
{ 0, 0, 3, 2 }, /* L4IA initiatior agent */
|
| 1121 |
{ L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
|
| 1122 |
{ L4TAO(2), 5, 2, 1 }, /* 32K timer */
|
| 1123 |
{ L4TAO(3), 7, 3, 2 }, /* PRCM */
|
| 1124 |
{ L4TA(1), 10, 2, 1 }, /* BCM */
|
| 1125 |
{ L4TA(2), 12, 2, 1 }, /* Test JTAG */
|
| 1126 |
{ L4TA(3), 14, 6, 3 }, /* Quad GPIO */
|
| 1127 |
{ L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
|
| 1128 |
{ L4TA(7), 24, 2, 1 }, /* GP timer 1 */
|
| 1129 |
{ L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
|
| 1130 |
{ L4TA(10), 28, 5, 4 }, /* Display subsystem */
|
| 1131 |
{ L4TA(11), 33, 5, 4 }, /* Camera subsystem */
|
| 1132 |
{ L4TA(12), 38, 2, 1 }, /* sDMA */
|
| 1133 |
{ L4TA(13), 40, 5, 4 }, /* SSI */
|
| 1134 |
{ L4TAO(4), 45, 2, 1 }, /* USB */
|
| 1135 |
{ L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
|
| 1136 |
{ L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
|
| 1137 |
{ L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
|
| 1138 |
{ L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
|
| 1139 |
{ L4TA(18), 55, 2, 1 }, /* XTI */
|
| 1140 |
{ L4TA(19), 57, 2, 1 }, /* UART1 */
|
| 1141 |
{ L4TA(20), 59, 2, 1 }, /* UART2 */
|
| 1142 |
{ L4TA(21), 61, 2, 1 }, /* UART3 */
|
| 1143 |
{ L4TAO(5), 63, 2, 1 }, /* I2C1 */
|
| 1144 |
{ L4TAO(6), 65, 2, 1 }, /* I2C2 */
|
| 1145 |
{ L4TAO(7), 67, 2, 1 }, /* McBSP1 */
|
| 1146 |
{ L4TAO(8), 69, 2, 1 }, /* McBSP2 */
|
| 1147 |
{ L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
|
| 1148 |
{ L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
|
| 1149 |
{ L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
|
| 1150 |
{ L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
|
| 1151 |
{ L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
|
| 1152 |
{ L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
|
| 1153 |
{ L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
|
| 1154 |
{ L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
|
| 1155 |
{ L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
|
| 1156 |
{ L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
|
| 1157 |
{ L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
|
| 1158 |
{ L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
|
| 1159 |
{ L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
|
| 1160 |
{ L4TA(32), 97, 2, 1 }, /* EAC */
|
| 1161 |
{ L4TA(33), 99, 2, 1 }, /* FAC */
|
| 1162 |
{ L4TA(34), 101, 2, 1 }, /* IPC */
|
| 1163 |
{ L4TA(35), 103, 2, 1 }, /* SPI1 */
|
| 1164 |
{ L4TA(36), 105, 2, 1 }, /* SPI2 */
|
| 1165 |
{ L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
|
| 1166 |
{ L4TAO(10), 109, 2, 1 },
|
| 1167 |
{ L4TAO(11), 111, 2, 1 }, /* RNG */
|
| 1168 |
{ L4TAO(12), 113, 2, 1 }, /* DES3DES */
|
| 1169 |
{ L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
|
| 1170 |
{ L4TA(37), 117, 2, 1 }, /* AES */
|
| 1171 |
{ L4TA(38), 119, 2, 1 }, /* PKA */
|
| 1172 |
{ -1, 121, 2, 1 },
|
| 1173 |
{ L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
|
| 1174 |
}; |
| 1175 |
|
| 1176 |
#define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
|
| 1177 |
#define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
|
| 1178 |
|
| 1179 |
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs) |
| 1180 |
{
|
| 1181 |
int i, iomemtype;
|
| 1182 |
struct omap_target_agent_s *ta = NULL; |
| 1183 |
struct omap_l4_agent_info_s *info = NULL; |
| 1184 |
|
| 1185 |
for (i = 0; i < bus->ta_num; i ++) |
| 1186 |
if (omap_l4_agent_info[i].ta == cs) {
|
| 1187 |
ta = &bus->ta[i]; |
| 1188 |
info = &omap_l4_agent_info[i]; |
| 1189 |
break;
|
| 1190 |
} |
| 1191 |
if (!ta) {
|
| 1192 |
fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
|
| 1193 |
exit(-1);
|
| 1194 |
} |
| 1195 |
|
| 1196 |
ta->bus = bus; |
| 1197 |
ta->start = &omap_l4_region[info->region]; |
| 1198 |
ta->regions = info->regions; |
| 1199 |
|
| 1200 |
ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 1201 |
ta->status = 0x00000000;
|
| 1202 |
ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ |
| 1203 |
|
| 1204 |
iomemtype = l4_register_io_memory(omap_l4ta_readfn, |
| 1205 |
omap_l4ta_writefn, ta); |
| 1206 |
ta->base = omap_l4_attach(ta, info->ta_region, iomemtype); |
| 1207 |
|
| 1208 |
return ta;
|
| 1209 |
} |
| 1210 |
|
| 1211 |
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
| 1212 |
int iotype)
|
| 1213 |
{
|
| 1214 |
target_phys_addr_t base; |
| 1215 |
ssize_t size; |
| 1216 |
#ifdef L4_MUX_HACK
|
| 1217 |
int i;
|
| 1218 |
#endif
|
| 1219 |
|
| 1220 |
if (region < 0 || region >= ta->regions) { |
| 1221 |
fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
|
| 1222 |
exit(-1);
|
| 1223 |
} |
| 1224 |
|
| 1225 |
base = ta->bus->base + ta->start[region].offset; |
| 1226 |
size = ta->start[region].size; |
| 1227 |
if (iotype) {
|
| 1228 |
#ifndef L4_MUX_HACK
|
| 1229 |
cpu_register_physical_memory(base, size, iotype); |
| 1230 |
#else
|
| 1231 |
cpu_register_physical_memory(base, size, omap_cpu_io_entry); |
| 1232 |
i = (base - ta->bus->base) / TARGET_PAGE_SIZE; |
| 1233 |
for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) { |
| 1234 |
omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
|
| 1235 |
omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
|
| 1236 |
omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
|
| 1237 |
omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
|
| 1238 |
omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
|
| 1239 |
omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
|
| 1240 |
omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque; |
| 1241 |
} |
| 1242 |
#endif
|
| 1243 |
} |
| 1244 |
|
| 1245 |
return base;
|
| 1246 |
} |
| 1247 |
|
| 1248 |
/* TEST-Chip-level TAP */
|
| 1249 |
static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) |
| 1250 |
{
|
| 1251 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 1252 |
|
| 1253 |
switch (addr) {
|
| 1254 |
case 0x204: /* IDCODE_reg */ |
| 1255 |
switch (s->mpu_model) {
|
| 1256 |
case omap2420:
|
| 1257 |
case omap2422:
|
| 1258 |
case omap2423:
|
| 1259 |
return 0x5b5d902f; /* ES 2.2 */ |
| 1260 |
case omap2430:
|
| 1261 |
return 0x5b68a02f; /* ES 2.2 */ |
| 1262 |
case omap3430:
|
| 1263 |
return 0x1b7ae02f; /* ES 2 */ |
| 1264 |
default:
|
| 1265 |
hw_error("%s: Bad mpu model\n", __FUNCTION__);
|
| 1266 |
} |
| 1267 |
|
| 1268 |
case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ |
| 1269 |
case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ |
| 1270 |
switch (s->mpu_model) {
|
| 1271 |
case omap2420:
|
| 1272 |
return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ |
| 1273 |
case omap2422:
|
| 1274 |
return 0x000400f0; |
| 1275 |
case omap2423:
|
| 1276 |
return 0x000800f0; |
| 1277 |
case omap2430:
|
| 1278 |
return 0x000000f0; |
| 1279 |
case omap3430:
|
| 1280 |
return 0x000000f0; |
| 1281 |
default:
|
| 1282 |
hw_error("%s: Bad mpu model\n", __FUNCTION__);
|
| 1283 |
} |
| 1284 |
|
| 1285 |
case 0x20c: |
| 1286 |
switch (s->mpu_model) {
|
| 1287 |
case omap2420:
|
| 1288 |
case omap2422:
|
| 1289 |
case omap2423:
|
| 1290 |
return 0xcafeb5d9; /* ES 2.2 */ |
| 1291 |
case omap2430:
|
| 1292 |
return 0xcafeb68a; /* ES 2.2 */ |
| 1293 |
case omap3430:
|
| 1294 |
return 0xcafeb7ae; /* ES 2 */ |
| 1295 |
default:
|
| 1296 |
hw_error("%s: Bad mpu model\n", __FUNCTION__);
|
| 1297 |
} |
| 1298 |
|
| 1299 |
case 0x218: /* DIE_ID_reg */ |
| 1300 |
return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 1301 |
case 0x21c: /* DIE_ID_reg */ |
| 1302 |
return 0x54 << 24; |
| 1303 |
case 0x220: /* DIE_ID_reg */ |
| 1304 |
return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 1305 |
case 0x224: /* DIE_ID_reg */ |
| 1306 |
return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 1307 |
} |
| 1308 |
|
| 1309 |
OMAP_BAD_REG(addr); |
| 1310 |
return 0; |
| 1311 |
} |
| 1312 |
|
| 1313 |
static void omap_tap_write(void *opaque, target_phys_addr_t addr, |
| 1314 |
uint32_t value) |
| 1315 |
{
|
| 1316 |
OMAP_BAD_REG(addr); |
| 1317 |
} |
| 1318 |
|
| 1319 |
static CPUReadMemoryFunc * const omap_tap_readfn[] = { |
| 1320 |
omap_badwidth_read32, |
| 1321 |
omap_badwidth_read32, |
| 1322 |
omap_tap_read, |
| 1323 |
}; |
| 1324 |
|
| 1325 |
static CPUWriteMemoryFunc * const omap_tap_writefn[] = { |
| 1326 |
omap_badwidth_write32, |
| 1327 |
omap_badwidth_write32, |
| 1328 |
omap_tap_write, |
| 1329 |
}; |
| 1330 |
|
| 1331 |
void omap_tap_init(struct omap_target_agent_s *ta, |
| 1332 |
struct omap_mpu_state_s *mpu)
|
| 1333 |
{
|
| 1334 |
omap_l4_attach(ta, 0, l4_register_io_memory(
|
| 1335 |
omap_tap_readfn, omap_tap_writefn, mpu)); |
| 1336 |
} |
| 1337 |
|
| 1338 |
/* Power, Reset, and Clock Management */
|
| 1339 |
struct omap_prcm_s {
|
| 1340 |
qemu_irq irq[3];
|
| 1341 |
struct omap_mpu_state_s *mpu;
|
| 1342 |
|
| 1343 |
uint32_t irqst[3];
|
| 1344 |
uint32_t irqen[3];
|
| 1345 |
|
| 1346 |
uint32_t sysconfig; |
| 1347 |
uint32_t voltctrl; |
| 1348 |
uint32_t scratch[20];
|
| 1349 |
|
| 1350 |
uint32_t clksrc[1];
|
| 1351 |
uint32_t clkout[1];
|
| 1352 |
uint32_t clkemul[1];
|
| 1353 |
uint32_t clkpol[1];
|
| 1354 |
uint32_t clksel[8];
|
| 1355 |
uint32_t clken[12];
|
| 1356 |
uint32_t clkctrl[4];
|
| 1357 |
uint32_t clkidle[7];
|
| 1358 |
uint32_t setuptime[2];
|
| 1359 |
|
| 1360 |
uint32_t wkup[3];
|
| 1361 |
uint32_t wken[3];
|
| 1362 |
uint32_t wkst[3];
|
| 1363 |
uint32_t rst[4];
|
| 1364 |
uint32_t rstctrl[1];
|
| 1365 |
uint32_t power[4];
|
| 1366 |
uint32_t rsttime_wkup; |
| 1367 |
|
| 1368 |
uint32_t ev; |
| 1369 |
uint32_t evtime[2];
|
| 1370 |
|
| 1371 |
int dpll_lock, apll_lock[2]; |
| 1372 |
}; |
| 1373 |
|
| 1374 |
static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) |
| 1375 |
{
|
| 1376 |
qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); |
| 1377 |
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
|
| 1378 |
} |
| 1379 |
|
| 1380 |
static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr) |
| 1381 |
{
|
| 1382 |
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
| 1383 |
uint32_t ret; |
| 1384 |
|
| 1385 |
switch (addr) {
|
| 1386 |
case 0x000: /* PRCM_REVISION */ |
| 1387 |
return 0x10; |
| 1388 |
|
| 1389 |
case 0x010: /* PRCM_SYSCONFIG */ |
| 1390 |
return s->sysconfig;
|
| 1391 |
|
| 1392 |
case 0x018: /* PRCM_IRQSTATUS_MPU */ |
| 1393 |
return s->irqst[0]; |
| 1394 |
|
| 1395 |
case 0x01c: /* PRCM_IRQENABLE_MPU */ |
| 1396 |
return s->irqen[0]; |
| 1397 |
|
| 1398 |
case 0x050: /* PRCM_VOLTCTRL */ |
| 1399 |
return s->voltctrl;
|
| 1400 |
case 0x054: /* PRCM_VOLTST */ |
| 1401 |
return s->voltctrl & 3; |
| 1402 |
|
| 1403 |
case 0x060: /* PRCM_CLKSRC_CTRL */ |
| 1404 |
return s->clksrc[0]; |
| 1405 |
case 0x070: /* PRCM_CLKOUT_CTRL */ |
| 1406 |
return s->clkout[0]; |
| 1407 |
case 0x078: /* PRCM_CLKEMUL_CTRL */ |
| 1408 |
return s->clkemul[0]; |
| 1409 |
case 0x080: /* PRCM_CLKCFG_CTRL */ |
| 1410 |
case 0x084: /* PRCM_CLKCFG_STATUS */ |
| 1411 |
return 0; |
| 1412 |
|
| 1413 |
case 0x090: /* PRCM_VOLTSETUP */ |
| 1414 |
return s->setuptime[0]; |
| 1415 |
|
| 1416 |
case 0x094: /* PRCM_CLKSSETUP */ |
| 1417 |
return s->setuptime[1]; |
| 1418 |
|
| 1419 |
case 0x098: /* PRCM_POLCTRL */ |
| 1420 |
return s->clkpol[0]; |
| 1421 |
|
| 1422 |
case 0x0b0: /* GENERAL_PURPOSE1 */ |
| 1423 |
case 0x0b4: /* GENERAL_PURPOSE2 */ |
| 1424 |
case 0x0b8: /* GENERAL_PURPOSE3 */ |
| 1425 |
case 0x0bc: /* GENERAL_PURPOSE4 */ |
| 1426 |
case 0x0c0: /* GENERAL_PURPOSE5 */ |
| 1427 |
case 0x0c4: /* GENERAL_PURPOSE6 */ |
| 1428 |
case 0x0c8: /* GENERAL_PURPOSE7 */ |
| 1429 |
case 0x0cc: /* GENERAL_PURPOSE8 */ |
| 1430 |
case 0x0d0: /* GENERAL_PURPOSE9 */ |
| 1431 |
case 0x0d4: /* GENERAL_PURPOSE10 */ |
| 1432 |
case 0x0d8: /* GENERAL_PURPOSE11 */ |
| 1433 |
case 0x0dc: /* GENERAL_PURPOSE12 */ |
| 1434 |
case 0x0e0: /* GENERAL_PURPOSE13 */ |
| 1435 |
case 0x0e4: /* GENERAL_PURPOSE14 */ |
| 1436 |
case 0x0e8: /* GENERAL_PURPOSE15 */ |
| 1437 |
case 0x0ec: /* GENERAL_PURPOSE16 */ |
| 1438 |
case 0x0f0: /* GENERAL_PURPOSE17 */ |
| 1439 |
case 0x0f4: /* GENERAL_PURPOSE18 */ |
| 1440 |
case 0x0f8: /* GENERAL_PURPOSE19 */ |
| 1441 |
case 0x0fc: /* GENERAL_PURPOSE20 */ |
| 1442 |
return s->scratch[(addr - 0xb0) >> 2]; |
| 1443 |
|
| 1444 |
case 0x140: /* CM_CLKSEL_MPU */ |
| 1445 |
return s->clksel[0]; |
| 1446 |
case 0x148: /* CM_CLKSTCTRL_MPU */ |
| 1447 |
return s->clkctrl[0]; |
| 1448 |
|
| 1449 |
case 0x158: /* RM_RSTST_MPU */ |
| 1450 |
return s->rst[0]; |
| 1451 |
case 0x1c8: /* PM_WKDEP_MPU */ |
| 1452 |
return s->wkup[0]; |
| 1453 |
case 0x1d4: /* PM_EVGENCTRL_MPU */ |
| 1454 |
return s->ev;
|
| 1455 |
case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
| 1456 |
return s->evtime[0]; |
| 1457 |
case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
| 1458 |
return s->evtime[1]; |
| 1459 |
case 0x1e0: /* PM_PWSTCTRL_MPU */ |
| 1460 |
return s->power[0]; |
| 1461 |
case 0x1e4: /* PM_PWSTST_MPU */ |
| 1462 |
return 0; |
| 1463 |
|
| 1464 |
case 0x200: /* CM_FCLKEN1_CORE */ |
| 1465 |
return s->clken[0]; |
| 1466 |
case 0x204: /* CM_FCLKEN2_CORE */ |
| 1467 |
return s->clken[1]; |
| 1468 |
case 0x210: /* CM_ICLKEN1_CORE */ |
| 1469 |
return s->clken[2]; |
| 1470 |
case 0x214: /* CM_ICLKEN2_CORE */ |
| 1471 |
return s->clken[3]; |
| 1472 |
case 0x21c: /* CM_ICLKEN4_CORE */ |
| 1473 |
return s->clken[4]; |
| 1474 |
|
| 1475 |
case 0x220: /* CM_IDLEST1_CORE */ |
| 1476 |
/* TODO: check the actual iclk status */
|
| 1477 |
return 0x7ffffff9; |
| 1478 |
case 0x224: /* CM_IDLEST2_CORE */ |
| 1479 |
/* TODO: check the actual iclk status */
|
| 1480 |
return 0x00000007; |
| 1481 |
case 0x22c: /* CM_IDLEST4_CORE */ |
| 1482 |
/* TODO: check the actual iclk status */
|
| 1483 |
return 0x0000001f; |
| 1484 |
|
| 1485 |
case 0x230: /* CM_AUTOIDLE1_CORE */ |
| 1486 |
return s->clkidle[0]; |
| 1487 |
case 0x234: /* CM_AUTOIDLE2_CORE */ |
| 1488 |
return s->clkidle[1]; |
| 1489 |
case 0x238: /* CM_AUTOIDLE3_CORE */ |
| 1490 |
return s->clkidle[2]; |
| 1491 |
case 0x23c: /* CM_AUTOIDLE4_CORE */ |
| 1492 |
return s->clkidle[3]; |
| 1493 |
|
| 1494 |
case 0x240: /* CM_CLKSEL1_CORE */ |
| 1495 |
return s->clksel[1]; |
| 1496 |
case 0x244: /* CM_CLKSEL2_CORE */ |
| 1497 |
return s->clksel[2]; |
| 1498 |
|
| 1499 |
case 0x248: /* CM_CLKSTCTRL_CORE */ |
| 1500 |
return s->clkctrl[1]; |
| 1501 |
|
| 1502 |
case 0x2a0: /* PM_WKEN1_CORE */ |
| 1503 |
return s->wken[0]; |
| 1504 |
case 0x2a4: /* PM_WKEN2_CORE */ |
| 1505 |
return s->wken[1]; |
| 1506 |
|
| 1507 |
case 0x2b0: /* PM_WKST1_CORE */ |
| 1508 |
return s->wkst[0]; |
| 1509 |
case 0x2b4: /* PM_WKST2_CORE */ |
| 1510 |
return s->wkst[1]; |
| 1511 |
case 0x2c8: /* PM_WKDEP_CORE */ |
| 1512 |
return 0x1e; |
| 1513 |
|
| 1514 |
case 0x2e0: /* PM_PWSTCTRL_CORE */ |
| 1515 |
return s->power[1]; |
| 1516 |
case 0x2e4: /* PM_PWSTST_CORE */ |
| 1517 |
return 0x000030 | (s->power[1] & 0xfc00); |
| 1518 |
|
| 1519 |
case 0x300: /* CM_FCLKEN_GFX */ |
| 1520 |
return s->clken[5]; |
| 1521 |
case 0x310: /* CM_ICLKEN_GFX */ |
| 1522 |
return s->clken[6]; |
| 1523 |
case 0x320: /* CM_IDLEST_GFX */ |
| 1524 |
/* TODO: check the actual iclk status */
|
| 1525 |
return 0x00000001; |
| 1526 |
case 0x340: /* CM_CLKSEL_GFX */ |
| 1527 |
return s->clksel[3]; |
| 1528 |
case 0x348: /* CM_CLKSTCTRL_GFX */ |
| 1529 |
return s->clkctrl[2]; |
| 1530 |
case 0x350: /* RM_RSTCTRL_GFX */ |
| 1531 |
return s->rstctrl[0]; |
| 1532 |
case 0x358: /* RM_RSTST_GFX */ |
| 1533 |
return s->rst[1]; |
| 1534 |
case 0x3c8: /* PM_WKDEP_GFX */ |
| 1535 |
return s->wkup[1]; |
| 1536 |
|
| 1537 |
case 0x3e0: /* PM_PWSTCTRL_GFX */ |
| 1538 |
return s->power[2]; |
| 1539 |
case 0x3e4: /* PM_PWSTST_GFX */ |
| 1540 |
return s->power[2] & 3; |
| 1541 |
|
| 1542 |
case 0x400: /* CM_FCLKEN_WKUP */ |
| 1543 |
return s->clken[7]; |
| 1544 |
case 0x410: /* CM_ICLKEN_WKUP */ |
| 1545 |
return s->clken[8]; |
| 1546 |
case 0x420: /* CM_IDLEST_WKUP */ |
| 1547 |
/* TODO: check the actual iclk status */
|
| 1548 |
return 0x0000003f; |
| 1549 |
case 0x430: /* CM_AUTOIDLE_WKUP */ |
| 1550 |
return s->clkidle[4]; |
| 1551 |
case 0x440: /* CM_CLKSEL_WKUP */ |
| 1552 |
return s->clksel[4]; |
| 1553 |
case 0x450: /* RM_RSTCTRL_WKUP */ |
| 1554 |
return 0; |
| 1555 |
case 0x454: /* RM_RSTTIME_WKUP */ |
| 1556 |
return s->rsttime_wkup;
|
| 1557 |
case 0x458: /* RM_RSTST_WKUP */ |
| 1558 |
return s->rst[2]; |
| 1559 |
case 0x4a0: /* PM_WKEN_WKUP */ |
| 1560 |
return s->wken[2]; |
| 1561 |
case 0x4b0: /* PM_WKST_WKUP */ |
| 1562 |
return s->wkst[2]; |
| 1563 |
|
| 1564 |
case 0x500: /* CM_CLKEN_PLL */ |
| 1565 |
return s->clken[9]; |
| 1566 |
case 0x520: /* CM_IDLEST_CKGEN */ |
| 1567 |
ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8); |
| 1568 |
if (!(s->clksel[6] & 3)) |
| 1569 |
/* Core uses 32-kHz clock */
|
| 1570 |
ret |= 3 << 0; |
| 1571 |
else if (!s->dpll_lock) |
| 1572 |
/* DPLL not locked, core uses ref_clk */
|
| 1573 |
ret |= 1 << 0; |
| 1574 |
else
|
| 1575 |
/* Core uses DPLL */
|
| 1576 |
ret |= 2 << 0; |
| 1577 |
return ret;
|
| 1578 |
case 0x530: /* CM_AUTOIDLE_PLL */ |
| 1579 |
return s->clkidle[5]; |
| 1580 |
case 0x540: /* CM_CLKSEL1_PLL */ |
| 1581 |
return s->clksel[5]; |
| 1582 |
case 0x544: /* CM_CLKSEL2_PLL */ |
| 1583 |
return s->clksel[6]; |
| 1584 |
|
| 1585 |
case 0x800: /* CM_FCLKEN_DSP */ |
| 1586 |
return s->clken[10]; |
| 1587 |
case 0x810: /* CM_ICLKEN_DSP */ |
| 1588 |
return s->clken[11]; |
| 1589 |
case 0x820: /* CM_IDLEST_DSP */ |
| 1590 |
/* TODO: check the actual iclk status */
|
| 1591 |
return 0x00000103; |
| 1592 |
case 0x830: /* CM_AUTOIDLE_DSP */ |
| 1593 |
return s->clkidle[6]; |
| 1594 |
case 0x840: /* CM_CLKSEL_DSP */ |
| 1595 |
return s->clksel[7]; |
| 1596 |
case 0x848: /* CM_CLKSTCTRL_DSP */ |
| 1597 |
return s->clkctrl[3]; |
| 1598 |
case 0x850: /* RM_RSTCTRL_DSP */ |
| 1599 |
return 0; |
| 1600 |
case 0x858: /* RM_RSTST_DSP */ |
| 1601 |
return s->rst[3]; |
| 1602 |
case 0x8c8: /* PM_WKDEP_DSP */ |
| 1603 |
return s->wkup[2]; |
| 1604 |
case 0x8e0: /* PM_PWSTCTRL_DSP */ |
| 1605 |
return s->power[3]; |
| 1606 |
case 0x8e4: /* PM_PWSTST_DSP */ |
| 1607 |
return 0x008030 | (s->power[3] & 0x3003); |
| 1608 |
|
| 1609 |
case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
| 1610 |
return s->irqst[1]; |
| 1611 |
case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
| 1612 |
return s->irqen[1]; |
| 1613 |
|
| 1614 |
case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
| 1615 |
return s->irqst[2]; |
| 1616 |
case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
| 1617 |
return s->irqen[2]; |
| 1618 |
} |
| 1619 |
|
| 1620 |
OMAP_BAD_REG(addr); |
| 1621 |
return 0; |
| 1622 |
} |
| 1623 |
|
| 1624 |
static void omap_prcm_apll_update(struct omap_prcm_s *s) |
| 1625 |
{
|
| 1626 |
int mode[2]; |
| 1627 |
|
| 1628 |
mode[0] = (s->clken[9] >> 6) & 3; |
| 1629 |
s->apll_lock[0] = (mode[0] == 3); |
| 1630 |
mode[1] = (s->clken[9] >> 2) & 3; |
| 1631 |
s->apll_lock[1] = (mode[1] == 3); |
| 1632 |
/* TODO: update clocks */
|
| 1633 |
|
| 1634 |
if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2) |
| 1635 |
fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
|
| 1636 |
__FUNCTION__); |
| 1637 |
} |
| 1638 |
|
| 1639 |
static void omap_prcm_dpll_update(struct omap_prcm_s *s) |
| 1640 |
{
|
| 1641 |
omap_clk dpll = omap_findclk(s->mpu, "dpll");
|
| 1642 |
omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
|
| 1643 |
omap_clk core = omap_findclk(s->mpu, "core_clk");
|
| 1644 |
int mode = (s->clken[9] >> 0) & 3; |
| 1645 |
int mult, div;
|
| 1646 |
|
| 1647 |
mult = (s->clksel[5] >> 12) & 0x3ff; |
| 1648 |
div = (s->clksel[5] >> 8) & 0xf; |
| 1649 |
if (mult == 0 || mult == 1) |
| 1650 |
mode = 1; /* Bypass */ |
| 1651 |
|
| 1652 |
s->dpll_lock = 0;
|
| 1653 |
switch (mode) {
|
| 1654 |
case 0: |
| 1655 |
fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
|
| 1656 |
break;
|
| 1657 |
case 1: /* Low-power bypass mode (Default) */ |
| 1658 |
case 2: /* Fast-relock bypass mode */ |
| 1659 |
omap_clk_setrate(dpll, 1, 1); |
| 1660 |
omap_clk_setrate(dpll_x2, 1, 1); |
| 1661 |
break;
|
| 1662 |
case 3: /* Lock mode */ |
| 1663 |
s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */ |
| 1664 |
|
| 1665 |
omap_clk_setrate(dpll, div + 1, mult);
|
| 1666 |
omap_clk_setrate(dpll_x2, div + 1, mult * 2); |
| 1667 |
break;
|
| 1668 |
} |
| 1669 |
|
| 1670 |
switch ((s->clksel[6] >> 0) & 3) { |
| 1671 |
case 0: |
| 1672 |
omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
|
| 1673 |
break;
|
| 1674 |
case 1: |
| 1675 |
omap_clk_reparent(core, dpll); |
| 1676 |
break;
|
| 1677 |
case 2: |
| 1678 |
/* Default */
|
| 1679 |
omap_clk_reparent(core, dpll_x2); |
| 1680 |
break;
|
| 1681 |
case 3: |
| 1682 |
fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
|
| 1683 |
break;
|
| 1684 |
} |
| 1685 |
} |
| 1686 |
|
| 1687 |
static void omap_prcm_write(void *opaque, target_phys_addr_t addr, |
| 1688 |
uint32_t value) |
| 1689 |
{
|
| 1690 |
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
| 1691 |
|
| 1692 |
switch (addr) {
|
| 1693 |
case 0x000: /* PRCM_REVISION */ |
| 1694 |
case 0x054: /* PRCM_VOLTST */ |
| 1695 |
case 0x084: /* PRCM_CLKCFG_STATUS */ |
| 1696 |
case 0x1e4: /* PM_PWSTST_MPU */ |
| 1697 |
case 0x220: /* CM_IDLEST1_CORE */ |
| 1698 |
case 0x224: /* CM_IDLEST2_CORE */ |
| 1699 |
case 0x22c: /* CM_IDLEST4_CORE */ |
| 1700 |
case 0x2c8: /* PM_WKDEP_CORE */ |
| 1701 |
case 0x2e4: /* PM_PWSTST_CORE */ |
| 1702 |
case 0x320: /* CM_IDLEST_GFX */ |
| 1703 |
case 0x3e4: /* PM_PWSTST_GFX */ |
| 1704 |
case 0x420: /* CM_IDLEST_WKUP */ |
| 1705 |
case 0x520: /* CM_IDLEST_CKGEN */ |
| 1706 |
case 0x820: /* CM_IDLEST_DSP */ |
| 1707 |
case 0x8e4: /* PM_PWSTST_DSP */ |
| 1708 |
OMAP_RO_REG(addr); |
| 1709 |
return;
|
| 1710 |
|
| 1711 |
case 0x010: /* PRCM_SYSCONFIG */ |
| 1712 |
s->sysconfig = value & 1;
|
| 1713 |
break;
|
| 1714 |
|
| 1715 |
case 0x018: /* PRCM_IRQSTATUS_MPU */ |
| 1716 |
s->irqst[0] &= ~value;
|
| 1717 |
omap_prcm_int_update(s, 0);
|
| 1718 |
break;
|
| 1719 |
case 0x01c: /* PRCM_IRQENABLE_MPU */ |
| 1720 |
s->irqen[0] = value & 0x3f; |
| 1721 |
omap_prcm_int_update(s, 0);
|
| 1722 |
break;
|
| 1723 |
|
| 1724 |
case 0x050: /* PRCM_VOLTCTRL */ |
| 1725 |
s->voltctrl = value & 0xf1c3;
|
| 1726 |
break;
|
| 1727 |
|
| 1728 |
case 0x060: /* PRCM_CLKSRC_CTRL */ |
| 1729 |
s->clksrc[0] = value & 0xdb; |
| 1730 |
/* TODO update clocks */
|
| 1731 |
break;
|
| 1732 |
|
| 1733 |
case 0x070: /* PRCM_CLKOUT_CTRL */ |
| 1734 |
s->clkout[0] = value & 0xbbbb; |
| 1735 |
/* TODO update clocks */
|
| 1736 |
break;
|
| 1737 |
|
| 1738 |
case 0x078: /* PRCM_CLKEMUL_CTRL */ |
| 1739 |
s->clkemul[0] = value & 1; |
| 1740 |
/* TODO update clocks */
|
| 1741 |
break;
|
| 1742 |
|
| 1743 |
case 0x080: /* PRCM_CLKCFG_CTRL */ |
| 1744 |
break;
|
| 1745 |
|
| 1746 |
case 0x090: /* PRCM_VOLTSETUP */ |
| 1747 |
s->setuptime[0] = value & 0xffff; |
| 1748 |
break;
|
| 1749 |
case 0x094: /* PRCM_CLKSSETUP */ |
| 1750 |
s->setuptime[1] = value & 0xffff; |
| 1751 |
break;
|
| 1752 |
|
| 1753 |
case 0x098: /* PRCM_POLCTRL */ |
| 1754 |
s->clkpol[0] = value & 0x701; |
| 1755 |
break;
|
| 1756 |
|
| 1757 |
case 0x0b0: /* GENERAL_PURPOSE1 */ |
| 1758 |
case 0x0b4: /* GENERAL_PURPOSE2 */ |
| 1759 |
case 0x0b8: /* GENERAL_PURPOSE3 */ |
| 1760 |
case 0x0bc: /* GENERAL_PURPOSE4 */ |
| 1761 |
case 0x0c0: /* GENERAL_PURPOSE5 */ |
| 1762 |
case 0x0c4: /* GENERAL_PURPOSE6 */ |
| 1763 |
case 0x0c8: /* GENERAL_PURPOSE7 */ |
| 1764 |
case 0x0cc: /* GENERAL_PURPOSE8 */ |
| 1765 |
case 0x0d0: /* GENERAL_PURPOSE9 */ |
| 1766 |
case 0x0d4: /* GENERAL_PURPOSE10 */ |
| 1767 |
case 0x0d8: /* GENERAL_PURPOSE11 */ |
| 1768 |
case 0x0dc: /* GENERAL_PURPOSE12 */ |
| 1769 |
case 0x0e0: /* GENERAL_PURPOSE13 */ |
| 1770 |
case 0x0e4: /* GENERAL_PURPOSE14 */ |
| 1771 |
case 0x0e8: /* GENERAL_PURPOSE15 */ |
| 1772 |
case 0x0ec: /* GENERAL_PURPOSE16 */ |
| 1773 |
case 0x0f0: /* GENERAL_PURPOSE17 */ |
| 1774 |
case 0x0f4: /* GENERAL_PURPOSE18 */ |
| 1775 |
case 0x0f8: /* GENERAL_PURPOSE19 */ |
| 1776 |
case 0x0fc: /* GENERAL_PURPOSE20 */ |
| 1777 |
s->scratch[(addr - 0xb0) >> 2] = value; |
| 1778 |
break;
|
| 1779 |
|
| 1780 |
case 0x140: /* CM_CLKSEL_MPU */ |
| 1781 |
s->clksel[0] = value & 0x1f; |
| 1782 |
/* TODO update clocks */
|
| 1783 |
break;
|
| 1784 |
case 0x148: /* CM_CLKSTCTRL_MPU */ |
| 1785 |
s->clkctrl[0] = value & 0x1f; |
| 1786 |
break;
|
| 1787 |
|
| 1788 |
case 0x158: /* RM_RSTST_MPU */ |
| 1789 |
s->rst[0] &= ~value;
|
| 1790 |
break;
|
| 1791 |
case 0x1c8: /* PM_WKDEP_MPU */ |
| 1792 |
s->wkup[0] = value & 0x15; |
| 1793 |
break;
|
| 1794 |
|
| 1795 |
case 0x1d4: /* PM_EVGENCTRL_MPU */ |
| 1796 |
s->ev = value & 0x1f;
|
| 1797 |
break;
|
| 1798 |
case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
| 1799 |
s->evtime[0] = value;
|
| 1800 |
break;
|
| 1801 |
case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
| 1802 |
s->evtime[1] = value;
|
| 1803 |
break;
|
| 1804 |
|
| 1805 |
case 0x1e0: /* PM_PWSTCTRL_MPU */ |
| 1806 |
s->power[0] = value & 0xc0f; |
| 1807 |
break;
|
| 1808 |
|
| 1809 |
case 0x200: /* CM_FCLKEN1_CORE */ |
| 1810 |
s->clken[0] = value & 0xbfffffff; |
| 1811 |
/* TODO update clocks */
|
| 1812 |
/* The EN_EAC bit only gets/puts func_96m_clk. */
|
| 1813 |
break;
|
| 1814 |
case 0x204: /* CM_FCLKEN2_CORE */ |
| 1815 |
s->clken[1] = value & 0x00000007; |
| 1816 |
/* TODO update clocks */
|
| 1817 |
break;
|
| 1818 |
case 0x210: /* CM_ICLKEN1_CORE */ |
| 1819 |
s->clken[2] = value & 0xfffffff9; |
| 1820 |
/* TODO update clocks */
|
| 1821 |
/* The EN_EAC bit only gets/puts core_l4_iclk. */
|
| 1822 |
break;
|
| 1823 |
case 0x214: /* CM_ICLKEN2_CORE */ |
| 1824 |
s->clken[3] = value & 0x00000007; |
| 1825 |
/* TODO update clocks */
|
| 1826 |
break;
|
| 1827 |
case 0x21c: /* CM_ICLKEN4_CORE */ |
| 1828 |
s->clken[4] = value & 0x0000001f; |
| 1829 |
/* TODO update clocks */
|
| 1830 |
break;
|
| 1831 |
|
| 1832 |
case 0x230: /* CM_AUTOIDLE1_CORE */ |
| 1833 |
s->clkidle[0] = value & 0xfffffff9; |
| 1834 |
/* TODO update clocks */
|
| 1835 |
break;
|
| 1836 |
case 0x234: /* CM_AUTOIDLE2_CORE */ |
| 1837 |
s->clkidle[1] = value & 0x00000007; |
| 1838 |
/* TODO update clocks */
|
| 1839 |
break;
|
| 1840 |
case 0x238: /* CM_AUTOIDLE3_CORE */ |
| 1841 |
s->clkidle[2] = value & 0x00000007; |
| 1842 |
/* TODO update clocks */
|
| 1843 |
break;
|
| 1844 |
case 0x23c: /* CM_AUTOIDLE4_CORE */ |
| 1845 |
s->clkidle[3] = value & 0x0000001f; |
| 1846 |
/* TODO update clocks */
|
| 1847 |
break;
|
| 1848 |
|
| 1849 |
case 0x240: /* CM_CLKSEL1_CORE */ |
| 1850 |
s->clksel[1] = value & 0x0fffbf7f; |
| 1851 |
/* TODO update clocks */
|
| 1852 |
break;
|
| 1853 |
|
| 1854 |
case 0x244: /* CM_CLKSEL2_CORE */ |
| 1855 |
s->clksel[2] = value & 0x00fffffc; |
| 1856 |
/* TODO update clocks */
|
| 1857 |
break;
|
| 1858 |
|
| 1859 |
case 0x248: /* CM_CLKSTCTRL_CORE */ |
| 1860 |
s->clkctrl[1] = value & 0x7; |
| 1861 |
break;
|
| 1862 |
|
| 1863 |
case 0x2a0: /* PM_WKEN1_CORE */ |
| 1864 |
s->wken[0] = value & 0x04667ff8; |
| 1865 |
break;
|
| 1866 |
case 0x2a4: /* PM_WKEN2_CORE */ |
| 1867 |
s->wken[1] = value & 0x00000005; |
| 1868 |
break;
|
| 1869 |
|
| 1870 |
case 0x2b0: /* PM_WKST1_CORE */ |
| 1871 |
s->wkst[0] &= ~value;
|
| 1872 |
break;
|
| 1873 |
case 0x2b4: /* PM_WKST2_CORE */ |
| 1874 |
s->wkst[1] &= ~value;
|
| 1875 |
break;
|
| 1876 |
|
| 1877 |
case 0x2e0: /* PM_PWSTCTRL_CORE */ |
| 1878 |
s->power[1] = (value & 0x00fc3f) | (1 << 2); |
| 1879 |
break;
|
| 1880 |
|
| 1881 |
case 0x300: /* CM_FCLKEN_GFX */ |
| 1882 |
s->clken[5] = value & 6; |
| 1883 |
/* TODO update clocks */
|
| 1884 |
break;
|
| 1885 |
case 0x310: /* CM_ICLKEN_GFX */ |
| 1886 |
s->clken[6] = value & 1; |
| 1887 |
/* TODO update clocks */
|
| 1888 |
break;
|
| 1889 |
case 0x340: /* CM_CLKSEL_GFX */ |
| 1890 |
s->clksel[3] = value & 7; |
| 1891 |
/* TODO update clocks */
|
| 1892 |
break;
|
| 1893 |
case 0x348: /* CM_CLKSTCTRL_GFX */ |
| 1894 |
s->clkctrl[2] = value & 1; |
| 1895 |
break;
|
| 1896 |
case 0x350: /* RM_RSTCTRL_GFX */ |
| 1897 |
s->rstctrl[0] = value & 1; |
| 1898 |
/* TODO: reset */
|
| 1899 |
break;
|
| 1900 |
case 0x358: /* RM_RSTST_GFX */ |
| 1901 |
s->rst[1] &= ~value;
|
| 1902 |
break;
|
| 1903 |
case 0x3c8: /* PM_WKDEP_GFX */ |
| 1904 |
s->wkup[1] = value & 0x13; |
| 1905 |
break;
|
| 1906 |
case 0x3e0: /* PM_PWSTCTRL_GFX */ |
| 1907 |
s->power[2] = (value & 0x00c0f) | (3 << 2); |
| 1908 |
break;
|
| 1909 |
|
| 1910 |
case 0x400: /* CM_FCLKEN_WKUP */ |
| 1911 |
s->clken[7] = value & 0xd; |
| 1912 |
/* TODO update clocks */
|
| 1913 |
break;
|
| 1914 |
case 0x410: /* CM_ICLKEN_WKUP */ |
| 1915 |
s->clken[8] = value & 0x3f; |
| 1916 |
/* TODO update clocks */
|
| 1917 |
break;
|
| 1918 |
case 0x430: /* CM_AUTOIDLE_WKUP */ |
| 1919 |
s->clkidle[4] = value & 0x0000003f; |
| 1920 |
/* TODO update clocks */
|
| 1921 |
break;
|
| 1922 |
case 0x440: /* CM_CLKSEL_WKUP */ |
| 1923 |
s->clksel[4] = value & 3; |
| 1924 |
/* TODO update clocks */
|
| 1925 |
break;
|
| 1926 |
case 0x450: /* RM_RSTCTRL_WKUP */ |
| 1927 |
/* TODO: reset */
|
| 1928 |
if (value & 2) |
| 1929 |
qemu_system_reset_request(); |
| 1930 |
break;
|
| 1931 |
case 0x454: /* RM_RSTTIME_WKUP */ |
| 1932 |
s->rsttime_wkup = value & 0x1fff;
|
| 1933 |
break;
|
| 1934 |
case 0x458: /* RM_RSTST_WKUP */ |
| 1935 |
s->rst[2] &= ~value;
|
| 1936 |
break;
|
| 1937 |
case 0x4a0: /* PM_WKEN_WKUP */ |
| 1938 |
s->wken[2] = value & 0x00000005; |
| 1939 |
break;
|
| 1940 |
case 0x4b0: /* PM_WKST_WKUP */ |
| 1941 |
s->wkst[2] &= ~value;
|
| 1942 |
break;
|
| 1943 |
|
| 1944 |
case 0x500: /* CM_CLKEN_PLL */ |
| 1945 |
if (value & 0xffffff30) |
| 1946 |
fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
|
| 1947 |
"future compatiblity\n", __FUNCTION__);
|
| 1948 |
if ((s->clken[9] ^ value) & 0xcc) { |
| 1949 |
s->clken[9] &= ~0xcc; |
| 1950 |
s->clken[9] |= value & 0xcc; |
| 1951 |
omap_prcm_apll_update(s); |
| 1952 |
} |
| 1953 |
if ((s->clken[9] ^ value) & 3) { |
| 1954 |
s->clken[9] &= ~3; |
| 1955 |
s->clken[9] |= value & 3; |
| 1956 |
omap_prcm_dpll_update(s); |
| 1957 |
} |
| 1958 |
break;
|
| 1959 |
case 0x530: /* CM_AUTOIDLE_PLL */ |
| 1960 |
s->clkidle[5] = value & 0x000000cf; |
| 1961 |
/* TODO update clocks */
|
| 1962 |
break;
|
| 1963 |
case 0x540: /* CM_CLKSEL1_PLL */ |
| 1964 |
if (value & 0xfc4000d7) |
| 1965 |
fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
|
| 1966 |
"future compatiblity\n", __FUNCTION__);
|
| 1967 |
if ((s->clksel[5] ^ value) & 0x003fff00) { |
| 1968 |
s->clksel[5] = value & 0x03bfff28; |
| 1969 |
omap_prcm_dpll_update(s); |
| 1970 |
} |
| 1971 |
/* TODO update the other clocks */
|
| 1972 |
|
| 1973 |
s->clksel[5] = value & 0x03bfff28; |
| 1974 |
break;
|
| 1975 |
case 0x544: /* CM_CLKSEL2_PLL */ |
| 1976 |
if (value & ~3) |
| 1977 |
fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
|
| 1978 |
"future compatiblity\n", __FUNCTION__);
|
| 1979 |
if (s->clksel[6] != (value & 3)) { |
| 1980 |
s->clksel[6] = value & 3; |
| 1981 |
omap_prcm_dpll_update(s); |
| 1982 |
} |
| 1983 |
break;
|
| 1984 |
|
| 1985 |
case 0x800: /* CM_FCLKEN_DSP */ |
| 1986 |
s->clken[10] = value & 0x501; |
| 1987 |
/* TODO update clocks */
|
| 1988 |
break;
|
| 1989 |
case 0x810: /* CM_ICLKEN_DSP */ |
| 1990 |
s->clken[11] = value & 0x2; |
| 1991 |
/* TODO update clocks */
|
| 1992 |
break;
|
| 1993 |
case 0x830: /* CM_AUTOIDLE_DSP */ |
| 1994 |
s->clkidle[6] = value & 0x2; |
| 1995 |
/* TODO update clocks */
|
| 1996 |
break;
|
| 1997 |
case 0x840: /* CM_CLKSEL_DSP */ |
| 1998 |
s->clksel[7] = value & 0x3fff; |
| 1999 |
/* TODO update clocks */
|
| 2000 |
break;
|
| 2001 |
case 0x848: /* CM_CLKSTCTRL_DSP */ |
| 2002 |
s->clkctrl[3] = value & 0x101; |
| 2003 |
break;
|
| 2004 |
case 0x850: /* RM_RSTCTRL_DSP */ |
| 2005 |
/* TODO: reset */
|
| 2006 |
break;
|
| 2007 |
case 0x858: /* RM_RSTST_DSP */ |
| 2008 |
s->rst[3] &= ~value;
|
| 2009 |
break;
|
| 2010 |
case 0x8c8: /* PM_WKDEP_DSP */ |
| 2011 |
s->wkup[2] = value & 0x13; |
| 2012 |
break;
|
| 2013 |
case 0x8e0: /* PM_PWSTCTRL_DSP */ |
| 2014 |
s->power[3] = (value & 0x03017) | (3 << 2); |
| 2015 |
break;
|
| 2016 |
|
| 2017 |
case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
| 2018 |
s->irqst[1] &= ~value;
|
| 2019 |
omap_prcm_int_update(s, 1);
|
| 2020 |
break;
|
| 2021 |
case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
| 2022 |
s->irqen[1] = value & 0x7; |
| 2023 |
omap_prcm_int_update(s, 1);
|
| 2024 |
break;
|
| 2025 |
|
| 2026 |
case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
| 2027 |
s->irqst[2] &= ~value;
|
| 2028 |
omap_prcm_int_update(s, 2);
|
| 2029 |
break;
|
| 2030 |
case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
| 2031 |
s->irqen[2] = value & 0x7; |
| 2032 |
omap_prcm_int_update(s, 2);
|
| 2033 |
break;
|
| 2034 |
|
| 2035 |
default:
|
| 2036 |
OMAP_BAD_REG(addr); |
| 2037 |
return;
|
| 2038 |
} |
| 2039 |
} |
| 2040 |
|
| 2041 |
static CPUReadMemoryFunc * const omap_prcm_readfn[] = { |
| 2042 |
omap_badwidth_read32, |
| 2043 |
omap_badwidth_read32, |
| 2044 |
omap_prcm_read, |
| 2045 |
}; |
| 2046 |
|
| 2047 |
static CPUWriteMemoryFunc * const omap_prcm_writefn[] = { |
| 2048 |
omap_badwidth_write32, |
| 2049 |
omap_badwidth_write32, |
| 2050 |
omap_prcm_write, |
| 2051 |
}; |
| 2052 |
|
| 2053 |
static void omap_prcm_reset(struct omap_prcm_s *s) |
| 2054 |
{
|
| 2055 |
s->sysconfig = 0;
|
| 2056 |
s->irqst[0] = 0; |
| 2057 |
s->irqst[1] = 0; |
| 2058 |
s->irqst[2] = 0; |
| 2059 |
s->irqen[0] = 0; |
| 2060 |
s->irqen[1] = 0; |
| 2061 |
s->irqen[2] = 0; |
| 2062 |
s->voltctrl = 0x1040;
|
| 2063 |
s->ev = 0x14;
|
| 2064 |
s->evtime[0] = 0; |
| 2065 |
s->evtime[1] = 0; |
| 2066 |
s->clkctrl[0] = 0; |
| 2067 |
s->clkctrl[1] = 0; |
| 2068 |
s->clkctrl[2] = 0; |
| 2069 |
s->clkctrl[3] = 0; |
| 2070 |
s->clken[1] = 7; |
| 2071 |
s->clken[3] = 7; |
| 2072 |
s->clken[4] = 0; |
| 2073 |
s->clken[5] = 0; |
| 2074 |
s->clken[6] = 0; |
| 2075 |
s->clken[7] = 0xc; |
| 2076 |
s->clken[8] = 0x3e; |
| 2077 |
s->clken[9] = 0x0d; |
| 2078 |
s->clken[10] = 0; |
| 2079 |
s->clken[11] = 0; |
| 2080 |
s->clkidle[0] = 0; |
| 2081 |
s->clkidle[2] = 7; |
| 2082 |
s->clkidle[3] = 0; |
| 2083 |
s->clkidle[4] = 0; |
| 2084 |
s->clkidle[5] = 0x0c; |
| 2085 |
s->clkidle[6] = 0; |
| 2086 |
s->clksel[0] = 0x01; |
| 2087 |
s->clksel[1] = 0x02100121; |
| 2088 |
s->clksel[2] = 0x00000000; |
| 2089 |
s->clksel[3] = 0x01; |
| 2090 |
s->clksel[4] = 0; |
| 2091 |
s->clksel[7] = 0x0121; |
| 2092 |
s->wkup[0] = 0x15; |
| 2093 |
s->wkup[1] = 0x13; |
| 2094 |
s->wkup[2] = 0x13; |
| 2095 |
s->wken[0] = 0x04667ff8; |
| 2096 |
s->wken[1] = 0x00000005; |
| 2097 |
s->wken[2] = 5; |
| 2098 |
s->wkst[0] = 0; |
| 2099 |
s->wkst[1] = 0; |
| 2100 |
s->wkst[2] = 0; |
| 2101 |
s->power[0] = 0x00c; |
| 2102 |
s->power[1] = 4; |
| 2103 |
s->power[2] = 0x0000c; |
| 2104 |
s->power[3] = 0x14; |
| 2105 |
s->rstctrl[0] = 1; |
| 2106 |
s->rst[3] = 1; |
| 2107 |
omap_prcm_apll_update(s); |
| 2108 |
omap_prcm_dpll_update(s); |
| 2109 |
} |
| 2110 |
|
| 2111 |
static void omap_prcm_coldreset(struct omap_prcm_s *s) |
| 2112 |
{
|
| 2113 |
s->setuptime[0] = 0; |
| 2114 |
s->setuptime[1] = 0; |
| 2115 |
memset(&s->scratch, 0, sizeof(s->scratch)); |
| 2116 |
s->rst[0] = 0x01; |
| 2117 |
s->rst[1] = 0x00; |
| 2118 |
s->rst[2] = 0x01; |
| 2119 |
s->clken[0] = 0; |
| 2120 |
s->clken[2] = 0; |
| 2121 |
s->clkidle[1] = 0; |
| 2122 |
s->clksel[5] = 0; |
| 2123 |
s->clksel[6] = 2; |
| 2124 |
s->clksrc[0] = 0x43; |
| 2125 |
s->clkout[0] = 0x0303; |
| 2126 |
s->clkemul[0] = 0; |
| 2127 |
s->clkpol[0] = 0x100; |
| 2128 |
s->rsttime_wkup = 0x1002;
|
| 2129 |
|
| 2130 |
omap_prcm_reset(s); |
| 2131 |
} |
| 2132 |
|
| 2133 |
struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
| 2134 |
qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
| 2135 |
struct omap_mpu_state_s *mpu)
|
| 2136 |
{
|
| 2137 |
int iomemtype;
|
| 2138 |
struct omap_prcm_s *s = (struct omap_prcm_s *) |
| 2139 |
qemu_mallocz(sizeof(struct omap_prcm_s)); |
| 2140 |
|
| 2141 |
s->irq[0] = mpu_int;
|
| 2142 |
s->irq[1] = dsp_int;
|
| 2143 |
s->irq[2] = iva_int;
|
| 2144 |
s->mpu = mpu; |
| 2145 |
omap_prcm_coldreset(s); |
| 2146 |
|
| 2147 |
iomemtype = l4_register_io_memory(omap_prcm_readfn, |
| 2148 |
omap_prcm_writefn, s); |
| 2149 |
omap_l4_attach(ta, 0, iomemtype);
|
| 2150 |
omap_l4_attach(ta, 1, iomemtype);
|
| 2151 |
|
| 2152 |
return s;
|
| 2153 |
} |
| 2154 |
|
| 2155 |
/* System and Pinout control */
|
| 2156 |
struct omap_sysctl_s {
|
| 2157 |
struct omap_mpu_state_s *mpu;
|
| 2158 |
|
| 2159 |
uint32_t sysconfig; |
| 2160 |
uint32_t devconfig; |
| 2161 |
uint32_t psaconfig; |
| 2162 |
uint32_t padconf[0x45];
|
| 2163 |
uint8_t obs; |
| 2164 |
uint32_t msuspendmux[5];
|
| 2165 |
}; |
| 2166 |
|
| 2167 |
static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr) |
| 2168 |
{
|
| 2169 |
|
| 2170 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 2171 |
int pad_offset, byte_offset;
|
| 2172 |
int value;
|
| 2173 |
|
| 2174 |
switch (addr) {
|
| 2175 |
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 2176 |
pad_offset = (addr - 0x30) >> 2; |
| 2177 |
byte_offset = (addr - 0x30) & (4 - 1); |
| 2178 |
|
| 2179 |
value = s->padconf[pad_offset]; |
| 2180 |
value = (value >> (byte_offset * 8)) & 0xff; |
| 2181 |
|
| 2182 |
return value;
|
| 2183 |
|
| 2184 |
default:
|
| 2185 |
break;
|
| 2186 |
} |
| 2187 |
|
| 2188 |
OMAP_BAD_REG(addr); |
| 2189 |
return 0; |
| 2190 |
} |
| 2191 |
|
| 2192 |
static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr) |
| 2193 |
{
|
| 2194 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 2195 |
|
| 2196 |
switch (addr) {
|
| 2197 |
case 0x000: /* CONTROL_REVISION */ |
| 2198 |
return 0x20; |
| 2199 |
|
| 2200 |
case 0x010: /* CONTROL_SYSCONFIG */ |
| 2201 |
return s->sysconfig;
|
| 2202 |
|
| 2203 |
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 2204 |
return s->padconf[(addr - 0x30) >> 2]; |
| 2205 |
|
| 2206 |
case 0x270: /* CONTROL_DEBOBS */ |
| 2207 |
return s->obs;
|
| 2208 |
|
| 2209 |
case 0x274: /* CONTROL_DEVCONF */ |
| 2210 |
return s->devconfig;
|
| 2211 |
|
| 2212 |
case 0x28c: /* CONTROL_EMU_SUPPORT */ |
| 2213 |
return 0; |
| 2214 |
|
| 2215 |
case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
| 2216 |
return s->msuspendmux[0]; |
| 2217 |
case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
| 2218 |
return s->msuspendmux[1]; |
| 2219 |
case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
| 2220 |
return s->msuspendmux[2]; |
| 2221 |
case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
| 2222 |
return s->msuspendmux[3]; |
| 2223 |
case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
| 2224 |
return s->msuspendmux[4]; |
| 2225 |
case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
| 2226 |
return 0; |
| 2227 |
|
| 2228 |
case 0x2b8: /* CONTROL_PSA_CTRL */ |
| 2229 |
return s->psaconfig;
|
| 2230 |
case 0x2bc: /* CONTROL_PSA_CMD */ |
| 2231 |
case 0x2c0: /* CONTROL_PSA_VALUE */ |
| 2232 |
return 0; |
| 2233 |
|
| 2234 |
case 0x2b0: /* CONTROL_SEC_CTRL */ |
| 2235 |
return 0x800000f1; |
| 2236 |
case 0x2d0: /* CONTROL_SEC_EMU */ |
| 2237 |
return 0x80000015; |
| 2238 |
case 0x2d4: /* CONTROL_SEC_TAP */ |
| 2239 |
return 0x8000007f; |
| 2240 |
case 0x2b4: /* CONTROL_SEC_TEST */ |
| 2241 |
case 0x2f0: /* CONTROL_SEC_STATUS */ |
| 2242 |
case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
| 2243 |
/* Secure mode is not present on general-pusrpose device. Outside
|
| 2244 |
* secure mode these values cannot be read or written. */
|
| 2245 |
return 0; |
| 2246 |
|
| 2247 |
case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
| 2248 |
return 0xff; |
| 2249 |
case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
| 2250 |
case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
| 2251 |
case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
| 2252 |
/* No secure mode so no Extended Secure RAM present. */
|
| 2253 |
return 0; |
| 2254 |
|
| 2255 |
case 0x2f8: /* CONTROL_STATUS */ |
| 2256 |
/* Device Type => General-purpose */
|
| 2257 |
return 0x0300; |
| 2258 |
case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
| 2259 |
|
| 2260 |
case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
| 2261 |
case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
| 2262 |
case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
| 2263 |
case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
| 2264 |
return 0xdecafbad; |
| 2265 |
|
| 2266 |
case 0x310: /* CONTROL_RAND_KEY_0 */ |
| 2267 |
case 0x314: /* CONTROL_RAND_KEY_1 */ |
| 2268 |
case 0x318: /* CONTROL_RAND_KEY_2 */ |
| 2269 |
case 0x31c: /* CONTROL_RAND_KEY_3 */ |
| 2270 |
case 0x320: /* CONTROL_CUST_KEY_0 */ |
| 2271 |
case 0x324: /* CONTROL_CUST_KEY_1 */ |
| 2272 |
case 0x330: /* CONTROL_TEST_KEY_0 */ |
| 2273 |
case 0x334: /* CONTROL_TEST_KEY_1 */ |
| 2274 |
case 0x338: /* CONTROL_TEST_KEY_2 */ |
| 2275 |
case 0x33c: /* CONTROL_TEST_KEY_3 */ |
| 2276 |
case 0x340: /* CONTROL_TEST_KEY_4 */ |
| 2277 |
case 0x344: /* CONTROL_TEST_KEY_5 */ |
| 2278 |
case 0x348: /* CONTROL_TEST_KEY_6 */ |
| 2279 |
case 0x34c: /* CONTROL_TEST_KEY_7 */ |
| 2280 |
case 0x350: /* CONTROL_TEST_KEY_8 */ |
| 2281 |
case 0x354: /* CONTROL_TEST_KEY_9 */ |
| 2282 |
/* Can only be accessed in secure mode and when C_FieldAccEnable
|
| 2283 |
* bit is set in CONTROL_SEC_CTRL.
|
| 2284 |
* TODO: otherwise an interconnect access error is generated. */
|
| 2285 |
return 0; |
| 2286 |
} |
| 2287 |
|
| 2288 |
OMAP_BAD_REG(addr); |
| 2289 |
return 0; |
| 2290 |
} |
| 2291 |
|
| 2292 |
static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr, |
| 2293 |
uint32_t value) |
| 2294 |
{
|
| 2295 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 2296 |
int pad_offset, byte_offset;
|
| 2297 |
int prev_value;
|
| 2298 |
|
| 2299 |
switch (addr) {
|
| 2300 |
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 2301 |
pad_offset = (addr - 0x30) >> 2; |
| 2302 |
byte_offset = (addr - 0x30) & (4 - 1); |
| 2303 |
|
| 2304 |
prev_value = s->padconf[pad_offset]; |
| 2305 |
prev_value &= ~(0xff << (byte_offset * 8)); |
| 2306 |
prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f; |
| 2307 |
s->padconf[pad_offset] = prev_value; |
| 2308 |
break;
|
| 2309 |
|
| 2310 |
default:
|
| 2311 |
OMAP_BAD_REG(addr); |
| 2312 |
break;
|
| 2313 |
} |
| 2314 |
} |
| 2315 |
|
| 2316 |
static void omap_sysctl_write(void *opaque, target_phys_addr_t addr, |
| 2317 |
uint32_t value) |
| 2318 |
{
|
| 2319 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 2320 |
|
| 2321 |
switch (addr) {
|
| 2322 |
case 0x000: /* CONTROL_REVISION */ |
| 2323 |
case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
| 2324 |
case 0x2c0: /* CONTROL_PSA_VALUE */ |
| 2325 |
case 0x2f8: /* CONTROL_STATUS */ |
| 2326 |
case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
| 2327 |
case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
| 2328 |
case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
| 2329 |
case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
| 2330 |
case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
| 2331 |
case 0x310: /* CONTROL_RAND_KEY_0 */ |
| 2332 |
case 0x314: /* CONTROL_RAND_KEY_1 */ |
| 2333 |
case 0x318: /* CONTROL_RAND_KEY_2 */ |
| 2334 |
case 0x31c: /* CONTROL_RAND_KEY_3 */ |
| 2335 |
case 0x320: /* CONTROL_CUST_KEY_0 */ |
| 2336 |
case 0x324: /* CONTROL_CUST_KEY_1 */ |
| 2337 |
case 0x330: /* CONTROL_TEST_KEY_0 */ |
| 2338 |
case 0x334: /* CONTROL_TEST_KEY_1 */ |
| 2339 |
case 0x338: /* CONTROL_TEST_KEY_2 */ |
| 2340 |
case 0x33c: /* CONTROL_TEST_KEY_3 */ |
| 2341 |
case 0x340: /* CONTROL_TEST_KEY_4 */ |
| 2342 |
case 0x344: /* CONTROL_TEST_KEY_5 */ |
| 2343 |
case 0x348: /* CONTROL_TEST_KEY_6 */ |
| 2344 |
case 0x34c: /* CONTROL_TEST_KEY_7 */ |
| 2345 |
case 0x350: /* CONTROL_TEST_KEY_8 */ |
| 2346 |
case 0x354: /* CONTROL_TEST_KEY_9 */ |
| 2347 |
OMAP_RO_REG(addr); |
| 2348 |
return;
|
| 2349 |
|
| 2350 |
case 0x010: /* CONTROL_SYSCONFIG */ |
| 2351 |
s->sysconfig = value & 0x1e;
|
| 2352 |
break;
|
| 2353 |
|
| 2354 |
case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 2355 |
/* XXX: should check constant bits */
|
| 2356 |
s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f; |
| 2357 |
break;
|
| 2358 |
|
| 2359 |
case 0x270: /* CONTROL_DEBOBS */ |
| 2360 |
s->obs = value & 0xff;
|
| 2361 |
break;
|
| 2362 |
|
| 2363 |
case 0x274: /* CONTROL_DEVCONF */ |
| 2364 |
s->devconfig = value & 0xffffc7ff;
|
| 2365 |
break;
|
| 2366 |
|
| 2367 |
case 0x28c: /* CONTROL_EMU_SUPPORT */ |
| 2368 |
break;
|
| 2369 |
|
| 2370 |
case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
| 2371 |
s->msuspendmux[0] = value & 0x3fffffff; |
| 2372 |
break;
|
| 2373 |
case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
| 2374 |
s->msuspendmux[1] = value & 0x3fffffff; |
| 2375 |
break;
|
| 2376 |
case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
| 2377 |
s->msuspendmux[2] = value & 0x3fffffff; |
| 2378 |
break;
|
| 2379 |
case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
| 2380 |
s->msuspendmux[3] = value & 0x3fffffff; |
| 2381 |
break;
|
| 2382 |
case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
| 2383 |
s->msuspendmux[4] = value & 0x3fffffff; |
| 2384 |
break;
|
| 2385 |
|
| 2386 |
case 0x2b8: /* CONTROL_PSA_CTRL */ |
| 2387 |
s->psaconfig = value & 0x1c;
|
| 2388 |
s->psaconfig |= (value & 0x20) ? 2 : 1; |
| 2389 |
break;
|
| 2390 |
case 0x2bc: /* CONTROL_PSA_CMD */ |
| 2391 |
break;
|
| 2392 |
|
| 2393 |
case 0x2b0: /* CONTROL_SEC_CTRL */ |
| 2394 |
case 0x2b4: /* CONTROL_SEC_TEST */ |
| 2395 |
case 0x2d0: /* CONTROL_SEC_EMU */ |
| 2396 |
case 0x2d4: /* CONTROL_SEC_TAP */ |
| 2397 |
case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
| 2398 |
case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
| 2399 |
case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
| 2400 |
case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
| 2401 |
case 0x2f0: /* CONTROL_SEC_STATUS */ |
| 2402 |
case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
| 2403 |
break;
|
| 2404 |
|
| 2405 |
default:
|
| 2406 |
OMAP_BAD_REG(addr); |
| 2407 |
return;
|
| 2408 |
} |
| 2409 |
} |
| 2410 |
|
| 2411 |
static CPUReadMemoryFunc * const omap_sysctl_readfn[] = { |
| 2412 |
omap_sysctl_read8, |
| 2413 |
omap_badwidth_read32, /* TODO */
|
| 2414 |
omap_sysctl_read, |
| 2415 |
}; |
| 2416 |
|
| 2417 |
static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = { |
| 2418 |
omap_sysctl_write8, |
| 2419 |
omap_badwidth_write32, /* TODO */
|
| 2420 |
omap_sysctl_write, |
| 2421 |
}; |
| 2422 |
|
| 2423 |
static void omap_sysctl_reset(struct omap_sysctl_s *s) |
| 2424 |
{
|
| 2425 |
/* (power-on reset) */
|
| 2426 |
s->sysconfig = 0;
|
| 2427 |
s->obs = 0;
|
| 2428 |
s->devconfig = 0x0c000000;
|
| 2429 |
s->msuspendmux[0] = 0x00000000; |
| 2430 |
s->msuspendmux[1] = 0x00000000; |
| 2431 |
s->msuspendmux[2] = 0x00000000; |
| 2432 |
s->msuspendmux[3] = 0x00000000; |
| 2433 |
s->msuspendmux[4] = 0x00000000; |
| 2434 |
s->psaconfig = 1;
|
| 2435 |
|
| 2436 |
s->padconf[0x00] = 0x000f0f0f; |
| 2437 |
s->padconf[0x01] = 0x00000000; |
| 2438 |
s->padconf[0x02] = 0x00000000; |
| 2439 |
s->padconf[0x03] = 0x00000000; |
| 2440 |
s->padconf[0x04] = 0x00000000; |
| 2441 |
s->padconf[0x05] = 0x00000000; |
| 2442 |
s->padconf[0x06] = 0x00000000; |
| 2443 |
s->padconf[0x07] = 0x00000000; |
| 2444 |
s->padconf[0x08] = 0x08080800; |
| 2445 |
s->padconf[0x09] = 0x08080808; |
| 2446 |
s->padconf[0x0a] = 0x08080808; |
| 2447 |
s->padconf[0x0b] = 0x08080808; |
| 2448 |
s->padconf[0x0c] = 0x08080808; |
| 2449 |
s->padconf[0x0d] = 0x08080800; |
| 2450 |
s->padconf[0x0e] = 0x08080808; |
| 2451 |
s->padconf[0x0f] = 0x08080808; |
| 2452 |
s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ |
| 2453 |
s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
| 2454 |
s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
| 2455 |
s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
| 2456 |
s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ |
| 2457 |
s->padconf[0x15] = 0x18181818; |
| 2458 |
s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ |
| 2459 |
s->padconf[0x17] = 0x1f001f00; |
| 2460 |
s->padconf[0x18] = 0x1f1f1f1f; |
| 2461 |
s->padconf[0x19] = 0x00000000; |
| 2462 |
s->padconf[0x1a] = 0x1f180000; |
| 2463 |
s->padconf[0x1b] = 0x00001f1f; |
| 2464 |
s->padconf[0x1c] = 0x1f001f00; |
| 2465 |
s->padconf[0x1d] = 0x00000000; |
| 2466 |
s->padconf[0x1e] = 0x00000000; |
| 2467 |
s->padconf[0x1f] = 0x08000000; |
| 2468 |
s->padconf[0x20] = 0x08080808; |
| 2469 |
s->padconf[0x21] = 0x08080808; |
| 2470 |
s->padconf[0x22] = 0x0f080808; |
| 2471 |
s->padconf[0x23] = 0x0f0f0f0f; |
| 2472 |
s->padconf[0x24] = 0x000f0f0f; |
| 2473 |
s->padconf[0x25] = 0x1f1f1f0f; |
| 2474 |
s->padconf[0x26] = 0x080f0f1f; |
| 2475 |
s->padconf[0x27] = 0x070f1808; |
| 2476 |
s->padconf[0x28] = 0x0f070707; |
| 2477 |
s->padconf[0x29] = 0x000f0f1f; |
| 2478 |
s->padconf[0x2a] = 0x0f0f0f1f; |
| 2479 |
s->padconf[0x2b] = 0x08000000; |
| 2480 |
s->padconf[0x2c] = 0x0000001f; |
| 2481 |
s->padconf[0x2d] = 0x0f0f1f00; |
| 2482 |
s->padconf[0x2e] = 0x1f1f0f0f; |
| 2483 |
s->padconf[0x2f] = 0x0f1f1f1f; |
| 2484 |
s->padconf[0x30] = 0x0f0f0f0f; |
| 2485 |
s->padconf[0x31] = 0x0f1f0f1f; |
| 2486 |
s->padconf[0x32] = 0x0f0f0f0f; |
| 2487 |
s->padconf[0x33] = 0x0f1f0f1f; |
| 2488 |
s->padconf[0x34] = 0x1f1f0f0f; |
| 2489 |
s->padconf[0x35] = 0x0f0f1f1f; |
| 2490 |
s->padconf[0x36] = 0x0f0f1f0f; |
| 2491 |
s->padconf[0x37] = 0x0f0f0f0f; |
| 2492 |
s->padconf[0x38] = 0x1f18180f; |
| 2493 |
s->padconf[0x39] = 0x1f1f1f1f; |
| 2494 |
s->padconf[0x3a] = 0x00001f1f; |
| 2495 |
s->padconf[0x3b] = 0x00000000; |
| 2496 |
s->padconf[0x3c] = 0x00000000; |
| 2497 |
s->padconf[0x3d] = 0x0f0f0f0f; |
| 2498 |
s->padconf[0x3e] = 0x18000f0f; |
| 2499 |
s->padconf[0x3f] = 0x00070000; |
| 2500 |
s->padconf[0x40] = 0x00000707; |
| 2501 |
s->padconf[0x41] = 0x0f1f0700; |
| 2502 |
s->padconf[0x42] = 0x1f1f070f; |
| 2503 |
s->padconf[0x43] = 0x0008081f; |
| 2504 |
s->padconf[0x44] = 0x00000800; |
| 2505 |
} |
| 2506 |
|
| 2507 |
struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
| 2508 |
omap_clk iclk, struct omap_mpu_state_s *mpu)
|
| 2509 |
{
|
| 2510 |
int iomemtype;
|
| 2511 |
struct omap_sysctl_s *s = (struct omap_sysctl_s *) |
| 2512 |
qemu_mallocz(sizeof(struct omap_sysctl_s)); |
| 2513 |
|
| 2514 |
s->mpu = mpu; |
| 2515 |
omap_sysctl_reset(s); |
| 2516 |
|
| 2517 |
iomemtype = l4_register_io_memory(omap_sysctl_readfn, |
| 2518 |
omap_sysctl_writefn, s); |
| 2519 |
omap_l4_attach(ta, 0, iomemtype);
|
| 2520 |
|
| 2521 |
return s;
|
| 2522 |
} |
| 2523 |
|
| 2524 |
/* General chip reset */
|
| 2525 |
static void omap2_mpu_reset(void *opaque) |
| 2526 |
{
|
| 2527 |
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
| 2528 |
|
| 2529 |
omap_inth_reset(mpu->ih[0]);
|
| 2530 |
omap_dma_reset(mpu->dma); |
| 2531 |
omap_prcm_reset(mpu->prcm); |
| 2532 |
omap_sysctl_reset(mpu->sysc); |
| 2533 |
omap_gp_timer_reset(mpu->gptimer[0]);
|
| 2534 |
omap_gp_timer_reset(mpu->gptimer[1]);
|
| 2535 |
omap_gp_timer_reset(mpu->gptimer[2]);
|
| 2536 |
omap_gp_timer_reset(mpu->gptimer[3]);
|
| 2537 |
omap_gp_timer_reset(mpu->gptimer[4]);
|
| 2538 |
omap_gp_timer_reset(mpu->gptimer[5]);
|
| 2539 |
omap_gp_timer_reset(mpu->gptimer[6]);
|
| 2540 |
omap_gp_timer_reset(mpu->gptimer[7]);
|
| 2541 |
omap_gp_timer_reset(mpu->gptimer[8]);
|
| 2542 |
omap_gp_timer_reset(mpu->gptimer[9]);
|
| 2543 |
omap_gp_timer_reset(mpu->gptimer[10]);
|
| 2544 |
omap_gp_timer_reset(mpu->gptimer[11]);
|
| 2545 |
omap_synctimer_reset(mpu->synctimer); |
| 2546 |
omap_sdrc_reset(mpu->sdrc); |
| 2547 |
omap_gpmc_reset(mpu->gpmc); |
| 2548 |
omap_dss_reset(mpu->dss); |
| 2549 |
omap_uart_reset(mpu->uart[0]);
|
| 2550 |
omap_uart_reset(mpu->uart[1]);
|
| 2551 |
omap_uart_reset(mpu->uart[2]);
|
| 2552 |
omap_mmc_reset(mpu->mmc); |
| 2553 |
omap_gpif_reset(mpu->gpif); |
| 2554 |
omap_mcspi_reset(mpu->mcspi[0]);
|
| 2555 |
omap_mcspi_reset(mpu->mcspi[1]);
|
| 2556 |
omap_i2c_reset(mpu->i2c[0]);
|
| 2557 |
omap_i2c_reset(mpu->i2c[1]);
|
| 2558 |
cpu_reset(mpu->env); |
| 2559 |
} |
| 2560 |
|
| 2561 |
static int omap2_validate_addr(struct omap_mpu_state_s *s, |
| 2562 |
target_phys_addr_t addr) |
| 2563 |
{
|
| 2564 |
return 1; |
| 2565 |
} |
| 2566 |
|
| 2567 |
static const struct dma_irq_map omap2_dma_irq_map[] = { |
| 2568 |
{ 0, OMAP_INT_24XX_SDMA_IRQ0 },
|
| 2569 |
{ 0, OMAP_INT_24XX_SDMA_IRQ1 },
|
| 2570 |
{ 0, OMAP_INT_24XX_SDMA_IRQ2 },
|
| 2571 |
{ 0, OMAP_INT_24XX_SDMA_IRQ3 },
|
| 2572 |
}; |
| 2573 |
|
| 2574 |
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
| 2575 |
const char *core) |
| 2576 |
{
|
| 2577 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
| 2578 |
qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
| 2579 |
ram_addr_t sram_base, q2_base; |
| 2580 |
qemu_irq *cpu_irq; |
| 2581 |
qemu_irq dma_irqs[4];
|
| 2582 |
omap_clk gpio_clks[4];
|
| 2583 |
DriveInfo *dinfo; |
| 2584 |
int i;
|
| 2585 |
|
| 2586 |
/* Core */
|
| 2587 |
s->mpu_model = omap2420; |
| 2588 |
s->env = cpu_init(core ?: "arm1136-r2");
|
| 2589 |
if (!s->env) {
|
| 2590 |
fprintf(stderr, "Unable to find CPU definition\n");
|
| 2591 |
exit(1);
|
| 2592 |
} |
| 2593 |
s->sdram_size = sdram_size; |
| 2594 |
s->sram_size = OMAP242X_SRAM_SIZE; |
| 2595 |
|
| 2596 |
s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
| 2597 |
|
| 2598 |
/* Clocks */
|
| 2599 |
omap_clk_init(s); |
| 2600 |
|
| 2601 |
/* Memory-mapped stuff */
|
| 2602 |
cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size, |
| 2603 |
(q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
| 2604 |
cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size, |
| 2605 |
(sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
| 2606 |
|
| 2607 |
s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
|
| 2608 |
|
| 2609 |
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
|
| 2610 |
cpu_irq = arm_pic_init_cpu(s->env); |
| 2611 |
s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0], |
| 2612 |
cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
| 2613 |
omap_findclk(s, "mpu_intc_fclk"),
|
| 2614 |
omap_findclk(s, "mpu_intc_iclk"));
|
| 2615 |
|
| 2616 |
s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
|
| 2617 |
s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s); |
| 2618 |
|
| 2619 |
s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
|
| 2620 |
omap_findclk(s, "omapctrl_iclk"), s);
|
| 2621 |
|
| 2622 |
for (i = 0; i < 4; i ++) |
| 2623 |
dma_irqs[i] = |
| 2624 |
s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr]; |
| 2625 |
s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32, |
| 2626 |
omap_findclk(s, "sdma_iclk"),
|
| 2627 |
omap_findclk(s, "sdma_fclk"));
|
| 2628 |
s->port->addr_valid = omap2_validate_addr; |
| 2629 |
|
| 2630 |
/* Register SDRAM and SRAM ports for fast DMA transfers. */
|
| 2631 |
soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size); |
| 2632 |
soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size); |
| 2633 |
|
| 2634 |
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19), |
| 2635 |
s->irq[0][OMAP_INT_24XX_UART1_IRQ],
|
| 2636 |
omap_findclk(s, "uart1_fclk"),
|
| 2637 |
omap_findclk(s, "uart1_iclk"),
|
| 2638 |
s->drq[OMAP24XX_DMA_UART1_TX], |
| 2639 |
s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
|
| 2640 |
s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20), |
| 2641 |
s->irq[0][OMAP_INT_24XX_UART2_IRQ],
|
| 2642 |
omap_findclk(s, "uart2_fclk"),
|
| 2643 |
omap_findclk(s, "uart2_iclk"),
|
| 2644 |
s->drq[OMAP24XX_DMA_UART2_TX], |
| 2645 |
s->drq[OMAP24XX_DMA_UART2_RX], |
| 2646 |
serial_hds[0] ? serial_hds[1] : NULL); |
| 2647 |
s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21), |
| 2648 |
s->irq[0][OMAP_INT_24XX_UART3_IRQ],
|
| 2649 |
omap_findclk(s, "uart3_fclk"),
|
| 2650 |
omap_findclk(s, "uart3_iclk"),
|
| 2651 |
s->drq[OMAP24XX_DMA_UART3_TX], |
| 2652 |
s->drq[OMAP24XX_DMA_UART3_RX], |
| 2653 |
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
| 2654 |
|
| 2655 |
s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), |
| 2656 |
s->irq[0][OMAP_INT_24XX_GPTIMER1],
|
| 2657 |
omap_findclk(s, "wu_gpt1_clk"),
|
| 2658 |
omap_findclk(s, "wu_l4_iclk"));
|
| 2659 |
s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), |
| 2660 |
s->irq[0][OMAP_INT_24XX_GPTIMER2],
|
| 2661 |
omap_findclk(s, "core_gpt2_clk"),
|
| 2662 |
omap_findclk(s, "core_l4_iclk"));
|
| 2663 |
s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), |
| 2664 |
s->irq[0][OMAP_INT_24XX_GPTIMER3],
|
| 2665 |
omap_findclk(s, "core_gpt3_clk"),
|
| 2666 |
omap_findclk(s, "core_l4_iclk"));
|
| 2667 |
s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), |
| 2668 |
s->irq[0][OMAP_INT_24XX_GPTIMER4],
|
| 2669 |
omap_findclk(s, "core_gpt4_clk"),
|
| 2670 |
omap_findclk(s, "core_l4_iclk"));
|
| 2671 |
s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), |
| 2672 |
s->irq[0][OMAP_INT_24XX_GPTIMER5],
|
| 2673 |
omap_findclk(s, "core_gpt5_clk"),
|
| 2674 |
omap_findclk(s, "core_l4_iclk"));
|
| 2675 |
s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), |
| 2676 |
s->irq[0][OMAP_INT_24XX_GPTIMER6],
|
| 2677 |
omap_findclk(s, "core_gpt6_clk"),
|
| 2678 |
omap_findclk(s, "core_l4_iclk"));
|
| 2679 |
s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), |
| 2680 |
s->irq[0][OMAP_INT_24XX_GPTIMER7],
|
| 2681 |
omap_findclk(s, "core_gpt7_clk"),
|
| 2682 |
omap_findclk(s, "core_l4_iclk"));
|
| 2683 |
s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), |
| 2684 |
s->irq[0][OMAP_INT_24XX_GPTIMER8],
|
| 2685 |
omap_findclk(s, "core_gpt8_clk"),
|
| 2686 |
omap_findclk(s, "core_l4_iclk"));
|
| 2687 |
s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), |
| 2688 |
s->irq[0][OMAP_INT_24XX_GPTIMER9],
|
| 2689 |
omap_findclk(s, "core_gpt9_clk"),
|
| 2690 |
omap_findclk(s, "core_l4_iclk"));
|
| 2691 |
s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), |
| 2692 |
s->irq[0][OMAP_INT_24XX_GPTIMER10],
|
| 2693 |
omap_findclk(s, "core_gpt10_clk"),
|
| 2694 |
omap_findclk(s, "core_l4_iclk"));
|
| 2695 |
s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), |
| 2696 |
s->irq[0][OMAP_INT_24XX_GPTIMER11],
|
| 2697 |
omap_findclk(s, "core_gpt11_clk"),
|
| 2698 |
omap_findclk(s, "core_l4_iclk"));
|
| 2699 |
s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), |
| 2700 |
s->irq[0][OMAP_INT_24XX_GPTIMER12],
|
| 2701 |
omap_findclk(s, "core_gpt12_clk"),
|
| 2702 |
omap_findclk(s, "core_l4_iclk"));
|
| 2703 |
|
| 2704 |
omap_tap_init(omap_l4ta(s->l4, 2), s);
|
| 2705 |
|
| 2706 |
s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
|
| 2707 |
omap_findclk(s, "clk32-kHz"),
|
| 2708 |
omap_findclk(s, "core_l4_iclk"));
|
| 2709 |
|
| 2710 |
s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5), |
| 2711 |
s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
|
| 2712 |
&s->drq[OMAP24XX_DMA_I2C1_TX], |
| 2713 |
omap_findclk(s, "i2c1.fclk"),
|
| 2714 |
omap_findclk(s, "i2c1.iclk"));
|
| 2715 |
s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6), |
| 2716 |
s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
|
| 2717 |
&s->drq[OMAP24XX_DMA_I2C2_TX], |
| 2718 |
omap_findclk(s, "i2c2.fclk"),
|
| 2719 |
omap_findclk(s, "i2c2.iclk"));
|
| 2720 |
|
| 2721 |
gpio_clks[0] = omap_findclk(s, "gpio1_dbclk"); |
| 2722 |
gpio_clks[1] = omap_findclk(s, "gpio2_dbclk"); |
| 2723 |
gpio_clks[2] = omap_findclk(s, "gpio3_dbclk"); |
| 2724 |
gpio_clks[3] = omap_findclk(s, "gpio4_dbclk"); |
| 2725 |
s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
|
| 2726 |
&s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
|
| 2727 |
gpio_clks, omap_findclk(s, "gpio_iclk"), 4); |
| 2728 |
|
| 2729 |
s->sdrc = omap_sdrc_init(0x68009000);
|
| 2730 |
s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]); |
| 2731 |
|
| 2732 |
dinfo = drive_get(IF_SD, 0, 0); |
| 2733 |
if (!dinfo) {
|
| 2734 |
fprintf(stderr, "qemu: missing SecureDigital device\n");
|
| 2735 |
exit(1);
|
| 2736 |
} |
| 2737 |
s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
|
| 2738 |
s->irq[0][OMAP_INT_24XX_MMC_IRQ],
|
| 2739 |
&s->drq[OMAP24XX_DMA_MMC1_TX], |
| 2740 |
omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); |
| 2741 |
|
| 2742 |
s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, |
| 2743 |
s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
|
| 2744 |
&s->drq[OMAP24XX_DMA_SPI1_TX0], |
| 2745 |
omap_findclk(s, "spi1_fclk"),
|
| 2746 |
omap_findclk(s, "spi1_iclk"));
|
| 2747 |
s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, |
| 2748 |
s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
|
| 2749 |
&s->drq[OMAP24XX_DMA_SPI2_TX0], |
| 2750 |
omap_findclk(s, "spi2_fclk"),
|
| 2751 |
omap_findclk(s, "spi2_iclk"));
|
| 2752 |
|
| 2753 |
s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, |
| 2754 |
/* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
|
| 2755 |
s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
|
| 2756 |
omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), |
| 2757 |
omap_findclk(s, "dss_54m_clk"),
|
| 2758 |
omap_findclk(s, "dss_l3_iclk"),
|
| 2759 |
omap_findclk(s, "dss_l4_iclk"));
|
| 2760 |
|
| 2761 |
omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000, |
| 2762 |
s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"), |
| 2763 |
serial_hds[0] && serial_hds[1] && serial_hds[2] ? |
| 2764 |
serial_hds[3] : NULL); |
| 2765 |
|
| 2766 |
s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
|
| 2767 |
s->irq[0][OMAP_INT_24XX_EAC_IRQ],
|
| 2768 |
/* Ten consecutive lines */
|
| 2769 |
&s->drq[OMAP24XX_DMA_EAC_AC_RD], |
| 2770 |
omap_findclk(s, "func_96m_clk"),
|
| 2771 |
omap_findclk(s, "core_l4_iclk"));
|
| 2772 |
|
| 2773 |
/* All register mappings (includin those not currenlty implemented):
|
| 2774 |
* SystemControlMod 48000000 - 48000fff
|
| 2775 |
* SystemControlL4 48001000 - 48001fff
|
| 2776 |
* 32kHz Timer Mod 48004000 - 48004fff
|
| 2777 |
* 32kHz Timer L4 48005000 - 48005fff
|
| 2778 |
* PRCM ModA 48008000 - 480087ff
|
| 2779 |
* PRCM ModB 48008800 - 48008fff
|
| 2780 |
* PRCM L4 48009000 - 48009fff
|
| 2781 |
* TEST-BCM Mod 48012000 - 48012fff
|
| 2782 |
* TEST-BCM L4 48013000 - 48013fff
|
| 2783 |
* TEST-TAP Mod 48014000 - 48014fff
|
| 2784 |
* TEST-TAP L4 48015000 - 48015fff
|
| 2785 |
* GPIO1 Mod 48018000 - 48018fff
|
| 2786 |
* GPIO Top 48019000 - 48019fff
|
| 2787 |
* GPIO2 Mod 4801a000 - 4801afff
|
| 2788 |
* GPIO L4 4801b000 - 4801bfff
|
| 2789 |
* GPIO3 Mod 4801c000 - 4801cfff
|
| 2790 |
* GPIO4 Mod 4801e000 - 4801efff
|
| 2791 |
* WDTIMER1 Mod 48020000 - 48010fff
|
| 2792 |
* WDTIMER Top 48021000 - 48011fff
|
| 2793 |
* WDTIMER2 Mod 48022000 - 48012fff
|
| 2794 |
* WDTIMER L4 48023000 - 48013fff
|
| 2795 |
* WDTIMER3 Mod 48024000 - 48014fff
|
| 2796 |
* WDTIMER3 L4 48025000 - 48015fff
|
| 2797 |
* WDTIMER4 Mod 48026000 - 48016fff
|
| 2798 |
* WDTIMER4 L4 48027000 - 48017fff
|
| 2799 |
* GPTIMER1 Mod 48028000 - 48018fff
|
| 2800 |
* GPTIMER1 L4 48029000 - 48019fff
|
| 2801 |
* GPTIMER2 Mod 4802a000 - 4801afff
|
| 2802 |
* GPTIMER2 L4 4802b000 - 4801bfff
|
| 2803 |
* L4-Config AP 48040000 - 480407ff
|
| 2804 |
* L4-Config IP 48040800 - 48040fff
|
| 2805 |
* L4-Config LA 48041000 - 48041fff
|
| 2806 |
* ARM11ETB Mod 48048000 - 48049fff
|
| 2807 |
* ARM11ETB L4 4804a000 - 4804afff
|
| 2808 |
* DISPLAY Top 48050000 - 480503ff
|
| 2809 |
* DISPLAY DISPC 48050400 - 480507ff
|
| 2810 |
* DISPLAY RFBI 48050800 - 48050bff
|
| 2811 |
* DISPLAY VENC 48050c00 - 48050fff
|
| 2812 |
* DISPLAY L4 48051000 - 48051fff
|
| 2813 |
* CAMERA Top 48052000 - 480523ff
|
| 2814 |
* CAMERA core 48052400 - 480527ff
|
| 2815 |
* CAMERA DMA 48052800 - 48052bff
|
| 2816 |
* CAMERA MMU 48052c00 - 48052fff
|
| 2817 |
* CAMERA L4 48053000 - 48053fff
|
| 2818 |
* SDMA Mod 48056000 - 48056fff
|
| 2819 |
* SDMA L4 48057000 - 48057fff
|
| 2820 |
* SSI Top 48058000 - 48058fff
|
| 2821 |
* SSI GDD 48059000 - 48059fff
|
| 2822 |
* SSI Port1 4805a000 - 4805afff
|
| 2823 |
* SSI Port2 4805b000 - 4805bfff
|
| 2824 |
* SSI L4 4805c000 - 4805cfff
|
| 2825 |
* USB Mod 4805e000 - 480fefff
|
| 2826 |
* USB L4 4805f000 - 480fffff
|
| 2827 |
* WIN_TRACER1 Mod 48060000 - 48060fff
|
| 2828 |
* WIN_TRACER1 L4 48061000 - 48061fff
|
| 2829 |
* WIN_TRACER2 Mod 48062000 - 48062fff
|
| 2830 |
* WIN_TRACER2 L4 48063000 - 48063fff
|
| 2831 |
* WIN_TRACER3 Mod 48064000 - 48064fff
|
| 2832 |
* WIN_TRACER3 L4 48065000 - 48065fff
|
| 2833 |
* WIN_TRACER4 Top 48066000 - 480660ff
|
| 2834 |
* WIN_TRACER4 ETT 48066100 - 480661ff
|
| 2835 |
* WIN_TRACER4 WT 48066200 - 480662ff
|
| 2836 |
* WIN_TRACER4 L4 48067000 - 48067fff
|
| 2837 |
* XTI Mod 48068000 - 48068fff
|
| 2838 |
* XTI L4 48069000 - 48069fff
|
| 2839 |
* UART1 Mod 4806a000 - 4806afff
|
| 2840 |
* UART1 L4 4806b000 - 4806bfff
|
| 2841 |
* UART2 Mod 4806c000 - 4806cfff
|
| 2842 |
* UART2 L4 4806d000 - 4806dfff
|
| 2843 |
* UART3 Mod 4806e000 - 4806efff
|
| 2844 |
* UART3 L4 4806f000 - 4806ffff
|
| 2845 |
* I2C1 Mod 48070000 - 48070fff
|
| 2846 |
* I2C1 L4 48071000 - 48071fff
|
| 2847 |
* I2C2 Mod 48072000 - 48072fff
|
| 2848 |
* I2C2 L4 48073000 - 48073fff
|
| 2849 |
* McBSP1 Mod 48074000 - 48074fff
|
| 2850 |
* McBSP1 L4 48075000 - 48075fff
|
| 2851 |
* McBSP2 Mod 48076000 - 48076fff
|
| 2852 |
* McBSP2 L4 48077000 - 48077fff
|
| 2853 |
* GPTIMER3 Mod 48078000 - 48078fff
|
| 2854 |
* GPTIMER3 L4 48079000 - 48079fff
|
| 2855 |
* GPTIMER4 Mod 4807a000 - 4807afff
|
| 2856 |
* GPTIMER4 L4 4807b000 - 4807bfff
|
| 2857 |
* GPTIMER5 Mod 4807c000 - 4807cfff
|
| 2858 |
* GPTIMER5 L4 4807d000 - 4807dfff
|
| 2859 |
* GPTIMER6 Mod 4807e000 - 4807efff
|
| 2860 |
* GPTIMER6 L4 4807f000 - 4807ffff
|
| 2861 |
* GPTIMER7 Mod 48080000 - 48080fff
|
| 2862 |
* GPTIMER7 L4 48081000 - 48081fff
|
| 2863 |
* GPTIMER8 Mod 48082000 - 48082fff
|
| 2864 |
* GPTIMER8 L4 48083000 - 48083fff
|
| 2865 |
* GPTIMER9 Mod 48084000 - 48084fff
|
| 2866 |
* GPTIMER9 L4 48085000 - 48085fff
|
| 2867 |
* GPTIMER10 Mod 48086000 - 48086fff
|
| 2868 |
* GPTIMER10 L4 48087000 - 48087fff
|
| 2869 |
* GPTIMER11 Mod 48088000 - 48088fff
|
| 2870 |
* GPTIMER11 L4 48089000 - 48089fff
|
| 2871 |
* GPTIMER12 Mod 4808a000 - 4808afff
|
| 2872 |
* GPTIMER12 L4 4808b000 - 4808bfff
|
| 2873 |
* EAC Mod 48090000 - 48090fff
|
| 2874 |
* EAC L4 48091000 - 48091fff
|
| 2875 |
* FAC Mod 48092000 - 48092fff
|
| 2876 |
* FAC L4 48093000 - 48093fff
|
| 2877 |
* MAILBOX Mod 48094000 - 48094fff
|
| 2878 |
* MAILBOX L4 48095000 - 48095fff
|
| 2879 |
* SPI1 Mod 48098000 - 48098fff
|
| 2880 |
* SPI1 L4 48099000 - 48099fff
|
| 2881 |
* SPI2 Mod 4809a000 - 4809afff
|
| 2882 |
* SPI2 L4 4809b000 - 4809bfff
|
| 2883 |
* MMC/SDIO Mod 4809c000 - 4809cfff
|
| 2884 |
* MMC/SDIO L4 4809d000 - 4809dfff
|
| 2885 |
* MS_PRO Mod 4809e000 - 4809efff
|
| 2886 |
* MS_PRO L4 4809f000 - 4809ffff
|
| 2887 |
* RNG Mod 480a0000 - 480a0fff
|
| 2888 |
* RNG L4 480a1000 - 480a1fff
|
| 2889 |
* DES3DES Mod 480a2000 - 480a2fff
|
| 2890 |
* DES3DES L4 480a3000 - 480a3fff
|
| 2891 |
* SHA1MD5 Mod 480a4000 - 480a4fff
|
| 2892 |
* SHA1MD5 L4 480a5000 - 480a5fff
|
| 2893 |
* AES Mod 480a6000 - 480a6fff
|
| 2894 |
* AES L4 480a7000 - 480a7fff
|
| 2895 |
* PKA Mod 480a8000 - 480a9fff
|
| 2896 |
* PKA L4 480aa000 - 480aafff
|
| 2897 |
* MG Mod 480b0000 - 480b0fff
|
| 2898 |
* MG L4 480b1000 - 480b1fff
|
| 2899 |
* HDQ/1-wire Mod 480b2000 - 480b2fff
|
| 2900 |
* HDQ/1-wire L4 480b3000 - 480b3fff
|
| 2901 |
* MPU interrupt 480fe000 - 480fefff
|
| 2902 |
* STI channel base 54000000 - 5400ffff
|
| 2903 |
* IVA RAM 5c000000 - 5c01ffff
|
| 2904 |
* IVA ROM 5c020000 - 5c027fff
|
| 2905 |
* IMG_BUF_A 5c040000 - 5c040fff
|
| 2906 |
* IMG_BUF_B 5c042000 - 5c042fff
|
| 2907 |
* VLCDS 5c048000 - 5c0487ff
|
| 2908 |
* IMX_COEF 5c049000 - 5c04afff
|
| 2909 |
* IMX_CMD 5c051000 - 5c051fff
|
| 2910 |
* VLCDQ 5c053000 - 5c0533ff
|
| 2911 |
* VLCDH 5c054000 - 5c054fff
|
| 2912 |
* SEQ_CMD 5c055000 - 5c055fff
|
| 2913 |
* IMX_REG 5c056000 - 5c0560ff
|
| 2914 |
* VLCD_REG 5c056100 - 5c0561ff
|
| 2915 |
* SEQ_REG 5c056200 - 5c0562ff
|
| 2916 |
* IMG_BUF_REG 5c056300 - 5c0563ff
|
| 2917 |
* SEQIRQ_REG 5c056400 - 5c0564ff
|
| 2918 |
* OCP_REG 5c060000 - 5c060fff
|
| 2919 |
* SYSC_REG 5c070000 - 5c070fff
|
| 2920 |
* MMU_REG 5d000000 - 5d000fff
|
| 2921 |
* sDMA R 68000400 - 680005ff
|
| 2922 |
* sDMA W 68000600 - 680007ff
|
| 2923 |
* Display Control 68000800 - 680009ff
|
| 2924 |
* DSP subsystem 68000a00 - 68000bff
|
| 2925 |
* MPU subsystem 68000c00 - 68000dff
|
| 2926 |
* IVA subsystem 68001000 - 680011ff
|
| 2927 |
* USB 68001200 - 680013ff
|
| 2928 |
* Camera 68001400 - 680015ff
|
| 2929 |
* VLYNQ (firewall) 68001800 - 68001bff
|
| 2930 |
* VLYNQ 68001e00 - 68001fff
|
| 2931 |
* SSI 68002000 - 680021ff
|
| 2932 |
* L4 68002400 - 680025ff
|
| 2933 |
* DSP (firewall) 68002800 - 68002bff
|
| 2934 |
* DSP subsystem 68002e00 - 68002fff
|
| 2935 |
* IVA (firewall) 68003000 - 680033ff
|
| 2936 |
* IVA 68003600 - 680037ff
|
| 2937 |
* GFX 68003a00 - 68003bff
|
| 2938 |
* CMDWR emulation 68003c00 - 68003dff
|
| 2939 |
* SMS 68004000 - 680041ff
|
| 2940 |
* OCM 68004200 - 680043ff
|
| 2941 |
* GPMC 68004400 - 680045ff
|
| 2942 |
* RAM (firewall) 68005000 - 680053ff
|
| 2943 |
* RAM (err login) 68005400 - 680057ff
|
| 2944 |
* ROM (firewall) 68005800 - 68005bff
|
| 2945 |
* ROM (err login) 68005c00 - 68005fff
|
| 2946 |
* GPMC (firewall) 68006000 - 680063ff
|
| 2947 |
* GPMC (err login) 68006400 - 680067ff
|
| 2948 |
* SMS (err login) 68006c00 - 68006fff
|
| 2949 |
* SMS registers 68008000 - 68008fff
|
| 2950 |
* SDRC registers 68009000 - 68009fff
|
| 2951 |
* GPMC registers 6800a000 6800afff
|
| 2952 |
*/
|
| 2953 |
|
| 2954 |
qemu_register_reset(omap2_mpu_reset, s); |
| 2955 |
|
| 2956 |
return s;
|
| 2957 |
} |