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tcg-hppa: Constrain immediate inputs to and_i32, or_i32, andc_i32.
Define "M" constraint for and_mask_p and "O" constraint for or_mask_p.Assume that inputs are correct in tcg_out_ori and tcg_out_andi.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-hppa: Fix GUEST_BASE initialization in prologue.
Load from the guest_base variable rather than embed a constant.Always reserve TCG_GUEST_BASE_REG if guest base support enabled.
tcg-hppa: Fix softmmu loads and stores.
Along the tlb hit path, we were modifying the variables holding the inputregister numbers, which lead to incorrect expansion of the tlb miss path.Fix this by extracting the tlb hit path to separate functions with their...
tcg-hppa: Schedule the address masking after the TLB load.
Issue the tlb load as early as possible and perform the addressmasking while the load is completing.
tcg-hppa: Fix branch offset during retranslation.
Branch offsets should only be overwritten during relocation,to support partial retranslation.
tcg-hppa: Don't try to calls to non-constant addresses.
PA-RISC uses procedure descriptors. We'd need to emit a call tothe millicode routine $$dyncall. However, this situation doesn'tactually arise, since we always have the descriptor available atTCG code generation time....
tcg-hppa: Fix in/out register overlap in add2/sub2.
Handle the output log part overlapping the input high parts.Also, improve sub2 to handle some constants the second input low part.
tcg-hppa: Finish the port.
Delete inline functions from tcg-target.h that don't need to be there,move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE supportsimilar to ppc64, with the value stored in a register. Add missing...
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
Suppress some variants of English in comments
Replace surpress, supress by suppress.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add some missing static and const qualifiers, reg_names only used if NDEBUG set
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
HPPA (PA-RISC) host support
(Stuart Brady)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162