Revision 2d5f20b5 target-i386/cpu.h
| b/target-i386/cpu.h | ||
|---|---|---|
| 438 | 438 |
#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ |
| 439 | 439 |
|
| 440 | 440 |
#define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ |
| 441 |
#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
|
|
| 441 |
#define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
|
| 442 | 442 |
#define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
| 443 | 443 |
|
| 444 |
#define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */ |
|
| 445 |
#define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */ |
|
| 446 |
#define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */ |
|
| 447 |
|
|
| 444 | 448 |
#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ |
| 445 | 449 |
#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ |
| 446 | 450 |
|
| ... | ... | |
| 730 | 734 |
uint32_t cpuid_ext3_features; |
| 731 | 735 |
uint32_t cpuid_apic_id; |
| 732 | 736 |
int cpuid_vendor_override; |
| 737 |
/* Store the results of Centaur's CPUID instructions */ |
|
| 738 |
uint32_t cpuid_xlevel2; |
|
| 739 |
uint32_t cpuid_ext4_features; |
|
| 733 | 740 |
|
| 734 | 741 |
/* MTRRs */ |
| 735 | 742 |
uint64_t mtrr_fixed[11]; |
Also available in: Unified diff