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target-alpha: Merge HW_REI and HW_RET implementations.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-alpha: Rationalize internal processor registers.
Delete all the code that tried to emulate the real IPRs of someunnamed CPU. Replace those with just 3 slots that we can use tocommunicate trap information between the helper functions thatsignal exceptions and the OS trap handler....
target-alpha: Fix translation of PALmode memory insns.
All of the "raw" memory accesses should be "phys" instead. Fixsome confusion about argument ordering of the store routines.Fix the implementation of store-conditional.
Delete the "alt-mode" helpers. Because we only implement two...
target-alpha: Implement cpys{, n, e} inline.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-alpha: Implement rs/rc properly.
This is a per-cpu flag; there's no need for a spinlock of any kind.
We were also failing to manipulate the flag with $31 as a target regand failing to clear the flag on execution of a return-from-interruptinstruction....
target-alpha: Implement cvtlq inline.
It's a simple shift and mask sequence.
target-alpha: Implement cvtql inline.
It's a simple mask and shift sequence.Also, fix a typo in the actual masks used.
target-alpha: Add flags markups to helpers.h.
Almost all alpha helpers are at least TCG_CALL_CONSTand a fair few are also TCG_CALL_PURE.
target-alpha: Implement IEEE FP qualifiers.
IEEE FP instructions are split up so that the rounding modecoming from the instruction and exceptions (both masking anddelivery) are handled external to the base FP operation.FP exceptions are properly raised for non-finite inputs to...
target-alpha: Implement fp branch/cmov inline.
The old fcmov implementation had a typo:- tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);which moved the condition, not the second source, to the destination.
But it's also easy to implement the simplified fp comparison inline....
target-alpha: Expand ins*l inline.
Similar in difficulty to ext*l, already expanded.
target-alpha: Expand msk*l inline.
target-alpha: Expand msk*h inline.
target-alpha: Expand ins*h inline.
target-alpha: Implement missing MVI instructions.
target-alpha: Remove bogus DO_TB_FLUSH code from translator.
target-alpha: remove amask helper
The direct use of helper_amask in translate.c was bogus (as env is notassigned). Directly code amask in tcg and remove the helper.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: remove helper_load_implver
There is no need to use an helper. Directly load the value with tcg code.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7074 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert palcode ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert FP ops to TCG
- Convert FP ops to TCG- Fix S format- Implement F and G formats (untested)- Fix MF_FPCR an MT_FPCR- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT- Fix CPYSN, CPYSE
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert remaining arith3 functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: switch a few helpers to TCG
Switch a few helpers to TCG and implement RC and RS instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert byte manipulation instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert arith2 instructions to TCG
Replace gen_arith2 generic macro and dyngon ops by instruction specificoptimized TCG code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: fix helper.h
the content of target-alpha/helper.h is duplicated twice
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5212 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: add target-alpha/helper.h (missing from commit r5150)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5161 c046a42c-6fe2-441c-8c8c-71466251a162