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1
/*
2
 *  i386 translation
3
 *
4
 *  Copyright (c) 2003 Fabrice Bellard
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
19
#include <stdarg.h>
20
#include <stdlib.h>
21
#include <stdio.h>
22
#include <string.h>
23
#include <inttypes.h>
24
#include <signal.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
28
#include "disas.h"
29
#include "tcg-op.h"
30

    
31
#include "helper.h"
32
#define GEN_HELPER 1
33
#include "helper.h"
34

    
35
#define PREFIX_REPZ   0x01
36
#define PREFIX_REPNZ  0x02
37
#define PREFIX_LOCK   0x04
38
#define PREFIX_DATA   0x08
39
#define PREFIX_ADR    0x10
40

    
41
#ifdef TARGET_X86_64
42
#define X86_64_ONLY(x) x
43
#define X86_64_DEF(...)  __VA_ARGS__
44
#define CODE64(s) ((s)->code64)
45
#define REX_X(s) ((s)->rex_x)
46
#define REX_B(s) ((s)->rex_b)
47
/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48
#if 1
49
#define BUGGY_64(x) NULL
50
#endif
51
#else
52
#define X86_64_ONLY(x) NULL
53
#define X86_64_DEF(...)
54
#define CODE64(s) 0
55
#define REX_X(s) 0
56
#define REX_B(s) 0
57
#endif
58

    
59
//#define MACRO_TEST   1
60

    
61
/* global register indexes */
62
static TCGv_ptr cpu_env;
63
static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
64
static TCGv_i32 cpu_cc_op;
65
static TCGv cpu_regs[CPU_NB_REGS];
66
/* local temps */
67
static TCGv cpu_T[2], cpu_T3;
68
/* local register indexes (only used inside old micro ops) */
69
static TCGv cpu_tmp0, cpu_tmp4;
70
static TCGv_ptr cpu_ptr0, cpu_ptr1;
71
static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
72
static TCGv_i64 cpu_tmp1_i64;
73
static TCGv cpu_tmp5;
74

    
75
#include "gen-icount.h"
76

    
77
#ifdef TARGET_X86_64
78
static int x86_64_hregs;
79
#endif
80

    
81
typedef struct DisasContext {
82
    /* current insn context */
83
    int override; /* -1 if no override */
84
    int prefix;
85
    int aflag, dflag;
86
    target_ulong pc; /* pc = eip + cs_base */
87
    int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
88
                   static state change (stop translation) */
89
    /* current block context */
90
    target_ulong cs_base; /* base of CS segment */
91
    int pe;     /* protected mode */
92
    int code32; /* 32 bit code segment */
93
#ifdef TARGET_X86_64
94
    int lma;    /* long mode active */
95
    int code64; /* 64 bit code segment */
96
    int rex_x, rex_b;
97
#endif
98
    int ss32;   /* 32 bit stack segment */
99
    int cc_op;  /* current CC operation */
100
    int addseg; /* non zero if either DS/ES/SS have a non zero base */
101
    int f_st;   /* currently unused */
102
    int vm86;   /* vm86 mode */
103
    int cpl;
104
    int iopl;
105
    int tf;     /* TF cpu flag */
106
    int singlestep_enabled; /* "hardware" single step enabled */
107
    int jmp_opt; /* use direct block chaining for direct jumps */
108
    int mem_index; /* select memory access functions */
109
    uint64_t flags; /* all execution flags */
110
    struct TranslationBlock *tb;
111
    int popl_esp_hack; /* for correct popl with esp base handling */
112
    int rip_offset; /* only used in x86_64, but left for simplicity */
113
    int cpuid_features;
114
    int cpuid_ext_features;
115
    int cpuid_ext2_features;
116
    int cpuid_ext3_features;
117
} DisasContext;
118

    
119
static void gen_eob(DisasContext *s);
120
static void gen_jmp(DisasContext *s, target_ulong eip);
121
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
122

    
123
/* i386 arith/logic operations */
124
enum {
125
    OP_ADDL,
126
    OP_ORL,
127
    OP_ADCL,
128
    OP_SBBL,
129
    OP_ANDL,
130
    OP_SUBL,
131
    OP_XORL,
132
    OP_CMPL,
133
};
134

    
135
/* i386 shift ops */
136
enum {
137
    OP_ROL,
138
    OP_ROR,
139
    OP_RCL,
140
    OP_RCR,
141
    OP_SHL,
142
    OP_SHR,
143
    OP_SHL1, /* undocumented */
144
    OP_SAR = 7,
145
};
146

    
147
enum {
148
    JCC_O,
149
    JCC_B,
150
    JCC_Z,
151
    JCC_BE,
152
    JCC_S,
153
    JCC_P,
154
    JCC_L,
155
    JCC_LE,
156
};
157

    
158
/* operand size */
159
enum {
160
    OT_BYTE = 0,
161
    OT_WORD,
162
    OT_LONG,
163
    OT_QUAD,
164
};
165

    
166
enum {
167
    /* I386 int registers */
168
    OR_EAX,   /* MUST be even numbered */
169
    OR_ECX,
170
    OR_EDX,
171
    OR_EBX,
172
    OR_ESP,
173
    OR_EBP,
174
    OR_ESI,
175
    OR_EDI,
176

    
177
    OR_TMP0 = 16,    /* temporary operand register */
178
    OR_TMP1,
179
    OR_A0, /* temporary register used when doing address evaluation */
180
};
181

    
182
static inline void gen_op_movl_T0_0(void)
183
{
184
    tcg_gen_movi_tl(cpu_T[0], 0);
185
}
186

    
187
static inline void gen_op_movl_T0_im(int32_t val)
188
{
189
    tcg_gen_movi_tl(cpu_T[0], val);
190
}
191

    
192
static inline void gen_op_movl_T0_imu(uint32_t val)
193
{
194
    tcg_gen_movi_tl(cpu_T[0], val);
195
}
196

    
197
static inline void gen_op_movl_T1_im(int32_t val)
198
{
199
    tcg_gen_movi_tl(cpu_T[1], val);
200
}
201

    
202
static inline void gen_op_movl_T1_imu(uint32_t val)
203
{
204
    tcg_gen_movi_tl(cpu_T[1], val);
205
}
206

    
207
static inline void gen_op_movl_A0_im(uint32_t val)
208
{
209
    tcg_gen_movi_tl(cpu_A0, val);
210
}
211

    
212
#ifdef TARGET_X86_64
213
static inline void gen_op_movq_A0_im(int64_t val)
214
{
215
    tcg_gen_movi_tl(cpu_A0, val);
216
}
217
#endif
218

    
219
static inline void gen_movtl_T0_im(target_ulong val)
220
{
221
    tcg_gen_movi_tl(cpu_T[0], val);
222
}
223

    
224
static inline void gen_movtl_T1_im(target_ulong val)
225
{
226
    tcg_gen_movi_tl(cpu_T[1], val);
227
}
228

    
229
static inline void gen_op_andl_T0_ffff(void)
230
{
231
    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
232
}
233

    
234
static inline void gen_op_andl_T0_im(uint32_t val)
235
{
236
    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
237
}
238

    
239
static inline void gen_op_movl_T0_T1(void)
240
{
241
    tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
242
}
243

    
244
static inline void gen_op_andl_A0_ffff(void)
245
{
246
    tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
247
}
248

    
249
#ifdef TARGET_X86_64
250

    
251
#define NB_OP_SIZES 4
252

    
253
#else /* !TARGET_X86_64 */
254

    
255
#define NB_OP_SIZES 3
256

    
257
#endif /* !TARGET_X86_64 */
258

    
259
#if defined(HOST_WORDS_BIGENDIAN)
260
#define REG_B_OFFSET (sizeof(target_ulong) - 1)
261
#define REG_H_OFFSET (sizeof(target_ulong) - 2)
262
#define REG_W_OFFSET (sizeof(target_ulong) - 2)
263
#define REG_L_OFFSET (sizeof(target_ulong) - 4)
264
#define REG_LH_OFFSET (sizeof(target_ulong) - 8)
265
#else
266
#define REG_B_OFFSET 0
267
#define REG_H_OFFSET 1
268
#define REG_W_OFFSET 0
269
#define REG_L_OFFSET 0
270
#define REG_LH_OFFSET 4
271
#endif
272

    
273
static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
274
{
275
    TCGv tmp;
276

    
277
    switch(ot) {
278
    case OT_BYTE:
279
        tmp = tcg_temp_new();
280
        tcg_gen_ext8u_tl(tmp, t0);
281
        if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
282
            tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff);
283
            tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
284
        } else {
285
            tcg_gen_shli_tl(tmp, tmp, 8);
286
            tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00);
287
            tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp);
288
        }
289
        tcg_temp_free(tmp);
290
        break;
291
    case OT_WORD:
292
        tmp = tcg_temp_new();
293
        tcg_gen_ext16u_tl(tmp, t0);
294
        tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
295
        tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
296
        tcg_temp_free(tmp);
297
        break;
298
    default: /* XXX this shouldn't be reached;  abort? */
299
    case OT_LONG:
300
        /* For x86_64, this sets the higher half of register to zero.
301
           For i386, this is equivalent to a mov. */
302
        tcg_gen_ext32u_tl(cpu_regs[reg], t0);
303
        break;
304
#ifdef TARGET_X86_64
305
    case OT_QUAD:
306
        tcg_gen_mov_tl(cpu_regs[reg], t0);
307
        break;
308
#endif
309
    }
310
}
311

    
312
static inline void gen_op_mov_reg_T0(int ot, int reg)
313
{
314
    gen_op_mov_reg_v(ot, reg, cpu_T[0]);
315
}
316

    
317
static inline void gen_op_mov_reg_T1(int ot, int reg)
318
{
319
    gen_op_mov_reg_v(ot, reg, cpu_T[1]);
320
}
321

    
322
static inline void gen_op_mov_reg_A0(int size, int reg)
323
{
324
    TCGv tmp;
325

    
326
    switch(size) {
327
    case 0:
328
        tmp = tcg_temp_new();
329
        tcg_gen_ext16u_tl(tmp, cpu_A0);
330
        tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
331
        tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
332
        tcg_temp_free(tmp);
333
        break;
334
    default: /* XXX this shouldn't be reached;  abort? */
335
    case 1:
336
        /* For x86_64, this sets the higher half of register to zero.
337
           For i386, this is equivalent to a mov. */
338
        tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
339
        break;
340
#ifdef TARGET_X86_64
341
    case 2:
342
        tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
343
        break;
344
#endif
345
    }
346
}
347

    
348
static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
349
{
350
    switch(ot) {
351
    case OT_BYTE:
352
        if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
353
            goto std_case;
354
        } else {
355
            tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
356
            tcg_gen_ext8u_tl(t0, t0);
357
        }
358
        break;
359
    default:
360
    std_case:
361
        tcg_gen_mov_tl(t0, cpu_regs[reg]);
362
        break;
363
    }
364
}
365

    
366
static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
367
{
368
    gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
369
}
370

    
371
static inline void gen_op_movl_A0_reg(int reg)
372
{
373
    tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
374
}
375

    
376
static inline void gen_op_addl_A0_im(int32_t val)
377
{
378
    tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
379
#ifdef TARGET_X86_64
380
    tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
381
#endif
382
}
383

    
384
#ifdef TARGET_X86_64
385
static inline void gen_op_addq_A0_im(int64_t val)
386
{
387
    tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
388
}
389
#endif
390
    
391
static void gen_add_A0_im(DisasContext *s, int val)
392
{
393
#ifdef TARGET_X86_64
394
    if (CODE64(s))
395
        gen_op_addq_A0_im(val);
396
    else
397
#endif
398
        gen_op_addl_A0_im(val);
399
}
400

    
401
static inline void gen_op_addl_T0_T1(void)
402
{
403
    tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
404
}
405

    
406
static inline void gen_op_jmp_T0(void)
407
{
408
    tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
409
}
410

    
411
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
412
{
413
    switch(size) {
414
    case 0:
415
        tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
416
        tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
417
        tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
418
        tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
419
        break;
420
    case 1:
421
        tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
422
        /* For x86_64, this sets the higher half of register to zero.
423
           For i386, this is equivalent to a nop. */
424
        tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
425
        tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
426
        break;
427
#ifdef TARGET_X86_64
428
    case 2:
429
        tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
430
        break;
431
#endif
432
    }
433
}
434

    
435
static inline void gen_op_add_reg_T0(int size, int reg)
436
{
437
    switch(size) {
438
    case 0:
439
        tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
440
        tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
441
        tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
442
        tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
443
        break;
444
    case 1:
445
        tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
446
        /* For x86_64, this sets the higher half of register to zero.
447
           For i386, this is equivalent to a nop. */
448
        tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
449
        tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
450
        break;
451
#ifdef TARGET_X86_64
452
    case 2:
453
        tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
454
        break;
455
#endif
456
    }
457
}
458

    
459
static inline void gen_op_set_cc_op(int32_t val)
460
{
461
    tcg_gen_movi_i32(cpu_cc_op, val);
462
}
463

    
464
static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
465
{
466
    tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
467
    if (shift != 0)
468
        tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
469
    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
470
    /* For x86_64, this sets the higher half of register to zero.
471
       For i386, this is equivalent to a nop. */
472
    tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
473
}
474

    
475
static inline void gen_op_movl_A0_seg(int reg)
476
{
477
    tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
478
}
479

    
480
static inline void gen_op_addl_A0_seg(int reg)
481
{
482
    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
483
    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
484
#ifdef TARGET_X86_64
485
    tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
486
#endif
487
}
488

    
489
#ifdef TARGET_X86_64
490
static inline void gen_op_movq_A0_seg(int reg)
491
{
492
    tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
493
}
494

    
495
static inline void gen_op_addq_A0_seg(int reg)
496
{
497
    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
498
    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
499
}
500

    
501
static inline void gen_op_movq_A0_reg(int reg)
502
{
503
    tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
504
}
505

    
506
static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
507
{
508
    tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
509
    if (shift != 0)
510
        tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
511
    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
512
}
513
#endif
514

    
515
static inline void gen_op_lds_T0_A0(int idx)
516
{
517
    int mem_index = (idx >> 2) - 1;
518
    switch(idx & 3) {
519
    case 0:
520
        tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
521
        break;
522
    case 1:
523
        tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
524
        break;
525
    default:
526
    case 2:
527
        tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
528
        break;
529
    }
530
}
531

    
532
static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
533
{
534
    int mem_index = (idx >> 2) - 1;
535
    switch(idx & 3) {
536
    case 0:
537
        tcg_gen_qemu_ld8u(t0, a0, mem_index);
538
        break;
539
    case 1:
540
        tcg_gen_qemu_ld16u(t0, a0, mem_index);
541
        break;
542
    case 2:
543
        tcg_gen_qemu_ld32u(t0, a0, mem_index);
544
        break;
545
    default:
546
    case 3:
547
        /* Should never happen on 32-bit targets.  */
548
#ifdef TARGET_X86_64
549
        tcg_gen_qemu_ld64(t0, a0, mem_index);
550
#endif
551
        break;
552
    }
553
}
554

    
555
/* XXX: always use ldu or lds */
556
static inline void gen_op_ld_T0_A0(int idx)
557
{
558
    gen_op_ld_v(idx, cpu_T[0], cpu_A0);
559
}
560

    
561
static inline void gen_op_ldu_T0_A0(int idx)
562
{
563
    gen_op_ld_v(idx, cpu_T[0], cpu_A0);
564
}
565

    
566
static inline void gen_op_ld_T1_A0(int idx)
567
{
568
    gen_op_ld_v(idx, cpu_T[1], cpu_A0);
569
}
570

    
571
static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
572
{
573
    int mem_index = (idx >> 2) - 1;
574
    switch(idx & 3) {
575
    case 0:
576
        tcg_gen_qemu_st8(t0, a0, mem_index);
577
        break;
578
    case 1:
579
        tcg_gen_qemu_st16(t0, a0, mem_index);
580
        break;
581
    case 2:
582
        tcg_gen_qemu_st32(t0, a0, mem_index);
583
        break;
584
    default:
585
    case 3:
586
        /* Should never happen on 32-bit targets.  */
587
#ifdef TARGET_X86_64
588
        tcg_gen_qemu_st64(t0, a0, mem_index);
589
#endif
590
        break;
591
    }
592
}
593

    
594
static inline void gen_op_st_T0_A0(int idx)
595
{
596
    gen_op_st_v(idx, cpu_T[0], cpu_A0);
597
}
598

    
599
static inline void gen_op_st_T1_A0(int idx)
600
{
601
    gen_op_st_v(idx, cpu_T[1], cpu_A0);
602
}
603

    
604
static inline void gen_jmp_im(target_ulong pc)
605
{
606
    tcg_gen_movi_tl(cpu_tmp0, pc);
607
    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
608
}
609

    
610
static inline void gen_string_movl_A0_ESI(DisasContext *s)
611
{
612
    int override;
613

    
614
    override = s->override;
615
#ifdef TARGET_X86_64
616
    if (s->aflag == 2) {
617
        if (override >= 0) {
618
            gen_op_movq_A0_seg(override);
619
            gen_op_addq_A0_reg_sN(0, R_ESI);
620
        } else {
621
            gen_op_movq_A0_reg(R_ESI);
622
        }
623
    } else
624
#endif
625
    if (s->aflag) {
626
        /* 32 bit address */
627
        if (s->addseg && override < 0)
628
            override = R_DS;
629
        if (override >= 0) {
630
            gen_op_movl_A0_seg(override);
631
            gen_op_addl_A0_reg_sN(0, R_ESI);
632
        } else {
633
            gen_op_movl_A0_reg(R_ESI);
634
        }
635
    } else {
636
        /* 16 address, always override */
637
        if (override < 0)
638
            override = R_DS;
639
        gen_op_movl_A0_reg(R_ESI);
640
        gen_op_andl_A0_ffff();
641
        gen_op_addl_A0_seg(override);
642
    }
643
}
644

    
645
static inline void gen_string_movl_A0_EDI(DisasContext *s)
646
{
647
#ifdef TARGET_X86_64
648
    if (s->aflag == 2) {
649
        gen_op_movq_A0_reg(R_EDI);
650
    } else
651
#endif
652
    if (s->aflag) {
653
        if (s->addseg) {
654
            gen_op_movl_A0_seg(R_ES);
655
            gen_op_addl_A0_reg_sN(0, R_EDI);
656
        } else {
657
            gen_op_movl_A0_reg(R_EDI);
658
        }
659
    } else {
660
        gen_op_movl_A0_reg(R_EDI);
661
        gen_op_andl_A0_ffff();
662
        gen_op_addl_A0_seg(R_ES);
663
    }
664
}
665

    
666
static inline void gen_op_movl_T0_Dshift(int ot) 
667
{
668
    tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
669
    tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
670
};
671

    
672
static void gen_extu(int ot, TCGv reg)
673
{
674
    switch(ot) {
675
    case OT_BYTE:
676
        tcg_gen_ext8u_tl(reg, reg);
677
        break;
678
    case OT_WORD:
679
        tcg_gen_ext16u_tl(reg, reg);
680
        break;
681
    case OT_LONG:
682
        tcg_gen_ext32u_tl(reg, reg);
683
        break;
684
    default:
685
        break;
686
    }
687
}
688

    
689
static void gen_exts(int ot, TCGv reg)
690
{
691
    switch(ot) {
692
    case OT_BYTE:
693
        tcg_gen_ext8s_tl(reg, reg);
694
        break;
695
    case OT_WORD:
696
        tcg_gen_ext16s_tl(reg, reg);
697
        break;
698
    case OT_LONG:
699
        tcg_gen_ext32s_tl(reg, reg);
700
        break;
701
    default:
702
        break;
703
    }
704
}
705

    
706
static inline void gen_op_jnz_ecx(int size, int label1)
707
{
708
    tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
709
    gen_extu(size + 1, cpu_tmp0);
710
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
711
}
712

    
713
static inline void gen_op_jz_ecx(int size, int label1)
714
{
715
    tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
716
    gen_extu(size + 1, cpu_tmp0);
717
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
718
}
719

    
720
static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
721
{
722
    switch (ot) {
723
    case 0: gen_helper_inb(v, n); break;
724
    case 1: gen_helper_inw(v, n); break;
725
    case 2: gen_helper_inl(v, n); break;
726
    }
727

    
728
}
729

    
730
static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
731
{
732
    switch (ot) {
733
    case 0: gen_helper_outb(v, n); break;
734
    case 1: gen_helper_outw(v, n); break;
735
    case 2: gen_helper_outl(v, n); break;
736
    }
737

    
738
}
739

    
740
static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
741
                         uint32_t svm_flags)
742
{
743
    int state_saved;
744
    target_ulong next_eip;
745

    
746
    state_saved = 0;
747
    if (s->pe && (s->cpl > s->iopl || s->vm86)) {
748
        if (s->cc_op != CC_OP_DYNAMIC)
749
            gen_op_set_cc_op(s->cc_op);
750
        gen_jmp_im(cur_eip);
751
        state_saved = 1;
752
        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
753
        switch (ot) {
754
        case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
755
        case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
756
        case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
757
        }
758
    }
759
    if(s->flags & HF_SVMI_MASK) {
760
        if (!state_saved) {
761
            if (s->cc_op != CC_OP_DYNAMIC)
762
                gen_op_set_cc_op(s->cc_op);
763
            gen_jmp_im(cur_eip);
764
            state_saved = 1;
765
        }
766
        svm_flags |= (1 << (4 + ot));
767
        next_eip = s->pc - s->cs_base;
768
        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
769
        gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
770
                                tcg_const_i32(next_eip - cur_eip));
771
    }
772
}
773

    
774
static inline void gen_movs(DisasContext *s, int ot)
775
{
776
    gen_string_movl_A0_ESI(s);
777
    gen_op_ld_T0_A0(ot + s->mem_index);
778
    gen_string_movl_A0_EDI(s);
779
    gen_op_st_T0_A0(ot + s->mem_index);
780
    gen_op_movl_T0_Dshift(ot);
781
    gen_op_add_reg_T0(s->aflag, R_ESI);
782
    gen_op_add_reg_T0(s->aflag, R_EDI);
783
}
784

    
785
static inline void gen_update_cc_op(DisasContext *s)
786
{
787
    if (s->cc_op != CC_OP_DYNAMIC) {
788
        gen_op_set_cc_op(s->cc_op);
789
        s->cc_op = CC_OP_DYNAMIC;
790
    }
791
}
792

    
793
static void gen_op_update1_cc(void)
794
{
795
    tcg_gen_discard_tl(cpu_cc_src);
796
    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
797
}
798

    
799
static void gen_op_update2_cc(void)
800
{
801
    tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
802
    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
803
}
804

    
805
static inline void gen_op_cmpl_T0_T1_cc(void)
806
{
807
    tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
808
    tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
809
}
810

    
811
static inline void gen_op_testl_T0_T1_cc(void)
812
{
813
    tcg_gen_discard_tl(cpu_cc_src);
814
    tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
815
}
816

    
817
static void gen_op_update_neg_cc(void)
818
{
819
    tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
820
    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
821
}
822

    
823
/* compute eflags.C to reg */
824
static void gen_compute_eflags_c(TCGv reg)
825
{
826
    gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
827
    tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
828
}
829

    
830
/* compute all eflags to cc_src */
831
static void gen_compute_eflags(TCGv reg)
832
{
833
    gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
834
    tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
835
}
836

    
837
static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
838
{
839
    if (s->cc_op != CC_OP_DYNAMIC)
840
        gen_op_set_cc_op(s->cc_op);
841
    switch(jcc_op) {
842
    case JCC_O:
843
        gen_compute_eflags(cpu_T[0]);
844
        tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
845
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
846
        break;
847
    case JCC_B:
848
        gen_compute_eflags_c(cpu_T[0]);
849
        break;
850
    case JCC_Z:
851
        gen_compute_eflags(cpu_T[0]);
852
        tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
853
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
854
        break;
855
    case JCC_BE:
856
        gen_compute_eflags(cpu_tmp0);
857
        tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
858
        tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
859
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
860
        break;
861
    case JCC_S:
862
        gen_compute_eflags(cpu_T[0]);
863
        tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
864
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865
        break;
866
    case JCC_P:
867
        gen_compute_eflags(cpu_T[0]);
868
        tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
869
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
870
        break;
871
    case JCC_L:
872
        gen_compute_eflags(cpu_tmp0);
873
        tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
874
        tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
875
        tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
876
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
877
        break;
878
    default:
879
    case JCC_LE:
880
        gen_compute_eflags(cpu_tmp0);
881
        tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
882
        tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
883
        tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
884
        tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
885
        tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
886
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
887
        break;
888
    }
889
}
890

    
891
/* return true if setcc_slow is not needed (WARNING: must be kept in
892
   sync with gen_jcc1) */
893
static int is_fast_jcc_case(DisasContext *s, int b)
894
{
895
    int jcc_op;
896
    jcc_op = (b >> 1) & 7;
897
    switch(s->cc_op) {
898
        /* we optimize the cmp/jcc case */
899
    case CC_OP_SUBB:
900
    case CC_OP_SUBW:
901
    case CC_OP_SUBL:
902
    case CC_OP_SUBQ:
903
        if (jcc_op == JCC_O || jcc_op == JCC_P)
904
            goto slow_jcc;
905
        break;
906

    
907
        /* some jumps are easy to compute */
908
    case CC_OP_ADDB:
909
    case CC_OP_ADDW:
910
    case CC_OP_ADDL:
911
    case CC_OP_ADDQ:
912

    
913
    case CC_OP_LOGICB:
914
    case CC_OP_LOGICW:
915
    case CC_OP_LOGICL:
916
    case CC_OP_LOGICQ:
917

    
918
    case CC_OP_INCB:
919
    case CC_OP_INCW:
920
    case CC_OP_INCL:
921
    case CC_OP_INCQ:
922

    
923
    case CC_OP_DECB:
924
    case CC_OP_DECW:
925
    case CC_OP_DECL:
926
    case CC_OP_DECQ:
927

    
928
    case CC_OP_SHLB:
929
    case CC_OP_SHLW:
930
    case CC_OP_SHLL:
931
    case CC_OP_SHLQ:
932
        if (jcc_op != JCC_Z && jcc_op != JCC_S)
933
            goto slow_jcc;
934
        break;
935
    default:
936
    slow_jcc:
937
        return 0;
938
    }
939
    return 1;
940
}
941

    
942
/* generate a conditional jump to label 'l1' according to jump opcode
943
   value 'b'. In the fast case, T0 is guaranted not to be used. */
944
static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
945
{
946
    int inv, jcc_op, size, cond;
947
    TCGv t0;
948

    
949
    inv = b & 1;
950
    jcc_op = (b >> 1) & 7;
951

    
952
    switch(cc_op) {
953
        /* we optimize the cmp/jcc case */
954
    case CC_OP_SUBB:
955
    case CC_OP_SUBW:
956
    case CC_OP_SUBL:
957
    case CC_OP_SUBQ:
958
        
959
        size = cc_op - CC_OP_SUBB;
960
        switch(jcc_op) {
961
        case JCC_Z:
962
        fast_jcc_z:
963
            switch(size) {
964
            case 0:
965
                tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
966
                t0 = cpu_tmp0;
967
                break;
968
            case 1:
969
                tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
970
                t0 = cpu_tmp0;
971
                break;
972
#ifdef TARGET_X86_64
973
            case 2:
974
                tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
975
                t0 = cpu_tmp0;
976
                break;
977
#endif
978
            default:
979
                t0 = cpu_cc_dst;
980
                break;
981
            }
982
            tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
983
            break;
984
        case JCC_S:
985
        fast_jcc_s:
986
            switch(size) {
987
            case 0:
988
                tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
989
                tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 
990
                                   0, l1);
991
                break;
992
            case 1:
993
                tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
994
                tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 
995
                                   0, l1);
996
                break;
997
#ifdef TARGET_X86_64
998
            case 2:
999
                tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1000
                tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 
1001
                                   0, l1);
1002
                break;
1003
#endif
1004
            default:
1005
                tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, 
1006
                                   0, l1);
1007
                break;
1008
            }
1009
            break;
1010
            
1011
        case JCC_B:
1012
            cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1013
            goto fast_jcc_b;
1014
        case JCC_BE:
1015
            cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1016
        fast_jcc_b:
1017
            tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1018
            switch(size) {
1019
            case 0:
1020
                t0 = cpu_tmp0;
1021
                tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1022
                tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1023
                break;
1024
            case 1:
1025
                t0 = cpu_tmp0;
1026
                tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1027
                tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1028
                break;
1029
#ifdef TARGET_X86_64
1030
            case 2:
1031
                t0 = cpu_tmp0;
1032
                tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1033
                tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1034
                break;
1035
#endif
1036
            default:
1037
                t0 = cpu_cc_src;
1038
                break;
1039
            }
1040
            tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1041
            break;
1042
            
1043
        case JCC_L:
1044
            cond = inv ? TCG_COND_GE : TCG_COND_LT;
1045
            goto fast_jcc_l;
1046
        case JCC_LE:
1047
            cond = inv ? TCG_COND_GT : TCG_COND_LE;
1048
        fast_jcc_l:
1049
            tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1050
            switch(size) {
1051
            case 0:
1052
                t0 = cpu_tmp0;
1053
                tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1054
                tcg_gen_ext8s_tl(t0, cpu_cc_src);
1055
                break;
1056
            case 1:
1057
                t0 = cpu_tmp0;
1058
                tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1059
                tcg_gen_ext16s_tl(t0, cpu_cc_src);
1060
                break;
1061
#ifdef TARGET_X86_64
1062
            case 2:
1063
                t0 = cpu_tmp0;
1064
                tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1065
                tcg_gen_ext32s_tl(t0, cpu_cc_src);
1066
                break;
1067
#endif
1068
            default:
1069
                t0 = cpu_cc_src;
1070
                break;
1071
            }
1072
            tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1073
            break;
1074
            
1075
        default:
1076
            goto slow_jcc;
1077
        }
1078
        break;
1079
        
1080
        /* some jumps are easy to compute */
1081
    case CC_OP_ADDB:
1082
    case CC_OP_ADDW:
1083
    case CC_OP_ADDL:
1084
    case CC_OP_ADDQ:
1085
        
1086
    case CC_OP_ADCB:
1087
    case CC_OP_ADCW:
1088
    case CC_OP_ADCL:
1089
    case CC_OP_ADCQ:
1090
        
1091
    case CC_OP_SBBB:
1092
    case CC_OP_SBBW:
1093
    case CC_OP_SBBL:
1094
    case CC_OP_SBBQ:
1095
        
1096
    case CC_OP_LOGICB:
1097
    case CC_OP_LOGICW:
1098
    case CC_OP_LOGICL:
1099
    case CC_OP_LOGICQ:
1100
        
1101
    case CC_OP_INCB:
1102
    case CC_OP_INCW:
1103
    case CC_OP_INCL:
1104
    case CC_OP_INCQ:
1105
        
1106
    case CC_OP_DECB:
1107
    case CC_OP_DECW:
1108
    case CC_OP_DECL:
1109
    case CC_OP_DECQ:
1110
        
1111
    case CC_OP_SHLB:
1112
    case CC_OP_SHLW:
1113
    case CC_OP_SHLL:
1114
    case CC_OP_SHLQ:
1115
        
1116
    case CC_OP_SARB:
1117
    case CC_OP_SARW:
1118
    case CC_OP_SARL:
1119
    case CC_OP_SARQ:
1120
        switch(jcc_op) {
1121
        case JCC_Z:
1122
            size = (cc_op - CC_OP_ADDB) & 3;
1123
            goto fast_jcc_z;
1124
        case JCC_S:
1125
            size = (cc_op - CC_OP_ADDB) & 3;
1126
            goto fast_jcc_s;
1127
        default:
1128
            goto slow_jcc;
1129
        }
1130
        break;
1131
    default:
1132
    slow_jcc:
1133
        gen_setcc_slow_T0(s, jcc_op);
1134
        tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, 
1135
                           cpu_T[0], 0, l1);
1136
        break;
1137
    }
1138
}
1139

    
1140
/* XXX: does not work with gdbstub "ice" single step - not a
1141
   serious problem */
1142
static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1143
{
1144
    int l1, l2;
1145

    
1146
    l1 = gen_new_label();
1147
    l2 = gen_new_label();
1148
    gen_op_jnz_ecx(s->aflag, l1);
1149
    gen_set_label(l2);
1150
    gen_jmp_tb(s, next_eip, 1);
1151
    gen_set_label(l1);
1152
    return l2;
1153
}
1154

    
1155
static inline void gen_stos(DisasContext *s, int ot)
1156
{
1157
    gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1158
    gen_string_movl_A0_EDI(s);
1159
    gen_op_st_T0_A0(ot + s->mem_index);
1160
    gen_op_movl_T0_Dshift(ot);
1161
    gen_op_add_reg_T0(s->aflag, R_EDI);
1162
}
1163

    
1164
static inline void gen_lods(DisasContext *s, int ot)
1165
{
1166
    gen_string_movl_A0_ESI(s);
1167
    gen_op_ld_T0_A0(ot + s->mem_index);
1168
    gen_op_mov_reg_T0(ot, R_EAX);
1169
    gen_op_movl_T0_Dshift(ot);
1170
    gen_op_add_reg_T0(s->aflag, R_ESI);
1171
}
1172

    
1173
static inline void gen_scas(DisasContext *s, int ot)
1174
{
1175
    gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1176
    gen_string_movl_A0_EDI(s);
1177
    gen_op_ld_T1_A0(ot + s->mem_index);
1178
    gen_op_cmpl_T0_T1_cc();
1179
    gen_op_movl_T0_Dshift(ot);
1180
    gen_op_add_reg_T0(s->aflag, R_EDI);
1181
}
1182

    
1183
static inline void gen_cmps(DisasContext *s, int ot)
1184
{
1185
    gen_string_movl_A0_ESI(s);
1186
    gen_op_ld_T0_A0(ot + s->mem_index);
1187
    gen_string_movl_A0_EDI(s);
1188
    gen_op_ld_T1_A0(ot + s->mem_index);
1189
    gen_op_cmpl_T0_T1_cc();
1190
    gen_op_movl_T0_Dshift(ot);
1191
    gen_op_add_reg_T0(s->aflag, R_ESI);
1192
    gen_op_add_reg_T0(s->aflag, R_EDI);
1193
}
1194

    
1195
static inline void gen_ins(DisasContext *s, int ot)
1196
{
1197
    if (use_icount)
1198
        gen_io_start();
1199
    gen_string_movl_A0_EDI(s);
1200
    /* Note: we must do this dummy write first to be restartable in
1201
       case of page fault. */
1202
    gen_op_movl_T0_0();
1203
    gen_op_st_T0_A0(ot + s->mem_index);
1204
    gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1205
    tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1206
    tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1207
    gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1208
    gen_op_st_T0_A0(ot + s->mem_index);
1209
    gen_op_movl_T0_Dshift(ot);
1210
    gen_op_add_reg_T0(s->aflag, R_EDI);
1211
    if (use_icount)
1212
        gen_io_end();
1213
}
1214

    
1215
static inline void gen_outs(DisasContext *s, int ot)
1216
{
1217
    if (use_icount)
1218
        gen_io_start();
1219
    gen_string_movl_A0_ESI(s);
1220
    gen_op_ld_T0_A0(ot + s->mem_index);
1221

    
1222
    gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1223
    tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1224
    tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1225
    tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1226
    gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1227

    
1228
    gen_op_movl_T0_Dshift(ot);
1229
    gen_op_add_reg_T0(s->aflag, R_ESI);
1230
    if (use_icount)
1231
        gen_io_end();
1232
}
1233

    
1234
/* same method as Valgrind : we generate jumps to current or next
1235
   instruction */
1236
#define GEN_REPZ(op)                                                          \
1237
static inline void gen_repz_ ## op(DisasContext *s, int ot,                   \
1238
                                 target_ulong cur_eip, target_ulong next_eip) \
1239
{                                                                             \
1240
    int l2;\
1241
    gen_update_cc_op(s);                                                      \
1242
    l2 = gen_jz_ecx_string(s, next_eip);                                      \
1243
    gen_ ## op(s, ot);                                                        \
1244
    gen_op_add_reg_im(s->aflag, R_ECX, -1);                                   \
1245
    /* a loop would cause two single step exceptions if ECX = 1               \
1246
       before rep string_insn */                                              \
1247
    if (!s->jmp_opt)                                                          \
1248
        gen_op_jz_ecx(s->aflag, l2);                                          \
1249
    gen_jmp(s, cur_eip);                                                      \
1250
}
1251

    
1252
#define GEN_REPZ2(op)                                                         \
1253
static inline void gen_repz_ ## op(DisasContext *s, int ot,                   \
1254
                                   target_ulong cur_eip,                      \
1255
                                   target_ulong next_eip,                     \
1256
                                   int nz)                                    \
1257
{                                                                             \
1258
    int l2;\
1259
    gen_update_cc_op(s);                                                      \
1260
    l2 = gen_jz_ecx_string(s, next_eip);                                      \
1261
    gen_ ## op(s, ot);                                                        \
1262
    gen_op_add_reg_im(s->aflag, R_ECX, -1);                                   \
1263
    gen_op_set_cc_op(CC_OP_SUBB + ot);                                        \
1264
    gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2);                \
1265
    if (!s->jmp_opt)                                                          \
1266
        gen_op_jz_ecx(s->aflag, l2);                                          \
1267
    gen_jmp(s, cur_eip);                                                      \
1268
}
1269

    
1270
GEN_REPZ(movs)
1271
GEN_REPZ(stos)
1272
GEN_REPZ(lods)
1273
GEN_REPZ(ins)
1274
GEN_REPZ(outs)
1275
GEN_REPZ2(scas)
1276
GEN_REPZ2(cmps)
1277

    
1278
static void gen_helper_fp_arith_ST0_FT0(int op)
1279
{
1280
    switch (op) {
1281
    case 0: gen_helper_fadd_ST0_FT0(); break;
1282
    case 1: gen_helper_fmul_ST0_FT0(); break;
1283
    case 2: gen_helper_fcom_ST0_FT0(); break;
1284
    case 3: gen_helper_fcom_ST0_FT0(); break;
1285
    case 4: gen_helper_fsub_ST0_FT0(); break;
1286
    case 5: gen_helper_fsubr_ST0_FT0(); break;
1287
    case 6: gen_helper_fdiv_ST0_FT0(); break;
1288
    case 7: gen_helper_fdivr_ST0_FT0(); break;
1289
    }
1290
}
1291

    
1292
/* NOTE the exception in "r" op ordering */
1293
static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1294
{
1295
    TCGv_i32 tmp = tcg_const_i32(opreg);
1296
    switch (op) {
1297
    case 0: gen_helper_fadd_STN_ST0(tmp); break;
1298
    case 1: gen_helper_fmul_STN_ST0(tmp); break;
1299
    case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1300
    case 5: gen_helper_fsub_STN_ST0(tmp); break;
1301
    case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1302
    case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1303
    }
1304
}
1305

    
1306
/* if d == OR_TMP0, it means memory operand (address in A0) */
1307
static void gen_op(DisasContext *s1, int op, int ot, int d)
1308
{
1309
    if (d != OR_TMP0) {
1310
        gen_op_mov_TN_reg(ot, 0, d);
1311
    } else {
1312
        gen_op_ld_T0_A0(ot + s1->mem_index);
1313
    }
1314
    switch(op) {
1315
    case OP_ADCL:
1316
        if (s1->cc_op != CC_OP_DYNAMIC)
1317
            gen_op_set_cc_op(s1->cc_op);
1318
        gen_compute_eflags_c(cpu_tmp4);
1319
        tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1320
        tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1321
        if (d != OR_TMP0)
1322
            gen_op_mov_reg_T0(ot, d);
1323
        else
1324
            gen_op_st_T0_A0(ot + s1->mem_index);
1325
        tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1326
        tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1327
        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1328
        tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1329
        tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1330
        s1->cc_op = CC_OP_DYNAMIC;
1331
        break;
1332
    case OP_SBBL:
1333
        if (s1->cc_op != CC_OP_DYNAMIC)
1334
            gen_op_set_cc_op(s1->cc_op);
1335
        gen_compute_eflags_c(cpu_tmp4);
1336
        tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1337
        tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1338
        if (d != OR_TMP0)
1339
            gen_op_mov_reg_T0(ot, d);
1340
        else
1341
            gen_op_st_T0_A0(ot + s1->mem_index);
1342
        tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1343
        tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1344
        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1345
        tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1346
        tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1347
        s1->cc_op = CC_OP_DYNAMIC;
1348
        break;
1349
    case OP_ADDL:
1350
        gen_op_addl_T0_T1();
1351
        if (d != OR_TMP0)
1352
            gen_op_mov_reg_T0(ot, d);
1353
        else
1354
            gen_op_st_T0_A0(ot + s1->mem_index);
1355
        gen_op_update2_cc();
1356
        s1->cc_op = CC_OP_ADDB + ot;
1357
        break;
1358
    case OP_SUBL:
1359
        tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1360
        if (d != OR_TMP0)
1361
            gen_op_mov_reg_T0(ot, d);
1362
        else
1363
            gen_op_st_T0_A0(ot + s1->mem_index);
1364
        gen_op_update2_cc();
1365
        s1->cc_op = CC_OP_SUBB + ot;
1366
        break;
1367
    default:
1368
    case OP_ANDL:
1369
        tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1370
        if (d != OR_TMP0)
1371
            gen_op_mov_reg_T0(ot, d);
1372
        else
1373
            gen_op_st_T0_A0(ot + s1->mem_index);
1374
        gen_op_update1_cc();
1375
        s1->cc_op = CC_OP_LOGICB + ot;
1376
        break;
1377
    case OP_ORL:
1378
        tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1379
        if (d != OR_TMP0)
1380
            gen_op_mov_reg_T0(ot, d);
1381
        else
1382
            gen_op_st_T0_A0(ot + s1->mem_index);
1383
        gen_op_update1_cc();
1384
        s1->cc_op = CC_OP_LOGICB + ot;
1385
        break;
1386
    case OP_XORL:
1387
        tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1388
        if (d != OR_TMP0)
1389
            gen_op_mov_reg_T0(ot, d);
1390
        else
1391
            gen_op_st_T0_A0(ot + s1->mem_index);
1392
        gen_op_update1_cc();
1393
        s1->cc_op = CC_OP_LOGICB + ot;
1394
        break;
1395
    case OP_CMPL:
1396
        gen_op_cmpl_T0_T1_cc();
1397
        s1->cc_op = CC_OP_SUBB + ot;
1398
        break;
1399
    }
1400
}
1401

    
1402
/* if d == OR_TMP0, it means memory operand (address in A0) */
1403
static void gen_inc(DisasContext *s1, int ot, int d, int c)
1404
{
1405
    if (d != OR_TMP0)
1406
        gen_op_mov_TN_reg(ot, 0, d);
1407
    else
1408
        gen_op_ld_T0_A0(ot + s1->mem_index);
1409
    if (s1->cc_op != CC_OP_DYNAMIC)
1410
        gen_op_set_cc_op(s1->cc_op);
1411
    if (c > 0) {
1412
        tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1413
        s1->cc_op = CC_OP_INCB + ot;
1414
    } else {
1415
        tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1416
        s1->cc_op = CC_OP_DECB + ot;
1417
    }
1418
    if (d != OR_TMP0)
1419
        gen_op_mov_reg_T0(ot, d);
1420
    else
1421
        gen_op_st_T0_A0(ot + s1->mem_index);
1422
    gen_compute_eflags_c(cpu_cc_src);
1423
    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1424
}
1425

    
1426
static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, 
1427
                            int is_right, int is_arith)
1428
{
1429
    target_ulong mask;
1430
    int shift_label;
1431
    TCGv t0, t1;
1432

    
1433
    if (ot == OT_QUAD)
1434
        mask = 0x3f;
1435
    else
1436
        mask = 0x1f;
1437

    
1438
    /* load */
1439
    if (op1 == OR_TMP0)
1440
        gen_op_ld_T0_A0(ot + s->mem_index);
1441
    else
1442
        gen_op_mov_TN_reg(ot, 0, op1);
1443

    
1444
    tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1445

    
1446
    tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1447

    
1448
    if (is_right) {
1449
        if (is_arith) {
1450
            gen_exts(ot, cpu_T[0]);
1451
            tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1452
            tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1453
        } else {
1454
            gen_extu(ot, cpu_T[0]);
1455
            tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1456
            tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1457
        }
1458
    } else {
1459
        tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1460
        tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1461
    }
1462

    
1463
    /* store */
1464
    if (op1 == OR_TMP0)
1465
        gen_op_st_T0_A0(ot + s->mem_index);
1466
    else
1467
        gen_op_mov_reg_T0(ot, op1);
1468
        
1469
    /* update eflags if non zero shift */
1470
    if (s->cc_op != CC_OP_DYNAMIC)
1471
        gen_op_set_cc_op(s->cc_op);
1472

    
1473
    /* XXX: inefficient */
1474
    t0 = tcg_temp_local_new();
1475
    t1 = tcg_temp_local_new();
1476

    
1477
    tcg_gen_mov_tl(t0, cpu_T[0]);
1478
    tcg_gen_mov_tl(t1, cpu_T3);
1479

    
1480
    shift_label = gen_new_label();
1481
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1482

    
1483
    tcg_gen_mov_tl(cpu_cc_src, t1);
1484
    tcg_gen_mov_tl(cpu_cc_dst, t0);
1485
    if (is_right)
1486
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1487
    else
1488
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1489
        
1490
    gen_set_label(shift_label);
1491
    s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1492

    
1493
    tcg_temp_free(t0);
1494
    tcg_temp_free(t1);
1495
}
1496

    
1497
static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1498
                            int is_right, int is_arith)
1499
{
1500
    int mask;
1501
    
1502
    if (ot == OT_QUAD)
1503
        mask = 0x3f;
1504
    else
1505
        mask = 0x1f;
1506

    
1507
    /* load */
1508
    if (op1 == OR_TMP0)
1509
        gen_op_ld_T0_A0(ot + s->mem_index);
1510
    else
1511
        gen_op_mov_TN_reg(ot, 0, op1);
1512

    
1513
    op2 &= mask;
1514
    if (op2 != 0) {
1515
        if (is_right) {
1516
            if (is_arith) {
1517
                gen_exts(ot, cpu_T[0]);
1518
                tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1519
                tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1520
            } else {
1521
                gen_extu(ot, cpu_T[0]);
1522
                tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1523
                tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1524
            }
1525
        } else {
1526
            tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1527
            tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1528
        }
1529
    }
1530

    
1531
    /* store */
1532
    if (op1 == OR_TMP0)
1533
        gen_op_st_T0_A0(ot + s->mem_index);
1534
    else
1535
        gen_op_mov_reg_T0(ot, op1);
1536
        
1537
    /* update eflags if non zero shift */
1538
    if (op2 != 0) {
1539
        tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1540
        tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1541
        if (is_right)
1542
            s->cc_op = CC_OP_SARB + ot;
1543
        else
1544
            s->cc_op = CC_OP_SHLB + ot;
1545
    }
1546
}
1547

    
1548
static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1549
{
1550
    if (arg2 >= 0)
1551
        tcg_gen_shli_tl(ret, arg1, arg2);
1552
    else
1553
        tcg_gen_shri_tl(ret, arg1, -arg2);
1554
}
1555

    
1556
static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, 
1557
                          int is_right)
1558
{
1559
    target_ulong mask;
1560
    int label1, label2, data_bits;
1561
    TCGv t0, t1, t2, a0;
1562

    
1563
    /* XXX: inefficient, but we must use local temps */
1564
    t0 = tcg_temp_local_new();
1565
    t1 = tcg_temp_local_new();
1566
    t2 = tcg_temp_local_new();
1567
    a0 = tcg_temp_local_new();
1568

    
1569
    if (ot == OT_QUAD)
1570
        mask = 0x3f;
1571
    else
1572
        mask = 0x1f;
1573

    
1574
    /* load */
1575
    if (op1 == OR_TMP0) {
1576
        tcg_gen_mov_tl(a0, cpu_A0);
1577
        gen_op_ld_v(ot + s->mem_index, t0, a0);
1578
    } else {
1579
        gen_op_mov_v_reg(ot, t0, op1);
1580
    }
1581

    
1582
    tcg_gen_mov_tl(t1, cpu_T[1]);
1583

    
1584
    tcg_gen_andi_tl(t1, t1, mask);
1585

    
1586
    /* Must test zero case to avoid using undefined behaviour in TCG
1587
       shifts. */
1588
    label1 = gen_new_label();
1589
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1590
    
1591
    if (ot <= OT_WORD)
1592
        tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1593
    else
1594
        tcg_gen_mov_tl(cpu_tmp0, t1);
1595
    
1596
    gen_extu(ot, t0);
1597
    tcg_gen_mov_tl(t2, t0);
1598

    
1599
    data_bits = 8 << ot;
1600
    /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1601
       fix TCG definition) */
1602
    if (is_right) {
1603
        tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1604
        tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1605
        tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1606
    } else {
1607
        tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1608
        tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1609
        tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1610
    }
1611
    tcg_gen_or_tl(t0, t0, cpu_tmp4);
1612

    
1613
    gen_set_label(label1);
1614
    /* store */
1615
    if (op1 == OR_TMP0) {
1616
        gen_op_st_v(ot + s->mem_index, t0, a0);
1617
    } else {
1618
        gen_op_mov_reg_v(ot, op1, t0);
1619
    }
1620
    
1621
    /* update eflags */
1622
    if (s->cc_op != CC_OP_DYNAMIC)
1623
        gen_op_set_cc_op(s->cc_op);
1624

    
1625
    label2 = gen_new_label();
1626
    tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1627

    
1628
    gen_compute_eflags(cpu_cc_src);
1629
    tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1630
    tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1631
    tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1632
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1633
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1634
    if (is_right) {
1635
        tcg_gen_shri_tl(t0, t0, data_bits - 1);
1636
    }
1637
    tcg_gen_andi_tl(t0, t0, CC_C);
1638
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1639
    
1640
    tcg_gen_discard_tl(cpu_cc_dst);
1641
    tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1642
        
1643
    gen_set_label(label2);
1644
    s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1645

    
1646
    tcg_temp_free(t0);
1647
    tcg_temp_free(t1);
1648
    tcg_temp_free(t2);
1649
    tcg_temp_free(a0);
1650
}
1651

    
1652
static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1653
                          int is_right)
1654
{
1655
    int mask;
1656
    int data_bits;
1657
    TCGv t0, t1, a0;
1658

    
1659
    /* XXX: inefficient, but we must use local temps */
1660
    t0 = tcg_temp_local_new();
1661
    t1 = tcg_temp_local_new();
1662
    a0 = tcg_temp_local_new();
1663

    
1664
    if (ot == OT_QUAD)
1665
        mask = 0x3f;
1666
    else
1667
        mask = 0x1f;
1668

    
1669
    /* load */
1670
    if (op1 == OR_TMP0) {
1671
        tcg_gen_mov_tl(a0, cpu_A0);
1672
        gen_op_ld_v(ot + s->mem_index, t0, a0);
1673
    } else {
1674
        gen_op_mov_v_reg(ot, t0, op1);
1675
    }
1676

    
1677
    gen_extu(ot, t0);
1678
    tcg_gen_mov_tl(t1, t0);
1679

    
1680
    op2 &= mask;
1681
    data_bits = 8 << ot;
1682
    if (op2 != 0) {
1683
        int shift = op2 & ((1 << (3 + ot)) - 1);
1684
        if (is_right) {
1685
            tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1686
            tcg_gen_shli_tl(t0, t0, data_bits - shift);
1687
        }
1688
        else {
1689
            tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1690
            tcg_gen_shri_tl(t0, t0, data_bits - shift);
1691
        }
1692
        tcg_gen_or_tl(t0, t0, cpu_tmp4);
1693
    }
1694

    
1695
    /* store */
1696
    if (op1 == OR_TMP0) {
1697
        gen_op_st_v(ot + s->mem_index, t0, a0);
1698
    } else {
1699
        gen_op_mov_reg_v(ot, op1, t0);
1700
    }
1701

    
1702
    if (op2 != 0) {
1703
        /* update eflags */
1704
        if (s->cc_op != CC_OP_DYNAMIC)
1705
            gen_op_set_cc_op(s->cc_op);
1706

    
1707
        gen_compute_eflags(cpu_cc_src);
1708
        tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1709
        tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1710
        tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1711
        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1712
        tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1713
        if (is_right) {
1714
            tcg_gen_shri_tl(t0, t0, data_bits - 1);
1715
        }
1716
        tcg_gen_andi_tl(t0, t0, CC_C);
1717
        tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1718

    
1719
        tcg_gen_discard_tl(cpu_cc_dst);
1720
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1721
        s->cc_op = CC_OP_EFLAGS;
1722
    }
1723

    
1724
    tcg_temp_free(t0);
1725
    tcg_temp_free(t1);
1726
    tcg_temp_free(a0);
1727
}
1728

    
1729
/* XXX: add faster immediate = 1 case */
1730
static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, 
1731
                           int is_right)
1732
{
1733
    int label1;
1734

    
1735
    if (s->cc_op != CC_OP_DYNAMIC)
1736
        gen_op_set_cc_op(s->cc_op);
1737

    
1738
    /* load */
1739
    if (op1 == OR_TMP0)
1740
        gen_op_ld_T0_A0(ot + s->mem_index);
1741
    else
1742
        gen_op_mov_TN_reg(ot, 0, op1);
1743
    
1744
    if (is_right) {
1745
        switch (ot) {
1746
        case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1747
        case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1748
        case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1749
#ifdef TARGET_X86_64
1750
        case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1751
#endif
1752
        }
1753
    } else {
1754
        switch (ot) {
1755
        case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1756
        case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1757
        case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1758
#ifdef TARGET_X86_64
1759
        case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1760
#endif
1761
        }
1762
    }
1763
    /* store */
1764
    if (op1 == OR_TMP0)
1765
        gen_op_st_T0_A0(ot + s->mem_index);
1766
    else
1767
        gen_op_mov_reg_T0(ot, op1);
1768

    
1769
    /* update eflags */
1770
    label1 = gen_new_label();
1771
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1772

    
1773
    tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1774
    tcg_gen_discard_tl(cpu_cc_dst);
1775
    tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1776
        
1777
    gen_set_label(label1);
1778
    s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1779
}
1780

    
1781
/* XXX: add faster immediate case */
1782
static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, 
1783
                                int is_right)
1784
{
1785
    int label1, label2, data_bits;
1786
    target_ulong mask;
1787
    TCGv t0, t1, t2, a0;
1788

    
1789
    t0 = tcg_temp_local_new();
1790
    t1 = tcg_temp_local_new();
1791
    t2 = tcg_temp_local_new();
1792
    a0 = tcg_temp_local_new();
1793

    
1794
    if (ot == OT_QUAD)
1795
        mask = 0x3f;
1796
    else
1797
        mask = 0x1f;
1798

    
1799
    /* load */
1800
    if (op1 == OR_TMP0) {
1801
        tcg_gen_mov_tl(a0, cpu_A0);
1802
        gen_op_ld_v(ot + s->mem_index, t0, a0);
1803
    } else {
1804
        gen_op_mov_v_reg(ot, t0, op1);
1805
    }
1806

    
1807
    tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1808

    
1809
    tcg_gen_mov_tl(t1, cpu_T[1]);
1810
    tcg_gen_mov_tl(t2, cpu_T3);
1811

    
1812
    /* Must test zero case to avoid using undefined behaviour in TCG
1813
       shifts. */
1814
    label1 = gen_new_label();
1815
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1816
    
1817
    tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1818
    if (ot == OT_WORD) {
1819
        /* Note: we implement the Intel behaviour for shift count > 16 */
1820
        if (is_right) {
1821
            tcg_gen_andi_tl(t0, t0, 0xffff);
1822
            tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1823
            tcg_gen_or_tl(t0, t0, cpu_tmp0);
1824
            tcg_gen_ext32u_tl(t0, t0);
1825

    
1826
            tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1827
            
1828
            /* only needed if count > 16, but a test would complicate */
1829
            tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1830
            tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1831

    
1832
            tcg_gen_shr_tl(t0, t0, t2);
1833

    
1834
            tcg_gen_or_tl(t0, t0, cpu_tmp0);
1835
        } else {
1836
            /* XXX: not optimal */
1837
            tcg_gen_andi_tl(t0, t0, 0xffff);
1838
            tcg_gen_shli_tl(t1, t1, 16);
1839
            tcg_gen_or_tl(t1, t1, t0);
1840
            tcg_gen_ext32u_tl(t1, t1);
1841
            
1842
            tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1843
            tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1844
            tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1845
            tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1846

    
1847
            tcg_gen_shl_tl(t0, t0, t2);
1848
            tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1849
            tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1850
            tcg_gen_or_tl(t0, t0, t1);
1851
        }
1852
    } else {
1853
        data_bits = 8 << ot;
1854
        if (is_right) {
1855
            if (ot == OT_LONG)
1856
                tcg_gen_ext32u_tl(t0, t0);
1857

    
1858
            tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1859

    
1860
            tcg_gen_shr_tl(t0, t0, t2);
1861
            tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1862
            tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1863
            tcg_gen_or_tl(t0, t0, t1);
1864
            
1865
        } else {
1866
            if (ot == OT_LONG)
1867
                tcg_gen_ext32u_tl(t1, t1);
1868

    
1869
            tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1870
            
1871
            tcg_gen_shl_tl(t0, t0, t2);
1872
            tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1873
            tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1874
            tcg_gen_or_tl(t0, t0, t1);
1875
        }
1876
    }
1877
    tcg_gen_mov_tl(t1, cpu_tmp4);
1878

    
1879
    gen_set_label(label1);
1880
    /* store */
1881
    if (op1 == OR_TMP0) {
1882
        gen_op_st_v(ot + s->mem_index, t0, a0);
1883
    } else {
1884
        gen_op_mov_reg_v(ot, op1, t0);
1885
    }
1886
    
1887
    /* update eflags */
1888
    if (s->cc_op != CC_OP_DYNAMIC)
1889
        gen_op_set_cc_op(s->cc_op);
1890

    
1891
    label2 = gen_new_label();
1892
    tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1893

    
1894
    tcg_gen_mov_tl(cpu_cc_src, t1);
1895
    tcg_gen_mov_tl(cpu_cc_dst, t0);
1896
    if (is_right) {
1897
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1898
    } else {
1899
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1900
    }
1901
    gen_set_label(label2);
1902
    s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1903

    
1904
    tcg_temp_free(t0);
1905
    tcg_temp_free(t1);
1906
    tcg_temp_free(t2);
1907
    tcg_temp_free(a0);
1908
}
1909

    
1910
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1911
{
1912
    if (s != OR_TMP1)
1913
        gen_op_mov_TN_reg(ot, 1, s);
1914
    switch(op) {
1915
    case OP_ROL:
1916
        gen_rot_rm_T1(s1, ot, d, 0);
1917
        break;
1918
    case OP_ROR:
1919
        gen_rot_rm_T1(s1, ot, d, 1);
1920
        break;
1921
    case OP_SHL:
1922
    case OP_SHL1:
1923
        gen_shift_rm_T1(s1, ot, d, 0, 0);
1924
        break;
1925
    case OP_SHR:
1926
        gen_shift_rm_T1(s1, ot, d, 1, 0);
1927
        break;
1928
    case OP_SAR:
1929
        gen_shift_rm_T1(s1, ot, d, 1, 1);
1930
        break;
1931
    case OP_RCL:
1932
        gen_rotc_rm_T1(s1, ot, d, 0);
1933
        break;
1934
    case OP_RCR:
1935
        gen_rotc_rm_T1(s1, ot, d, 1);
1936
        break;
1937
    }
1938
}
1939

    
1940
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1941
{
1942
    switch(op) {
1943
    case OP_ROL:
1944
        gen_rot_rm_im(s1, ot, d, c, 0);
1945
        break;
1946
    case OP_ROR:
1947
        gen_rot_rm_im(s1, ot, d, c, 1);
1948
        break;
1949
    case OP_SHL:
1950
    case OP_SHL1:
1951
        gen_shift_rm_im(s1, ot, d, c, 0, 0);
1952
        break;
1953
    case OP_SHR:
1954
        gen_shift_rm_im(s1, ot, d, c, 1, 0);
1955
        break;
1956
    case OP_SAR:
1957
        gen_shift_rm_im(s1, ot, d, c, 1, 1);
1958
        break;
1959
    default:
1960
        /* currently not optimized */
1961
        gen_op_movl_T1_im(c);
1962
        gen_shift(s1, op, ot, d, OR_TMP1);
1963
        break;
1964
    }
1965
}
1966

    
1967
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1968
{
1969
    target_long disp;
1970
    int havesib;
1971
    int base;
1972
    int index;
1973
    int scale;
1974
    int opreg;
1975
    int mod, rm, code, override, must_add_seg;
1976

    
1977
    override = s->override;
1978
    must_add_seg = s->addseg;
1979
    if (override >= 0)
1980
        must_add_seg = 1;
1981
    mod = (modrm >> 6) & 3;
1982
    rm = modrm & 7;
1983

    
1984
    if (s->aflag) {
1985

    
1986
        havesib = 0;
1987
        base = rm;
1988
        index = 0;
1989
        scale = 0;
1990

    
1991
        if (base == 4) {
1992
            havesib = 1;
1993
            code = ldub_code(s->pc++);
1994
            scale = (code >> 6) & 3;
1995
            index = ((code >> 3) & 7) | REX_X(s);
1996
            base = (code & 7);
1997
        }
1998
        base |= REX_B(s);
1999

    
2000
        switch (mod) {
2001
        case 0:
2002
            if ((base & 7) == 5) {
2003
                base = -1;
2004
                disp = (int32_t)ldl_code(s->pc);
2005
                s->pc += 4;
2006
                if (CODE64(s) && !havesib) {
2007
                    disp += s->pc + s->rip_offset;
2008
                }
2009
            } else {
2010
                disp = 0;
2011
            }
2012
            break;
2013
        case 1:
2014
            disp = (int8_t)ldub_code(s->pc++);
2015
            break;
2016
        default:
2017
        case 2:
2018
            disp = ldl_code(s->pc);
2019
            s->pc += 4;
2020
            break;
2021
        }
2022

    
2023
        if (base >= 0) {
2024
            /* for correct popl handling with esp */
2025
            if (base == 4 && s->popl_esp_hack)
2026
                disp += s->popl_esp_hack;
2027
#ifdef TARGET_X86_64
2028
            if (s->aflag == 2) {
2029
                gen_op_movq_A0_reg(base);
2030
                if (disp != 0) {
2031
                    gen_op_addq_A0_im(disp);
2032
                }
2033
            } else
2034
#endif
2035
            {
2036
                gen_op_movl_A0_reg(base);
2037
                if (disp != 0)
2038
                    gen_op_addl_A0_im(disp);
2039
            }
2040
        } else {
2041
#ifdef TARGET_X86_64
2042
            if (s->aflag == 2) {
2043
                gen_op_movq_A0_im(disp);
2044
            } else
2045
#endif
2046
            {
2047
                gen_op_movl_A0_im(disp);
2048
            }
2049
        }
2050
        /* index == 4 means no index */
2051
        if (havesib && (index != 4)) {
2052
#ifdef TARGET_X86_64
2053
            if (s->aflag == 2) {
2054
                gen_op_addq_A0_reg_sN(scale, index);
2055
            } else
2056
#endif
2057
            {
2058
                gen_op_addl_A0_reg_sN(scale, index);
2059
            }
2060
        }
2061
        if (must_add_seg) {
2062
            if (override < 0) {
2063
                if (base == R_EBP || base == R_ESP)
2064
                    override = R_SS;
2065
                else
2066
                    override = R_DS;
2067
            }
2068
#ifdef TARGET_X86_64
2069
            if (s->aflag == 2) {
2070
                gen_op_addq_A0_seg(override);
2071
            } else
2072
#endif
2073
            {
2074
                gen_op_addl_A0_seg(override);
2075
            }
2076
        }
2077
    } else {
2078
        switch (mod) {
2079
        case 0:
2080
            if (rm == 6) {
2081
                disp = lduw_code(s->pc);
2082
                s->pc += 2;
2083
                gen_op_movl_A0_im(disp);
2084
                rm = 0; /* avoid SS override */
2085
                goto no_rm;
2086
            } else {
2087
                disp = 0;
2088
            }
2089
            break;
2090
        case 1:
2091
            disp = (int8_t)ldub_code(s->pc++);
2092
            break;
2093
        default:
2094
        case 2:
2095
            disp = lduw_code(s->pc);
2096
            s->pc += 2;
2097
            break;
2098
        }
2099
        switch(rm) {
2100
        case 0:
2101
            gen_op_movl_A0_reg(R_EBX);
2102
            gen_op_addl_A0_reg_sN(0, R_ESI);
2103
            break;
2104
        case 1:
2105
            gen_op_movl_A0_reg(R_EBX);
2106
            gen_op_addl_A0_reg_sN(0, R_EDI);
2107
            break;
2108
        case 2:
2109
            gen_op_movl_A0_reg(R_EBP);
2110
            gen_op_addl_A0_reg_sN(0, R_ESI);
2111
            break;
2112
        case 3:
2113
            gen_op_movl_A0_reg(R_EBP);
2114
            gen_op_addl_A0_reg_sN(0, R_EDI);
2115
            break;
2116
        case 4:
2117
            gen_op_movl_A0_reg(R_ESI);
2118
            break;
2119
        case 5:
2120
            gen_op_movl_A0_reg(R_EDI);
2121
            break;
2122
        case 6:
2123
            gen_op_movl_A0_reg(R_EBP);
2124
            break;
2125
        default:
2126
        case 7:
2127
            gen_op_movl_A0_reg(R_EBX);
2128
            break;
2129
        }
2130
        if (disp != 0)
2131
            gen_op_addl_A0_im(disp);
2132
        gen_op_andl_A0_ffff();
2133
    no_rm:
2134
        if (must_add_seg) {
2135
            if (override < 0) {
2136
                if (rm == 2 || rm == 3 || rm == 6)
2137
                    override = R_SS;
2138
                else
2139
                    override = R_DS;
2140
            }
2141
            gen_op_addl_A0_seg(override);
2142
        }
2143
    }
2144

    
2145
    opreg = OR_A0;
2146
    disp = 0;
2147
    *reg_ptr = opreg;
2148
    *offset_ptr = disp;
2149
}
2150

    
2151
static void gen_nop_modrm(DisasContext *s, int modrm)
2152
{
2153
    int mod, rm, base, code;
2154

    
2155
    mod = (modrm >> 6) & 3;
2156
    if (mod == 3)
2157
        return;
2158
    rm = modrm & 7;
2159

    
2160
    if (s->aflag) {
2161

    
2162
        base = rm;
2163

    
2164
        if (base == 4) {
2165
            code = ldub_code(s->pc++);
2166
            base = (code & 7);
2167
        }
2168

    
2169
        switch (mod) {
2170
        case 0:
2171
            if (base == 5) {
2172
                s->pc += 4;
2173
            }
2174
            break;
2175
        case 1:
2176
            s->pc++;
2177
            break;
2178
        default:
2179
        case 2:
2180
            s->pc += 4;
2181
            break;
2182
        }
2183
    } else {
2184
        switch (mod) {
2185
        case 0:
2186
            if (rm == 6) {
2187
                s->pc += 2;
2188
            }
2189
            break;
2190
        case 1:
2191
            s->pc++;
2192
            break;
2193
        default:
2194
        case 2:
2195
            s->pc += 2;
2196
            break;
2197
        }
2198
    }
2199
}
2200

    
2201
/* used for LEA and MOV AX, mem */
2202
static void gen_add_A0_ds_seg(DisasContext *s)
2203
{
2204
    int override, must_add_seg;
2205
    must_add_seg = s->addseg;
2206
    override = R_DS;
2207
    if (s->override >= 0) {
2208
        override = s->override;
2209
        must_add_seg = 1;
2210
    }
2211
    if (must_add_seg) {
2212
#ifdef TARGET_X86_64
2213
        if (CODE64(s)) {
2214
            gen_op_addq_A0_seg(override);
2215
        } else
2216
#endif
2217
        {
2218
            gen_op_addl_A0_seg(override);
2219
        }
2220
    }
2221
}
2222

    
2223
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2224
   OR_TMP0 */
2225
static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2226
{
2227
    int mod, rm, opreg, disp;
2228

    
2229
    mod = (modrm >> 6) & 3;
2230
    rm = (modrm & 7) | REX_B(s);
2231
    if (mod == 3) {
2232
        if (is_store) {
2233
            if (reg != OR_TMP0)
2234
                gen_op_mov_TN_reg(ot, 0, reg);
2235
            gen_op_mov_reg_T0(ot, rm);
2236
        } else {
2237
            gen_op_mov_TN_reg(ot, 0, rm);
2238
            if (reg != OR_TMP0)
2239
                gen_op_mov_reg_T0(ot, reg);
2240
        }
2241
    } else {
2242
        gen_lea_modrm(s, modrm, &opreg, &disp);
2243
        if (is_store) {
2244
            if (reg != OR_TMP0)
2245
                gen_op_mov_TN_reg(ot, 0, reg);
2246
            gen_op_st_T0_A0(ot + s->mem_index);
2247
        } else {
2248
            gen_op_ld_T0_A0(ot + s->mem_index);
2249
            if (reg != OR_TMP0)
2250
                gen_op_mov_reg_T0(ot, reg);
2251
        }
2252
    }
2253
}
2254

    
2255
static inline uint32_t insn_get(DisasContext *s, int ot)
2256
{
2257
    uint32_t ret;
2258

    
2259
    switch(ot) {
2260
    case OT_BYTE:
2261
        ret = ldub_code(s->pc);
2262
        s->pc++;
2263
        break;
2264
    case OT_WORD:
2265
        ret = lduw_code(s->pc);
2266
        s->pc += 2;
2267
        break;
2268
    default:
2269
    case OT_LONG:
2270
        ret = ldl_code(s->pc);
2271
        s->pc += 4;
2272
        break;
2273
    }
2274
    return ret;
2275
}
2276

    
2277
static inline int insn_const_size(unsigned int ot)
2278
{
2279
    if (ot <= OT_LONG)
2280
        return 1 << ot;
2281
    else
2282
        return 4;
2283
}
2284

    
2285
static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2286
{
2287
    TranslationBlock *tb;
2288
    target_ulong pc;
2289

    
2290
    pc = s->cs_base + eip;
2291
    tb = s->tb;
2292
    /* NOTE: we handle the case where the TB spans two pages here */
2293
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2294
        (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))  {
2295
        /* jump to same page: we can use a direct jump */
2296
        tcg_gen_goto_tb(tb_num);
2297
        gen_jmp_im(eip);
2298
        tcg_gen_exit_tb((long)tb + tb_num);
2299
    } else {
2300
        /* jump to another page: currently not optimized */
2301
        gen_jmp_im(eip);
2302
        gen_eob(s);
2303
    }
2304
}
2305

    
2306
static inline void gen_jcc(DisasContext *s, int b,
2307
                           target_ulong val, target_ulong next_eip)
2308
{
2309
    int l1, l2, cc_op;
2310

    
2311
    cc_op = s->cc_op;
2312
    if (s->cc_op != CC_OP_DYNAMIC) {
2313
        gen_op_set_cc_op(s->cc_op);
2314
        s->cc_op = CC_OP_DYNAMIC;
2315
    }
2316
    if (s->jmp_opt) {
2317
        l1 = gen_new_label();
2318
        gen_jcc1(s, cc_op, b, l1);
2319
        
2320
        gen_goto_tb(s, 0, next_eip);
2321

    
2322
        gen_set_label(l1);
2323
        gen_goto_tb(s, 1, val);
2324
        s->is_jmp = 3;
2325
    } else {
2326

    
2327
        l1 = gen_new_label();
2328
        l2 = gen_new_label();
2329
        gen_jcc1(s, cc_op, b, l1);
2330

    
2331
        gen_jmp_im(next_eip);
2332
        tcg_gen_br(l2);
2333

    
2334
        gen_set_label(l1);
2335
        gen_jmp_im(val);
2336
        gen_set_label(l2);
2337
        gen_eob(s);
2338
    }
2339
}
2340

    
2341
static void gen_setcc(DisasContext *s, int b)
2342
{
2343
    int inv, jcc_op, l1;
2344
    TCGv t0;
2345

    
2346
    if (is_fast_jcc_case(s, b)) {
2347
        /* nominal case: we use a jump */
2348
        /* XXX: make it faster by adding new instructions in TCG */
2349
        t0 = tcg_temp_local_new();
2350
        tcg_gen_movi_tl(t0, 0);
2351
        l1 = gen_new_label();
2352
        gen_jcc1(s, s->cc_op, b ^ 1, l1);
2353
        tcg_gen_movi_tl(t0, 1);
2354
        gen_set_label(l1);
2355
        tcg_gen_mov_tl(cpu_T[0], t0);
2356
        tcg_temp_free(t0);
2357
    } else {
2358
        /* slow case: it is more efficient not to generate a jump,
2359
           although it is questionnable whether this optimization is
2360
           worth to */
2361
        inv = b & 1;
2362
        jcc_op = (b >> 1) & 7;
2363
        gen_setcc_slow_T0(s, jcc_op);
2364
        if (inv) {
2365
            tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2366
        }
2367
    }
2368
}
2369

    
2370
static inline void gen_op_movl_T0_seg(int seg_reg)
2371
{
2372
    tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 
2373
                     offsetof(CPUX86State,segs[seg_reg].selector));
2374
}
2375

    
2376
static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2377
{
2378
    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2379
    tcg_gen_st32_tl(cpu_T[0], cpu_env, 
2380
                    offsetof(CPUX86State,segs[seg_reg].selector));
2381
    tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2382
    tcg_gen_st_tl(cpu_T[0], cpu_env, 
2383
                  offsetof(CPUX86State,segs[seg_reg].base));
2384
}
2385

    
2386
/* move T0 to seg_reg and compute if the CPU state may change. Never
2387
   call this function with seg_reg == R_CS */
2388
static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2389
{
2390
    if (s->pe && !s->vm86) {
2391
        /* XXX: optimize by finding processor state dynamically */
2392
        if (s->cc_op != CC_OP_DYNAMIC)
2393
            gen_op_set_cc_op(s->cc_op);
2394
        gen_jmp_im(cur_eip);
2395
        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2396
        gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2397
        /* abort translation because the addseg value may change or
2398
           because ss32 may change. For R_SS, translation must always
2399
           stop as a special handling must be done to disable hardware
2400
           interrupts for the next instruction */
2401
        if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2402
            s->is_jmp = 3;
2403
    } else {
2404
        gen_op_movl_seg_T0_vm(seg_reg);
2405
        if (seg_reg == R_SS)
2406
            s->is_jmp = 3;
2407
    }
2408
}
2409

    
2410
static inline int svm_is_rep(int prefixes)
2411
{
2412
    return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2413
}
2414

    
2415
static inline void
2416
gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2417
                              uint32_t type, uint64_t param)
2418
{
2419
    /* no SVM activated; fast case */
2420
    if (likely(!(s->flags & HF_SVMI_MASK)))
2421
        return;
2422
    if (s->cc_op != CC_OP_DYNAMIC)
2423
        gen_op_set_cc_op(s->cc_op);
2424
    gen_jmp_im(pc_start - s->cs_base);
2425
    gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2426
                                         tcg_const_i64(param));
2427
}
2428

    
2429
static inline void
2430
gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2431
{
2432
    gen_svm_check_intercept_param(s, pc_start, type, 0);
2433
}
2434

    
2435
static inline void gen_stack_update(DisasContext *s, int addend)
2436
{
2437
#ifdef TARGET_X86_64
2438
    if (CODE64(s)) {
2439
        gen_op_add_reg_im(2, R_ESP, addend);
2440
    } else
2441
#endif
2442
    if (s->ss32) {
2443
        gen_op_add_reg_im(1, R_ESP, addend);
2444
    } else {
2445
        gen_op_add_reg_im(0, R_ESP, addend);
2446
    }
2447
}
2448

    
2449
/* generate a push. It depends on ss32, addseg and dflag */
2450
static void gen_push_T0(DisasContext *s)
2451
{
2452
#ifdef TARGET_X86_64
2453
    if (CODE64(s)) {
2454
        gen_op_movq_A0_reg(R_ESP);
2455
        if (s->dflag) {
2456
            gen_op_addq_A0_im(-8);
2457
            gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2458
        } else {
2459
            gen_op_addq_A0_im(-2);
2460
            gen_op_st_T0_A0(OT_WORD + s->mem_index);
2461
        }
2462
        gen_op_mov_reg_A0(2, R_ESP);
2463
    } else
2464
#endif
2465
    {
2466
        gen_op_movl_A0_reg(R_ESP);
2467
        if (!s->dflag)
2468
            gen_op_addl_A0_im(-2);
2469
        else
2470
            gen_op_addl_A0_im(-4);
2471
        if (s->ss32) {
2472
            if (s->addseg) {
2473
                tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2474
                gen_op_addl_A0_seg(R_SS);
2475
            }
2476
        } else {
2477
            gen_op_andl_A0_ffff();
2478
            tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2479
            gen_op_addl_A0_seg(R_SS);
2480
        }
2481
        gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2482
        if (s->ss32 && !s->addseg)
2483
            gen_op_mov_reg_A0(1, R_ESP);
2484
        else
2485
            gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2486
    }
2487
}
2488

    
2489
/* generate a push. It depends on ss32, addseg and dflag */
2490
/* slower version for T1, only used for call Ev */
2491
static void gen_push_T1(DisasContext *s)
2492
{
2493
#ifdef TARGET_X86_64
2494
    if (CODE64(s)) {
2495
        gen_op_movq_A0_reg(R_ESP);
2496
        if (s->dflag) {
2497
            gen_op_addq_A0_im(-8);
2498
            gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2499
        } else {
2500
            gen_op_addq_A0_im(-2);
2501
            gen_op_st_T0_A0(OT_WORD + s->mem_index);
2502
        }
2503
        gen_op_mov_reg_A0(2, R_ESP);
2504
    } else
2505
#endif
2506
    {
2507
        gen_op_movl_A0_reg(R_ESP);
2508
        if (!s->dflag)
2509
            gen_op_addl_A0_im(-2);
2510
        else
2511
            gen_op_addl_A0_im(-4);
2512
        if (s->ss32) {
2513
            if (s->addseg) {
2514
                gen_op_addl_A0_seg(R_SS);
2515
            }
2516
        } else {
2517
            gen_op_andl_A0_ffff();
2518
            gen_op_addl_A0_seg(R_SS);
2519
        }
2520
        gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2521

    
2522
        if (s->ss32 && !s->addseg)
2523
            gen_op_mov_reg_A0(1, R_ESP);
2524
        else
2525
            gen_stack_update(s, (-2) << s->dflag);
2526
    }
2527
}
2528

    
2529
/* two step pop is necessary for precise exceptions */
2530
static void gen_pop_T0(DisasContext *s)
2531
{
2532
#ifdef TARGET_X86_64
2533
    if (CODE64(s)) {
2534
        gen_op_movq_A0_reg(R_ESP);
2535
        gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2536
    } else
2537
#endif
2538
    {
2539
        gen_op_movl_A0_reg(R_ESP);
2540
        if (s->ss32) {
2541
            if (s->addseg)
2542
                gen_op_addl_A0_seg(R_SS);
2543
        } else {
2544
            gen_op_andl_A0_ffff();
2545
            gen_op_addl_A0_seg(R_SS);
2546
        }
2547
        gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2548
    }
2549
}
2550

    
2551
static void gen_pop_update(DisasContext *s)
2552
{
2553
#ifdef TARGET_X86_64
2554
    if (CODE64(s) && s->dflag) {
2555
        gen_stack_update(s, 8);
2556
    } else
2557
#endif
2558
    {
2559
        gen_stack_update(s, 2 << s->dflag);
2560
    }
2561
}
2562

    
2563
static void gen_stack_A0(DisasContext *s)
2564
{
2565
    gen_op_movl_A0_reg(R_ESP);
2566
    if (!s->ss32)
2567
        gen_op_andl_A0_ffff();
2568
    tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2569
    if (s->addseg)
2570
        gen_op_addl_A0_seg(R_SS);
2571
}
2572

    
2573
/* NOTE: wrap around in 16 bit not fully handled */
2574
static void gen_pusha(DisasContext *s)
2575
{
2576
    int i;
2577
    gen_op_movl_A0_reg(R_ESP);
2578
    gen_op_addl_A0_im(-16 <<  s->dflag);
2579
    if (!s->ss32)
2580
        gen_op_andl_A0_ffff();
2581
    tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2582
    if (s->addseg)
2583
        gen_op_addl_A0_seg(R_SS);
2584
    for(i = 0;i < 8; i++) {
2585
        gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2586
        gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2587
        gen_op_addl_A0_im(2 <<  s->dflag);
2588
    }
2589
    gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2590
}
2591

    
2592
/* NOTE: wrap around in 16 bit not fully handled */
2593
static void gen_popa(DisasContext *s)
2594
{
2595
    int i;
2596
    gen_op_movl_A0_reg(R_ESP);
2597
    if (!s->ss32)
2598
        gen_op_andl_A0_ffff();
2599
    tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2600
    tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 <<  s->dflag);
2601
    if (s->addseg)
2602
        gen_op_addl_A0_seg(R_SS);
2603
    for(i = 0;i < 8; i++) {
2604
        /* ESP is not reloaded */
2605
        if (i != 3) {
2606
            gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2607
            gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2608
        }
2609
        gen_op_addl_A0_im(2 <<  s->dflag);
2610
    }
2611
    gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2612
}
2613

    
2614
static void gen_enter(DisasContext *s, int esp_addend, int level)
2615
{
2616
    int ot, opsize;
2617

    
2618
    level &= 0x1f;
2619
#ifdef TARGET_X86_64
2620
    if (CODE64(s)) {
2621
        ot = s->dflag ? OT_QUAD : OT_WORD;
2622
        opsize = 1 << ot;
2623

    
2624
        gen_op_movl_A0_reg(R_ESP);
2625
        gen_op_addq_A0_im(-opsize);
2626
        tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2627

    
2628
        /* push bp */
2629
        gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2630
        gen_op_st_T0_A0(ot + s->mem_index);
2631
        if (level) {
2632
            /* XXX: must save state */
2633
            gen_helper_enter64_level(tcg_const_i32(level),
2634
                                     tcg_const_i32((ot == OT_QUAD)),
2635
                                     cpu_T[1]);
2636
        }
2637
        gen_op_mov_reg_T1(ot, R_EBP);
2638
        tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2639
        gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2640
    } else
2641
#endif
2642
    {
2643
        ot = s->dflag + OT_WORD;
2644
        opsize = 2 << s->dflag;
2645

    
2646
        gen_op_movl_A0_reg(R_ESP);
2647
        gen_op_addl_A0_im(-opsize);
2648
        if (!s->ss32)
2649
            gen_op_andl_A0_ffff();
2650
        tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2651
        if (s->addseg)
2652
            gen_op_addl_A0_seg(R_SS);
2653
        /* push bp */
2654
        gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2655
        gen_op_st_T0_A0(ot + s->mem_index);
2656
        if (level) {
2657
            /* XXX: must save state */
2658
            gen_helper_enter_level(tcg_const_i32(level),
2659
                                   tcg_const_i32(s->dflag),
2660
                                   cpu_T[1]);
2661
        }
2662
        gen_op_mov_reg_T1(ot, R_EBP);
2663
        tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2664
        gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2665
    }
2666
}
2667

    
2668
static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2669
{
2670
    if (s->cc_op != CC_OP_DYNAMIC)
2671
        gen_op_set_cc_op(s->cc_op);
2672
    gen_jmp_im(cur_eip);
2673
    gen_helper_raise_exception(tcg_const_i32(trapno));
2674
    s->is_jmp = 3;
2675
}
2676

    
2677
/* an interrupt is different from an exception because of the
2678
   privilege checks */
2679
static void gen_interrupt(DisasContext *s, int intno,
2680
                          target_ulong cur_eip, target_ulong next_eip)
2681
{
2682
    if (s->cc_op != CC_OP_DYNAMIC)
2683
        gen_op_set_cc_op(s->cc_op);
2684
    gen_jmp_im(cur_eip);
2685
    gen_helper_raise_interrupt(tcg_const_i32(intno), 
2686
                               tcg_const_i32(next_eip - cur_eip));
2687
    s->is_jmp = 3;
2688
}
2689

    
2690
static void gen_debug(DisasContext *s, target_ulong cur_eip)
2691
{
2692
    if (s->cc_op != CC_OP_DYNAMIC)
2693
        gen_op_set_cc_op(s->cc_op);
2694
    gen_jmp_im(cur_eip);
2695
    gen_helper_debug();
2696
    s->is_jmp = 3;
2697
}
2698

    
2699
/* generate a generic end of block. Trace exception is also generated
2700
   if needed */
2701
static void gen_eob(DisasContext *s)
2702
{
2703
    if (s->cc_op != CC_OP_DYNAMIC)
2704
        gen_op_set_cc_op(s->cc_op);
2705
    if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2706
        gen_helper_reset_inhibit_irq();
2707
    }
2708
    if (s->tb->flags & HF_RF_MASK) {
2709
        gen_helper_reset_rf();
2710
    }
2711
    if (s->singlestep_enabled) {
2712
        gen_helper_debug();
2713
    } else if (s->tf) {
2714
        gen_helper_single_step();
2715
    } else {
2716
        tcg_gen_exit_tb(0);
2717
    }
2718
    s->is_jmp = 3;
2719
}
2720

    
2721
/* generate a jump to eip. No segment change must happen before as a
2722
   direct call to the next block may occur */
2723
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2724
{
2725
    if (s->jmp_opt) {
2726
        if (s->cc_op != CC_OP_DYNAMIC) {
2727
            gen_op_set_cc_op(s->cc_op);
2728
            s->cc_op = CC_OP_DYNAMIC;
2729
        }
2730
        gen_goto_tb(s, tb_num, eip);
2731
        s->is_jmp = 3;
2732
    } else {
2733
        gen_jmp_im(eip);
2734
        gen_eob(s);
2735
    }
2736
}
2737

    
2738
static void gen_jmp(DisasContext *s, target_ulong eip)
2739
{
2740
    gen_jmp_tb(s, eip, 0);
2741
}
2742

    
2743
static inline void gen_ldq_env_A0(int idx, int offset)
2744
{
2745
    int mem_index = (idx >> 2) - 1;
2746
    tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2747
    tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2748
}
2749

    
2750
static inline void gen_stq_env_A0(int idx, int offset)
2751
{
2752
    int mem_index = (idx >> 2) - 1;
2753
    tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2754
    tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2755
}
2756

    
2757
static inline void gen_ldo_env_A0(int idx, int offset)
2758
{
2759
    int mem_index = (idx >> 2) - 1;
2760
    tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2761
    tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2762
    tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2763
    tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2764
    tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2765
}
2766

    
2767
static inline void gen_sto_env_A0(int idx, int offset)
2768
{
2769
    int mem_index = (idx >> 2) - 1;
2770
    tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2771
    tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2772
    tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2773
    tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2774
    tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2775
}
2776

    
2777
static inline void gen_op_movo(int d_offset, int s_offset)
2778
{
2779
    tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2780
    tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2781
    tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2782
    tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2783
}
2784

    
2785
static inline void gen_op_movq(int d_offset, int s_offset)
2786
{
2787
    tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2788
    tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2789
}
2790

    
2791
static inline void gen_op_movl(int d_offset, int s_offset)
2792
{
2793
    tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2794
    tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2795
}
2796

    
2797
static inline void gen_op_movq_env_0(int d_offset)
2798
{
2799
    tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2800
    tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2801
}
2802

    
2803
#define SSE_SPECIAL ((void *)1)
2804
#define SSE_DUMMY ((void *)2)
2805

    
2806
#define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2807
#define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2808
                     gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2809

    
2810
static void *sse_op_table1[256][4] = {
2811
    /* 3DNow! extensions */
2812
    [0x0e] = { SSE_DUMMY }, /* femms */
2813
    [0x0f] = { SSE_DUMMY }, /* pf... */
2814
    /* pure SSE operations */
2815
    [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2816
    [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2817
    [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2818
    [0x13] = { SSE_SPECIAL, SSE_SPECIAL },  /* movlps, movlpd */
2819
    [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2820
    [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2821
    [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },  /* movhps, movhpd, movshdup */
2822
    [0x17] = { SSE_SPECIAL, SSE_SPECIAL },  /* movhps, movhpd */
2823

    
2824
    [0x28] = { SSE_SPECIAL, SSE_SPECIAL },  /* movaps, movapd */
2825
    [0x29] = { SSE_SPECIAL, SSE_SPECIAL },  /* movaps, movapd */
2826
    [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2827
    [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2828
    [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2829
    [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2830
    [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2831
    [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2832
    [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2833
    [0x51] = SSE_FOP(sqrt),
2834
    [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2835
    [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2836
    [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2837
    [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2838
    [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2839
    [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2840
    [0x58] = SSE_FOP(add),
2841
    [0x59] = SSE_FOP(mul),
2842
    [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2843
               gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2844
    [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2845
    [0x5c] = SSE_FOP(sub),
2846
    [0x5d] = SSE_FOP(min),
2847
    [0x5e] = SSE_FOP(div),
2848
    [0x5f] = SSE_FOP(max),
2849

    
2850
    [0xc2] = SSE_FOP(cmpeq),
2851
    [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
2852

    
2853
    [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2854
    [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2855

    
2856
    /* MMX ops and their SSE extensions */
2857
    [0x60] = MMX_OP2(punpcklbw),
2858
    [0x61] = MMX_OP2(punpcklwd),
2859
    [0x62] = MMX_OP2(punpckldq),
2860
    [0x63] = MMX_OP2(packsswb),
2861
    [0x64] = MMX_OP2(pcmpgtb),
2862
    [0x65] = MMX_OP2(pcmpgtw),
2863
    [0x66] = MMX_OP2(pcmpgtl),
2864
    [0x67] = MMX_OP2(packuswb),
2865
    [0x68] = MMX_OP2(punpckhbw),
2866
    [0x69] = MMX_OP2(punpckhwd),
2867
    [0x6a] = MMX_OP2(punpckhdq),
2868
    [0x6b] = MMX_OP2(packssdw),
2869
    [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2870
    [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2871
    [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2872
    [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2873
    [0x70] = { gen_helper_pshufw_mmx,
2874
               gen_helper_pshufd_xmm,
2875
               gen_helper_pshufhw_xmm,
2876
               gen_helper_pshuflw_xmm },
2877
    [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2878
    [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2879
    [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2880
    [0x74] = MMX_OP2(pcmpeqb),
2881
    [0x75] = MMX_OP2(pcmpeqw),
2882
    [0x76] = MMX_OP2(pcmpeql),
2883
    [0x77] = { SSE_DUMMY }, /* emms */
2884
    [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2885
    [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2886
    [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2887
    [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2888
    [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2889
    [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2890
    [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2891
    [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2892
    [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2893
    [0xd1] = MMX_OP2(psrlw),
2894
    [0xd2] = MMX_OP2(psrld),
2895
    [0xd3] = MMX_OP2(psrlq),
2896
    [0xd4] = MMX_OP2(paddq),
2897
    [0xd5] = MMX_OP2(pmullw),
2898
    [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2899
    [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2900
    [0xd8] = MMX_OP2(psubusb),
2901
    [0xd9] = MMX_OP2(psubusw),
2902
    [0xda] = MMX_OP2(pminub),
2903
    [0xdb] = MMX_OP2(pand),
2904
    [0xdc] = MMX_OP2(paddusb),
2905
    [0xdd] = MMX_OP2(paddusw),
2906
    [0xde] = MMX_OP2(pmaxub),
2907
    [0xdf] = MMX_OP2(pandn),
2908
    [0xe0] = MMX_OP2(pavgb),
2909
    [0xe1] = MMX_OP2(psraw),
2910
    [0xe2] = MMX_OP2(psrad),
2911
    [0xe3] = MMX_OP2(pavgw),
2912
    [0xe4] = MMX_OP2(pmulhuw),
2913
    [0xe5] = MMX_OP2(pmulhw),
2914
    [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2915
    [0xe7] = { SSE_SPECIAL , SSE_SPECIAL },  /* movntq, movntq */
2916
    [0xe8] = MMX_OP2(psubsb),
2917
    [0xe9] = MMX_OP2(psubsw),
2918
    [0xea] = MMX_OP2(pminsw),
2919
    [0xeb] = MMX_OP2(por),
2920
    [0xec] = MMX_OP2(paddsb),
2921
    [0xed] = MMX_OP2(paddsw),
2922
    [0xee] = MMX_OP2(pmaxsw),
2923
    [0xef] = MMX_OP2(pxor),
2924
    [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2925
    [0xf1] = MMX_OP2(psllw),
2926
    [0xf2] = MMX_OP2(pslld),
2927
    [0xf3] = MMX_OP2(psllq),
2928
    [0xf4] = MMX_OP2(pmuludq),
2929
    [0xf5] = MMX_OP2(pmaddwd),
2930
    [0xf6] = MMX_OP2(psadbw),
2931
    [0xf7] = MMX_OP2(maskmov),
2932
    [0xf8] = MMX_OP2(psubb),
2933
    [0xf9] = MMX_OP2(psubw),
2934
    [0xfa] = MMX_OP2(psubl),
2935
    [0xfb] = MMX_OP2(psubq),
2936
    [0xfc] = MMX_OP2(paddb),
2937
    [0xfd] = MMX_OP2(paddw),
2938
    [0xfe] = MMX_OP2(paddl),
2939
};
2940

    
2941
static void *sse_op_table2[3 * 8][2] = {
2942
    [0 + 2] = MMX_OP2(psrlw),
2943
    [0 + 4] = MMX_OP2(psraw),
2944
    [0 + 6] = MMX_OP2(psllw),
2945
    [8 + 2] = MMX_OP2(psrld),
2946
    [8 + 4] = MMX_OP2(psrad),
2947
    [8 + 6] = MMX_OP2(pslld),
2948
    [16 + 2] = MMX_OP2(psrlq),
2949
    [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2950
    [16 + 6] = MMX_OP2(psllq),
2951
    [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2952
};
2953

    
2954
static void *sse_op_table3[4 * 3] = {
2955
    gen_helper_cvtsi2ss,
2956
    gen_helper_cvtsi2sd,
2957
    X86_64_ONLY(gen_helper_cvtsq2ss),
2958
    X86_64_ONLY(gen_helper_cvtsq2sd),
2959

    
2960
    gen_helper_cvttss2si,
2961
    gen_helper_cvttsd2si,
2962
    X86_64_ONLY(gen_helper_cvttss2sq),
2963
    X86_64_ONLY(gen_helper_cvttsd2sq),
2964

    
2965
    gen_helper_cvtss2si,
2966
    gen_helper_cvtsd2si,
2967
    X86_64_ONLY(gen_helper_cvtss2sq),
2968
    X86_64_ONLY(gen_helper_cvtsd2sq),
2969
};
2970

    
2971
static void *sse_op_table4[8][4] = {
2972
    SSE_FOP(cmpeq),
2973
    SSE_FOP(cmplt),
2974
    SSE_FOP(cmple),
2975
    SSE_FOP(cmpunord),
2976
    SSE_FOP(cmpneq),
2977
    SSE_FOP(cmpnlt),
2978
    SSE_FOP(cmpnle),
2979
    SSE_FOP(cmpord),
2980
};
2981

    
2982
static void *sse_op_table5[256] = {
2983
    [0x0c] = gen_helper_pi2fw,
2984
    [0x0d] = gen_helper_pi2fd,
2985
    [0x1c] = gen_helper_pf2iw,
2986
    [0x1d] = gen_helper_pf2id,
2987
    [0x8a] = gen_helper_pfnacc,
2988
    [0x8e] = gen_helper_pfpnacc,
2989
    [0x90] = gen_helper_pfcmpge,
2990
    [0x94] = gen_helper_pfmin,
2991
    [0x96] = gen_helper_pfrcp,
2992
    [0x97] = gen_helper_pfrsqrt,
2993
    [0x9a] = gen_helper_pfsub,
2994
    [0x9e] = gen_helper_pfadd,
2995
    [0xa0] = gen_helper_pfcmpgt,
2996
    [0xa4] = gen_helper_pfmax,
2997
    [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
2998
    [0xa7] = gen_helper_movq, /* pfrsqit1 */
2999
    [0xaa] = gen_helper_pfsubr,
3000
    [0xae] = gen_helper_pfacc,
3001
    [0xb0] = gen_helper_pfcmpeq,
3002
    [0xb4] = gen_helper_pfmul,
3003
    [0xb6] = gen_helper_movq, /* pfrcpit2 */
3004
    [0xb7] = gen_helper_pmulhrw_mmx,
3005
    [0xbb] = gen_helper_pswapd,
3006
    [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3007
};
3008

    
3009
struct sse_op_helper_s {
3010
    void *op[2]; uint32_t ext_mask;
3011
};
3012
#define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3013
#define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3014
#define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3015
#define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3016
static struct sse_op_helper_s sse_op_table6[256] = {
3017
    [0x00] = SSSE3_OP(pshufb),
3018
    [0x01] = SSSE3_OP(phaddw),
3019
    [0x02] = SSSE3_OP(phaddd),
3020
    [0x03] = SSSE3_OP(phaddsw),
3021
    [0x04] = SSSE3_OP(pmaddubsw),
3022
    [0x05] = SSSE3_OP(phsubw),
3023
    [0x06] = SSSE3_OP(phsubd),
3024
    [0x07] = SSSE3_OP(phsubsw),
3025
    [0x08] = SSSE3_OP(psignb),
3026
    [0x09] = SSSE3_OP(psignw),
3027
    [0x0a] = SSSE3_OP(psignd),
3028
    [0x0b] = SSSE3_OP(pmulhrsw),
3029
    [0x10] = SSE41_OP(pblendvb),
3030
    [0x14] = SSE41_OP(blendvps),
3031
    [0x15] = SSE41_OP(blendvpd),
3032
    [0x17] = SSE41_OP(ptest),
3033
    [0x1c] = SSSE3_OP(pabsb),
3034
    [0x1d] = SSSE3_OP(pabsw),
3035
    [0x1e] = SSSE3_OP(pabsd),
3036
    [0x20] = SSE41_OP(pmovsxbw),
3037
    [0x21] = SSE41_OP(pmovsxbd),
3038
    [0x22] = SSE41_OP(pmovsxbq),
3039
    [0x23] = SSE41_OP(pmovsxwd),
3040
    [0x24] = SSE41_OP(pmovsxwq),
3041
    [0x25] = SSE41_OP(pmovsxdq),
3042
    [0x28] = SSE41_OP(pmuldq),
3043
    [0x29] = SSE41_OP(pcmpeqq),
3044
    [0x2a] = SSE41_SPECIAL, /* movntqda */
3045
    [0x2b] = SSE41_OP(packusdw),
3046
    [0x30] = SSE41_OP(pmovzxbw),
3047
    [0x31] = SSE41_OP(pmovzxbd),
3048
    [0x32] = SSE41_OP(pmovzxbq),
3049
    [0x33] = SSE41_OP(pmovzxwd),
3050
    [0x34] = SSE41_OP(pmovzxwq),
3051
    [0x35] = SSE41_OP(pmovzxdq),
3052
    [0x37] = SSE42_OP(pcmpgtq),
3053
    [0x38] = SSE41_OP(pminsb),
3054
    [0x39] = SSE41_OP(pminsd),
3055
    [0x3a] = SSE41_OP(pminuw),
3056
    [0x3b] = SSE41_OP(pminud),
3057
    [0x3c] = SSE41_OP(pmaxsb),
3058
    [0x3d] = SSE41_OP(pmaxsd),
3059
    [0x3e] = SSE41_OP(pmaxuw),
3060
    [0x3f] = SSE41_OP(pmaxud),
3061
    [0x40] = SSE41_OP(pmulld),
3062
    [0x41] = SSE41_OP(phminposuw),
3063
};
3064

    
3065
static struct sse_op_helper_s sse_op_table7[256] = {
3066
    [0x08] = SSE41_OP(roundps),
3067
    [0x09] = SSE41_OP(roundpd),
3068
    [0x0a] = SSE41_OP(roundss),
3069
    [0x0b] = SSE41_OP(roundsd),
3070
    [0x0c] = SSE41_OP(blendps),
3071
    [0x0d] = SSE41_OP(blendpd),
3072
    [0x0e] = SSE41_OP(pblendw),
3073
    [0x0f] = SSSE3_OP(palignr),
3074
    [0x14] = SSE41_SPECIAL, /* pextrb */
3075
    [0x15] = SSE41_SPECIAL, /* pextrw */
3076
    [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3077
    [0x17] = SSE41_SPECIAL, /* extractps */
3078
    [0x20] = SSE41_SPECIAL, /* pinsrb */
3079
    [0x21] = SSE41_SPECIAL, /* insertps */
3080
    [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3081
    [0x40] = SSE41_OP(dpps),
3082
    [0x41] = SSE41_OP(dppd),
3083
    [0x42] = SSE41_OP(mpsadbw),
3084
    [0x60] = SSE42_OP(pcmpestrm),
3085
    [0x61] = SSE42_OP(pcmpestri),
3086
    [0x62] = SSE42_OP(pcmpistrm),
3087
    [0x63] = SSE42_OP(pcmpistri),
3088
};
3089

    
3090
static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3091
{
3092
    int b1, op1_offset, op2_offset, is_xmm, val, ot;
3093
    int modrm, mod, rm, reg, reg_addr, offset_addr;
3094
    void *sse_op2;
3095

    
3096
    b &= 0xff;
3097
    if (s->prefix & PREFIX_DATA)
3098
        b1 = 1;
3099
    else if (s->prefix & PREFIX_REPZ)
3100
        b1 = 2;
3101
    else if (s->prefix & PREFIX_REPNZ)
3102
        b1 = 3;
3103
    else
3104
        b1 = 0;
3105
    sse_op2 = sse_op_table1[b][b1];
3106
    if (!sse_op2)
3107
        goto illegal_op;
3108
    if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3109
        is_xmm = 1;
3110
    } else {
3111
        if (b1 == 0) {
3112
            /* MMX case */
3113
            is_xmm = 0;
3114
        } else {
3115
            is_xmm = 1;
3116
        }
3117
    }
3118
    /* simple MMX/SSE operation */
3119
    if (s->flags & HF_TS_MASK) {
3120
        gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3121
        return;
3122
    }
3123
    if (s->flags & HF_EM_MASK) {
3124
    illegal_op:
3125
        gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3126
        return;
3127
    }
3128
    if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3129
        if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3130
            goto illegal_op;
3131
    if (b == 0x0e) {
3132
        if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3133
            goto illegal_op;
3134
        /* femms */
3135
        gen_helper_emms();
3136
        return;
3137
    }
3138
    if (b == 0x77) {
3139
        /* emms */
3140
        gen_helper_emms();
3141
        return;
3142
    }
3143
    /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3144
       the static cpu state) */
3145
    if (!is_xmm) {
3146
        gen_helper_enter_mmx();
3147
    }
3148

    
3149
    modrm = ldub_code(s->pc++);
3150
    reg = ((modrm >> 3) & 7);
3151
    if (is_xmm)
3152
        reg |= rex_r;
3153
    mod = (modrm >> 6) & 3;
3154
    if (sse_op2 == SSE_SPECIAL) {
3155
        b |= (b1 << 8);
3156
        switch(b) {
3157
        case 0x0e7: /* movntq */
3158
            if (mod == 3)
3159
                goto illegal_op;
3160
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3161
            gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3162
            break;
3163
        case 0x1e7: /* movntdq */
3164
        case 0x02b: /* movntps */
3165
        case 0x12b: /* movntps */
3166
            if (mod == 3)
3167
                goto illegal_op;
3168
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3169
            gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3170
            break;
3171
        case 0x3f0: /* lddqu */
3172
            if (mod == 3)
3173
                goto illegal_op;
3174
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3175
            gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3176
            break;
3177
        case 0x22b: /* movntss */
3178
        case 0x32b: /* movntsd */
3179
            if (mod == 3)
3180
                goto illegal_op;
3181
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3182
            if (b1 & 1) {
3183
                gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3184
                    xmm_regs[reg]));
3185
            } else {
3186
                tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3187
                    xmm_regs[reg].XMM_L(0)));
3188
                gen_op_st_T0_A0(OT_LONG + s->mem_index);
3189
            }
3190
            break;
3191
        case 0x6e: /* movd mm, ea */
3192
#ifdef TARGET_X86_64
3193
            if (s->dflag == 2) {
3194
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3195
                tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3196
            } else
3197
#endif
3198
            {
3199
                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3200
                tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
3201
                                 offsetof(CPUX86State,fpregs[reg].mmx));
3202
                tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3203
                gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3204
            }
3205
            break;
3206
        case 0x16e: /* movd xmm, ea */
3207
#ifdef TARGET_X86_64
3208
            if (s->dflag == 2) {
3209
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3210
                tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
3211
                                 offsetof(CPUX86State,xmm_regs[reg]));
3212
                gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3213
            } else
3214
#endif
3215
            {
3216
                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3217
                tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
3218
                                 offsetof(CPUX86State,xmm_regs[reg]));
3219
                tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3220
                gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3221
            }
3222
            break;
3223
        case 0x6f: /* movq mm, ea */
3224
            if (mod != 3) {
3225
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3226
                gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3227
            } else {
3228
                rm = (modrm & 7);
3229
                tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3230
                               offsetof(CPUX86State,fpregs[rm].mmx));
3231
                tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3232
                               offsetof(CPUX86State,fpregs[reg].mmx));
3233
            }
3234
            break;
3235
        case 0x010: /* movups */
3236
        case 0x110: /* movupd */
3237
        case 0x028: /* movaps */
3238
        case 0x128: /* movapd */
3239
        case 0x16f: /* movdqa xmm, ea */
3240
        case 0x26f: /* movdqu xmm, ea */
3241
            if (mod != 3) {
3242
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3243
                gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3244
            } else {
3245
                rm = (modrm & 7) | REX_B(s);
3246
                gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3247
                            offsetof(CPUX86State,xmm_regs[rm]));
3248
            }
3249
            break;
3250
        case 0x210: /* movss xmm, ea */
3251
            if (mod != 3) {
3252
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3253
                gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3254
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3255
                gen_op_movl_T0_0();
3256
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3257
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3258
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3259
            } else {
3260
                rm = (modrm & 7) | REX_B(s);
3261
                gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3262
                            offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3263
            }
3264
            break;
3265
        case 0x310: /* movsd xmm, ea */
3266
            if (mod != 3) {
3267
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3268
                gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3269
                gen_op_movl_T0_0();
3270
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3271
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3272
            } else {
3273
                rm = (modrm & 7) | REX_B(s);
3274
                gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3275
                            offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3276
            }
3277
            break;
3278
        case 0x012: /* movlps */
3279
        case 0x112: /* movlpd */
3280
            if (mod != 3) {
3281
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3282
                gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3283
            } else {
3284
                /* movhlps */
3285
                rm = (modrm & 7) | REX_B(s);
3286
                gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3287
                            offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3288
            }
3289
            break;
3290
        case 0x212: /* movsldup */
3291
            if (mod != 3) {
3292
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3293
                gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3294
            } else {
3295
                rm = (modrm & 7) | REX_B(s);
3296
                gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3297
                            offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3298
                gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3299
                            offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3300
            }
3301
            gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3302
                        offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3303
            gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3304
                        offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3305
            break;
3306
        case 0x312: /* movddup */
3307
            if (mod != 3) {
3308
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3309
                gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3310
            } else {
3311
                rm = (modrm & 7) | REX_B(s);
3312
                gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3313
                            offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3314
            }
3315
            gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3316
                        offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3317
            break;
3318
        case 0x016: /* movhps */
3319
        case 0x116: /* movhpd */
3320
            if (mod != 3) {
3321
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3322
                gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3323
            } else {
3324
                /* movlhps */
3325
                rm = (modrm & 7) | REX_B(s);
3326
                gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3327
                            offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3328
            }
3329
            break;
3330
        case 0x216: /* movshdup */
3331
            if (mod != 3) {
3332
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3333
                gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3334
            } else {
3335
                rm = (modrm & 7) | REX_B(s);
3336
                gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3337
                            offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3338
                gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3339
                            offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3340
            }
3341
            gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3342
                        offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3343
            gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3344
                        offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3345
            break;
3346
        case 0x178:
3347
        case 0x378:
3348
            {
3349
                int bit_index, field_length;
3350

    
3351
                if (b1 == 1 && reg != 0)
3352
                    goto illegal_op;
3353
                field_length = ldub_code(s->pc++) & 0x3F;
3354
                bit_index = ldub_code(s->pc++) & 0x3F;
3355
                tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3356
                    offsetof(CPUX86State,xmm_regs[reg]));
3357
                if (b1 == 1)
3358
                    gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index),
3359
                        tcg_const_i32(field_length));
3360
                else
3361
                    gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index),
3362
                        tcg_const_i32(field_length));
3363
            }
3364
            break;
3365
        case 0x7e: /* movd ea, mm */
3366
#ifdef TARGET_X86_64
3367
            if (s->dflag == 2) {
3368
                tcg_gen_ld_i64(cpu_T[0], cpu_env, 
3369
                               offsetof(CPUX86State,fpregs[reg].mmx));
3370
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3371
            } else
3372
#endif
3373
            {
3374
                tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 
3375
                                 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3376
                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3377
            }
3378
            break;
3379
        case 0x17e: /* movd ea, xmm */
3380
#ifdef TARGET_X86_64
3381
            if (s->dflag == 2) {
3382
                tcg_gen_ld_i64(cpu_T[0], cpu_env, 
3383
                               offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3384
                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3385
            } else
3386
#endif
3387
            {
3388
                tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 
3389
                                 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3390
                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3391
            }
3392
            break;
3393
        case 0x27e: /* movq xmm, ea */
3394
            if (mod != 3) {
3395
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3396
                gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3397
            } else {
3398
                rm = (modrm & 7) | REX_B(s);
3399
                gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3400
                            offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3401
            }
3402
            gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3403
            break;
3404
        case 0x7f: /* movq ea, mm */
3405
            if (mod != 3) {
3406
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3407
                gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3408
            } else {
3409
                rm = (modrm & 7);
3410
                gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3411
                            offsetof(CPUX86State,fpregs[reg].mmx));
3412
            }
3413
            break;
3414
        case 0x011: /* movups */
3415
        case 0x111: /* movupd */
3416
        case 0x029: /* movaps */
3417
        case 0x129: /* movapd */
3418
        case 0x17f: /* movdqa ea, xmm */
3419
        case 0x27f: /* movdqu ea, xmm */
3420
            if (mod != 3) {
3421
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3422
                gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3423
            } else {
3424
                rm = (modrm & 7) | REX_B(s);
3425
                gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3426
                            offsetof(CPUX86State,xmm_regs[reg]));
3427
            }
3428
            break;
3429
        case 0x211: /* movss ea, xmm */
3430
            if (mod != 3) {
3431
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3432
                tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3433
                gen_op_st_T0_A0(OT_LONG + s->mem_index);
3434
            } else {
3435
                rm = (modrm & 7) | REX_B(s);
3436
                gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3437
                            offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3438
            }
3439
            break;
3440
        case 0x311: /* movsd ea, xmm */
3441
            if (mod != 3) {
3442
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3443
                gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3444
            } else {
3445
                rm = (modrm & 7) | REX_B(s);
3446
                gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3447
                            offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3448
            }
3449
            break;
3450
        case 0x013: /* movlps */
3451
        case 0x113: /* movlpd */
3452
            if (mod != 3) {
3453
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3454
                gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3455
            } else {
3456
                goto illegal_op;
3457
            }
3458
            break;
3459
        case 0x017: /* movhps */
3460
        case 0x117: /* movhpd */
3461
            if (mod != 3) {
3462
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3463
                gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3464
            } else {
3465
                goto illegal_op;
3466
            }
3467
            break;
3468
        case 0x71: /* shift mm, im */
3469
        case 0x72:
3470
        case 0x73:
3471
        case 0x171: /* shift xmm, im */
3472
        case 0x172:
3473
        case 0x173:
3474
            val = ldub_code(s->pc++);
3475
            if (is_xmm) {
3476
                gen_op_movl_T0_im(val);
3477
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3478
                gen_op_movl_T0_0();
3479
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3480
                op1_offset = offsetof(CPUX86State,xmm_t0);
3481
            } else {
3482
                gen_op_movl_T0_im(val);
3483
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3484
                gen_op_movl_T0_0();
3485
                tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3486
                op1_offset = offsetof(CPUX86State,mmx_t0);
3487
            }
3488
            sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3489
            if (!sse_op2)
3490
                goto illegal_op;
3491
            if (is_xmm) {
3492
                rm = (modrm & 7) | REX_B(s);
3493
                op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3494
            } else {
3495
                rm = (modrm & 7);
3496
                op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3497
            }
3498
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3499
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3500
            ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3501
            break;
3502
        case 0x050: /* movmskps */
3503
            rm = (modrm & 7) | REX_B(s);
3504
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
3505
                             offsetof(CPUX86State,xmm_regs[rm]));
3506
            gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3507
            tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3508
            gen_op_mov_reg_T0(OT_LONG, reg);
3509
            break;
3510
        case 0x150: /* movmskpd */
3511
            rm = (modrm & 7) | REX_B(s);
3512
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
3513
                             offsetof(CPUX86State,xmm_regs[rm]));
3514
            gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3515
            tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3516
            gen_op_mov_reg_T0(OT_LONG, reg);
3517
            break;
3518
        case 0x02a: /* cvtpi2ps */
3519
        case 0x12a: /* cvtpi2pd */
3520
            gen_helper_enter_mmx();
3521
            if (mod != 3) {
3522
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3523
                op2_offset = offsetof(CPUX86State,mmx_t0);
3524
                gen_ldq_env_A0(s->mem_index, op2_offset);
3525
            } else {
3526
                rm = (modrm & 7);
3527
                op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3528
            }
3529
            op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3530
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3531
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3532
            switch(b >> 8) {
3533
            case 0x0:
3534
                gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
3535
                break;
3536
            default:
3537
            case 0x1:
3538
                gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
3539
                break;
3540
            }
3541
            break;
3542
        case 0x22a: /* cvtsi2ss */
3543
        case 0x32a: /* cvtsi2sd */
3544
            ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3545
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3546
            op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3547
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3548
            sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3549
            if (ot == OT_LONG) {
3550
                tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3551
                ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
3552
            } else {
3553
                ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]);
3554
            }
3555
            break;
3556
        case 0x02c: /* cvttps2pi */
3557
        case 0x12c: /* cvttpd2pi */
3558
        case 0x02d: /* cvtps2pi */
3559
        case 0x12d: /* cvtpd2pi */
3560
            gen_helper_enter_mmx();
3561
            if (mod != 3) {
3562
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3563
                op2_offset = offsetof(CPUX86State,xmm_t0);
3564
                gen_ldo_env_A0(s->mem_index, op2_offset);
3565
            } else {
3566
                rm = (modrm & 7) | REX_B(s);
3567
                op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3568
            }
3569
            op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3570
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3571
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3572
            switch(b) {
3573
            case 0x02c:
3574
                gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
3575
                break;
3576
            case 0x12c:
3577
                gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
3578
                break;
3579
            case 0x02d:
3580
                gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
3581
                break;
3582
            case 0x12d:
3583
                gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
3584
                break;
3585
            }
3586
            break;
3587
        case 0x22c: /* cvttss2si */
3588
        case 0x32c: /* cvttsd2si */
3589
        case 0x22d: /* cvtss2si */
3590
        case 0x32d: /* cvtsd2si */
3591
            ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3592
            if (mod != 3) {
3593
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3594
                if ((b >> 8) & 1) {
3595
                    gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3596
                } else {
3597
                    gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3598
                    tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3599
                }
3600
                op2_offset = offsetof(CPUX86State,xmm_t0);
3601
            } else {
3602
                rm = (modrm & 7) | REX_B(s);
3603
                op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3604
            }
3605
            sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3606
                                    (b & 1) * 4];
3607
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3608
            if (ot == OT_LONG) {
3609
                ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
3610
                tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3611
            } else {
3612
                ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0);
3613
            }
3614
            gen_op_mov_reg_T0(ot, reg);
3615
            break;
3616
        case 0xc4: /* pinsrw */
3617
        case 0x1c4:
3618
            s->rip_offset = 1;
3619
            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3620
            val = ldub_code(s->pc++);
3621
            if (b1) {
3622
                val &= 7;
3623
                tcg_gen_st16_tl(cpu_T[0], cpu_env,
3624
                                offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3625
            } else {
3626
                val &= 3;
3627
                tcg_gen_st16_tl(cpu_T[0], cpu_env,
3628
                                offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3629
            }
3630
            break;
3631
        case 0xc5: /* pextrw */
3632
        case 0x1c5:
3633
            if (mod != 3)
3634
                goto illegal_op;
3635
            ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3636
            val = ldub_code(s->pc++);
3637
            if (b1) {
3638
                val &= 7;
3639
                rm = (modrm & 7) | REX_B(s);
3640
                tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3641
                                 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3642
            } else {
3643
                val &= 3;
3644
                rm = (modrm & 7);
3645
                tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3646
                                offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3647
            }
3648
            reg = ((modrm >> 3) & 7) | rex_r;
3649
            gen_op_mov_reg_T0(ot, reg);
3650
            break;
3651
        case 0x1d6: /* movq ea, xmm */
3652
            if (mod != 3) {
3653
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3654
                gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3655
            } else {
3656
                rm = (modrm & 7) | REX_B(s);
3657
                gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3658
                            offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3659
                gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3660
            }
3661
            break;
3662
        case 0x2d6: /* movq2dq */
3663
            gen_helper_enter_mmx();
3664
            rm = (modrm & 7);
3665
            gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3666
                        offsetof(CPUX86State,fpregs[rm].mmx));
3667
            gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3668
            break;
3669
        case 0x3d6: /* movdq2q */
3670
            gen_helper_enter_mmx();
3671
            rm = (modrm & 7) | REX_B(s);
3672
            gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3673
                        offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3674
            break;
3675
        case 0xd7: /* pmovmskb */
3676
        case 0x1d7:
3677
            if (mod != 3)
3678
                goto illegal_op;
3679
            if (b1) {
3680
                rm = (modrm & 7) | REX_B(s);
3681
                tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3682
                gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
3683
            } else {
3684
                rm = (modrm & 7);
3685
                tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3686
                gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3687
            }
3688
            tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3689
            reg = ((modrm >> 3) & 7) | rex_r;
3690
            gen_op_mov_reg_T0(OT_LONG, reg);
3691
            break;
3692
        case 0x138:
3693
            if (s->prefix & PREFIX_REPNZ)
3694
                goto crc32;
3695
        case 0x038:
3696
            b = modrm;
3697
            modrm = ldub_code(s->pc++);
3698
            rm = modrm & 7;
3699
            reg = ((modrm >> 3) & 7) | rex_r;
3700
            mod = (modrm >> 6) & 3;
3701

    
3702
            sse_op2 = sse_op_table6[b].op[b1];
3703
            if (!sse_op2)
3704
                goto illegal_op;
3705
            if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3706
                goto illegal_op;
3707

    
3708
            if (b1) {
3709
                op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3710
                if (mod == 3) {
3711
                    op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3712
                } else {
3713
                    op2_offset = offsetof(CPUX86State,xmm_t0);
3714
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3715
                    switch (b) {
3716
                    case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3717
                    case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3718
                    case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3719
                        gen_ldq_env_A0(s->mem_index, op2_offset +
3720
                                        offsetof(XMMReg, XMM_Q(0)));
3721
                        break;
3722
                    case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3723
                    case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3724
                        tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3725
                                          (s->mem_index >> 2) - 1);
3726
                        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3727
                        tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3728
                                        offsetof(XMMReg, XMM_L(0)));
3729
                        break;
3730
                    case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3731
                        tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3732
                                          (s->mem_index >> 2) - 1);
3733
                        tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3734
                                        offsetof(XMMReg, XMM_W(0)));
3735
                        break;
3736
                    case 0x2a:            /* movntqda */
3737
                        gen_ldo_env_A0(s->mem_index, op1_offset);
3738
                        return;
3739
                    default:
3740
                        gen_ldo_env_A0(s->mem_index, op2_offset);
3741
                    }
3742
                }
3743
            } else {
3744
                op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3745
                if (mod == 3) {
3746
                    op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3747
                } else {
3748
                    op2_offset = offsetof(CPUX86State,mmx_t0);
3749
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3750
                    gen_ldq_env_A0(s->mem_index, op2_offset);
3751
                }
3752
            }
3753
            if (sse_op2 == SSE_SPECIAL)
3754
                goto illegal_op;
3755

    
3756
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3757
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3758
            ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3759

    
3760
            if (b == 0x17)
3761
                s->cc_op = CC_OP_EFLAGS;
3762
            break;
3763
        case 0x338: /* crc32 */
3764
        crc32:
3765
            b = modrm;
3766
            modrm = ldub_code(s->pc++);
3767
            reg = ((modrm >> 3) & 7) | rex_r;
3768

    
3769
            if (b != 0xf0 && b != 0xf1)
3770
                goto illegal_op;
3771
            if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3772
                goto illegal_op;
3773

    
3774
            if (b == 0xf0)
3775
                ot = OT_BYTE;
3776
            else if (b == 0xf1 && s->dflag != 2)
3777
                if (s->prefix & PREFIX_DATA)
3778
                    ot = OT_WORD;
3779
                else
3780
                    ot = OT_LONG;
3781
            else
3782
                ot = OT_QUAD;
3783

    
3784
            gen_op_mov_TN_reg(OT_LONG, 0, reg);
3785
            tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3786
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3787
            gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3788
                             cpu_T[0], tcg_const_i32(8 << ot));
3789

    
3790
            ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3791
            gen_op_mov_reg_T0(ot, reg);
3792
            break;
3793
        case 0x03a:
3794
        case 0x13a:
3795
            b = modrm;
3796
            modrm = ldub_code(s->pc++);
3797
            rm = modrm & 7;
3798
            reg = ((modrm >> 3) & 7) | rex_r;
3799
            mod = (modrm >> 6) & 3;
3800

    
3801
            sse_op2 = sse_op_table7[b].op[b1];
3802
            if (!sse_op2)
3803
                goto illegal_op;
3804
            if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3805
                goto illegal_op;
3806

    
3807
            if (sse_op2 == SSE_SPECIAL) {
3808
                ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3809
                rm = (modrm & 7) | REX_B(s);
3810
                if (mod != 3)
3811
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3812
                reg = ((modrm >> 3) & 7) | rex_r;
3813
                val = ldub_code(s->pc++);
3814
                switch (b) {
3815
                case 0x14: /* pextrb */
3816
                    tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3817
                                            xmm_regs[reg].XMM_B(val & 15)));
3818
                    if (mod == 3)
3819
                        gen_op_mov_reg_T0(ot, rm);
3820
                    else
3821
                        tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3822
                                        (s->mem_index >> 2) - 1);
3823
                    break;
3824
                case 0x15: /* pextrw */
3825
                    tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3826
                                            xmm_regs[reg].XMM_W(val & 7)));
3827
                    if (mod == 3)
3828
                        gen_op_mov_reg_T0(ot, rm);
3829
                    else
3830
                        tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3831
                                        (s->mem_index >> 2) - 1);
3832
                    break;
3833
                case 0x16:
3834
                    if (ot == OT_LONG) { /* pextrd */
3835
                        tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3836
                                        offsetof(CPUX86State,
3837
                                                xmm_regs[reg].XMM_L(val & 3)));
3838
                        tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3839
                        if (mod == 3)
3840
                            gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3841
                        else
3842
                            tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3843
                                            (s->mem_index >> 2) - 1);
3844
                    } else { /* pextrq */
3845
#ifdef TARGET_X86_64
3846
                        tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3847
                                        offsetof(CPUX86State,
3848
                                                xmm_regs[reg].XMM_Q(val & 1)));
3849
                        if (mod == 3)
3850
                            gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3851
                        else
3852
                            tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3853
                                            (s->mem_index >> 2) - 1);
3854
#else
3855
                        goto illegal_op;
3856
#endif
3857
                    }
3858
                    break;
3859
                case 0x17: /* extractps */
3860
                    tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3861
                                            xmm_regs[reg].XMM_L(val & 3)));
3862
                    if (mod == 3)
3863
                        gen_op_mov_reg_T0(ot, rm);
3864
                    else
3865
                        tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3866
                                        (s->mem_index >> 2) - 1);
3867
                    break;
3868
                case 0x20: /* pinsrb */
3869
                    if (mod == 3)
3870
                        gen_op_mov_TN_reg(OT_LONG, 0, rm);
3871
                    else
3872
                        tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3873
                                        (s->mem_index >> 2) - 1);
3874
                    tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3875
                                            xmm_regs[reg].XMM_B(val & 15)));
3876
                    break;
3877
                case 0x21: /* insertps */
3878
                    if (mod == 3) {
3879
                        tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3880
                                        offsetof(CPUX86State,xmm_regs[rm]
3881
                                                .XMM_L((val >> 6) & 3)));
3882
                    } else {
3883
                        tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3884
                                        (s->mem_index >> 2) - 1);
3885
                        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3886
                    }
3887
                    tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3888
                                    offsetof(CPUX86State,xmm_regs[reg]
3889
                                            .XMM_L((val >> 4) & 3)));
3890
                    if ((val >> 0) & 1)
3891
                        tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3892
                                        cpu_env, offsetof(CPUX86State,
3893
                                                xmm_regs[reg].XMM_L(0)));
3894
                    if ((val >> 1) & 1)
3895
                        tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3896
                                        cpu_env, offsetof(CPUX86State,
3897
                                                xmm_regs[reg].XMM_L(1)));
3898
                    if ((val >> 2) & 1)
3899
                        tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3900
                                        cpu_env, offsetof(CPUX86State,
3901
                                                xmm_regs[reg].XMM_L(2)));
3902
                    if ((val >> 3) & 1)
3903
                        tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3904
                                        cpu_env, offsetof(CPUX86State,
3905
                                                xmm_regs[reg].XMM_L(3)));
3906
                    break;
3907
                case 0x22:
3908
                    if (ot == OT_LONG) { /* pinsrd */
3909
                        if (mod == 3)
3910
                            gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3911
                        else
3912
                            tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3913
                                            (s->mem_index >> 2) - 1);
3914
                        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3915
                        tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3916
                                        offsetof(CPUX86State,
3917
                                                xmm_regs[reg].XMM_L(val & 3)));
3918
                    } else { /* pinsrq */
3919
#ifdef TARGET_X86_64
3920
                        if (mod == 3)
3921
                            gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3922
                        else
3923
                            tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3924
                                            (s->mem_index >> 2) - 1);
3925
                        tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3926
                                        offsetof(CPUX86State,
3927
                                                xmm_regs[reg].XMM_Q(val & 1)));
3928
#else
3929
                        goto illegal_op;
3930
#endif
3931
                    }
3932
                    break;
3933
                }
3934
                return;
3935
            }
3936

    
3937
            if (b1) {
3938
                op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3939
                if (mod == 3) {
3940
                    op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3941
                } else {
3942
                    op2_offset = offsetof(CPUX86State,xmm_t0);
3943
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3944
                    gen_ldo_env_A0(s->mem_index, op2_offset);
3945
                }
3946
            } else {
3947
                op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3948
                if (mod == 3) {
3949
                    op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3950
                } else {
3951
                    op2_offset = offsetof(CPUX86State,mmx_t0);
3952
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3953
                    gen_ldq_env_A0(s->mem_index, op2_offset);
3954
                }
3955
            }
3956
            val = ldub_code(s->pc++);
3957

    
3958
            if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3959
                s->cc_op = CC_OP_EFLAGS;
3960

    
3961
                if (s->dflag == 2)
3962
                    /* The helper must use entire 64-bit gp registers */
3963
                    val |= 1 << 8;
3964
            }
3965

    
3966
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3967
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3968
            ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3969
            break;
3970
        default:
3971
            goto illegal_op;
3972
        }
3973
    } else {
3974
        /* generic MMX or SSE operation */
3975
        switch(b) {
3976
        case 0x70: /* pshufx insn */
3977
        case 0xc6: /* pshufx insn */
3978
        case 0xc2: /* compare insns */
3979
            s->rip_offset = 1;
3980
            break;
3981
        default:
3982
            break;
3983
        }
3984
        if (is_xmm) {
3985
            op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3986
            if (mod != 3) {
3987
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3988
                op2_offset = offsetof(CPUX86State,xmm_t0);
3989
                if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3990
                                b == 0xc2)) {
3991
                    /* specific case for SSE single instructions */
3992
                    if (b1 == 2) {
3993
                        /* 32 bit access */
3994
                        gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3995
                        tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3996
                    } else {
3997
                        /* 64 bit access */
3998
                        gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3999
                    }
4000
                } else {
4001
                    gen_ldo_env_A0(s->mem_index, op2_offset);
4002
                }
4003
            } else {
4004
                rm = (modrm & 7) | REX_B(s);
4005
                op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4006
            }
4007
        } else {
4008
            op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4009
            if (mod != 3) {
4010
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4011
                op2_offset = offsetof(CPUX86State,mmx_t0);
4012
                gen_ldq_env_A0(s->mem_index, op2_offset);
4013
            } else {
4014
                rm = (modrm & 7);
4015
                op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4016
            }
4017
        }
4018
        switch(b) {
4019
        case 0x0f: /* 3DNow! data insns */
4020
            if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4021
                goto illegal_op;
4022
            val = ldub_code(s->pc++);
4023
            sse_op2 = sse_op_table5[val];
4024
            if (!sse_op2)
4025
                goto illegal_op;
4026
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4027
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4028
            ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4029
            break;
4030
        case 0x70: /* pshufx insn */
4031
        case 0xc6: /* pshufx insn */
4032
            val = ldub_code(s->pc++);
4033
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4034
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4035
            ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4036
            break;
4037
        case 0xc2:
4038
            /* compare insns */
4039
            val = ldub_code(s->pc++);
4040
            if (val >= 8)
4041
                goto illegal_op;
4042
            sse_op2 = sse_op_table4[val][b1];
4043
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4044
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4045
            ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4046
            break;
4047
        case 0xf7:
4048
            /* maskmov : we must prepare A0 */
4049
            if (mod != 3)
4050
                goto illegal_op;
4051
#ifdef TARGET_X86_64
4052
            if (s->aflag == 2) {
4053
                gen_op_movq_A0_reg(R_EDI);
4054
            } else
4055
#endif
4056
            {
4057
                gen_op_movl_A0_reg(R_EDI);
4058
                if (s->aflag == 0)
4059
                    gen_op_andl_A0_ffff();
4060
            }
4061
            gen_add_A0_ds_seg(s);
4062

    
4063
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4064
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4065
            ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
4066
            break;
4067
        default:
4068
            tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4069
            tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4070
            ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4071
            break;
4072
        }
4073
        if (b == 0x2e || b == 0x2f) {
4074
            s->cc_op = CC_OP_EFLAGS;
4075
        }
4076
    }
4077
}
4078

    
4079
/* convert one instruction. s->is_jmp is set if the translation must
4080
   be stopped. Return the next pc value */
4081
static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4082
{
4083
    int b, prefixes, aflag, dflag;
4084
    int shift, ot;
4085
    int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4086
    target_ulong next_eip, tval;
4087
    int rex_w, rex_r;
4088

    
4089
    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4090
        tcg_gen_debug_insn_start(pc_start);
4091
    s->pc = pc_start;
4092
    prefixes = 0;
4093
    aflag = s->code32;
4094
    dflag = s->code32;
4095
    s->override = -1;
4096
    rex_w = -1;
4097
    rex_r = 0;
4098
#ifdef TARGET_X86_64
4099
    s->rex_x = 0;
4100
    s->rex_b = 0;
4101
    x86_64_hregs = 0;
4102
#endif
4103
    s->rip_offset = 0; /* for relative ip address */
4104
 next_byte:
4105
    b = ldub_code(s->pc);
4106
    s->pc++;
4107
    /* check prefixes */
4108
#ifdef TARGET_X86_64
4109
    if (CODE64(s)) {
4110
        switch (b) {
4111
        case 0xf3:
4112
            prefixes |= PREFIX_REPZ;
4113
            goto next_byte;
4114
        case 0xf2:
4115
            prefixes |= PREFIX_REPNZ;
4116
            goto next_byte;
4117
        case 0xf0:
4118
            prefixes |= PREFIX_LOCK;
4119
            goto next_byte;
4120
        case 0x2e:
4121
            s->override = R_CS;
4122
            goto next_byte;
4123
        case 0x36:
4124
            s->override = R_SS;
4125
            goto next_byte;
4126
        case 0x3e:
4127
            s->override = R_DS;
4128
            goto next_byte;
4129
        case 0x26:
4130
            s->override = R_ES;
4131
            goto next_byte;
4132
        case 0x64:
4133
            s->override = R_FS;
4134
            goto next_byte;
4135
        case 0x65:
4136
            s->override = R_GS;
4137
            goto next_byte;
4138
        case 0x66:
4139
            prefixes |= PREFIX_DATA;
4140
            goto next_byte;
4141
        case 0x67:
4142
            prefixes |= PREFIX_ADR;
4143
            goto next_byte;
4144
        case 0x40 ... 0x4f:
4145
            /* REX prefix */
4146
            rex_w = (b >> 3) & 1;
4147
            rex_r = (b & 0x4) << 1;
4148
            s->rex_x = (b & 0x2) << 2;
4149
            REX_B(s) = (b & 0x1) << 3;
4150
            x86_64_hregs = 1; /* select uniform byte register addressing */
4151
            goto next_byte;
4152
        }
4153
        if (rex_w == 1) {
4154
            /* 0x66 is ignored if rex.w is set */
4155
            dflag = 2;
4156
        } else {
4157
            if (prefixes & PREFIX_DATA)
4158
                dflag ^= 1;
4159
        }
4160
        if (!(prefixes & PREFIX_ADR))
4161
            aflag = 2;
4162
    } else
4163
#endif
4164
    {
4165
        switch (b) {
4166
        case 0xf3:
4167
            prefixes |= PREFIX_REPZ;
4168
            goto next_byte;
4169
        case 0xf2:
4170
            prefixes |= PREFIX_REPNZ;
4171
            goto next_byte;
4172
        case 0xf0:
4173
            prefixes |= PREFIX_LOCK;
4174
            goto next_byte;
4175
        case 0x2e:
4176
            s->override = R_CS;
4177
            goto next_byte;
4178
        case 0x36:
4179
            s->override = R_SS;
4180
            goto next_byte;
4181
        case 0x3e:
4182
            s->override = R_DS;
4183
            goto next_byte;
4184
        case 0x26:
4185
            s->override = R_ES;
4186
            goto next_byte;
4187
        case 0x64:
4188
            s->override = R_FS;
4189
            goto next_byte;
4190
        case 0x65:
4191
            s->override = R_GS;
4192
            goto next_byte;
4193
        case 0x66:
4194
            prefixes |= PREFIX_DATA;
4195
            goto next_byte;
4196
        case 0x67:
4197
            prefixes |= PREFIX_ADR;
4198
            goto next_byte;
4199
        }
4200
        if (prefixes & PREFIX_DATA)
4201
            dflag ^= 1;
4202
        if (prefixes & PREFIX_ADR)
4203
            aflag ^= 1;
4204
    }
4205

    
4206
    s->prefix = prefixes;
4207
    s->aflag = aflag;
4208
    s->dflag = dflag;
4209

    
4210
    /* lock generation */
4211
    if (prefixes & PREFIX_LOCK)
4212
        gen_helper_lock();
4213

    
4214
    /* now check op code */
4215
 reswitch:
4216
    switch(b) {
4217
    case 0x0f:
4218
        /**************************/
4219
        /* extended op code */
4220
        b = ldub_code(s->pc++) | 0x100;
4221
        goto reswitch;
4222

    
4223
        /**************************/
4224
        /* arith & logic */
4225
    case 0x00 ... 0x05:
4226
    case 0x08 ... 0x0d:
4227
    case 0x10 ... 0x15:
4228
    case 0x18 ... 0x1d:
4229
    case 0x20 ... 0x25:
4230
    case 0x28 ... 0x2d:
4231
    case 0x30 ... 0x35:
4232
    case 0x38 ... 0x3d:
4233
        {
4234
            int op, f, val;
4235
            op = (b >> 3) & 7;
4236
            f = (b >> 1) & 3;
4237

    
4238
            if ((b & 1) == 0)
4239
                ot = OT_BYTE;
4240
            else
4241
                ot = dflag + OT_WORD;
4242

    
4243
            switch(f) {
4244
            case 0: /* OP Ev, Gv */
4245
                modrm = ldub_code(s->pc++);
4246
                reg = ((modrm >> 3) & 7) | rex_r;
4247
                mod = (modrm >> 6) & 3;
4248
                rm = (modrm & 7) | REX_B(s);
4249
                if (mod != 3) {
4250
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4251
                    opreg = OR_TMP0;
4252
                } else if (op == OP_XORL && rm == reg) {
4253
                xor_zero:
4254
                    /* xor reg, reg optimisation */
4255
                    gen_op_movl_T0_0();
4256
                    s->cc_op = CC_OP_LOGICB + ot;
4257
                    gen_op_mov_reg_T0(ot, reg);
4258
                    gen_op_update1_cc();
4259
                    break;
4260
                } else {
4261
                    opreg = rm;
4262
                }
4263
                gen_op_mov_TN_reg(ot, 1, reg);
4264
                gen_op(s, op, ot, opreg);
4265
                break;
4266
            case 1: /* OP Gv, Ev */
4267
                modrm = ldub_code(s->pc++);
4268
                mod = (modrm >> 6) & 3;
4269
                reg = ((modrm >> 3) & 7) | rex_r;
4270
                rm = (modrm & 7) | REX_B(s);
4271
                if (mod != 3) {
4272
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4273
                    gen_op_ld_T1_A0(ot + s->mem_index);
4274
                } else if (op == OP_XORL && rm == reg) {
4275
                    goto xor_zero;
4276
                } else {
4277
                    gen_op_mov_TN_reg(ot, 1, rm);
4278
                }
4279
                gen_op(s, op, ot, reg);
4280
                break;
4281
            case 2: /* OP A, Iv */
4282
                val = insn_get(s, ot);
4283
                gen_op_movl_T1_im(val);
4284
                gen_op(s, op, ot, OR_EAX);
4285
                break;
4286
            }
4287
        }
4288
        break;
4289

    
4290
    case 0x82:
4291
        if (CODE64(s))
4292
            goto illegal_op;
4293
    case 0x80: /* GRP1 */
4294
    case 0x81:
4295
    case 0x83:
4296
        {
4297
            int val;
4298

    
4299
            if ((b & 1) == 0)
4300
                ot = OT_BYTE;
4301
            else
4302
                ot = dflag + OT_WORD;
4303

    
4304
            modrm = ldub_code(s->pc++);
4305
            mod = (modrm >> 6) & 3;
4306
            rm = (modrm & 7) | REX_B(s);
4307
            op = (modrm >> 3) & 7;
4308

    
4309
            if (mod != 3) {
4310
                if (b == 0x83)
4311
                    s->rip_offset = 1;
4312
                else
4313
                    s->rip_offset = insn_const_size(ot);
4314
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4315
                opreg = OR_TMP0;
4316
            } else {
4317
                opreg = rm;
4318
            }
4319

    
4320
            switch(b) {
4321
            default:
4322
            case 0x80:
4323
            case 0x81:
4324
            case 0x82:
4325
                val = insn_get(s, ot);
4326
                break;
4327
            case 0x83:
4328
                val = (int8_t)insn_get(s, OT_BYTE);
4329
                break;
4330
            }
4331
            gen_op_movl_T1_im(val);
4332
            gen_op(s, op, ot, opreg);
4333
        }
4334
        break;
4335

    
4336
        /**************************/
4337
        /* inc, dec, and other misc arith */
4338
    case 0x40 ... 0x47: /* inc Gv */
4339
        ot = dflag ? OT_LONG : OT_WORD;
4340
        gen_inc(s, ot, OR_EAX + (b & 7), 1);
4341
        break;
4342
    case 0x48 ... 0x4f: /* dec Gv */
4343
        ot = dflag ? OT_LONG : OT_WORD;
4344
        gen_inc(s, ot, OR_EAX + (b & 7), -1);
4345
        break;
4346
    case 0xf6: /* GRP3 */
4347
    case 0xf7:
4348
        if ((b & 1) == 0)
4349
            ot = OT_BYTE;
4350
        else
4351
            ot = dflag + OT_WORD;
4352

    
4353
        modrm = ldub_code(s->pc++);
4354
        mod = (modrm >> 6) & 3;
4355
        rm = (modrm & 7) | REX_B(s);
4356
        op = (modrm >> 3) & 7;
4357
        if (mod != 3) {
4358
            if (op == 0)
4359
                s->rip_offset = insn_const_size(ot);
4360
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4361
            gen_op_ld_T0_A0(ot + s->mem_index);
4362
        } else {
4363
            gen_op_mov_TN_reg(ot, 0, rm);
4364
        }
4365

    
4366
        switch(op) {
4367
        case 0: /* test */
4368
            val = insn_get(s, ot);
4369
            gen_op_movl_T1_im(val);
4370
            gen_op_testl_T0_T1_cc();
4371
            s->cc_op = CC_OP_LOGICB + ot;
4372
            break;
4373
        case 2: /* not */
4374
            tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4375
            if (mod != 3) {
4376
                gen_op_st_T0_A0(ot + s->mem_index);
4377
            } else {
4378
                gen_op_mov_reg_T0(ot, rm);
4379
            }
4380
            break;
4381
        case 3: /* neg */
4382
            tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4383
            if (mod != 3) {
4384
                gen_op_st_T0_A0(ot + s->mem_index);
4385
            } else {
4386
                gen_op_mov_reg_T0(ot, rm);
4387
            }
4388
            gen_op_update_neg_cc();
4389
            s->cc_op = CC_OP_SUBB + ot;
4390
            break;
4391
        case 4: /* mul */
4392
            switch(ot) {
4393
            case OT_BYTE:
4394
                gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4395
                tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4396
                tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4397
                /* XXX: use 32 bit mul which could be faster */
4398
                tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4399
                gen_op_mov_reg_T0(OT_WORD, R_EAX);
4400
                tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4401
                tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4402
                s->cc_op = CC_OP_MULB;
4403
                break;
4404
            case OT_WORD:
4405
                gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4406
                tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4407
                tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4408
                /* XXX: use 32 bit mul which could be faster */
4409
                tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4410
                gen_op_mov_reg_T0(OT_WORD, R_EAX);
4411
                tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4412
                tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4413
                gen_op_mov_reg_T0(OT_WORD, R_EDX);
4414
                tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4415
                s->cc_op = CC_OP_MULW;
4416
                break;
4417
            default:
4418
            case OT_LONG:
4419
#ifdef TARGET_X86_64
4420
                gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4421
                tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4422
                tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4423
                tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4424
                gen_op_mov_reg_T0(OT_LONG, R_EAX);
4425
                tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4426
                tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4427
                gen_op_mov_reg_T0(OT_LONG, R_EDX);
4428
                tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4429
#else
4430
                {
4431
                    TCGv_i64 t0, t1;
4432
                    t0 = tcg_temp_new_i64();
4433
                    t1 = tcg_temp_new_i64();
4434
                    gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4435
                    tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4436
                    tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4437
                    tcg_gen_mul_i64(t0, t0, t1);
4438
                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4439
                    gen_op_mov_reg_T0(OT_LONG, R_EAX);
4440
                    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4441
                    tcg_gen_shri_i64(t0, t0, 32);
4442
                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4443
                    gen_op_mov_reg_T0(OT_LONG, R_EDX);
4444
                    tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4445
                }
4446
#endif
4447
                s->cc_op = CC_OP_MULL;
4448
                break;
4449
#ifdef TARGET_X86_64
4450
            case OT_QUAD:
4451
                gen_helper_mulq_EAX_T0(cpu_T[0]);
4452
                s->cc_op = CC_OP_MULQ;
4453
                break;
4454
#endif
4455
            }
4456
            break;
4457
        case 5: /* imul */
4458
            switch(ot) {
4459
            case OT_BYTE:
4460
                gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4461
                tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4462
                tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4463
                /* XXX: use 32 bit mul which could be faster */
4464
                tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4465
                gen_op_mov_reg_T0(OT_WORD, R_EAX);
4466
                tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4467
                tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4468
                tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4469
                s->cc_op = CC_OP_MULB;
4470
                break;
4471
            case OT_WORD:
4472
                gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4473
                tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4474
                tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4475
                /* XXX: use 32 bit mul which could be faster */
4476
                tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4477
                gen_op_mov_reg_T0(OT_WORD, R_EAX);
4478
                tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4479
                tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4480
                tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4481
                tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4482
                gen_op_mov_reg_T0(OT_WORD, R_EDX);
4483
                s->cc_op = CC_OP_MULW;
4484
                break;
4485
            default:
4486
            case OT_LONG:
4487
#ifdef TARGET_X86_64
4488
                gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4489
                tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4490
                tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4491
                tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4492
                gen_op_mov_reg_T0(OT_LONG, R_EAX);
4493
                tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4494
                tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4495
                tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4496
                tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4497
                gen_op_mov_reg_T0(OT_LONG, R_EDX);
4498
#else
4499
                {
4500
                    TCGv_i64 t0, t1;
4501
                    t0 = tcg_temp_new_i64();
4502
                    t1 = tcg_temp_new_i64();
4503
                    gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4504
                    tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4505
                    tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4506
                    tcg_gen_mul_i64(t0, t0, t1);
4507
                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4508
                    gen_op_mov_reg_T0(OT_LONG, R_EAX);
4509
                    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4510
                    tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4511
                    tcg_gen_shri_i64(t0, t0, 32);
4512
                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4513
                    gen_op_mov_reg_T0(OT_LONG, R_EDX);
4514
                    tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4515
                }
4516
#endif
4517
                s->cc_op = CC_OP_MULL;
4518
                break;
4519
#ifdef TARGET_X86_64
4520
            case OT_QUAD:
4521
                gen_helper_imulq_EAX_T0(cpu_T[0]);
4522
                s->cc_op = CC_OP_MULQ;
4523
                break;
4524
#endif
4525
            }
4526
            break;
4527
        case 6: /* div */
4528
            switch(ot) {
4529
            case OT_BYTE:
4530
                gen_jmp_im(pc_start - s->cs_base);
4531
                gen_helper_divb_AL(cpu_T[0]);
4532
                break;
4533
            case OT_WORD:
4534
                gen_jmp_im(pc_start - s->cs_base);
4535
                gen_helper_divw_AX(cpu_T[0]);
4536
                break;
4537
            default:
4538
            case OT_LONG:
4539
                gen_jmp_im(pc_start - s->cs_base);
4540
                gen_helper_divl_EAX(cpu_T[0]);
4541
                break;
4542
#ifdef TARGET_X86_64
4543
            case OT_QUAD:
4544
                gen_jmp_im(pc_start - s->cs_base);
4545
                gen_helper_divq_EAX(cpu_T[0]);
4546
                break;
4547
#endif
4548
            }
4549
            break;
4550
        case 7: /* idiv */
4551
            switch(ot) {
4552
            case OT_BYTE:
4553
                gen_jmp_im(pc_start - s->cs_base);
4554
                gen_helper_idivb_AL(cpu_T[0]);
4555
                break;
4556
            case OT_WORD:
4557
                gen_jmp_im(pc_start - s->cs_base);
4558
                gen_helper_idivw_AX(cpu_T[0]);
4559
                break;
4560
            default:
4561
            case OT_LONG:
4562
                gen_jmp_im(pc_start - s->cs_base);
4563
                gen_helper_idivl_EAX(cpu_T[0]);
4564
                break;
4565
#ifdef TARGET_X86_64
4566
            case OT_QUAD:
4567
                gen_jmp_im(pc_start - s->cs_base);
4568
                gen_helper_idivq_EAX(cpu_T[0]);
4569
                break;
4570
#endif
4571
            }
4572
            break;
4573
        default:
4574
            goto illegal_op;
4575
        }
4576
        break;
4577

    
4578
    case 0xfe: /* GRP4 */
4579
    case 0xff: /* GRP5 */
4580
        if ((b & 1) == 0)
4581
            ot = OT_BYTE;
4582
        else
4583
            ot = dflag + OT_WORD;
4584

    
4585
        modrm = ldub_code(s->pc++);
4586
        mod = (modrm >> 6) & 3;
4587
        rm = (modrm & 7) | REX_B(s);
4588
        op = (modrm >> 3) & 7;
4589
        if (op >= 2 && b == 0xfe) {
4590
            goto illegal_op;
4591
        }
4592
        if (CODE64(s)) {
4593
            if (op == 2 || op == 4) {
4594
                /* operand size for jumps is 64 bit */
4595
                ot = OT_QUAD;
4596
            } else if (op == 3 || op == 5) {
4597
                ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4598
            } else if (op == 6) {
4599
                /* default push size is 64 bit */
4600
                ot = dflag ? OT_QUAD : OT_WORD;
4601
            }
4602
        }
4603
        if (mod != 3) {
4604
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4605
            if (op >= 2 && op != 3 && op != 5)
4606
                gen_op_ld_T0_A0(ot + s->mem_index);
4607
        } else {
4608
            gen_op_mov_TN_reg(ot, 0, rm);
4609
        }
4610

    
4611
        switch(op) {
4612
        case 0: /* inc Ev */
4613
            if (mod != 3)
4614
                opreg = OR_TMP0;
4615
            else
4616
                opreg = rm;
4617
            gen_inc(s, ot, opreg, 1);
4618
            break;
4619
        case 1: /* dec Ev */
4620
            if (mod != 3)
4621
                opreg = OR_TMP0;
4622
            else
4623
                opreg = rm;
4624
            gen_inc(s, ot, opreg, -1);
4625
            break;
4626
        case 2: /* call Ev */
4627
            /* XXX: optimize if memory (no 'and' is necessary) */
4628
            if (s->dflag == 0)
4629
                gen_op_andl_T0_ffff();
4630
            next_eip = s->pc - s->cs_base;
4631
            gen_movtl_T1_im(next_eip);
4632
            gen_push_T1(s);
4633
            gen_op_jmp_T0();
4634
            gen_eob(s);
4635
            break;
4636
        case 3: /* lcall Ev */
4637
            gen_op_ld_T1_A0(ot + s->mem_index);
4638
            gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4639
            gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4640
        do_lcall:
4641
            if (s->pe && !s->vm86) {
4642
                if (s->cc_op != CC_OP_DYNAMIC)
4643
                    gen_op_set_cc_op(s->cc_op);
4644
                gen_jmp_im(pc_start - s->cs_base);
4645
                tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4646
                gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4647
                                           tcg_const_i32(dflag), 
4648
                                           tcg_const_i32(s->pc - pc_start));
4649
            } else {
4650
                tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4651
                gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4652
                                      tcg_const_i32(dflag), 
4653
                                      tcg_const_i32(s->pc - s->cs_base));
4654
            }
4655
            gen_eob(s);
4656
            break;
4657
        case 4: /* jmp Ev */
4658
            if (s->dflag == 0)
4659
                gen_op_andl_T0_ffff();
4660
            gen_op_jmp_T0();
4661
            gen_eob(s);
4662
            break;
4663
        case 5: /* ljmp Ev */
4664
            gen_op_ld_T1_A0(ot + s->mem_index);
4665
            gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4666
            gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4667
        do_ljmp:
4668
            if (s->pe && !s->vm86) {
4669
                if (s->cc_op != CC_OP_DYNAMIC)
4670
                    gen_op_set_cc_op(s->cc_op);
4671
                gen_jmp_im(pc_start - s->cs_base);
4672
                tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4673
                gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4674
                                          tcg_const_i32(s->pc - pc_start));
4675
            } else {
4676
                gen_op_movl_seg_T0_vm(R_CS);
4677
                gen_op_movl_T0_T1();
4678
                gen_op_jmp_T0();
4679
            }
4680
            gen_eob(s);
4681
            break;
4682
        case 6: /* push Ev */
4683
            gen_push_T0(s);
4684
            break;
4685
        default:
4686
            goto illegal_op;
4687
        }
4688
        break;
4689

    
4690
    case 0x84: /* test Ev, Gv */
4691
    case 0x85:
4692
        if ((b & 1) == 0)
4693
            ot = OT_BYTE;
4694
        else
4695
            ot = dflag + OT_WORD;
4696

    
4697
        modrm = ldub_code(s->pc++);
4698
        reg = ((modrm >> 3) & 7) | rex_r;
4699

    
4700
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4701
        gen_op_mov_TN_reg(ot, 1, reg);
4702
        gen_op_testl_T0_T1_cc();
4703
        s->cc_op = CC_OP_LOGICB + ot;
4704
        break;
4705

    
4706
    case 0xa8: /* test eAX, Iv */
4707
    case 0xa9:
4708
        if ((b & 1) == 0)
4709
            ot = OT_BYTE;
4710
        else
4711
            ot = dflag + OT_WORD;
4712
        val = insn_get(s, ot);
4713

    
4714
        gen_op_mov_TN_reg(ot, 0, OR_EAX);
4715
        gen_op_movl_T1_im(val);
4716
        gen_op_testl_T0_T1_cc();
4717
        s->cc_op = CC_OP_LOGICB + ot;
4718
        break;
4719

    
4720
    case 0x98: /* CWDE/CBW */
4721
#ifdef TARGET_X86_64
4722
        if (dflag == 2) {
4723
            gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4724
            tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4725
            gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4726
        } else
4727
#endif
4728
        if (dflag == 1) {
4729
            gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4730
            tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4731
            gen_op_mov_reg_T0(OT_LONG, R_EAX);
4732
        } else {
4733
            gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4734
            tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4735
            gen_op_mov_reg_T0(OT_WORD, R_EAX);
4736
        }
4737
        break;
4738
    case 0x99: /* CDQ/CWD */
4739
#ifdef TARGET_X86_64
4740
        if (dflag == 2) {
4741
            gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4742
            tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4743
            gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4744
        } else
4745
#endif
4746
        if (dflag == 1) {
4747
            gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4748
            tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4749
            tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4750
            gen_op_mov_reg_T0(OT_LONG, R_EDX);
4751
        } else {
4752
            gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4753
            tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4754
            tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4755
            gen_op_mov_reg_T0(OT_WORD, R_EDX);
4756
        }
4757
        break;
4758
    case 0x1af: /* imul Gv, Ev */
4759
    case 0x69: /* imul Gv, Ev, I */
4760
    case 0x6b:
4761
        ot = dflag + OT_WORD;
4762
        modrm = ldub_code(s->pc++);
4763
        reg = ((modrm >> 3) & 7) | rex_r;
4764
        if (b == 0x69)
4765
            s->rip_offset = insn_const_size(ot);
4766
        else if (b == 0x6b)
4767
            s->rip_offset = 1;
4768
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4769
        if (b == 0x69) {
4770
            val = insn_get(s, ot);
4771
            gen_op_movl_T1_im(val);
4772
        } else if (b == 0x6b) {
4773
            val = (int8_t)insn_get(s, OT_BYTE);
4774
            gen_op_movl_T1_im(val);
4775
        } else {
4776
            gen_op_mov_TN_reg(ot, 1, reg);
4777
        }
4778

    
4779
#ifdef TARGET_X86_64
4780
        if (ot == OT_QUAD) {
4781
            gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4782
        } else
4783
#endif
4784
        if (ot == OT_LONG) {
4785
#ifdef TARGET_X86_64
4786
                tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4787
                tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4788
                tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4789
                tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4790
                tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4791
                tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4792
#else
4793
                {
4794
                    TCGv_i64 t0, t1;
4795
                    t0 = tcg_temp_new_i64();
4796
                    t1 = tcg_temp_new_i64();
4797
                    tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4798
                    tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4799
                    tcg_gen_mul_i64(t0, t0, t1);
4800
                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4801
                    tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4802
                    tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4803
                    tcg_gen_shri_i64(t0, t0, 32);
4804
                    tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4805
                    tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4806
                }
4807
#endif
4808
        } else {
4809
            tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4810
            tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4811
            /* XXX: use 32 bit mul which could be faster */
4812
            tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4813
            tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4814
            tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4815
            tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4816
        }
4817
        gen_op_mov_reg_T0(ot, reg);
4818
        s->cc_op = CC_OP_MULB + ot;
4819
        break;
4820
    case 0x1c0:
4821
    case 0x1c1: /* xadd Ev, Gv */
4822
        if ((b & 1) == 0)
4823
            ot = OT_BYTE;
4824
        else
4825
            ot = dflag + OT_WORD;
4826
        modrm = ldub_code(s->pc++);
4827
        reg = ((modrm >> 3) & 7) | rex_r;
4828
        mod = (modrm >> 6) & 3;
4829
        if (mod == 3) {
4830
            rm = (modrm & 7) | REX_B(s);
4831
            gen_op_mov_TN_reg(ot, 0, reg);
4832
            gen_op_mov_TN_reg(ot, 1, rm);
4833
            gen_op_addl_T0_T1();
4834
            gen_op_mov_reg_T1(ot, reg);
4835
            gen_op_mov_reg_T0(ot, rm);
4836
        } else {
4837
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4838
            gen_op_mov_TN_reg(ot, 0, reg);
4839
            gen_op_ld_T1_A0(ot + s->mem_index);
4840
            gen_op_addl_T0_T1();
4841
            gen_op_st_T0_A0(ot + s->mem_index);
4842
            gen_op_mov_reg_T1(ot, reg);
4843
        }
4844
        gen_op_update2_cc();
4845
        s->cc_op = CC_OP_ADDB + ot;
4846
        break;
4847
    case 0x1b0:
4848
    case 0x1b1: /* cmpxchg Ev, Gv */
4849
        {
4850
            int label1, label2;
4851
            TCGv t0, t1, t2, a0;
4852

    
4853
            if ((b & 1) == 0)
4854
                ot = OT_BYTE;
4855
            else
4856
                ot = dflag + OT_WORD;
4857
            modrm = ldub_code(s->pc++);
4858
            reg = ((modrm >> 3) & 7) | rex_r;
4859
            mod = (modrm >> 6) & 3;
4860
            t0 = tcg_temp_local_new();
4861
            t1 = tcg_temp_local_new();
4862
            t2 = tcg_temp_local_new();
4863
            a0 = tcg_temp_local_new();
4864
            gen_op_mov_v_reg(ot, t1, reg);
4865
            if (mod == 3) {
4866
                rm = (modrm & 7) | REX_B(s);
4867
                gen_op_mov_v_reg(ot, t0, rm);
4868
            } else {
4869
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4870
                tcg_gen_mov_tl(a0, cpu_A0);
4871
                gen_op_ld_v(ot + s->mem_index, t0, a0);
4872
                rm = 0; /* avoid warning */
4873
            }
4874
            label1 = gen_new_label();
4875
            tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
4876
            gen_extu(ot, t2);
4877
            tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4878
            if (mod == 3) {
4879
                label2 = gen_new_label();
4880
                gen_op_mov_reg_v(ot, R_EAX, t0);
4881
                tcg_gen_br(label2);
4882
                gen_set_label(label1);
4883
                gen_op_mov_reg_v(ot, rm, t1);
4884
                gen_set_label(label2);
4885
            } else {
4886
                tcg_gen_mov_tl(t1, t0);
4887
                gen_op_mov_reg_v(ot, R_EAX, t0);
4888
                gen_set_label(label1);
4889
                /* always store */
4890
                gen_op_st_v(ot + s->mem_index, t1, a0);
4891
            }
4892
            tcg_gen_mov_tl(cpu_cc_src, t0);
4893
            tcg_gen_mov_tl(cpu_cc_dst, t2);
4894
            s->cc_op = CC_OP_SUBB + ot;
4895
            tcg_temp_free(t0);
4896
            tcg_temp_free(t1);
4897
            tcg_temp_free(t2);
4898
            tcg_temp_free(a0);
4899
        }
4900
        break;
4901
    case 0x1c7: /* cmpxchg8b */
4902
        modrm = ldub_code(s->pc++);
4903
        mod = (modrm >> 6) & 3;
4904
        if ((mod == 3) || ((modrm & 0x38) != 0x8))
4905
            goto illegal_op;
4906
#ifdef TARGET_X86_64
4907
        if (dflag == 2) {
4908
            if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4909
                goto illegal_op;
4910
            gen_jmp_im(pc_start - s->cs_base);
4911
            if (s->cc_op != CC_OP_DYNAMIC)
4912
                gen_op_set_cc_op(s->cc_op);
4913
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4914
            gen_helper_cmpxchg16b(cpu_A0);
4915
        } else
4916
#endif        
4917
        {
4918
            if (!(s->cpuid_features & CPUID_CX8))
4919
                goto illegal_op;
4920
            gen_jmp_im(pc_start - s->cs_base);
4921
            if (s->cc_op != CC_OP_DYNAMIC)
4922
                gen_op_set_cc_op(s->cc_op);
4923
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4924
            gen_helper_cmpxchg8b(cpu_A0);
4925
        }
4926
        s->cc_op = CC_OP_EFLAGS;
4927
        break;
4928

    
4929
        /**************************/
4930
        /* push/pop */
4931
    case 0x50 ... 0x57: /* push */
4932
        gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4933
        gen_push_T0(s);
4934