Archipelago » qemu

    __attribute__ ((__noreturn__));

extern CPUState *first_cpu;

extern CPUState *cpu_single_env;

#define CPU_INTERRUPT_EXIT   0x01 /* wants exit from main loop */

#define CPU_INTERRUPT_HARD   0x02 /* hardware interrupt pending */

                   sizeof(target_phys_addr_t))];

} CPUTLBEntry;

#define CPU_TEMP_BUF_NLONGS 128

#define CPU_COMMON                                                      \

    struct TranslationBlock *current_tb; /* currently executing TB  */  \

    /* soft mmu support */                                              \

       context) */                                                      \

    int halted; /* TRUE if the CPU is in suspend state */               \

    /* The meaning of the MMU modes is defined in the target code. */   \

    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \

    /* buffer for temporaries in the code generator */                  \

    long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \

                                                                        \

    /* from this point: preserved by CPU reset */                       \

    /* ice debug support */                                             \

    target_ulong breakpoints[MAX_BREAKPOINTS];                          \

    longjmp(env->jmp_env, 1);

}

static TranslationBlock *tb_find_slow(target_ulong pc,

                                      target_ulong cs_base,

                                      uint64_t flags)

{

    TranslationBlock *tb, **ptb1;

    unsigned int h;

    target_ulong phys_pc, phys_page1, phys_page2, virt_page2;

    tb_invalidated_flag = 0;

        ptb1 = &tb->phys_hash_next;

    }

 not_found:

 found:

    /* we add the TB in the virtual pc hash table */

                       of memory exceptions while generating the code, we

                       must recompute the hash index here */

                    next_tb = 0;

                }

#ifdef DEBUG_EXEC

                if ((loglevel & CPU_LOG_EXEC)) {

                }

                }

                spin_unlock(&tb_lock);

                env->current_tb = tb;

                /* execute the generated code */

#if defined(__sparc__) && !defined(HOST_SOLARIS)

#undef env

#define env cpu_single_env

#endif

                /* reset soft MMU for next block (it can currently

                   only be set by a memory fault) */

#if defined(USE_KQEMU)

#define DISAS_UPDATE  2 /* cpu state was modified dynamically */

#define DISAS_TB_JUMP 3 /* only pc was modified statically */

/* XXX: make safe guess about sizes */

#define MAX_OP_PER_INSTR 64

extern target_ulong gen_opc_npc[OPC_BUF_SIZE];

extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];

extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];

extern target_ulong gen_opc_jump_pc[2];

extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

                           CPUState *env, unsigned long searched_pc,

                           void *puc);

void cpu_resume_from_signal(CPUState *env1, void *puc);

void cpu_exec_init(CPUState *env);

int page_unprotect(target_ulong address, unsigned long pc, void *puc);

void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,

#define USE_DIRECT_JUMP

#endif

    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */

    target_ulong cs_base; /* CS base for this block */

    uint64_t flags; /* flags defining in which context the code was generated */

    uint16_t size;      /* size of target code for this block (1 <=

                           size <= TARGET_PAGE_SIZE) */

    uint16_t cflags;    /* compile flags */

    uint8_t *tc_ptr;    /* pointer to the translated code */

    /* next matching tb for physical address. */

       jmp_first */

    struct TranslationBlock *jmp_next[2];

    struct TranslationBlock *jmp_first;

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)

{

}

TranslationBlock *tb_alloc(target_ulong pc);

void tb_flush(CPUState *env);

void tb_link_phys(TranslationBlock *tb,

                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t *code_gen_ptr;

    }

    return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;

}

#endif

#ifdef USE_KQEMU

/* current CPU in the current thread. It is only valid inside

   cpu_exec() */

CPUState *cpu_single_env;

typedef struct PageDesc {

    /* list of TBs intersecting this ram page */

    tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));

}

{

    CPUState *env;

    PageDesc *p;

    }

}

{

    TranslationBlock *tb;

    uint8_t *tc_ptr;

        tb_flush(env);

        /* cannot fail at this point */

        tb = tb_alloc(pc);

    }

    tc_ptr = code_gen_ptr;

    tb->tc_ptr = tc_ptr;

        phys_page2 = get_phys_addr_code(env, virt_page2);

    }

    tb_link_phys(tb, phys_pc, phys_page2);

}

/* invalidate all TBs which intersect with the target physical page

   starting in range [start;end[. NOTE: start and end must refer to

            if (current_tb_not_found) {

                current_tb_not_found = 0;

                current_tb = NULL;

                    /* now we have a real cpu fault */

                }

            }

            if (current_tb == tb &&

                /* If we are modifying the current TB, we must stop

                its execution. We could be more precise by checking

                that the modification is after the current PC, but it

                current_tb_modified = 1;

                cpu_restore_state(current_tb, env,

#if defined(TARGET_I386)

                current_flags = env->hflags;

                current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));

    if (!p->first_tb) {

        invalidate_page_bitmap(p);

        if (is_cpu_write_access) {

        }

    }

#endif

           modifying the memory. It will ensure that it cannot modify

           itself */

        env->current_tb = NULL;

        cpu_resume_from_signal(env, NULL);

    }

#endif

    if (1) {

        if (loglevel) {

            fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",

                   cpu_single_env->eip,

                   cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);

        }

        tb = (TranslationBlock *)((long)tb & ~3);

#ifdef TARGET_HAS_PRECISE_SMC

        if (current_tb == tb &&

                /* If we are modifying the current TB, we must stop

                   its execution. We could be more precise by checking

                   that the modification is after the current PC, but it

           modifying the memory. It will ensure that it cannot modify

           itself */

        env->current_tb = NULL;

        cpu_resume_from_signal(env, puc);

    }

#endif

    return tb;

}

/* add a new TB and link it to the physical page tables. phys_page2 is

   (-1) to indicate that only one page contains the TB. */

void tb_link_phys(TranslationBlock *tb,

    TranslationBlock *tb;

    static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;

#endif

    /* FIXME: This is probably not threadsafe.  A different thread could

       be in the mittle of a read-modify-write operation.  */

    env->interrupt_request |= mask;

       emulation this often isn't actually as bad as it sounds.  Often

       signals are used primarily to interrupt blocking syscalls.  */

#else

    }

#endif

}

    /* we remove the notdirty callback only if the code has been

       flushed */

    if (dirty_flags == 0xff)

}

static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,

    /* we remove the notdirty callback only if the code has been

       flushed */

    if (dirty_flags == 0xff)

}

static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,

    /* we remove the notdirty callback only if the code has been

       flushed */

    if (dirty_flags == 0xff)

}

static CPUReadMemoryFunc *error_mem_read[3] = {

    target_ulong vaddr;

    int i;

    for (i = 0; i < env->nb_watchpoints; i++) {

        if (vaddr == env->watchpoint[i].vaddr

                && (env->watchpoint[i].type & flags)) {

    return 0;

}

void dump_exec_info(FILE *f,

                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...))

{

    if (env->CP0_Cause & (1 << CP0Ca_DC))

        return;

    cpu_mips_timer_update(env);

    if (env->insn_flags & ISA_MIPS32R2)

        env->CP0_Cause |= 1 << CP0Ca_TI;

    qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);

Note that this allows guest direct access to the host filesystem,

so should only be used with trusted guest OS.

@end table

@c man end

                                                        int mmu_idx,

                                                        void *retaddr);

static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,

{

    DATA_TYPE res;

    int index;

    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;

#if SHIFT <= 2

    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);

            /* IO access */

            if ((addr & (DATA_SIZE - 1)) != 0)

                goto do_unaligned_access;

            addend = env->iotlb[mmu_idx][index];

        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {

            /* slow unaligned access (it spans two pages or IO) */

        do_unaligned_access:

            /* IO access */

            if ((addr & (DATA_SIZE - 1)) != 0)

                goto do_unaligned_access;

            addend = env->iotlb[mmu_idx][index];

        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {

        do_unaligned_access:

            /* slow unaligned access (it spans two pages) */

    int index;

    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;

#if SHIFT <= 2

    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);

#else

void pal_init (CPUState *env);

void call_pal (CPUState *env, int palcode);

#endif /* !defined (__CPU_ALPHA_H__) */

    uint32_t amask;

};

static always_inline void gen_op_nop (void)

{

#if defined(GENERATE_NOP)

    uint16_t *gen_opc_end;

    int j, lj = -1;

    int ret;

    pc_start = tb->pc;

    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;

    ctx.mem_idx = ((env->ps >> 3) & 3);

    ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;

#endif

    for (ret = 0; ret == 0;) {

        if (env->nb_breakpoints > 0) {

            for(j = 0; j < env->nb_breakpoints; j++) {

                    gen_opc_instr_start[lj++] = 0;

                gen_opc_pc[lj] = ctx.pc;

                gen_opc_instr_start[lj] = 1;

            }

        }

#if defined ALPHA_DEBUG_DISAS

        insn_count++;

        if (logfile != NULL) {

            fprintf(logfile, "opcode %08x %d\n", insn, insn_count);

        }

#endif

        ctx.pc += 4;

        ret = translate_one(ctxp, insn);

        if (ret != 0)

         * generation

         */

        if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||

            break;

        }

#if defined (DO_SINGLE_STEP)

#if defined (DO_TB_FLUSH)

    gen_op_tb_flush();

#endif

    /* Generate the return instruction */

    tcg_gen_exit_tb(0);

    *gen_opc_ptr = INDEX_op_end;

    if (search_pc) {

        j = gen_opc_ptr - gen_opc_buf;

            gen_opc_instr_start[lj++] = 0;

    } else {

        tb->size = ctx.pc - pc_start;

    }

#if defined ALPHA_DEBUG_DISAS

    if (loglevel & CPU_LOG_TB_CPU) {

    if (!env)

        return NULL;

    cpu_exec_init(env);

    tlb_flush(env, 1);

    /* XXX: should not be hardcoded */

    env->implver = IMPLVER_2106x;

}

#endif

#include "cpu-all.h"

#endif

static TCGv cpu_T[2];

static TCGv cpu_F0s, cpu_F1s, cpu_F0d, cpu_F1d;

/* initialize TCG globals.  */

void arm_translate_init(void)

{

    int j, lj;

    target_ulong pc_start;

    uint32_t next_page_start;

    /* generate intermediate code */

    num_temps = 0;

    cpu_M0 = tcg_temp_new(TCG_TYPE_I64);

    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    lj = -1;

    /* Reset the conditional execution bits immediately. This avoids

       complications trying to do it at the end of the block.  */

    if (env->condexec_bits)

            }

            gen_opc_pc[lj] = dc->pc;

            gen_opc_instr_start[lj] = 1;

        }

        if (env->thumb) {

            disas_thumb_insn(env, dc);

            if (dc->condexec_mask) {

         * Otherwise the subsequent code could get translated several times.

         * Also stop translation when a page boundary is reached.  This

         * ensures prefech aborts occur at the right place.  */

    } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&

             !env->singlestep_enabled &&

    /* At this stage dc->condjmp will only be set when the skipped

       instruction was a conditional branch or trap, and the PC has

            dc->condjmp = 0;

        }

    }

done_generating:

    *gen_opc_ptr = INDEX_op_end;

#ifdef DEBUG_DISAS

            gen_opc_instr_start[lj++] = 0;

    } else {

        tb->size = dc->pc - pc_start;

    }

    return 0;

}

#define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5

#define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6

#include "cpu-all.h"

#endif

TCGv env_btarget;

TCGv env_pc;

/* This is the state at translation time.  */

typedef struct DisasContext {

	CPUState *env;

	struct DisasContext *dc = &ctx;

	uint32_t next_page_start;

	target_ulong npc;

	if (!logfile)

		logfile = stderr;

	next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

	lj = -1;

	do

	{

		check_breakpoint(env, dc);

			else

				gen_opc_pc[lj] = dc->pc;

			gen_opc_instr_start[lj] = 1;

		}

		/* Pretty disas.  */

			DIS(fprintf(logfile, "%x ", dc->pc));

		}

		dc->clear_x = 1;

		if (unlikely(loglevel & CPU_LOG_TB_OP))

			tcg_gen_debug_insn_start(dc->pc);

		if (dc->clear_x)

			cris_clear_x_flag(dc);

		/* Check for delayed branches here. If we do it before

		   actually genereating any host code, the simulator will just

		   loop doing nothing for on this program location.  */

		if (!(tb->pc & 1) && env->singlestep_enabled)

			break;

	} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end

	npc = dc->pc;

	if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)

		npc = dc->jmp_pc;

	/* Force an update if the per-tb cpu state has changed.  */

	if (dc->is_jmp == DISAS_NEXT

	    && (dc->cpustate_changed || !dc->flagx_known 

				break;

		}

	}

	*gen_opc_ptr = INDEX_op_end;

	if (search_pc) {

		j = gen_opc_ptr - gen_opc_buf;

			gen_opc_instr_start[lj++] = 0;

	} else {

		tb->size = dc->pc - pc_start;

	}

#ifdef DEBUG_DISAS

}

#endif

#include "cpu-all.h"

#include "svm.h"

static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;

static TCGv cpu_tmp5, cpu_tmp6;

#ifdef TARGET_X86_64

static int x86_64_hregs;

#endif

static inline void gen_ins(DisasContext *s, int ot)

{

    gen_string_movl_A0_EDI(s);

    /* Note: we must do this dummy write first to be restartable in

       case of page fault. */

    gen_op_st_T0_A0(ot + s->mem_index);

    gen_op_movl_T0_Dshift(ot);

    gen_op_add_reg_T0(s->aflag, R_EDI);

}

static inline void gen_outs(DisasContext *s, int ot)

{

    gen_string_movl_A0_ESI(s);

    gen_op_ld_T0_A0(ot + s->mem_index);

    gen_op_movl_T0_Dshift(ot);

    gen_op_add_reg_T0(s->aflag, R_ESI);

}

/* same method as Valgrind : we generate jumps to current or next

            gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);

        } else {

            gen_ins(s, ot);

        }

        break;

    case 0x6e: /* outsS */

            gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);

        } else {

            gen_outs(s, ot);

        }

        break;

        gen_op_movl_T0_im(val);

        gen_check_io(s, ot, pc_start - s->cs_base,

                     SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));

        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);

        tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);

        gen_op_mov_reg_T1(ot, R_EAX);

        break;

    case 0xe6:

    case 0xe7:

                     svm_is_rep(prefixes));

        gen_op_mov_TN_reg(ot, 1, R_EAX);

        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);

        tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);

        tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);

        tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);

        break;

    case 0xec:

    case 0xed:

        gen_op_andl_T0_ffff();

        gen_check_io(s, ot, pc_start - s->cs_base,

                     SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));

        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);

        tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);

        gen_op_mov_reg_T1(ot, R_EAX);

        break;

    case 0xee:

    case 0xef:

                     svm_is_rep(prefixes));

        gen_op_mov_TN_reg(ot, 1, R_EAX);

        tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);

        tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);

        tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);

        tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);

        break;

        /************************/

    uint64_t flags;

    target_ulong pc_start;

    target_ulong cs_base;

    /* generate intermediate code */

    pc_start = tb->pc;

    dc->is_jmp = DISAS_NEXT;

    pc_ptr = pc_start;

    lj = -1;

    for(;;) {

        if (env->nb_breakpoints > 0) {

            for(j = 0; j < env->nb_breakpoints; j++) {

            gen_opc_pc[lj] = pc_ptr;

            gen_opc_cc_op[lj] = dc->cc_op;

            gen_opc_instr_start[lj] = 1;

        }

        pc_ptr = disas_insn(dc, pc_ptr);

        /* stop translation if indicated */

        if (dc->is_jmp)

            break;

           the flag and abort the translation to give the irqs a

           change to be happen */

        if (dc->tf || dc->singlestep_enabled ||

            gen_jmp_im(pc_ptr - dc->cs_base);

            gen_eob(dc);

            break;

        }

        /* if too long translation, stop generation too */

        if (gen_opc_ptr >= gen_opc_end ||

            gen_jmp_im(pc_ptr - dc->cs_base);

            gen_eob(dc);

            break;

        }

    }

    *gen_opc_ptr = INDEX_op_end;

    /* we don't forget to fill the last values */

    if (search_pc) {

    }

#endif

        tb->size = pc_ptr - pc_start;

    return 0;

}

}

#endif

#include "cpu-all.h"

#endif

/* Used to distinguish stores from bad addressing modes.  */

static TCGv store_dummy;

void m68k_tcg_init(void)

{

    char *p;

    target_ulong pc_start;

    int pc_offset;

    int last_cc_op;

    /* generate intermediate code */

    pc_start = tb->pc;

    dc->is_mem = 0;

    dc->mactmp = NULL_QREG;

    lj = -1;

    do {

        pc_offset = dc->pc - pc_start;

        gen_throws_exception = NULL;

            }

            gen_opc_pc[lj] = dc->pc;

            gen_opc_instr_start[lj] = 1;

        }

        last_cc_op = dc->cc_op;

        dc->insn_pc = dc->pc;

	disas_m68k_insn(env, dc);

        /* Terminate the TB on memory ops if watchpoints are present.  */

        /* FIXME: This should be replacd by the deterministic execution

            break;

    } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&

             !env->singlestep_enabled &&

    if (__builtin_expect(env->singlestep_enabled, 0)) {

        /* Make sure the pc is updated, and raise a debug exception.  */

        if (!dc->is_jmp) {

            break;

        }

    }

    *gen_opc_ptr = INDEX_op_end;

#ifdef DEBUG_DISAS

            gen_opc_instr_start[lj++] = 0;

    } else {

        tb->size = dc->pc - pc_start;

    }

    //optimize_flags();

uint32_t cpu_mips_get_clock (void);

int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);

#endif /* !defined (__MIPS_CPU_H__) */

/* FPU TNs, global for now. */

static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];

static inline void tcg_gen_helper_0_i(void *func, TCGv arg)

{

    TCGv tmp = tcg_const_i32(arg);

    case 9:

        switch (sel) {

        case 0:

            tcg_gen_helper_1_0(do_mfc0_count, t0);

            rn = "Count";

            break;

        /* 6,7 are implementation dependent */

    if (sel != 0)

        check_insn(env, ctx, ISA_MIPS32);

    switch (reg) {

    case 0:

        switch (sel) {

                rn, reg, sel);

    }

#endif

    return;

die:

    case 9:

        switch (sel) {

        case 0:

            tcg_gen_helper_1_0(do_mfc0_count, t0);

            rn = "Count";

            break;

        /* 6,7 are implementation dependent */

    if (sel != 0)

        check_insn(env, ctx, ISA_MIPS64);

    switch (reg) {

    case 0:

        switch (sel) {

    }

#endif

    tcg_temp_free(t0);

    return;

die:

        ctx->hflags &= ~MIPS_HFLAG_BMASK;

        ctx->bstate = BS_BRANCH;

        save_cpu_state(ctx, 0);

        switch (hflags) {

        case MIPS_HFLAG_B:

            /* unconditional branch */

    target_ulong pc_start;

    uint16_t *gen_opc_end;

    int j, lj = -1;

    if (search_pc && loglevel)

        fprintf (logfile, "search pc %d\n", search_pc);

#else

    ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;

#endif

#ifdef DEBUG_DISAS

    if (loglevel & CPU_LOG_TB_CPU) {

        fprintf(logfile, "------------------------------------------------\n");

        fprintf(logfile, "\ntb %p idx %d hflags %04x\n",

                tb, ctx.mem_idx, ctx.hflags);

#endif

    while (ctx.bstate == BS_NONE) {

        if (env->nb_breakpoints > 0) {

            for(j = 0; j < env->nb_breakpoints; j++) {

            gen_opc_pc[lj] = ctx.pc;

            gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;

            gen_opc_instr_start[lj] = 1;

        }

        ctx.opcode = ldl_code(ctx.pc);

        decode_opc(env, &ctx);

        ctx.pc += 4;

        if (env->singlestep_enabled)

            break;

        if (gen_opc_ptr >= gen_opc_end)

            break;