Revision 2e70f6ef hw/mips_timer.c

b/hw/mips_timer.c
91 91 
    if (env->CP0_Cause & (1 << CP0Ca_DC))
92 92 
        return;
93 93 

  		





  
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    /* ??? This callback should occur when the counter is exactly equal to


  		





  
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       the comparator value.  Offset the count by one to avoid immediately


  		





  
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       retriggering the callback before any virtual time has passed.  */


  		





  
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    env->CP0_Count++;


  		





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    cpu_mips_timer_update(env);


  		





  
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    env->CP0_Count--;


  		





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    if (env->insn_flags & ISA_MIPS32R2)


  		





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        env->CP0_Cause |= 1 << CP0Ca_TI;


  		





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    qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);


  		












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