Statistics
| Branch: | Revision:

root / exec.c @ 2e9a5713

History | View | Annotate | Download (117.3 kB)

1
/*
2
 *  virtual page mapping and translated block handling
3
 *
4
 *  Copyright (c) 2003 Fabrice Bellard
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18
 */
19
#include "config.h"
20
#ifdef _WIN32
21
#include <windows.h>
22
#else
23
#include <sys/types.h>
24
#include <sys/mman.h>
25
#endif
26
#include <stdlib.h>
27
#include <stdio.h>
28
#include <stdarg.h>
29
#include <string.h>
30
#include <errno.h>
31
#include <unistd.h>
32
#include <inttypes.h>
33

    
34
#include "cpu.h"
35
#include "exec-all.h"
36
#include "qemu-common.h"
37
#include "tcg.h"
38
#include "hw/hw.h"
39
#include "osdep.h"
40
#include "kvm.h"
41
#include "qemu-timer.h"
42
#if defined(CONFIG_USER_ONLY)
43
#include <qemu.h>
44
#include <signal.h>
45
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
46
#include <sys/param.h>
47
#if __FreeBSD_version >= 700104
48
#define HAVE_KINFO_GETVMMAP
49
#define sigqueue sigqueue_freebsd  /* avoid redefinition */
50
#include <sys/time.h>
51
#include <sys/proc.h>
52
#include <machine/profile.h>
53
#define _KERNEL
54
#include <sys/user.h>
55
#undef _KERNEL
56
#undef sigqueue
57
#include <libutil.h>
58
#endif
59
#endif
60
#endif
61

    
62
//#define DEBUG_TB_INVALIDATE
63
//#define DEBUG_FLUSH
64
//#define DEBUG_TLB
65
//#define DEBUG_UNASSIGNED
66

    
67
/* make various TB consistency checks */
68
//#define DEBUG_TB_CHECK
69
//#define DEBUG_TLB_CHECK
70

    
71
//#define DEBUG_IOPORT
72
//#define DEBUG_SUBPAGE
73

    
74
#if !defined(CONFIG_USER_ONLY)
75
/* TB consistency checks only implemented for usermode emulation.  */
76
#undef DEBUG_TB_CHECK
77
#endif
78

    
79
#define SMC_BITMAP_USE_THRESHOLD 10
80

    
81
static TranslationBlock *tbs;
82
int code_gen_max_blocks;
83
TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
84
static int nb_tbs;
85
/* any access to the tbs or the page table must use this lock */
86
spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
87

    
88
#if defined(__arm__) || defined(__sparc_v9__)
89
/* The prologue must be reachable with a direct jump. ARM and Sparc64
90
 have limited branch ranges (possibly also PPC) so place it in a
91
 section close to code segment. */
92
#define code_gen_section                                \
93
    __attribute__((__section__(".gen_code")))           \
94
    __attribute__((aligned (32)))
95
#elif defined(_WIN32)
96
/* Maximum alignment for Win32 is 16. */
97
#define code_gen_section                                \
98
    __attribute__((aligned (16)))
99
#else
100
#define code_gen_section                                \
101
    __attribute__((aligned (32)))
102
#endif
103

    
104
uint8_t code_gen_prologue[1024] code_gen_section;
105
static uint8_t *code_gen_buffer;
106
static unsigned long code_gen_buffer_size;
107
/* threshold to flush the translated code buffer */
108
static unsigned long code_gen_buffer_max_size;
109
uint8_t *code_gen_ptr;
110

    
111
#if !defined(CONFIG_USER_ONLY)
112
int phys_ram_fd;
113
uint8_t *phys_ram_dirty;
114
static int in_migration;
115

    
116
typedef struct RAMBlock {
117
    uint8_t *host;
118
    ram_addr_t offset;
119
    ram_addr_t length;
120
    struct RAMBlock *next;
121
} RAMBlock;
122

    
123
static RAMBlock *ram_blocks;
124
/* TODO: When we implement (and use) ram deallocation (e.g. for hotplug)
125
   then we can no longer assume contiguous ram offsets, and external uses
126
   of this variable will break.  */
127
ram_addr_t last_ram_offset;
128
#endif
129

    
130
CPUState *first_cpu;
131
/* current CPU in the current thread. It is only valid inside
132
   cpu_exec() */
133
CPUState *cpu_single_env;
134
/* 0 = Do not count executed instructions.
135
   1 = Precise instruction counting.
136
   2 = Adaptive rate instruction counting.  */
137
int use_icount = 0;
138
/* Current instruction counter.  While executing translated code this may
139
   include some instructions that have not yet been executed.  */
140
int64_t qemu_icount;
141

    
142
typedef struct PageDesc {
143
    /* list of TBs intersecting this ram page */
144
    TranslationBlock *first_tb;
145
    /* in order to optimize self modifying code, we count the number
146
       of lookups we do to a given page to use a bitmap */
147
    unsigned int code_write_count;
148
    uint8_t *code_bitmap;
149
#if defined(CONFIG_USER_ONLY)
150
    unsigned long flags;
151
#endif
152
} PageDesc;
153

    
154
/* In system mode we want L1_MAP to be based on ram offsets,
155
   while in user mode we want it to be based on virtual addresses.  */
156
#if !defined(CONFIG_USER_ONLY)
157
#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
158
# define L1_MAP_ADDR_SPACE_BITS  HOST_LONG_BITS
159
#else
160
# define L1_MAP_ADDR_SPACE_BITS  TARGET_PHYS_ADDR_SPACE_BITS
161
#endif
162
#else
163
# define L1_MAP_ADDR_SPACE_BITS  TARGET_VIRT_ADDR_SPACE_BITS
164
#endif
165

    
166
/* Size of the L2 (and L3, etc) page tables.  */
167
#define L2_BITS 10
168
#define L2_SIZE (1 << L2_BITS)
169

    
170
/* The bits remaining after N lower levels of page tables.  */
171
#define P_L1_BITS_REM \
172
    ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
173
#define V_L1_BITS_REM \
174
    ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
175

    
176
/* Size of the L1 page table.  Avoid silly small sizes.  */
177
#if P_L1_BITS_REM < 4
178
#define P_L1_BITS  (P_L1_BITS_REM + L2_BITS)
179
#else
180
#define P_L1_BITS  P_L1_BITS_REM
181
#endif
182

    
183
#if V_L1_BITS_REM < 4
184
#define V_L1_BITS  (V_L1_BITS_REM + L2_BITS)
185
#else
186
#define V_L1_BITS  V_L1_BITS_REM
187
#endif
188

    
189
#define P_L1_SIZE  ((target_phys_addr_t)1 << P_L1_BITS)
190
#define V_L1_SIZE  ((target_ulong)1 << V_L1_BITS)
191

    
192
#define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS)
193
#define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
194

    
195
unsigned long qemu_real_host_page_size;
196
unsigned long qemu_host_page_bits;
197
unsigned long qemu_host_page_size;
198
unsigned long qemu_host_page_mask;
199

    
200
/* This is a multi-level map on the virtual address space.
201
   The bottom level has pointers to PageDesc.  */
202
static void *l1_map[V_L1_SIZE];
203

    
204
#if !defined(CONFIG_USER_ONLY)
205
typedef struct PhysPageDesc {
206
    /* offset in host memory of the page + io_index in the low bits */
207
    ram_addr_t phys_offset;
208
    ram_addr_t region_offset;
209
} PhysPageDesc;
210

    
211
/* This is a multi-level map on the physical address space.
212
   The bottom level has pointers to PhysPageDesc.  */
213
static void *l1_phys_map[P_L1_SIZE];
214

    
215
static void io_mem_init(void);
216

    
217
/* io memory support */
218
CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
219
CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
220
void *io_mem_opaque[IO_MEM_NB_ENTRIES];
221
static char io_mem_used[IO_MEM_NB_ENTRIES];
222
static int io_mem_watch;
223
#endif
224

    
225
/* log support */
226
#ifdef WIN32
227
static const char *logfilename = "qemu.log";
228
#else
229
static const char *logfilename = "/tmp/qemu.log";
230
#endif
231
FILE *logfile;
232
int loglevel;
233
static int log_append = 0;
234

    
235
/* statistics */
236
#if !defined(CONFIG_USER_ONLY)
237
static int tlb_flush_count;
238
#endif
239
static int tb_flush_count;
240
static int tb_phys_invalidate_count;
241

    
242
#ifdef _WIN32
243
static void map_exec(void *addr, long size)
244
{
245
    DWORD old_protect;
246
    VirtualProtect(addr, size,
247
                   PAGE_EXECUTE_READWRITE, &old_protect);
248
    
249
}
250
#else
251
static void map_exec(void *addr, long size)
252
{
253
    unsigned long start, end, page_size;
254
    
255
    page_size = getpagesize();
256
    start = (unsigned long)addr;
257
    start &= ~(page_size - 1);
258
    
259
    end = (unsigned long)addr + size;
260
    end += page_size - 1;
261
    end &= ~(page_size - 1);
262
    
263
    mprotect((void *)start, end - start,
264
             PROT_READ | PROT_WRITE | PROT_EXEC);
265
}
266
#endif
267

    
268
static void page_init(void)
269
{
270
    /* NOTE: we can always suppose that qemu_host_page_size >=
271
       TARGET_PAGE_SIZE */
272
#ifdef _WIN32
273
    {
274
        SYSTEM_INFO system_info;
275

    
276
        GetSystemInfo(&system_info);
277
        qemu_real_host_page_size = system_info.dwPageSize;
278
    }
279
#else
280
    qemu_real_host_page_size = getpagesize();
281
#endif
282
    if (qemu_host_page_size == 0)
283
        qemu_host_page_size = qemu_real_host_page_size;
284
    if (qemu_host_page_size < TARGET_PAGE_SIZE)
285
        qemu_host_page_size = TARGET_PAGE_SIZE;
286
    qemu_host_page_bits = 0;
287
    while ((1 << qemu_host_page_bits) < qemu_host_page_size)
288
        qemu_host_page_bits++;
289
    qemu_host_page_mask = ~(qemu_host_page_size - 1);
290

    
291
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
292
    {
293
#ifdef HAVE_KINFO_GETVMMAP
294
        struct kinfo_vmentry *freep;
295
        int i, cnt;
296

    
297
        freep = kinfo_getvmmap(getpid(), &cnt);
298
        if (freep) {
299
            mmap_lock();
300
            for (i = 0; i < cnt; i++) {
301
                unsigned long startaddr, endaddr;
302

    
303
                startaddr = freep[i].kve_start;
304
                endaddr = freep[i].kve_end;
305
                if (h2g_valid(startaddr)) {
306
                    startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
307

    
308
                    if (h2g_valid(endaddr)) {
309
                        endaddr = h2g(endaddr);
310
                        page_set_flags(startaddr, endaddr, PAGE_RESERVED);
311
                    } else {
312
#if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS
313
                        endaddr = ~0ul;
314
                        page_set_flags(startaddr, endaddr, PAGE_RESERVED);
315
#endif
316
                    }
317
                }
318
            }
319
            free(freep);
320
            mmap_unlock();
321
        }
322
#else
323
        FILE *f;
324

    
325
        last_brk = (unsigned long)sbrk(0);
326

    
327
        f = fopen("/compat/linux/proc/self/maps", "r");
328
        if (f) {
329
            mmap_lock();
330

    
331
            do {
332
                unsigned long startaddr, endaddr;
333
                int n;
334

    
335
                n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr);
336

    
337
                if (n == 2 && h2g_valid(startaddr)) {
338
                    startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
339

    
340
                    if (h2g_valid(endaddr)) {
341
                        endaddr = h2g(endaddr);
342
                    } else {
343
                        endaddr = ~0ul;
344
                    }
345
                    page_set_flags(startaddr, endaddr, PAGE_RESERVED);
346
                }
347
            } while (!feof(f));
348

    
349
            fclose(f);
350
            mmap_unlock();
351
        }
352
#endif
353
    }
354
#endif
355
}
356

    
357
static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
358
{
359
    PageDesc *pd;
360
    void **lp;
361
    int i;
362

    
363
#if defined(CONFIG_USER_ONLY)
364
    /* We can't use qemu_malloc because it may recurse into a locked mutex. */
365
# define ALLOC(P, SIZE)                                 \
366
    do {                                                \
367
        P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE,    \
368
                 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);   \
369
    } while (0)
370
#else
371
# define ALLOC(P, SIZE) \
372
    do { P = qemu_mallocz(SIZE); } while (0)
373
#endif
374

    
375
    /* Level 1.  Always allocated.  */
376
    lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));
377

    
378
    /* Level 2..N-1.  */
379
    for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
380
        void **p = *lp;
381

    
382
        if (p == NULL) {
383
            if (!alloc) {
384
                return NULL;
385
            }
386
            ALLOC(p, sizeof(void *) * L2_SIZE);
387
            *lp = p;
388
        }
389

    
390
        lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
391
    }
392

    
393
    pd = *lp;
394
    if (pd == NULL) {
395
        if (!alloc) {
396
            return NULL;
397
        }
398
        ALLOC(pd, sizeof(PageDesc) * L2_SIZE);
399
        *lp = pd;
400
    }
401

    
402
#undef ALLOC
403

    
404
    return pd + (index & (L2_SIZE - 1));
405
}
406

    
407
static inline PageDesc *page_find(tb_page_addr_t index)
408
{
409
    return page_find_alloc(index, 0);
410
}
411

    
412
#if !defined(CONFIG_USER_ONLY)
413
static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
414
{
415
    PhysPageDesc *pd;
416
    void **lp;
417
    int i;
418

    
419
    /* Level 1.  Always allocated.  */
420
    lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1));
421

    
422
    /* Level 2..N-1.  */
423
    for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
424
        void **p = *lp;
425
        if (p == NULL) {
426
            if (!alloc) {
427
                return NULL;
428
            }
429
            *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE);
430
        }
431
        lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
432
    }
433

    
434
    pd = *lp;
435
    if (pd == NULL) {
436
        int i;
437

    
438
        if (!alloc) {
439
            return NULL;
440
        }
441

    
442
        *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE);
443

    
444
        for (i = 0; i < L2_SIZE; i++) {
445
            pd[i].phys_offset = IO_MEM_UNASSIGNED;
446
            pd[i].region_offset = (index + i) << TARGET_PAGE_BITS;
447
        }
448
    }
449

    
450
    return pd + (index & (L2_SIZE - 1));
451
}
452

    
453
static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
454
{
455
    return phys_page_find_alloc(index, 0);
456
}
457

    
458
static void tlb_protect_code(ram_addr_t ram_addr);
459
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
460
                                    target_ulong vaddr);
461
#define mmap_lock() do { } while(0)
462
#define mmap_unlock() do { } while(0)
463
#endif
464

    
465
#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
466

    
467
#if defined(CONFIG_USER_ONLY)
468
/* Currently it is not recommended to allocate big chunks of data in
469
   user mode. It will change when a dedicated libc will be used */
470
#define USE_STATIC_CODE_GEN_BUFFER
471
#endif
472

    
473
#ifdef USE_STATIC_CODE_GEN_BUFFER
474
static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]
475
               __attribute__((aligned (CODE_GEN_ALIGN)));
476
#endif
477

    
478
static void code_gen_alloc(unsigned long tb_size)
479
{
480
#ifdef USE_STATIC_CODE_GEN_BUFFER
481
    code_gen_buffer = static_code_gen_buffer;
482
    code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
483
    map_exec(code_gen_buffer, code_gen_buffer_size);
484
#else
485
    code_gen_buffer_size = tb_size;
486
    if (code_gen_buffer_size == 0) {
487
#if defined(CONFIG_USER_ONLY)
488
        /* in user mode, phys_ram_size is not meaningful */
489
        code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
490
#else
491
        /* XXX: needs adjustments */
492
        code_gen_buffer_size = (unsigned long)(ram_size / 4);
493
#endif
494
    }
495
    if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
496
        code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
497
    /* The code gen buffer location may have constraints depending on
498
       the host cpu and OS */
499
#if defined(__linux__) 
500
    {
501
        int flags;
502
        void *start = NULL;
503

    
504
        flags = MAP_PRIVATE | MAP_ANONYMOUS;
505
#if defined(__x86_64__)
506
        flags |= MAP_32BIT;
507
        /* Cannot map more than that */
508
        if (code_gen_buffer_size > (800 * 1024 * 1024))
509
            code_gen_buffer_size = (800 * 1024 * 1024);
510
#elif defined(__sparc_v9__)
511
        // Map the buffer below 2G, so we can use direct calls and branches
512
        flags |= MAP_FIXED;
513
        start = (void *) 0x60000000UL;
514
        if (code_gen_buffer_size > (512 * 1024 * 1024))
515
            code_gen_buffer_size = (512 * 1024 * 1024);
516
#elif defined(__arm__)
517
        /* Map the buffer below 32M, so we can use direct calls and branches */
518
        flags |= MAP_FIXED;
519
        start = (void *) 0x01000000UL;
520
        if (code_gen_buffer_size > 16 * 1024 * 1024)
521
            code_gen_buffer_size = 16 * 1024 * 1024;
522
#endif
523
        code_gen_buffer = mmap(start, code_gen_buffer_size,
524
                               PROT_WRITE | PROT_READ | PROT_EXEC,
525
                               flags, -1, 0);
526
        if (code_gen_buffer == MAP_FAILED) {
527
            fprintf(stderr, "Could not allocate dynamic translator buffer\n");
528
            exit(1);
529
        }
530
    }
531
#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
532
    {
533
        int flags;
534
        void *addr = NULL;
535
        flags = MAP_PRIVATE | MAP_ANONYMOUS;
536
#if defined(__x86_64__)
537
        /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
538
         * 0x40000000 is free */
539
        flags |= MAP_FIXED;
540
        addr = (void *)0x40000000;
541
        /* Cannot map more than that */
542
        if (code_gen_buffer_size > (800 * 1024 * 1024))
543
            code_gen_buffer_size = (800 * 1024 * 1024);
544
#endif
545
        code_gen_buffer = mmap(addr, code_gen_buffer_size,
546
                               PROT_WRITE | PROT_READ | PROT_EXEC, 
547
                               flags, -1, 0);
548
        if (code_gen_buffer == MAP_FAILED) {
549
            fprintf(stderr, "Could not allocate dynamic translator buffer\n");
550
            exit(1);
551
        }
552
    }
553
#else
554
    code_gen_buffer = qemu_malloc(code_gen_buffer_size);
555
    map_exec(code_gen_buffer, code_gen_buffer_size);
556
#endif
557
#endif /* !USE_STATIC_CODE_GEN_BUFFER */
558
    map_exec(code_gen_prologue, sizeof(code_gen_prologue));
559
    code_gen_buffer_max_size = code_gen_buffer_size - 
560
        code_gen_max_block_size();
561
    code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
562
    tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
563
}
564

    
565
/* Must be called before using the QEMU cpus. 'tb_size' is the size
566
   (in bytes) allocated to the translation buffer. Zero means default
567
   size. */
568
void cpu_exec_init_all(unsigned long tb_size)
569
{
570
    cpu_gen_init();
571
    code_gen_alloc(tb_size);
572
    code_gen_ptr = code_gen_buffer;
573
    page_init();
574
#if !defined(CONFIG_USER_ONLY)
575
    io_mem_init();
576
#endif
577
}
578

    
579
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
580

    
581
static int cpu_common_post_load(void *opaque, int version_id)
582
{
583
    CPUState *env = opaque;
584

    
585
    /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
586
       version_id is increased. */
587
    env->interrupt_request &= ~0x01;
588
    tlb_flush(env, 1);
589

    
590
    return 0;
591
}
592

    
593
static const VMStateDescription vmstate_cpu_common = {
594
    .name = "cpu_common",
595
    .version_id = 1,
596
    .minimum_version_id = 1,
597
    .minimum_version_id_old = 1,
598
    .post_load = cpu_common_post_load,
599
    .fields      = (VMStateField []) {
600
        VMSTATE_UINT32(halted, CPUState),
601
        VMSTATE_UINT32(interrupt_request, CPUState),
602
        VMSTATE_END_OF_LIST()
603
    }
604
};
605
#endif
606

    
607
CPUState *qemu_get_cpu(int cpu)
608
{
609
    CPUState *env = first_cpu;
610

    
611
    while (env) {
612
        if (env->cpu_index == cpu)
613
            break;
614
        env = env->next_cpu;
615
    }
616

    
617
    return env;
618
}
619

    
620
void cpu_exec_init(CPUState *env)
621
{
622
    CPUState **penv;
623
    int cpu_index;
624

    
625
#if defined(CONFIG_USER_ONLY)
626
    cpu_list_lock();
627
#endif
628
    env->next_cpu = NULL;
629
    penv = &first_cpu;
630
    cpu_index = 0;
631
    while (*penv != NULL) {
632
        penv = &(*penv)->next_cpu;
633
        cpu_index++;
634
    }
635
    env->cpu_index = cpu_index;
636
    env->numa_node = 0;
637
    QTAILQ_INIT(&env->breakpoints);
638
    QTAILQ_INIT(&env->watchpoints);
639
    *penv = env;
640
#if defined(CONFIG_USER_ONLY)
641
    cpu_list_unlock();
642
#endif
643
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
644
    vmstate_register(cpu_index, &vmstate_cpu_common, env);
645
    register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
646
                    cpu_save, cpu_load, env);
647
#endif
648
}
649

    
650
static inline void invalidate_page_bitmap(PageDesc *p)
651
{
652
    if (p->code_bitmap) {
653
        qemu_free(p->code_bitmap);
654
        p->code_bitmap = NULL;
655
    }
656
    p->code_write_count = 0;
657
}
658

    
659
/* Set to NULL all the 'first_tb' fields in all PageDescs. */
660

    
661
static void page_flush_tb_1 (int level, void **lp)
662
{
663
    int i;
664

    
665
    if (*lp == NULL) {
666
        return;
667
    }
668
    if (level == 0) {
669
        PageDesc *pd = *lp;
670
        for (i = 0; i < L2_SIZE; ++i) {
671
            pd[i].first_tb = NULL;
672
            invalidate_page_bitmap(pd + i);
673
        }
674
    } else {
675
        void **pp = *lp;
676
        for (i = 0; i < L2_SIZE; ++i) {
677
            page_flush_tb_1 (level - 1, pp + i);
678
        }
679
    }
680
}
681

    
682
static void page_flush_tb(void)
683
{
684
    int i;
685
    for (i = 0; i < V_L1_SIZE; i++) {
686
        page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i);
687
    }
688
}
689

    
690
/* flush all the translation blocks */
691
/* XXX: tb_flush is currently not thread safe */
692
void tb_flush(CPUState *env1)
693
{
694
    CPUState *env;
695
#if defined(DEBUG_FLUSH)
696
    printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
697
           (unsigned long)(code_gen_ptr - code_gen_buffer),
698
           nb_tbs, nb_tbs > 0 ?
699
           ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
700
#endif
701
    if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
702
        cpu_abort(env1, "Internal error: code buffer overflow\n");
703

    
704
    nb_tbs = 0;
705

    
706
    for(env = first_cpu; env != NULL; env = env->next_cpu) {
707
        memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
708
    }
709

    
710
    memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
711
    page_flush_tb();
712

    
713
    code_gen_ptr = code_gen_buffer;
714
    /* XXX: flush processor icache at this point if cache flush is
715
       expensive */
716
    tb_flush_count++;
717
}
718

    
719
#ifdef DEBUG_TB_CHECK
720

    
721
static void tb_invalidate_check(target_ulong address)
722
{
723
    TranslationBlock *tb;
724
    int i;
725
    address &= TARGET_PAGE_MASK;
726
    for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
727
        for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
728
            if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
729
                  address >= tb->pc + tb->size)) {
730
                printf("ERROR invalidate: address=" TARGET_FMT_lx
731
                       " PC=%08lx size=%04x\n",
732
                       address, (long)tb->pc, tb->size);
733
            }
734
        }
735
    }
736
}
737

    
738
/* verify that all the pages have correct rights for code */
739
static void tb_page_check(void)
740
{
741
    TranslationBlock *tb;
742
    int i, flags1, flags2;
743

    
744
    for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
745
        for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
746
            flags1 = page_get_flags(tb->pc);
747
            flags2 = page_get_flags(tb->pc + tb->size - 1);
748
            if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
749
                printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
750
                       (long)tb->pc, tb->size, flags1, flags2);
751
            }
752
        }
753
    }
754
}
755

    
756
#endif
757

    
758
/* invalidate one TB */
759
static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
760
                             int next_offset)
761
{
762
    TranslationBlock *tb1;
763
    for(;;) {
764
        tb1 = *ptb;
765
        if (tb1 == tb) {
766
            *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
767
            break;
768
        }
769
        ptb = (TranslationBlock **)((char *)tb1 + next_offset);
770
    }
771
}
772

    
773
static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
774
{
775
    TranslationBlock *tb1;
776
    unsigned int n1;
777

    
778
    for(;;) {
779
        tb1 = *ptb;
780
        n1 = (long)tb1 & 3;
781
        tb1 = (TranslationBlock *)((long)tb1 & ~3);
782
        if (tb1 == tb) {
783
            *ptb = tb1->page_next[n1];
784
            break;
785
        }
786
        ptb = &tb1->page_next[n1];
787
    }
788
}
789

    
790
static inline void tb_jmp_remove(TranslationBlock *tb, int n)
791
{
792
    TranslationBlock *tb1, **ptb;
793
    unsigned int n1;
794

    
795
    ptb = &tb->jmp_next[n];
796
    tb1 = *ptb;
797
    if (tb1) {
798
        /* find tb(n) in circular list */
799
        for(;;) {
800
            tb1 = *ptb;
801
            n1 = (long)tb1 & 3;
802
            tb1 = (TranslationBlock *)((long)tb1 & ~3);
803
            if (n1 == n && tb1 == tb)
804
                break;
805
            if (n1 == 2) {
806
                ptb = &tb1->jmp_first;
807
            } else {
808
                ptb = &tb1->jmp_next[n1];
809
            }
810
        }
811
        /* now we can suppress tb(n) from the list */
812
        *ptb = tb->jmp_next[n];
813

    
814
        tb->jmp_next[n] = NULL;
815
    }
816
}
817

    
818
/* reset the jump entry 'n' of a TB so that it is not chained to
819
   another TB */
820
static inline void tb_reset_jump(TranslationBlock *tb, int n)
821
{
822
    tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
823
}
824

    
825
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
826
{
827
    CPUState *env;
828
    PageDesc *p;
829
    unsigned int h, n1;
830
    tb_page_addr_t phys_pc;
831
    TranslationBlock *tb1, *tb2;
832

    
833
    /* remove the TB from the hash list */
834
    phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
835
    h = tb_phys_hash_func(phys_pc);
836
    tb_remove(&tb_phys_hash[h], tb,
837
              offsetof(TranslationBlock, phys_hash_next));
838

    
839
    /* remove the TB from the page list */
840
    if (tb->page_addr[0] != page_addr) {
841
        p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
842
        tb_page_remove(&p->first_tb, tb);
843
        invalidate_page_bitmap(p);
844
    }
845
    if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
846
        p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
847
        tb_page_remove(&p->first_tb, tb);
848
        invalidate_page_bitmap(p);
849
    }
850

    
851
    tb_invalidated_flag = 1;
852

    
853
    /* remove the TB from the hash list */
854
    h = tb_jmp_cache_hash_func(tb->pc);
855
    for(env = first_cpu; env != NULL; env = env->next_cpu) {
856
        if (env->tb_jmp_cache[h] == tb)
857
            env->tb_jmp_cache[h] = NULL;
858
    }
859

    
860
    /* suppress this TB from the two jump lists */
861
    tb_jmp_remove(tb, 0);
862
    tb_jmp_remove(tb, 1);
863

    
864
    /* suppress any remaining jumps to this TB */
865
    tb1 = tb->jmp_first;
866
    for(;;) {
867
        n1 = (long)tb1 & 3;
868
        if (n1 == 2)
869
            break;
870
        tb1 = (TranslationBlock *)((long)tb1 & ~3);
871
        tb2 = tb1->jmp_next[n1];
872
        tb_reset_jump(tb1, n1);
873
        tb1->jmp_next[n1] = NULL;
874
        tb1 = tb2;
875
    }
876
    tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
877

    
878
    tb_phys_invalidate_count++;
879
}
880

    
881
static inline void set_bits(uint8_t *tab, int start, int len)
882
{
883
    int end, mask, end1;
884

    
885
    end = start + len;
886
    tab += start >> 3;
887
    mask = 0xff << (start & 7);
888
    if ((start & ~7) == (end & ~7)) {
889
        if (start < end) {
890
            mask &= ~(0xff << (end & 7));
891
            *tab |= mask;
892
        }
893
    } else {
894
        *tab++ |= mask;
895
        start = (start + 8) & ~7;
896
        end1 = end & ~7;
897
        while (start < end1) {
898
            *tab++ = 0xff;
899
            start += 8;
900
        }
901
        if (start < end) {
902
            mask = ~(0xff << (end & 7));
903
            *tab |= mask;
904
        }
905
    }
906
}
907

    
908
static void build_page_bitmap(PageDesc *p)
909
{
910
    int n, tb_start, tb_end;
911
    TranslationBlock *tb;
912

    
913
    p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
914

    
915
    tb = p->first_tb;
916
    while (tb != NULL) {
917
        n = (long)tb & 3;
918
        tb = (TranslationBlock *)((long)tb & ~3);
919
        /* NOTE: this is subtle as a TB may span two physical pages */
920
        if (n == 0) {
921
            /* NOTE: tb_end may be after the end of the page, but
922
               it is not a problem */
923
            tb_start = tb->pc & ~TARGET_PAGE_MASK;
924
            tb_end = tb_start + tb->size;
925
            if (tb_end > TARGET_PAGE_SIZE)
926
                tb_end = TARGET_PAGE_SIZE;
927
        } else {
928
            tb_start = 0;
929
            tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
930
        }
931
        set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
932
        tb = tb->page_next[n];
933
    }
934
}
935

    
936
TranslationBlock *tb_gen_code(CPUState *env,
937
                              target_ulong pc, target_ulong cs_base,
938
                              int flags, int cflags)
939
{
940
    TranslationBlock *tb;
941
    uint8_t *tc_ptr;
942
    tb_page_addr_t phys_pc, phys_page2;
943
    target_ulong virt_page2;
944
    int code_gen_size;
945

    
946
    phys_pc = get_page_addr_code(env, pc);
947
    tb = tb_alloc(pc);
948
    if (!tb) {
949
        /* flush must be done */
950
        tb_flush(env);
951
        /* cannot fail at this point */
952
        tb = tb_alloc(pc);
953
        /* Don't forget to invalidate previous TB info.  */
954
        tb_invalidated_flag = 1;
955
    }
956
    tc_ptr = code_gen_ptr;
957
    tb->tc_ptr = tc_ptr;
958
    tb->cs_base = cs_base;
959
    tb->flags = flags;
960
    tb->cflags = cflags;
961
    cpu_gen_code(env, tb, &code_gen_size);
962
    code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
963

    
964
    /* check next page if needed */
965
    virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
966
    phys_page2 = -1;
967
    if ((pc & TARGET_PAGE_MASK) != virt_page2) {
968
        phys_page2 = get_page_addr_code(env, virt_page2);
969
    }
970
    tb_link_page(tb, phys_pc, phys_page2);
971
    return tb;
972
}
973

    
974
/* invalidate all TBs which intersect with the target physical page
975
   starting in range [start;end[. NOTE: start and end must refer to
976
   the same physical page. 'is_cpu_write_access' should be true if called
977
   from a real cpu write access: the virtual CPU will exit the current
978
   TB if code is modified inside this TB. */
979
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
980
                                   int is_cpu_write_access)
981
{
982
    TranslationBlock *tb, *tb_next, *saved_tb;
983
    CPUState *env = cpu_single_env;
984
    tb_page_addr_t tb_start, tb_end;
985
    PageDesc *p;
986
    int n;
987
#ifdef TARGET_HAS_PRECISE_SMC
988
    int current_tb_not_found = is_cpu_write_access;
989
    TranslationBlock *current_tb = NULL;
990
    int current_tb_modified = 0;
991
    target_ulong current_pc = 0;
992
    target_ulong current_cs_base = 0;
993
    int current_flags = 0;
994
#endif /* TARGET_HAS_PRECISE_SMC */
995

    
996
    p = page_find(start >> TARGET_PAGE_BITS);
997
    if (!p)
998
        return;
999
    if (!p->code_bitmap &&
1000
        ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
1001
        is_cpu_write_access) {
1002
        /* build code bitmap */
1003
        build_page_bitmap(p);
1004
    }
1005

    
1006
    /* we remove all the TBs in the range [start, end[ */
1007
    /* XXX: see if in some cases it could be faster to invalidate all the code */
1008
    tb = p->first_tb;
1009
    while (tb != NULL) {
1010
        n = (long)tb & 3;
1011
        tb = (TranslationBlock *)((long)tb & ~3);
1012
        tb_next = tb->page_next[n];
1013
        /* NOTE: this is subtle as a TB may span two physical pages */
1014
        if (n == 0) {
1015
            /* NOTE: tb_end may be after the end of the page, but
1016
               it is not a problem */
1017
            tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
1018
            tb_end = tb_start + tb->size;
1019
        } else {
1020
            tb_start = tb->page_addr[1];
1021
            tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
1022
        }
1023
        if (!(tb_end <= start || tb_start >= end)) {
1024
#ifdef TARGET_HAS_PRECISE_SMC
1025
            if (current_tb_not_found) {
1026
                current_tb_not_found = 0;
1027
                current_tb = NULL;
1028
                if (env->mem_io_pc) {
1029
                    /* now we have a real cpu fault */
1030
                    current_tb = tb_find_pc(env->mem_io_pc);
1031
                }
1032
            }
1033
            if (current_tb == tb &&
1034
                (current_tb->cflags & CF_COUNT_MASK) != 1) {
1035
                /* If we are modifying the current TB, we must stop
1036
                its execution. We could be more precise by checking
1037
                that the modification is after the current PC, but it
1038
                would require a specialized function to partially
1039
                restore the CPU state */
1040

    
1041
                current_tb_modified = 1;
1042
                cpu_restore_state(current_tb, env,
1043
                                  env->mem_io_pc, NULL);
1044
                cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1045
                                     &current_flags);
1046
            }
1047
#endif /* TARGET_HAS_PRECISE_SMC */
1048
            /* we need to do that to handle the case where a signal
1049
               occurs while doing tb_phys_invalidate() */
1050
            saved_tb = NULL;
1051
            if (env) {
1052
                saved_tb = env->current_tb;
1053
                env->current_tb = NULL;
1054
            }
1055
            tb_phys_invalidate(tb, -1);
1056
            if (env) {
1057
                env->current_tb = saved_tb;
1058
                if (env->interrupt_request && env->current_tb)
1059
                    cpu_interrupt(env, env->interrupt_request);
1060
            }
1061
        }
1062
        tb = tb_next;
1063
    }
1064
#if !defined(CONFIG_USER_ONLY)
1065
    /* if no code remaining, no need to continue to use slow writes */
1066
    if (!p->first_tb) {
1067
        invalidate_page_bitmap(p);
1068
        if (is_cpu_write_access) {
1069
            tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
1070
        }
1071
    }
1072
#endif
1073
#ifdef TARGET_HAS_PRECISE_SMC
1074
    if (current_tb_modified) {
1075
        /* we generate a block containing just the instruction
1076
           modifying the memory. It will ensure that it cannot modify
1077
           itself */
1078
        env->current_tb = NULL;
1079
        tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1080
        cpu_resume_from_signal(env, NULL);
1081
    }
1082
#endif
1083
}
1084

    
1085
/* len must be <= 8 and start must be a multiple of len */
1086
static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len)
1087
{
1088
    PageDesc *p;
1089
    int offset, b;
1090
#if 0
1091
    if (1) {
1092
        qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1093
                  cpu_single_env->mem_io_vaddr, len,
1094
                  cpu_single_env->eip,
1095
                  cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
1096
    }
1097
#endif
1098
    p = page_find(start >> TARGET_PAGE_BITS);
1099
    if (!p)
1100
        return;
1101
    if (p->code_bitmap) {
1102
        offset = start & ~TARGET_PAGE_MASK;
1103
        b = p->code_bitmap[offset >> 3] >> (offset & 7);
1104
        if (b & ((1 << len) - 1))
1105
            goto do_invalidate;
1106
    } else {
1107
    do_invalidate:
1108
        tb_invalidate_phys_page_range(start, start + len, 1);
1109
    }
1110
}
1111

    
1112
#if !defined(CONFIG_SOFTMMU)
1113
static void tb_invalidate_phys_page(tb_page_addr_t addr,
1114
                                    unsigned long pc, void *puc)
1115
{
1116
    TranslationBlock *tb;
1117
    PageDesc *p;
1118
    int n;
1119
#ifdef TARGET_HAS_PRECISE_SMC
1120
    TranslationBlock *current_tb = NULL;
1121
    CPUState *env = cpu_single_env;
1122
    int current_tb_modified = 0;
1123
    target_ulong current_pc = 0;
1124
    target_ulong current_cs_base = 0;
1125
    int current_flags = 0;
1126
#endif
1127

    
1128
    addr &= TARGET_PAGE_MASK;
1129
    p = page_find(addr >> TARGET_PAGE_BITS);
1130
    if (!p)
1131
        return;
1132
    tb = p->first_tb;
1133
#ifdef TARGET_HAS_PRECISE_SMC
1134
    if (tb && pc != 0) {
1135
        current_tb = tb_find_pc(pc);
1136
    }
1137
#endif
1138
    while (tb != NULL) {
1139
        n = (long)tb & 3;
1140
        tb = (TranslationBlock *)((long)tb & ~3);
1141
#ifdef TARGET_HAS_PRECISE_SMC
1142
        if (current_tb == tb &&
1143
            (current_tb->cflags & CF_COUNT_MASK) != 1) {
1144
                /* If we are modifying the current TB, we must stop
1145
                   its execution. We could be more precise by checking
1146
                   that the modification is after the current PC, but it
1147
                   would require a specialized function to partially
1148
                   restore the CPU state */
1149

    
1150
            current_tb_modified = 1;
1151
            cpu_restore_state(current_tb, env, pc, puc);
1152
            cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1153
                                 &current_flags);
1154
        }
1155
#endif /* TARGET_HAS_PRECISE_SMC */
1156
        tb_phys_invalidate(tb, addr);
1157
        tb = tb->page_next[n];
1158
    }
1159
    p->first_tb = NULL;
1160
#ifdef TARGET_HAS_PRECISE_SMC
1161
    if (current_tb_modified) {
1162
        /* we generate a block containing just the instruction
1163
           modifying the memory. It will ensure that it cannot modify
1164
           itself */
1165
        env->current_tb = NULL;
1166
        tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1167
        cpu_resume_from_signal(env, puc);
1168
    }
1169
#endif
1170
}
1171
#endif
1172

    
1173
/* add the tb in the target page and protect it if necessary */
1174
static inline void tb_alloc_page(TranslationBlock *tb,
1175
                                 unsigned int n, tb_page_addr_t page_addr)
1176
{
1177
    PageDesc *p;
1178
    TranslationBlock *last_first_tb;
1179

    
1180
    tb->page_addr[n] = page_addr;
1181
    p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1);
1182
    tb->page_next[n] = p->first_tb;
1183
    last_first_tb = p->first_tb;
1184
    p->first_tb = (TranslationBlock *)((long)tb | n);
1185
    invalidate_page_bitmap(p);
1186

    
1187
#if defined(TARGET_HAS_SMC) || 1
1188

    
1189
#if defined(CONFIG_USER_ONLY)
1190
    if (p->flags & PAGE_WRITE) {
1191
        target_ulong addr;
1192
        PageDesc *p2;
1193
        int prot;
1194

    
1195
        /* force the host page as non writable (writes will have a
1196
           page fault + mprotect overhead) */
1197
        page_addr &= qemu_host_page_mask;
1198
        prot = 0;
1199
        for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1200
            addr += TARGET_PAGE_SIZE) {
1201

    
1202
            p2 = page_find (addr >> TARGET_PAGE_BITS);
1203
            if (!p2)
1204
                continue;
1205
            prot |= p2->flags;
1206
            p2->flags &= ~PAGE_WRITE;
1207
          }
1208
        mprotect(g2h(page_addr), qemu_host_page_size,
1209
                 (prot & PAGE_BITS) & ~PAGE_WRITE);
1210
#ifdef DEBUG_TB_INVALIDATE
1211
        printf("protecting code page: 0x" TARGET_FMT_lx "\n",
1212
               page_addr);
1213
#endif
1214
    }
1215
#else
1216
    /* if some code is already present, then the pages are already
1217
       protected. So we handle the case where only the first TB is
1218
       allocated in a physical page */
1219
    if (!last_first_tb) {
1220
        tlb_protect_code(page_addr);
1221
    }
1222
#endif
1223

    
1224
#endif /* TARGET_HAS_SMC */
1225
}
1226

    
1227
/* Allocate a new translation block. Flush the translation buffer if
1228
   too many translation blocks or too much generated code. */
1229
TranslationBlock *tb_alloc(target_ulong pc)
1230
{
1231
    TranslationBlock *tb;
1232

    
1233
    if (nb_tbs >= code_gen_max_blocks ||
1234
        (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
1235
        return NULL;
1236
    tb = &tbs[nb_tbs++];
1237
    tb->pc = pc;
1238
    tb->cflags = 0;
1239
    return tb;
1240
}
1241

    
1242
void tb_free(TranslationBlock *tb)
1243
{
1244
    /* In practice this is mostly used for single use temporary TB
1245
       Ignore the hard cases and just back up if this TB happens to
1246
       be the last one generated.  */
1247
    if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1248
        code_gen_ptr = tb->tc_ptr;
1249
        nb_tbs--;
1250
    }
1251
}
1252

    
1253
/* add a new TB and link it to the physical page tables. phys_page2 is
1254
   (-1) to indicate that only one page contains the TB. */
1255
void tb_link_page(TranslationBlock *tb,
1256
                  tb_page_addr_t phys_pc, tb_page_addr_t phys_page2)
1257
{
1258
    unsigned int h;
1259
    TranslationBlock **ptb;
1260

    
1261
    /* Grab the mmap lock to stop another thread invalidating this TB
1262
       before we are done.  */
1263
    mmap_lock();
1264
    /* add in the physical hash table */
1265
    h = tb_phys_hash_func(phys_pc);
1266
    ptb = &tb_phys_hash[h];
1267
    tb->phys_hash_next = *ptb;
1268
    *ptb = tb;
1269

    
1270
    /* add in the page list */
1271
    tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1272
    if (phys_page2 != -1)
1273
        tb_alloc_page(tb, 1, phys_page2);
1274
    else
1275
        tb->page_addr[1] = -1;
1276

    
1277
    tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1278
    tb->jmp_next[0] = NULL;
1279
    tb->jmp_next[1] = NULL;
1280

    
1281
    /* init original jump addresses */
1282
    if (tb->tb_next_offset[0] != 0xffff)
1283
        tb_reset_jump(tb, 0);
1284
    if (tb->tb_next_offset[1] != 0xffff)
1285
        tb_reset_jump(tb, 1);
1286

    
1287
#ifdef DEBUG_TB_CHECK
1288
    tb_page_check();
1289
#endif
1290
    mmap_unlock();
1291
}
1292

    
1293
/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1294
   tb[1].tc_ptr. Return NULL if not found */
1295
TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1296
{
1297
    int m_min, m_max, m;
1298
    unsigned long v;
1299
    TranslationBlock *tb;
1300

    
1301
    if (nb_tbs <= 0)
1302
        return NULL;
1303
    if (tc_ptr < (unsigned long)code_gen_buffer ||
1304
        tc_ptr >= (unsigned long)code_gen_ptr)
1305
        return NULL;
1306
    /* binary search (cf Knuth) */
1307
    m_min = 0;
1308
    m_max = nb_tbs - 1;
1309
    while (m_min <= m_max) {
1310
        m = (m_min + m_max) >> 1;
1311
        tb = &tbs[m];
1312
        v = (unsigned long)tb->tc_ptr;
1313
        if (v == tc_ptr)
1314
            return tb;
1315
        else if (tc_ptr < v) {
1316
            m_max = m - 1;
1317
        } else {
1318
            m_min = m + 1;
1319
        }
1320
    }
1321
    return &tbs[m_max];
1322
}
1323

    
1324
static void tb_reset_jump_recursive(TranslationBlock *tb);
1325

    
1326
static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1327
{
1328
    TranslationBlock *tb1, *tb_next, **ptb;
1329
    unsigned int n1;
1330

    
1331
    tb1 = tb->jmp_next[n];
1332
    if (tb1 != NULL) {
1333
        /* find head of list */
1334
        for(;;) {
1335
            n1 = (long)tb1 & 3;
1336
            tb1 = (TranslationBlock *)((long)tb1 & ~3);
1337
            if (n1 == 2)
1338
                break;
1339
            tb1 = tb1->jmp_next[n1];
1340
        }
1341
        /* we are now sure now that tb jumps to tb1 */
1342
        tb_next = tb1;
1343

    
1344
        /* remove tb from the jmp_first list */
1345
        ptb = &tb_next->jmp_first;
1346
        for(;;) {
1347
            tb1 = *ptb;
1348
            n1 = (long)tb1 & 3;
1349
            tb1 = (TranslationBlock *)((long)tb1 & ~3);
1350
            if (n1 == n && tb1 == tb)
1351
                break;
1352
            ptb = &tb1->jmp_next[n1];
1353
        }
1354
        *ptb = tb->jmp_next[n];
1355
        tb->jmp_next[n] = NULL;
1356

    
1357
        /* suppress the jump to next tb in generated code */
1358
        tb_reset_jump(tb, n);
1359

    
1360
        /* suppress jumps in the tb on which we could have jumped */
1361
        tb_reset_jump_recursive(tb_next);
1362
    }
1363
}
1364

    
1365
static void tb_reset_jump_recursive(TranslationBlock *tb)
1366
{
1367
    tb_reset_jump_recursive2(tb, 0);
1368
    tb_reset_jump_recursive2(tb, 1);
1369
}
1370

    
1371
#if defined(TARGET_HAS_ICE)
1372
#if defined(CONFIG_USER_ONLY)
1373
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1374
{
1375
    tb_invalidate_phys_page_range(pc, pc + 1, 0);
1376
}
1377
#else
1378
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1379
{
1380
    target_phys_addr_t addr;
1381
    target_ulong pd;
1382
    ram_addr_t ram_addr;
1383
    PhysPageDesc *p;
1384

    
1385
    addr = cpu_get_phys_page_debug(env, pc);
1386
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
1387
    if (!p) {
1388
        pd = IO_MEM_UNASSIGNED;
1389
    } else {
1390
        pd = p->phys_offset;
1391
    }
1392
    ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
1393
    tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1394
}
1395
#endif
1396
#endif /* TARGET_HAS_ICE */
1397

    
1398
#if defined(CONFIG_USER_ONLY)
1399
void cpu_watchpoint_remove_all(CPUState *env, int mask)
1400

    
1401
{
1402
}
1403

    
1404
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1405
                          int flags, CPUWatchpoint **watchpoint)
1406
{
1407
    return -ENOSYS;
1408
}
1409
#else
1410
/* Add a watchpoint.  */
1411
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1412
                          int flags, CPUWatchpoint **watchpoint)
1413
{
1414
    target_ulong len_mask = ~(len - 1);
1415
    CPUWatchpoint *wp;
1416

    
1417
    /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
1418
    if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1419
        fprintf(stderr, "qemu: tried to set invalid watchpoint at "
1420
                TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1421
        return -EINVAL;
1422
    }
1423
    wp = qemu_malloc(sizeof(*wp));
1424

    
1425
    wp->vaddr = addr;
1426
    wp->len_mask = len_mask;
1427
    wp->flags = flags;
1428

    
1429
    /* keep all GDB-injected watchpoints in front */
1430
    if (flags & BP_GDB)
1431
        QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
1432
    else
1433
        QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
1434

    
1435
    tlb_flush_page(env, addr);
1436

    
1437
    if (watchpoint)
1438
        *watchpoint = wp;
1439
    return 0;
1440
}
1441

    
1442
/* Remove a specific watchpoint.  */
1443
int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1444
                          int flags)
1445
{
1446
    target_ulong len_mask = ~(len - 1);
1447
    CPUWatchpoint *wp;
1448

    
1449
    QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1450
        if (addr == wp->vaddr && len_mask == wp->len_mask
1451
                && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1452
            cpu_watchpoint_remove_by_ref(env, wp);
1453
            return 0;
1454
        }
1455
    }
1456
    return -ENOENT;
1457
}
1458

    
1459
/* Remove a specific watchpoint by reference.  */
1460
void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
1461
{
1462
    QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
1463

    
1464
    tlb_flush_page(env, watchpoint->vaddr);
1465

    
1466
    qemu_free(watchpoint);
1467
}
1468

    
1469
/* Remove all matching watchpoints.  */
1470
void cpu_watchpoint_remove_all(CPUState *env, int mask)
1471
{
1472
    CPUWatchpoint *wp, *next;
1473

    
1474
    QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
1475
        if (wp->flags & mask)
1476
            cpu_watchpoint_remove_by_ref(env, wp);
1477
    }
1478
}
1479
#endif
1480

    
1481
/* Add a breakpoint.  */
1482
int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
1483
                          CPUBreakpoint **breakpoint)
1484
{
1485
#if defined(TARGET_HAS_ICE)
1486
    CPUBreakpoint *bp;
1487

    
1488
    bp = qemu_malloc(sizeof(*bp));
1489

    
1490
    bp->pc = pc;
1491
    bp->flags = flags;
1492

    
1493
    /* keep all GDB-injected breakpoints in front */
1494
    if (flags & BP_GDB)
1495
        QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
1496
    else
1497
        QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
1498

    
1499
    breakpoint_invalidate(env, pc);
1500

    
1501
    if (breakpoint)
1502
        *breakpoint = bp;
1503
    return 0;
1504
#else
1505
    return -ENOSYS;
1506
#endif
1507
}
1508

    
1509
/* Remove a specific breakpoint.  */
1510
int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1511
{
1512
#if defined(TARGET_HAS_ICE)
1513
    CPUBreakpoint *bp;
1514

    
1515
    QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1516
        if (bp->pc == pc && bp->flags == flags) {
1517
            cpu_breakpoint_remove_by_ref(env, bp);
1518
            return 0;
1519
        }
1520
    }
1521
    return -ENOENT;
1522
#else
1523
    return -ENOSYS;
1524
#endif
1525
}
1526

    
1527
/* Remove a specific breakpoint by reference.  */
1528
void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
1529
{
1530
#if defined(TARGET_HAS_ICE)
1531
    QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
1532

    
1533
    breakpoint_invalidate(env, breakpoint->pc);
1534

    
1535
    qemu_free(breakpoint);
1536
#endif
1537
}
1538

    
1539
/* Remove all matching breakpoints. */
1540
void cpu_breakpoint_remove_all(CPUState *env, int mask)
1541
{
1542
#if defined(TARGET_HAS_ICE)
1543
    CPUBreakpoint *bp, *next;
1544

    
1545
    QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
1546
        if (bp->flags & mask)
1547
            cpu_breakpoint_remove_by_ref(env, bp);
1548
    }
1549
#endif
1550
}
1551

    
1552
/* enable or disable single step mode. EXCP_DEBUG is returned by the
1553
   CPU loop after each instruction */
1554
void cpu_single_step(CPUState *env, int enabled)
1555
{
1556
#if defined(TARGET_HAS_ICE)
1557
    if (env->singlestep_enabled != enabled) {
1558
        env->singlestep_enabled = enabled;
1559
        if (kvm_enabled())
1560
            kvm_update_guest_debug(env, 0);
1561
        else {
1562
            /* must flush all the translated code to avoid inconsistencies */
1563
            /* XXX: only flush what is necessary */
1564
            tb_flush(env);
1565
        }
1566
    }
1567
#endif
1568
}
1569

    
1570
/* enable or disable low levels log */
1571
void cpu_set_log(int log_flags)
1572
{
1573
    loglevel = log_flags;
1574
    if (loglevel && !logfile) {
1575
        logfile = fopen(logfilename, log_append ? "a" : "w");
1576
        if (!logfile) {
1577
            perror(logfilename);
1578
            _exit(1);
1579
        }
1580
#if !defined(CONFIG_SOFTMMU)
1581
        /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1582
        {
1583
            static char logfile_buf[4096];
1584
            setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1585
        }
1586
#elif !defined(_WIN32)
1587
        /* Win32 doesn't support line-buffering and requires size >= 2 */
1588
        setvbuf(logfile, NULL, _IOLBF, 0);
1589
#endif
1590
        log_append = 1;
1591
    }
1592
    if (!loglevel && logfile) {
1593
        fclose(logfile);
1594
        logfile = NULL;
1595
    }
1596
}
1597

    
1598
void cpu_set_log_filename(const char *filename)
1599
{
1600
    logfilename = strdup(filename);
1601
    if (logfile) {
1602
        fclose(logfile);
1603
        logfile = NULL;
1604
    }
1605
    cpu_set_log(loglevel);
1606
}
1607

    
1608
static void cpu_unlink_tb(CPUState *env)
1609
{
1610
    /* FIXME: TB unchaining isn't SMP safe.  For now just ignore the
1611
       problem and hope the cpu will stop of its own accord.  For userspace
1612
       emulation this often isn't actually as bad as it sounds.  Often
1613
       signals are used primarily to interrupt blocking syscalls.  */
1614
    TranslationBlock *tb;
1615
    static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
1616

    
1617
    spin_lock(&interrupt_lock);
1618
    tb = env->current_tb;
1619
    /* if the cpu is currently executing code, we must unlink it and
1620
       all the potentially executing TB */
1621
    if (tb) {
1622
        env->current_tb = NULL;
1623
        tb_reset_jump_recursive(tb);
1624
    }
1625
    spin_unlock(&interrupt_lock);
1626
}
1627

    
1628
/* mask must never be zero, except for A20 change call */
1629
void cpu_interrupt(CPUState *env, int mask)
1630
{
1631
    int old_mask;
1632

    
1633
    old_mask = env->interrupt_request;
1634
    env->interrupt_request |= mask;
1635

    
1636
#ifndef CONFIG_USER_ONLY
1637
    /*
1638
     * If called from iothread context, wake the target cpu in
1639
     * case its halted.
1640
     */
1641
    if (!qemu_cpu_self(env)) {
1642
        qemu_cpu_kick(env);
1643
        return;
1644
    }
1645
#endif
1646

    
1647
    if (use_icount) {
1648
        env->icount_decr.u16.high = 0xffff;
1649
#ifndef CONFIG_USER_ONLY
1650
        if (!can_do_io(env)
1651
            && (mask & ~old_mask) != 0) {
1652
            cpu_abort(env, "Raised interrupt while not in I/O function");
1653
        }
1654
#endif
1655
    } else {
1656
        cpu_unlink_tb(env);
1657
    }
1658
}
1659

    
1660
void cpu_reset_interrupt(CPUState *env, int mask)
1661
{
1662
    env->interrupt_request &= ~mask;
1663
}
1664

    
1665
void cpu_exit(CPUState *env)
1666
{
1667
    env->exit_request = 1;
1668
    cpu_unlink_tb(env);
1669
}
1670

    
1671
const CPULogItem cpu_log_items[] = {
1672
    { CPU_LOG_TB_OUT_ASM, "out_asm",
1673
      "show generated host assembly code for each compiled TB" },
1674
    { CPU_LOG_TB_IN_ASM, "in_asm",
1675
      "show target assembly code for each compiled TB" },
1676
    { CPU_LOG_TB_OP, "op",
1677
      "show micro ops for each compiled TB" },
1678
    { CPU_LOG_TB_OP_OPT, "op_opt",
1679
      "show micro ops "
1680
#ifdef TARGET_I386
1681
      "before eflags optimization and "
1682
#endif
1683
      "after liveness analysis" },
1684
    { CPU_LOG_INT, "int",
1685
      "show interrupts/exceptions in short format" },
1686
    { CPU_LOG_EXEC, "exec",
1687
      "show trace before each executed TB (lots of logs)" },
1688
    { CPU_LOG_TB_CPU, "cpu",
1689
      "show CPU state before block translation" },
1690
#ifdef TARGET_I386
1691
    { CPU_LOG_PCALL, "pcall",
1692
      "show protected mode far calls/returns/exceptions" },
1693
    { CPU_LOG_RESET, "cpu_reset",
1694
      "show CPU state before CPU resets" },
1695
#endif
1696
#ifdef DEBUG_IOPORT
1697
    { CPU_LOG_IOPORT, "ioport",
1698
      "show all i/o ports accesses" },
1699
#endif
1700
    { 0, NULL, NULL },
1701
};
1702

    
1703
#ifndef CONFIG_USER_ONLY
1704
static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list
1705
    = QLIST_HEAD_INITIALIZER(memory_client_list);
1706

    
1707
static void cpu_notify_set_memory(target_phys_addr_t start_addr,
1708
                                  ram_addr_t size,
1709
                                  ram_addr_t phys_offset)
1710
{
1711
    CPUPhysMemoryClient *client;
1712
    QLIST_FOREACH(client, &memory_client_list, list) {
1713
        client->set_memory(client, start_addr, size, phys_offset);
1714
    }
1715
}
1716

    
1717
static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start,
1718
                                        target_phys_addr_t end)
1719
{
1720
    CPUPhysMemoryClient *client;
1721
    QLIST_FOREACH(client, &memory_client_list, list) {
1722
        int r = client->sync_dirty_bitmap(client, start, end);
1723
        if (r < 0)
1724
            return r;
1725
    }
1726
    return 0;
1727
}
1728

    
1729
static int cpu_notify_migration_log(int enable)
1730
{
1731
    CPUPhysMemoryClient *client;
1732
    QLIST_FOREACH(client, &memory_client_list, list) {
1733
        int r = client->migration_log(client, enable);
1734
        if (r < 0)
1735
            return r;
1736
    }
1737
    return 0;
1738
}
1739

    
1740
static void phys_page_for_each_1(CPUPhysMemoryClient *client,
1741
                                 int level, void **lp)
1742
{
1743
    int i;
1744

    
1745
    if (*lp == NULL) {
1746
        return;
1747
    }
1748
    if (level == 0) {
1749
        PhysPageDesc *pd = *lp;
1750
        for (i = 0; i < L2_SIZE; ++i) {
1751
            if (pd[i].phys_offset != IO_MEM_UNASSIGNED) {
1752
                client->set_memory(client, pd[i].region_offset,
1753
                                   TARGET_PAGE_SIZE, pd[i].phys_offset);
1754
            }
1755
        }
1756
    } else {
1757
        void **pp = *lp;
1758
        for (i = 0; i < L2_SIZE; ++i) {
1759
            phys_page_for_each_1(client, level - 1, pp + i);
1760
        }
1761
    }
1762
}
1763

    
1764
static void phys_page_for_each(CPUPhysMemoryClient *client)
1765
{
1766
    int i;
1767
    for (i = 0; i < P_L1_SIZE; ++i) {
1768
        phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1,
1769
                             l1_phys_map + 1);
1770
    }
1771
}
1772

    
1773
void cpu_register_phys_memory_client(CPUPhysMemoryClient *client)
1774
{
1775
    QLIST_INSERT_HEAD(&memory_client_list, client, list);
1776
    phys_page_for_each(client);
1777
}
1778

    
1779
void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client)
1780
{
1781
    QLIST_REMOVE(client, list);
1782
}
1783
#endif
1784

    
1785
static int cmp1(const char *s1, int n, const char *s2)
1786
{
1787
    if (strlen(s2) != n)
1788
        return 0;
1789
    return memcmp(s1, s2, n) == 0;
1790
}
1791

    
1792
/* takes a comma separated list of log masks. Return 0 if error. */
1793
int cpu_str_to_log_mask(const char *str)
1794
{
1795
    const CPULogItem *item;
1796
    int mask;
1797
    const char *p, *p1;
1798

    
1799
    p = str;
1800
    mask = 0;
1801
    for(;;) {
1802
        p1 = strchr(p, ',');
1803
        if (!p1)
1804
            p1 = p + strlen(p);
1805
        if(cmp1(p,p1-p,"all")) {
1806
                for(item = cpu_log_items; item->mask != 0; item++) {
1807
                        mask |= item->mask;
1808
                }
1809
        } else {
1810
        for(item = cpu_log_items; item->mask != 0; item++) {
1811
            if (cmp1(p, p1 - p, item->name))
1812
                goto found;
1813
        }
1814
        return 0;
1815
        }
1816
    found:
1817
        mask |= item->mask;
1818
        if (*p1 != ',')
1819
            break;
1820
        p = p1 + 1;
1821
    }
1822
    return mask;
1823
}
1824

    
1825
void cpu_abort(CPUState *env, const char *fmt, ...)
1826
{
1827
    va_list ap;
1828
    va_list ap2;
1829

    
1830
    va_start(ap, fmt);
1831
    va_copy(ap2, ap);
1832
    fprintf(stderr, "qemu: fatal: ");
1833
    vfprintf(stderr, fmt, ap);
1834
    fprintf(stderr, "\n");
1835
#ifdef TARGET_I386
1836
    cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1837
#else
1838
    cpu_dump_state(env, stderr, fprintf, 0);
1839
#endif
1840
    if (qemu_log_enabled()) {
1841
        qemu_log("qemu: fatal: ");
1842
        qemu_log_vprintf(fmt, ap2);
1843
        qemu_log("\n");
1844
#ifdef TARGET_I386
1845
        log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1846
#else
1847
        log_cpu_state(env, 0);
1848
#endif
1849
        qemu_log_flush();
1850
        qemu_log_close();
1851
    }
1852
    va_end(ap2);
1853
    va_end(ap);
1854
#if defined(CONFIG_USER_ONLY)
1855
    {
1856
        struct sigaction act;
1857
        sigfillset(&act.sa_mask);
1858
        act.sa_handler = SIG_DFL;
1859
        sigaction(SIGABRT, &act, NULL);
1860
    }
1861
#endif
1862
    abort();
1863
}
1864

    
1865
CPUState *cpu_copy(CPUState *env)
1866
{
1867
    CPUState *new_env = cpu_init(env->cpu_model_str);
1868
    CPUState *next_cpu = new_env->next_cpu;
1869
    int cpu_index = new_env->cpu_index;
1870
#if defined(TARGET_HAS_ICE)
1871
    CPUBreakpoint *bp;
1872
    CPUWatchpoint *wp;
1873
#endif
1874

    
1875
    memcpy(new_env, env, sizeof(CPUState));
1876

    
1877
    /* Preserve chaining and index. */
1878
    new_env->next_cpu = next_cpu;
1879
    new_env->cpu_index = cpu_index;
1880

    
1881
    /* Clone all break/watchpoints.
1882
       Note: Once we support ptrace with hw-debug register access, make sure
1883
       BP_CPU break/watchpoints are handled correctly on clone. */
1884
    QTAILQ_INIT(&env->breakpoints);
1885
    QTAILQ_INIT(&env->watchpoints);
1886
#if defined(TARGET_HAS_ICE)
1887
    QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1888
        cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
1889
    }
1890
    QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1891
        cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
1892
                              wp->flags, NULL);
1893
    }
1894
#endif
1895

    
1896
    return new_env;
1897
}
1898

    
1899
#if !defined(CONFIG_USER_ONLY)
1900

    
1901
static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1902
{
1903
    unsigned int i;
1904

    
1905
    /* Discard jump cache entries for any tb which might potentially
1906
       overlap the flushed page.  */
1907
    i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1908
    memset (&env->tb_jmp_cache[i], 0, 
1909
            TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1910

    
1911
    i = tb_jmp_cache_hash_page(addr);
1912
    memset (&env->tb_jmp_cache[i], 0, 
1913
            TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1914
}
1915

    
1916
static CPUTLBEntry s_cputlb_empty_entry = {
1917
    .addr_read  = -1,
1918
    .addr_write = -1,
1919
    .addr_code  = -1,
1920
    .addend     = -1,
1921
};
1922

    
1923
/* NOTE: if flush_global is true, also flush global entries (not
1924
   implemented yet) */
1925
void tlb_flush(CPUState *env, int flush_global)
1926
{
1927
    int i;
1928

    
1929
#if defined(DEBUG_TLB)
1930
    printf("tlb_flush:\n");
1931
#endif
1932
    /* must reset current TB so that interrupts cannot modify the
1933
       links while we are modifying them */
1934
    env->current_tb = NULL;
1935

    
1936
    for(i = 0; i < CPU_TLB_SIZE; i++) {
1937
        int mmu_idx;
1938
        for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
1939
            env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
1940
        }
1941
    }
1942

    
1943
    memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
1944

    
1945
    env->tlb_flush_addr = -1;
1946
    env->tlb_flush_mask = 0;
1947
    tlb_flush_count++;
1948
}
1949

    
1950
static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1951
{
1952
    if (addr == (tlb_entry->addr_read &
1953
                 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1954
        addr == (tlb_entry->addr_write &
1955
                 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1956
        addr == (tlb_entry->addr_code &
1957
                 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1958
        *tlb_entry = s_cputlb_empty_entry;
1959
    }
1960
}
1961

    
1962
void tlb_flush_page(CPUState *env, target_ulong addr)
1963
{
1964
    int i;
1965
    int mmu_idx;
1966

    
1967
#if defined(DEBUG_TLB)
1968
    printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
1969
#endif
1970
    /* Check if we need to flush due to large pages.  */
1971
    if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
1972
#if defined(DEBUG_TLB)
1973
        printf("tlb_flush_page: forced full flush ("
1974
               TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
1975
               env->tlb_flush_addr, env->tlb_flush_mask);
1976
#endif
1977
        tlb_flush(env, 1);
1978
        return;
1979
    }
1980
    /* must reset current TB so that interrupts cannot modify the
1981
       links while we are modifying them */
1982
    env->current_tb = NULL;
1983

    
1984
    addr &= TARGET_PAGE_MASK;
1985
    i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1986
    for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
1987
        tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
1988

    
1989
    tlb_flush_jmp_cache(env, addr);
1990
}
1991

    
1992
/* update the TLBs so that writes to code in the virtual page 'addr'
1993
   can be detected */
1994
static void tlb_protect_code(ram_addr_t ram_addr)
1995
{
1996
    cpu_physical_memory_reset_dirty(ram_addr,
1997
                                    ram_addr + TARGET_PAGE_SIZE,
1998
                                    CODE_DIRTY_FLAG);
1999
}
2000

    
2001
/* update the TLB so that writes in physical page 'phys_addr' are no longer
2002
   tested for self modifying code */
2003
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
2004
                                    target_ulong vaddr)
2005
{
2006
    cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
2007
}
2008

    
2009
static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
2010
                                         unsigned long start, unsigned long length)
2011
{
2012
    unsigned long addr;
2013
    if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
2014
        addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
2015
        if ((addr - start) < length) {
2016
            tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
2017
        }
2018
    }
2019
}
2020

    
2021
/* Note: start and end must be within the same ram block.  */
2022
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
2023
                                     int dirty_flags)
2024
{
2025
    CPUState *env;
2026
    unsigned long length, start1;
2027
    int i;
2028

    
2029
    start &= TARGET_PAGE_MASK;
2030
    end = TARGET_PAGE_ALIGN(end);
2031

    
2032
    length = end - start;
2033
    if (length == 0)
2034
        return;
2035
    cpu_physical_memory_mask_dirty_range(start, length, dirty_flags);
2036

    
2037
    /* we modify the TLB cache so that the dirty bit will be set again
2038
       when accessing the range */
2039
    start1 = (unsigned long)qemu_get_ram_ptr(start);
2040
    /* Chek that we don't span multiple blocks - this breaks the
2041
       address comparisons below.  */
2042
    if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1
2043
            != (end - 1) - start) {
2044
        abort();
2045
    }
2046

    
2047
    for(env = first_cpu; env != NULL; env = env->next_cpu) {
2048
        int mmu_idx;
2049
        for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
2050
            for(i = 0; i < CPU_TLB_SIZE; i++)
2051
                tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
2052
                                      start1, length);
2053
        }
2054
    }
2055
}
2056

    
2057
int cpu_physical_memory_set_dirty_tracking(int enable)
2058
{
2059
    int ret = 0;
2060
    in_migration = enable;
2061
    ret = cpu_notify_migration_log(!!enable);
2062
    return ret;
2063
}
2064

    
2065
int cpu_physical_memory_get_dirty_tracking(void)
2066
{
2067
    return in_migration;
2068
}
2069

    
2070
int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
2071
                                   target_phys_addr_t end_addr)
2072
{
2073
    int ret;
2074

    
2075
    ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr);
2076
    return ret;
2077
}
2078

    
2079
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
2080
{
2081
    ram_addr_t ram_addr;
2082
    void *p;
2083

    
2084
    if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
2085
        p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK)
2086
            + tlb_entry->addend);
2087
        ram_addr = qemu_ram_addr_from_host(p);
2088
        if (!cpu_physical_memory_is_dirty(ram_addr)) {
2089
            tlb_entry->addr_write |= TLB_NOTDIRTY;
2090
        }
2091
    }
2092
}
2093

    
2094
/* update the TLB according to the current state of the dirty bits */
2095
void cpu_tlb_update_dirty(CPUState *env)
2096
{
2097
    int i;
2098
    int mmu_idx;
2099
    for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
2100
        for(i = 0; i < CPU_TLB_SIZE; i++)
2101
            tlb_update_dirty(&env->tlb_table[mmu_idx][i]);
2102
    }
2103
}
2104

    
2105
static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
2106
{
2107
    if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
2108
        tlb_entry->addr_write = vaddr;
2109
}
2110

    
2111
/* update the TLB corresponding to virtual page vaddr
2112
   so that it is no longer dirty */
2113
static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
2114
{
2115
    int i;
2116
    int mmu_idx;
2117

    
2118
    vaddr &= TARGET_PAGE_MASK;
2119
    i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2120
    for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
2121
        tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
2122
}
2123

    
2124
/* Our TLB does not support large pages, so remember the area covered by
2125
   large pages and trigger a full TLB flush if these are invalidated.  */
2126
static void tlb_add_large_page(CPUState *env, target_ulong vaddr,
2127
                               target_ulong size)
2128
{
2129
    target_ulong mask = ~(size - 1);
2130

    
2131
    if (env->tlb_flush_addr == (target_ulong)-1) {
2132
        env->tlb_flush_addr = vaddr & mask;
2133
        env->tlb_flush_mask = mask;
2134
        return;
2135
    }
2136
    /* Extend the existing region to include the new page.
2137
       This is a compromise between unnecessary flushes and the cost
2138
       of maintaining a full variable size TLB.  */
2139
    mask &= env->tlb_flush_mask;
2140
    while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
2141
        mask <<= 1;
2142
    }
2143
    env->tlb_flush_addr &= mask;
2144
    env->tlb_flush_mask = mask;
2145
}
2146

    
2147
/* Add a new TLB entry. At most one entry for a given virtual address
2148
   is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
2149
   supplied size is only used by tlb_flush_page.  */
2150
void tlb_set_page(CPUState *env, target_ulong vaddr,
2151
                  target_phys_addr_t paddr, int prot,
2152
                  int mmu_idx, target_ulong size)
2153
{
2154
    PhysPageDesc *p;
2155
    unsigned long pd;
2156
    unsigned int index;
2157
    target_ulong address;
2158
    target_ulong code_address;
2159
    unsigned long addend;
2160
    CPUTLBEntry *te;
2161
    CPUWatchpoint *wp;
2162
    target_phys_addr_t iotlb;
2163

    
2164
    assert(size >= TARGET_PAGE_SIZE);
2165
    if (size != TARGET_PAGE_SIZE) {
2166
        tlb_add_large_page(env, vaddr, size);
2167
    }
2168
    p = phys_page_find(paddr >> TARGET_PAGE_BITS);
2169
    if (!p) {
2170
        pd = IO_MEM_UNASSIGNED;
2171
    } else {
2172
        pd = p->phys_offset;
2173
    }
2174
#if defined(DEBUG_TLB)
2175
    printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
2176
           vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
2177
#endif
2178

    
2179
    address = vaddr;
2180
    if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
2181
        /* IO memory case (romd handled later) */
2182
        address |= TLB_MMIO;
2183
    }
2184
    addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);
2185
    if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
2186
        /* Normal RAM.  */
2187
        iotlb = pd & TARGET_PAGE_MASK;
2188
        if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
2189
            iotlb |= IO_MEM_NOTDIRTY;
2190
        else
2191
            iotlb |= IO_MEM_ROM;
2192
    } else {
2193
        /* IO handlers are currently passed a physical address.
2194
           It would be nice to pass an offset from the base address
2195
           of that region.  This would avoid having to special case RAM,
2196
           and avoid full address decoding in every device.
2197
           We can't use the high bits of pd for this because
2198
           IO_MEM_ROMD uses these as a ram address.  */
2199
        iotlb = (pd & ~TARGET_PAGE_MASK);
2200
        if (p) {
2201
            iotlb += p->region_offset;
2202
        } else {
2203
            iotlb += paddr;
2204
        }
2205
    }
2206

    
2207
    code_address = address;
2208
    /* Make accesses to pages with watchpoints go via the
2209
       watchpoint trap routines.  */
2210
    QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
2211
        if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
2212
            iotlb = io_mem_watch + paddr;
2213
            /* TODO: The memory case can be optimized by not trapping
2214
               reads of pages with a write breakpoint.  */
2215
            address |= TLB_MMIO;
2216
        }
2217
    }
2218

    
2219
    index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2220
    env->iotlb[mmu_idx][index] = iotlb - vaddr;
2221
    te = &env->tlb_table[mmu_idx][index];
2222
    te->addend = addend - vaddr;
2223
    if (prot & PAGE_READ) {
2224
        te->addr_read = address;
2225
    } else {
2226
        te->addr_read = -1;
2227
    }
2228

    
2229
    if (prot & PAGE_EXEC) {
2230
        te->addr_code = code_address;
2231
    } else {
2232
        te->addr_code = -1;
2233
    }
2234
    if (prot & PAGE_WRITE) {
2235
        if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2236
            (pd & IO_MEM_ROMD)) {
2237
            /* Write access calls the I/O callback.  */
2238
            te->addr_write = address | TLB_MMIO;
2239
        } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2240
                   !cpu_physical_memory_is_dirty(pd)) {
2241
            te->addr_write = address | TLB_NOTDIRTY;
2242
        } else {
2243
            te->addr_write = address;
2244
        }
2245
    } else {
2246
        te->addr_write = -1;
2247
    }
2248
}
2249

    
2250
#else
2251

    
2252
void tlb_flush(CPUState *env, int flush_global)
2253
{
2254
}
2255

    
2256
void tlb_flush_page(CPUState *env, target_ulong addr)
2257
{
2258
}
2259

    
2260
/*
2261
 * Walks guest process memory "regions" one by one
2262
 * and calls callback function 'fn' for each region.
2263
 */
2264

    
2265
struct walk_memory_regions_data
2266
{
2267
    walk_memory_regions_fn fn;
2268
    void *priv;
2269
    unsigned long start;
2270
    int prot;
2271
};
2272

    
2273
static int walk_memory_regions_end(struct walk_memory_regions_data *data,
2274
                                   abi_ulong end, int new_prot)
2275
{
2276
    if (data->start != -1ul) {
2277
        int rc = data->fn(data->priv, data->start, end, data->prot);
2278
        if (rc != 0) {
2279
            return rc;
2280
        }
2281
    }
2282

    
2283
    data->start = (new_prot ? end : -1ul);
2284
    data->prot = new_prot;
2285

    
2286
    return 0;
2287
}
2288

    
2289
static int walk_memory_regions_1(struct walk_memory_regions_data *data,
2290
                                 abi_ulong base, int level, void **lp)
2291
{
2292
    abi_ulong pa;
2293
    int i, rc;
2294

    
2295
    if (*lp == NULL) {
2296
        return walk_memory_regions_end(data, base, 0);
2297
    }
2298

    
2299
    if (level == 0) {
2300
        PageDesc *pd = *lp;
2301
        for (i = 0; i < L2_SIZE; ++i) {
2302
            int prot = pd[i].flags;
2303

    
2304
            pa = base | (i << TARGET_PAGE_BITS);
2305
            if (prot != data->prot) {
2306
                rc = walk_memory_regions_end(data, pa, prot);
2307
                if (rc != 0) {
2308
                    return rc;
2309
                }
2310
            }
2311
        }
2312
    } else {
2313
        void **pp = *lp;
2314
        for (i = 0; i < L2_SIZE; ++i) {
2315
            pa = base | ((abi_ulong)i <<
2316
                (TARGET_PAGE_BITS + L2_BITS * level));
2317
            rc = walk_memory_regions_1(data, pa, level - 1, pp + i);
2318
            if (rc != 0) {
2319
                return rc;
2320
            }
2321
        }
2322
    }
2323

    
2324
    return 0;
2325
}
2326

    
2327
int walk_memory_regions(void *priv, walk_memory_regions_fn fn)
2328
{
2329
    struct walk_memory_regions_data data;
2330
    unsigned long i;
2331

    
2332
    data.fn = fn;
2333
    data.priv = priv;
2334
    data.start = -1ul;
2335
    data.prot = 0;
2336

    
2337
    for (i = 0; i < V_L1_SIZE; i++) {
2338
        int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT,
2339
                                       V_L1_SHIFT / L2_BITS - 1, l1_map + i);
2340
        if (rc != 0) {
2341
            return rc;
2342
        }
2343
    }
2344

    
2345
    return walk_memory_regions_end(&data, 0, 0);
2346
}
2347

    
2348
static int dump_region(void *priv, abi_ulong start,
2349
    abi_ulong end, unsigned long prot)
2350
{
2351
    FILE *f = (FILE *)priv;
2352

    
2353
    (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx
2354
        " "TARGET_ABI_FMT_lx" %c%c%c\n",
2355
        start, end, end - start,
2356
        ((prot & PAGE_READ) ? 'r' : '-'),
2357
        ((prot & PAGE_WRITE) ? 'w' : '-'),
2358
        ((prot & PAGE_EXEC) ? 'x' : '-'));
2359

    
2360
    return (0);
2361
}
2362

    
2363
/* dump memory mappings */
2364
void page_dump(FILE *f)
2365
{
2366
    (void) fprintf(f, "%-8s %-8s %-8s %s\n",
2367
            "start", "end", "size", "prot");
2368
    walk_memory_regions(f, dump_region);
2369
}
2370

    
2371
int page_get_flags(target_ulong address)
2372
{
2373
    PageDesc *p;
2374

    
2375
    p = page_find(address >> TARGET_PAGE_BITS);
2376
    if (!p)
2377
        return 0;
2378
    return p->flags;
2379
}
2380

    
2381
/* Modify the flags of a page and invalidate the code if necessary.
2382
   The flag PAGE_WRITE_ORG is positioned automatically depending
2383
   on PAGE_WRITE.  The mmap_lock should already be held.  */
2384
void page_set_flags(target_ulong start, target_ulong end, int flags)
2385
{
2386
    target_ulong addr, len;
2387

    
2388
    /* This function should never be called with addresses outside the
2389
       guest address space.  If this assert fires, it probably indicates
2390
       a missing call to h2g_valid.  */
2391
#if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
2392
    assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
2393
#endif
2394
    assert(start < end);
2395

    
2396
    start = start & TARGET_PAGE_MASK;
2397
    end = TARGET_PAGE_ALIGN(end);
2398

    
2399
    if (flags & PAGE_WRITE) {
2400
        flags |= PAGE_WRITE_ORG;
2401
    }
2402

    
2403
    for (addr = start, len = end - start;
2404
         len != 0;
2405
         len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
2406
        PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2407

    
2408
        /* If the write protection bit is set, then we invalidate
2409
           the code inside.  */
2410
        if (!(p->flags & PAGE_WRITE) &&
2411
            (flags & PAGE_WRITE) &&
2412
            p->first_tb) {
2413
            tb_invalidate_phys_page(addr, 0, NULL);
2414
        }
2415
        p->flags = flags;
2416
    }
2417
}
2418

    
2419
int page_check_range(target_ulong start, target_ulong len, int flags)
2420
{
2421
    PageDesc *p;
2422
    target_ulong end;
2423
    target_ulong addr;
2424

    
2425
    /* This function should never be called with addresses outside the
2426
       guest address space.  If this assert fires, it probably indicates
2427
       a missing call to h2g_valid.  */
2428
#if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
2429
    assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
2430
#endif
2431

    
2432
    if (start + len - 1 < start) {
2433
        /* We've wrapped around.  */
2434
        return -1;
2435
    }
2436

    
2437
    end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2438
    start = start & TARGET_PAGE_MASK;
2439

    
2440
    for (addr = start, len = end - start;
2441
         len != 0;
2442
         len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
2443
        p = page_find(addr >> TARGET_PAGE_BITS);
2444
        if( !p )
2445
            return -1;
2446
        if( !(p->flags & PAGE_VALID) )
2447
            return -1;
2448

    
2449
        if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
2450
            return -1;
2451
        if (flags & PAGE_WRITE) {
2452
            if (!(p->flags & PAGE_WRITE_ORG))
2453
                return -1;
2454
            /* unprotect the page if it was put read-only because it
2455
               contains translated code */
2456
            if (!(p->flags & PAGE_WRITE)) {
2457
                if (!page_unprotect(addr, 0, NULL))
2458
                    return -1;
2459
            }
2460
            return 0;
2461
        }
2462
    }
2463
    return 0;
2464
}
2465

    
2466
/* called from signal handler: invalidate the code and unprotect the
2467
   page. Return TRUE if the fault was successfully handled. */
2468
int page_unprotect(target_ulong address, unsigned long pc, void *puc)
2469
{
2470
    unsigned int prot;
2471
    PageDesc *p;
2472
    target_ulong host_start, host_end, addr;
2473

    
2474
    /* Technically this isn't safe inside a signal handler.  However we
2475
       know this only ever happens in a synchronous SEGV handler, so in
2476
       practice it seems to be ok.  */
2477
    mmap_lock();
2478

    
2479
    p = page_find(address >> TARGET_PAGE_BITS);
2480
    if (!p) {
2481
        mmap_unlock();
2482
        return 0;
2483
    }
2484

    
2485
    /* if the page was really writable, then we change its
2486
       protection back to writable */
2487
    if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) {
2488
        host_start = address & qemu_host_page_mask;
2489
        host_end = host_start + qemu_host_page_size;
2490

    
2491
        prot = 0;
2492
        for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) {
2493
            p = page_find(addr >> TARGET_PAGE_BITS);
2494
            p->flags |= PAGE_WRITE;
2495
            prot |= p->flags;
2496

    
2497
            /* and since the content will be modified, we must invalidate
2498
               the corresponding translated code. */
2499
            tb_invalidate_phys_page(addr, pc, puc);
2500
#ifdef DEBUG_TB_CHECK
2501
            tb_invalidate_check(addr);
2502
#endif
2503
        }
2504
        mprotect((void *)g2h(host_start), qemu_host_page_size,
2505
                 prot & PAGE_BITS);
2506

    
2507
        mmap_unlock();
2508
        return 1;
2509
    }
2510
    mmap_unlock();
2511
    return 0;
2512
}
2513

    
2514
static inline void tlb_set_dirty(CPUState *env,
2515
                                 unsigned long addr, target_ulong vaddr)
2516
{
2517
}
2518
#endif /* defined(CONFIG_USER_ONLY) */
2519

    
2520
#if !defined(CONFIG_USER_ONLY)
2521

    
2522
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
2523
typedef struct subpage_t {
2524
    target_phys_addr_t base;
2525
    ram_addr_t sub_io_index[TARGET_PAGE_SIZE];
2526
    ram_addr_t region_offset[TARGET_PAGE_SIZE];
2527
} subpage_t;
2528

    
2529
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2530
                             ram_addr_t memory, ram_addr_t region_offset);
2531
static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2532
                                ram_addr_t orig_memory,
2533
                                ram_addr_t region_offset);
2534
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2535
                      need_subpage)                                     \
2536
    do {                                                                \
2537
        if (addr > start_addr)                                          \
2538
            start_addr2 = 0;                                            \
2539
        else {                                                          \
2540
            start_addr2 = start_addr & ~TARGET_PAGE_MASK;               \
2541
            if (start_addr2 > 0)                                        \
2542
                need_subpage = 1;                                       \
2543
        }                                                               \
2544
                                                                        \
2545
        if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE)        \
2546
            end_addr2 = TARGET_PAGE_SIZE - 1;                           \
2547
        else {                                                          \
2548
            end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2549
            if (end_addr2 < TARGET_PAGE_SIZE - 1)                       \
2550
                need_subpage = 1;                                       \
2551
        }                                                               \
2552
    } while (0)
2553

    
2554
/* register physical memory.
2555
   For RAM, 'size' must be a multiple of the target page size.
2556
   If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
2557
   io memory page.  The address used when calling the IO function is
2558
   the offset from the start of the region, plus region_offset.  Both
2559
   start_addr and region_offset are rounded down to a page boundary
2560
   before calculating this offset.  This should not be a problem unless
2561
   the low bits of start_addr and region_offset differ.  */
2562
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
2563
                                         ram_addr_t size,
2564
                                         ram_addr_t phys_offset,
2565
                                         ram_addr_t region_offset)
2566
{
2567
    target_phys_addr_t addr, end_addr;
2568
    PhysPageDesc *p;
2569
    CPUState *env;
2570
    ram_addr_t orig_size = size;
2571
    subpage_t *subpage;
2572

    
2573
    cpu_notify_set_memory(start_addr, size, phys_offset);
2574

    
2575
    if (phys_offset == IO_MEM_UNASSIGNED) {
2576
        region_offset = start_addr;
2577
    }
2578
    region_offset &= TARGET_PAGE_MASK;
2579
    size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2580
    end_addr = start_addr + (target_phys_addr_t)size;
2581
    for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
2582
        p = phys_page_find(addr >> TARGET_PAGE_BITS);
2583
        if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
2584
            ram_addr_t orig_memory = p->phys_offset;
2585
            target_phys_addr_t start_addr2, end_addr2;
2586
            int need_subpage = 0;
2587

    
2588
            CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2589
                          need_subpage);
2590
            if (need_subpage) {
2591
                if (!(orig_memory & IO_MEM_SUBPAGE)) {
2592
                    subpage = subpage_init((addr & TARGET_PAGE_MASK),
2593
                                           &p->phys_offset, orig_memory,
2594
                                           p->region_offset);
2595
                } else {
2596
                    subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2597
                                            >> IO_MEM_SHIFT];
2598
                }
2599
                subpage_register(subpage, start_addr2, end_addr2, phys_offset,
2600
                                 region_offset);
2601
                p->region_offset = 0;
2602
            } else {
2603
                p->phys_offset = phys_offset;
2604
                if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2605
                    (phys_offset & IO_MEM_ROMD))
2606
                    phys_offset += TARGET_PAGE_SIZE;
2607
            }
2608
        } else {
2609
            p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2610
            p->phys_offset = phys_offset;
2611
            p->region_offset = region_offset;
2612
            if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2613
                (phys_offset & IO_MEM_ROMD)) {
2614
                phys_offset += TARGET_PAGE_SIZE;
2615
            } else {
2616
                target_phys_addr_t start_addr2, end_addr2;
2617
                int need_subpage = 0;
2618

    
2619
                CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2620
                              end_addr2, need_subpage);
2621

    
2622
                if (need_subpage) {
2623
                    subpage = subpage_init((addr & TARGET_PAGE_MASK),
2624
                                           &p->phys_offset, IO_MEM_UNASSIGNED,
2625
                                           addr & TARGET_PAGE_MASK);
2626
                    subpage_register(subpage, start_addr2, end_addr2,
2627
                                     phys_offset, region_offset);
2628
                    p->region_offset = 0;
2629
                }
2630
            }
2631
        }
2632
        region_offset += TARGET_PAGE_SIZE;
2633
    }
2634

    
2635
    /* since each CPU stores ram addresses in its TLB cache, we must
2636
       reset the modified entries */
2637
    /* XXX: slow ! */
2638
    for(env = first_cpu; env != NULL; env = env->next_cpu) {
2639
        tlb_flush(env, 1);
2640
    }
2641
}
2642

    
2643
/* XXX: temporary until new memory mapping API */
2644
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
2645
{
2646
    PhysPageDesc *p;
2647

    
2648
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
2649
    if (!p)
2650
        return IO_MEM_UNASSIGNED;
2651
    return p->phys_offset;
2652
}
2653

    
2654
void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2655
{
2656
    if (kvm_enabled())
2657
        kvm_coalesce_mmio_region(addr, size);
2658
}
2659

    
2660
void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2661
{
2662
    if (kvm_enabled())
2663
        kvm_uncoalesce_mmio_region(addr, size);
2664
}
2665

    
2666
void qemu_flush_coalesced_mmio_buffer(void)
2667
{
2668
    if (kvm_enabled())
2669
        kvm_flush_coalesced_mmio_buffer();
2670
}
2671

    
2672
#if defined(__linux__) && !defined(TARGET_S390X)
2673

    
2674
#include <sys/vfs.h>
2675

    
2676
#define HUGETLBFS_MAGIC       0x958458f6
2677

    
2678
static long gethugepagesize(const char *path)
2679
{
2680
    struct statfs fs;
2681
    int ret;
2682

    
2683
    do {
2684
            ret = statfs(path, &fs);
2685
    } while (ret != 0 && errno == EINTR);
2686

    
2687
    if (ret != 0) {
2688
            perror(path);
2689
            return 0;
2690
    }
2691

    
2692
    if (fs.f_type != HUGETLBFS_MAGIC)
2693
            fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
2694

    
2695
    return fs.f_bsize;
2696
}
2697

    
2698
static void *file_ram_alloc(ram_addr_t memory, const char *path)
2699
{
2700
    char *filename;
2701
    void *area;
2702
    int fd;
2703
#ifdef MAP_POPULATE
2704
    int flags;
2705
#endif
2706
    unsigned long hpagesize;
2707

    
2708
    hpagesize = gethugepagesize(path);
2709
    if (!hpagesize) {
2710
        return NULL;
2711
    }
2712

    
2713
    if (memory < hpagesize) {
2714
        return NULL;
2715
    }
2716

    
2717
    if (kvm_enabled() && !kvm_has_sync_mmu()) {
2718
        fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n");
2719
        return NULL;
2720
    }
2721

    
2722
    if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) {
2723
        return NULL;
2724
    }
2725

    
2726
    fd = mkstemp(filename);
2727
    if (fd < 0) {
2728
        perror("unable to create backing store for hugepages");
2729
        free(filename);
2730
        return NULL;
2731
    }
2732
    unlink(filename);
2733
    free(filename);
2734

    
2735
    memory = (memory+hpagesize-1) & ~(hpagesize-1);
2736

    
2737
    /*
2738
     * ftruncate is not supported by hugetlbfs in older
2739
     * hosts, so don't bother bailing out on errors.
2740
     * If anything goes wrong with it under other filesystems,
2741
     * mmap will fail.
2742
     */
2743
    if (ftruncate(fd, memory))
2744
        perror("ftruncate");
2745

    
2746
#ifdef MAP_POPULATE
2747
    /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case
2748
     * MAP_PRIVATE is requested.  For mem_prealloc we mmap as MAP_SHARED
2749
     * to sidestep this quirk.
2750
     */
2751
    flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE;
2752
    area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0);
2753
#else
2754
    area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
2755
#endif
2756
    if (area == MAP_FAILED) {
2757
        perror("file_ram_alloc: can't mmap RAM pages");
2758
        close(fd);
2759
        return (NULL);
2760
    }
2761
    return area;
2762
}
2763
#endif
2764

    
2765
ram_addr_t qemu_ram_alloc(ram_addr_t size)
2766
{
2767
    RAMBlock *new_block;
2768

    
2769
    size = TARGET_PAGE_ALIGN(size);
2770
    new_block = qemu_malloc(sizeof(*new_block));
2771

    
2772
    if (mem_path) {
2773
#if defined (__linux__) && !defined(TARGET_S390X)
2774
        new_block->host = file_ram_alloc(size, mem_path);
2775
        if (!new_block->host)
2776
            exit(1);
2777
#else
2778
        fprintf(stderr, "-mem-path option unsupported\n");
2779
        exit(1);
2780
#endif
2781
    } else {
2782
#if defined(TARGET_S390X) && defined(CONFIG_KVM)
2783
        /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */
2784
        new_block->host = mmap((void*)0x1000000, size,
2785
                                PROT_EXEC|PROT_READ|PROT_WRITE,
2786
                                MAP_SHARED | MAP_ANONYMOUS, -1, 0);
2787
#else
2788
        new_block->host = qemu_vmalloc(size);
2789
#endif
2790
#ifdef MADV_MERGEABLE
2791
        madvise(new_block->host, size, MADV_MERGEABLE);
2792
#endif
2793
    }
2794
    new_block->offset = last_ram_offset;
2795
    new_block->length = size;
2796

    
2797
    new_block->next = ram_blocks;
2798
    ram_blocks = new_block;
2799

    
2800
    phys_ram_dirty = qemu_realloc(phys_ram_dirty,
2801
        (last_ram_offset + size) >> TARGET_PAGE_BITS);
2802
    memset(phys_ram_dirty + (last_ram_offset >> TARGET_PAGE_BITS),
2803
           0xff, size >> TARGET_PAGE_BITS);
2804

    
2805
    last_ram_offset += size;
2806

    
2807
    if (kvm_enabled())
2808
        kvm_setup_guest_memory(new_block->host, size);
2809

    
2810
    return new_block->offset;
2811
}
2812

    
2813
void qemu_ram_free(ram_addr_t addr)
2814
{
2815
    /* TODO: implement this.  */
2816
}
2817

    
2818
/* Return a host pointer to ram allocated with qemu_ram_alloc.
2819
   With the exception of the softmmu code in this file, this should
2820
   only be used for local memory (e.g. video ram) that the device owns,
2821
   and knows it isn't going to access beyond the end of the block.
2822

2823
   It should not be used for general purpose DMA.
2824
   Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
2825
 */
2826
void *qemu_get_ram_ptr(ram_addr_t addr)
2827
{
2828
    RAMBlock *prev;
2829
    RAMBlock **prevp;
2830
    RAMBlock *block;
2831

    
2832
    prev = NULL;
2833
    prevp = &ram_blocks;
2834
    block = ram_blocks;
2835
    while (block && (block->offset > addr
2836
                     || block->offset + block->length <= addr)) {
2837
        if (prev)
2838
          prevp = &prev->next;
2839
        prev = block;
2840
        block = block->next;
2841
    }
2842
    if (!block) {
2843
        fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
2844
        abort();
2845
    }
2846
    /* Move this entry to to start of the list.  */
2847
    if (prev) {
2848
        prev->next = block->next;
2849
        block->next = *prevp;
2850
        *prevp = block;
2851
    }
2852
    return block->host + (addr - block->offset);
2853
}
2854

    
2855
/* Some of the softmmu routines need to translate from a host pointer
2856
   (typically a TLB entry) back to a ram offset.  */
2857
ram_addr_t qemu_ram_addr_from_host(void *ptr)
2858
{
2859
    RAMBlock *block;
2860
    uint8_t *host = ptr;
2861

    
2862
    block = ram_blocks;
2863
    while (block && (block->host > host
2864
                     || block->host + block->length <= host)) {
2865
        block = block->next;
2866
    }
2867
    if (!block) {
2868
        fprintf(stderr, "Bad ram pointer %p\n", ptr);
2869
        abort();
2870
    }
2871
    return block->offset + (host - block->host);
2872
}
2873

    
2874
static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
2875
{
2876
#ifdef DEBUG_UNASSIGNED
2877
    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2878
#endif
2879
#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
2880
    do_unassigned_access(addr, 0, 0, 0, 1);
2881
#endif
2882
    return 0;
2883
}
2884

    
2885
static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2886
{
2887
#ifdef DEBUG_UNASSIGNED
2888
    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2889
#endif
2890
#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
2891
    do_unassigned_access(addr, 0, 0, 0, 2);
2892
#endif
2893
    return 0;
2894
}
2895

    
2896
static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2897
{
2898
#ifdef DEBUG_UNASSIGNED
2899
    printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2900
#endif
2901
#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
2902
    do_unassigned_access(addr, 0, 0, 0, 4);
2903
#endif
2904
    return 0;
2905
}
2906

    
2907
static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2908
{
2909
#ifdef DEBUG_UNASSIGNED
2910
    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2911
#endif
2912
#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
2913
    do_unassigned_access(addr, 1, 0, 0, 1);
2914
#endif
2915
}
2916

    
2917
static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2918
{
2919
#ifdef DEBUG_UNASSIGNED
2920
    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2921
#endif
2922
#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
2923
    do_unassigned_access(addr, 1, 0, 0, 2);
2924
#endif
2925
}
2926

    
2927
static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2928
{
2929
#ifdef DEBUG_UNASSIGNED
2930
    printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2931
#endif
2932
#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
2933
    do_unassigned_access(addr, 1, 0, 0, 4);
2934
#endif
2935
}
2936

    
2937
static CPUReadMemoryFunc * const unassigned_mem_read[3] = {
2938
    unassigned_mem_readb,
2939
    unassigned_mem_readw,
2940
    unassigned_mem_readl,
2941
};
2942

    
2943
static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
2944
    unassigned_mem_writeb,
2945
    unassigned_mem_writew,
2946
    unassigned_mem_writel,
2947
};
2948

    
2949
static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
2950
                                uint32_t val)
2951
{
2952
    int dirty_flags;
2953
    dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
2954
    if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2955
#if !defined(CONFIG_USER_ONLY)
2956
        tb_invalidate_phys_page_fast(ram_addr, 1);
2957
        dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
2958
#endif
2959
    }
2960
    stb_p(qemu_get_ram_ptr(ram_addr), val);
2961
    dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2962
    cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
2963
    /* we remove the notdirty callback only if the code has been
2964
       flushed */
2965
    if (dirty_flags == 0xff)
2966
        tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
2967
}
2968

    
2969
static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
2970
                                uint32_t val)
2971
{
2972
    int dirty_flags;
2973
    dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
2974
    if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2975
#if !defined(CONFIG_USER_ONLY)
2976
        tb_invalidate_phys_page_fast(ram_addr, 2);
2977
        dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
2978
#endif
2979
    }
2980
    stw_p(qemu_get_ram_ptr(ram_addr), val);
2981
    dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2982
    cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
2983
    /* we remove the notdirty callback only if the code has been
2984
       flushed */
2985
    if (dirty_flags == 0xff)
2986
        tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
2987
}
2988

    
2989
static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
2990
                                uint32_t val)
2991
{
2992
    int dirty_flags;
2993
    dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
2994
    if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2995
#if !defined(CONFIG_USER_ONLY)
2996
        tb_invalidate_phys_page_fast(ram_addr, 4);
2997
        dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
2998
#endif
2999
    }
3000
    stl_p(qemu_get_ram_ptr(ram_addr), val);
3001
    dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
3002
    cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
3003
    /* we remove the notdirty callback only if the code has been
3004
       flushed */
3005
    if (dirty_flags == 0xff)
3006
        tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
3007
}
3008

    
3009
static CPUReadMemoryFunc * const error_mem_read[3] = {
3010
    NULL, /* never used */
3011
    NULL, /* never used */
3012
    NULL, /* never used */
3013
};
3014

    
3015
static CPUWriteMemoryFunc * const notdirty_mem_write[3] = {
3016
    notdirty_mem_writeb,
3017
    notdirty_mem_writew,
3018
    notdirty_mem_writel,
3019
};
3020

    
3021
/* Generate a debug exception if a watchpoint has been hit.  */
3022
static void check_watchpoint(int offset, int len_mask, int flags)
3023
{
3024
    CPUState *env = cpu_single_env;
3025
    target_ulong pc, cs_base;
3026
    TranslationBlock *tb;
3027
    target_ulong vaddr;
3028
    CPUWatchpoint *wp;
3029
    int cpu_flags;
3030

    
3031
    if (env->watchpoint_hit) {
3032
        /* We re-entered the check after replacing the TB. Now raise
3033
         * the debug interrupt so that is will trigger after the
3034
         * current instruction. */
3035
        cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
3036
        return;
3037
    }
3038
    vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
3039
    QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
3040
        if ((vaddr == (wp->vaddr & len_mask) ||
3041
             (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
3042
            wp->flags |= BP_WATCHPOINT_HIT;
3043
            if (!env->watchpoint_hit) {
3044
                env->watchpoint_hit = wp;
3045
                tb = tb_find_pc(env->mem_io_pc);
3046
                if (!tb) {
3047
                    cpu_abort(env, "check_watchpoint: could not find TB for "
3048
                              "pc=%p", (void *)env->mem_io_pc);
3049
                }
3050
                cpu_restore_state(tb, env, env->mem_io_pc, NULL);
3051
                tb_phys_invalidate(tb, -1);
3052
                if (wp->flags & BP_STOP_BEFORE_ACCESS) {
3053
                    env->exception_index = EXCP_DEBUG;
3054
                } else {
3055
                    cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
3056
                    tb_gen_code(env, pc, cs_base, cpu_flags, 1);
3057
                }
3058
                cpu_resume_from_signal(env, NULL);
3059
            }
3060
        } else {
3061
            wp->flags &= ~BP_WATCHPOINT_HIT;
3062
        }
3063
    }
3064
}
3065

    
3066
/* Watchpoint access routines.  Watchpoints are inserted using TLB tricks,
3067
   so these check for a hit then pass through to the normal out-of-line
3068
   phys routines.  */
3069
static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
3070
{
3071
    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
3072
    return ldub_phys(addr);
3073
}
3074

    
3075
static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
3076
{
3077
    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
3078
    return lduw_phys(addr);
3079
}
3080

    
3081
static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
3082
{
3083
    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
3084
    return ldl_phys(addr);
3085
}
3086

    
3087
static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
3088
                             uint32_t val)
3089
{
3090
    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
3091
    stb_phys(addr, val);
3092
}
3093

    
3094
static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
3095
                             uint32_t val)
3096
{
3097
    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
3098
    stw_phys(addr, val);
3099
}
3100

    
3101
static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
3102
                             uint32_t val)
3103
{
3104
    check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
3105
    stl_phys(addr, val);
3106
}
3107

    
3108
static CPUReadMemoryFunc * const watch_mem_read[3] = {
3109
    watch_mem_readb,
3110
    watch_mem_readw,
3111
    watch_mem_readl,
3112
};
3113

    
3114
static CPUWriteMemoryFunc * const watch_mem_write[3] = {
3115
    watch_mem_writeb,
3116
    watch_mem_writew,
3117
    watch_mem_writel,
3118
};
3119

    
3120
static inline uint32_t subpage_readlen (subpage_t *mmio,
3121
                                        target_phys_addr_t addr,
3122
                                        unsigned int len)
3123
{
3124
    unsigned int idx = SUBPAGE_IDX(addr);
3125
#if defined(DEBUG_SUBPAGE)
3126
    printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
3127
           mmio, len, addr, idx);
3128
#endif
3129

    
3130
    addr += mmio->region_offset[idx];
3131
    idx = mmio->sub_io_index[idx];
3132
    return io_mem_read[idx][len](io_mem_opaque[idx], addr);
3133
}
3134

    
3135
static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
3136
                                     uint32_t value, unsigned int len)
3137
{
3138
    unsigned int idx = SUBPAGE_IDX(addr);
3139
#if defined(DEBUG_SUBPAGE)
3140
    printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n",
3141
           __func__, mmio, len, addr, idx, value);
3142
#endif
3143

    
3144
    addr += mmio->region_offset[idx];
3145
    idx = mmio->sub_io_index[idx];
3146
    io_mem_write[idx][len](io_mem_opaque[idx], addr, value);
3147
}
3148

    
3149
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
3150
{
3151
    return subpage_readlen(opaque, addr, 0);
3152
}
3153

    
3154
static void subpage_writeb (void *opaque, target_phys_addr_t addr,
3155
                            uint32_t value)
3156
{
3157
    subpage_writelen(opaque, addr, value, 0);
3158
}
3159

    
3160
static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
3161
{
3162
    return subpage_readlen(opaque, addr, 1);
3163
}
3164

    
3165
static void subpage_writew (void *opaque, target_phys_addr_t addr,
3166
                            uint32_t value)
3167
{
3168
    subpage_writelen(opaque, addr, value, 1);
3169
}
3170

    
3171
static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
3172
{
3173
    return subpage_readlen(opaque, addr, 2);
3174
}
3175

    
3176
static void subpage_writel (void *opaque, target_phys_addr_t addr,
3177
                            uint32_t value)
3178
{
3179
    subpage_writelen(opaque, addr, value, 2);
3180
}
3181

    
3182
static CPUReadMemoryFunc * const subpage_read[] = {
3183
    &subpage_readb,
3184
    &subpage_readw,
3185
    &subpage_readl,
3186
};
3187

    
3188
static CPUWriteMemoryFunc * const subpage_write[] = {
3189
    &subpage_writeb,
3190
    &subpage_writew,
3191
    &subpage_writel,
3192
};
3193

    
3194
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
3195
                             ram_addr_t memory, ram_addr_t region_offset)
3196
{
3197
    int idx, eidx;
3198

    
3199
    if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
3200
        return -1;
3201
    idx = SUBPAGE_IDX(start);
3202
    eidx = SUBPAGE_IDX(end);
3203
#if defined(DEBUG_SUBPAGE)
3204
    printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
3205
           mmio, start, end, idx, eidx, memory);
3206
#endif
3207
    memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3208
    for (; idx <= eidx; idx++) {
3209
        mmio->sub_io_index[idx] = memory;
3210
        mmio->region_offset[idx] = region_offset;
3211
    }
3212

    
3213
    return 0;
3214
}
3215

    
3216
static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
3217
                                ram_addr_t orig_memory,
3218
                                ram_addr_t region_offset)
3219
{
3220
    subpage_t *mmio;
3221
    int subpage_memory;
3222

    
3223
    mmio = qemu_mallocz(sizeof(subpage_t));
3224

    
3225
    mmio->base = base;
3226
    subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
3227
#if defined(DEBUG_SUBPAGE)
3228
    printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
3229
           mmio, base, TARGET_PAGE_SIZE, subpage_memory);
3230
#endif
3231
    *phys = subpage_memory | IO_MEM_SUBPAGE;
3232
    subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset);
3233

    
3234
    return mmio;
3235
}
3236

    
3237
static int get_free_io_mem_idx(void)
3238
{
3239
    int i;
3240

    
3241
    for (i = 0; i<IO_MEM_NB_ENTRIES; i++)
3242
        if (!io_mem_used[i]) {
3243
            io_mem_used[i] = 1;
3244
            return i;
3245
        }
3246
    fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES);
3247
    return -1;
3248
}
3249

    
3250
/* mem_read and mem_write are arrays of functions containing the
3251
   function to access byte (index 0), word (index 1) and dword (index
3252
   2). Functions can be omitted with a NULL function pointer.
3253
   If io_index is non zero, the corresponding io zone is
3254
   modified. If it is zero, a new io zone is allocated. The return
3255
   value can be used with cpu_register_physical_memory(). (-1) is
3256
   returned if error. */
3257
static int cpu_register_io_memory_fixed(int io_index,
3258
                                        CPUReadMemoryFunc * const *mem_read,
3259
                                        CPUWriteMemoryFunc * const *mem_write,
3260
                                        void *opaque)
3261
{
3262
    if (io_index <= 0) {
3263
        io_index = get_free_io_mem_idx();
3264
        if (io_index == -1)
3265
            return io_index;
3266
    } else {
3267
        io_index >>= IO_MEM_SHIFT;
3268
        if (io_index >= IO_MEM_NB_ENTRIES)
3269
            return -1;
3270
    }
3271

    
3272
    memcpy(io_mem_read[io_index], mem_read, 3 * sizeof(CPUReadMemoryFunc*));
3273
    memcpy(io_mem_write[io_index], mem_write, 3 * sizeof(CPUWriteMemoryFunc*));
3274
    io_mem_opaque[io_index] = opaque;
3275

    
3276
    return (io_index << IO_MEM_SHIFT);
3277
}
3278

    
3279
int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
3280
                           CPUWriteMemoryFunc * const *mem_write,
3281
                           void *opaque)
3282
{
3283
    return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
3284
}
3285

    
3286
void cpu_unregister_io_memory(int io_table_address)
3287
{
3288
    int i;
3289
    int io_index = io_table_address >> IO_MEM_SHIFT;
3290

    
3291
    for (i=0;i < 3; i++) {
3292
        io_mem_read[io_index][i] = unassigned_mem_read[i];
3293
        io_mem_write[io_index][i] = unassigned_mem_write[i];
3294
    }
3295
    io_mem_opaque[io_index] = NULL;
3296
    io_mem_used[io_index] = 0;
3297
}
3298

    
3299
static void io_mem_init(void)
3300
{
3301
    int i;
3302

    
3303
    cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL);
3304
    cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL);
3305
    cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL);
3306
    for (i=0; i<5; i++)
3307
        io_mem_used[i] = 1;
3308

    
3309
    io_mem_watch = cpu_register_io_memory(watch_mem_read,
3310
                                          watch_mem_write, NULL);
3311
}
3312

    
3313
#endif /* !defined(CONFIG_USER_ONLY) */
3314

    
3315
/* physical memory access (slow version, mainly for debug) */
3316
#if defined(CONFIG_USER_ONLY)
3317
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
3318
                        uint8_t *buf, int len, int is_write)
3319
{
3320
    int l, flags;
3321
    target_ulong page;
3322
    void * p;
3323

    
3324
    while (len > 0) {
3325
        page = addr & TARGET_PAGE_MASK;
3326
        l = (page + TARGET_PAGE_SIZE) - addr;
3327
        if (l > len)
3328
            l = len;
3329
        flags = page_get_flags(page);
3330
        if (!(flags & PAGE_VALID))
3331
            return -1;
3332
        if (is_write) {
3333
            if (!(flags & PAGE_WRITE))
3334
                return -1;
3335
            /* XXX: this code should not depend on lock_user */
3336
            if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3337
                return -1;
3338
            memcpy(p, buf, l);
3339
            unlock_user(p, addr, l);
3340
        } else {
3341
            if (!(flags & PAGE_READ))
3342
                return -1;
3343
            /* XXX: this code should not depend on lock_user */
3344
            if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3345
                return -1;
3346
            memcpy(buf, p, l);
3347
            unlock_user(p, addr, 0);
3348
        }
3349
        len -= l;
3350
        buf += l;
3351
        addr += l;
3352
    }
3353
    return 0;
3354
}
3355

    
3356
#else
3357
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
3358
                            int len, int is_write)
3359
{
3360
    int l, io_index;
3361
    uint8_t *ptr;
3362
    uint32_t val;
3363
    target_phys_addr_t page;
3364
    unsigned long pd;
3365
    PhysPageDesc *p;
3366

    
3367
    while (len > 0) {
3368
        page = addr & TARGET_PAGE_MASK;
3369
        l = (page + TARGET_PAGE_SIZE) - addr;
3370
        if (l > len)
3371
            l = len;
3372
        p = phys_page_find(page >> TARGET_PAGE_BITS);
3373
        if (!p) {
3374
            pd = IO_MEM_UNASSIGNED;
3375
        } else {
3376
            pd = p->phys_offset;
3377
        }
3378

    
3379
        if (is_write) {
3380
            if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3381
                target_phys_addr_t addr1 = addr;
3382
                io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3383
                if (p)
3384
                    addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3385
                /* XXX: could force cpu_single_env to NULL to avoid
3386
                   potential bugs */
3387
                if (l >= 4 && ((addr1 & 3) == 0)) {
3388
                    /* 32 bit write access */
3389
                    val = ldl_p(buf);
3390
                    io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val);
3391
                    l = 4;
3392
                } else if (l >= 2 && ((addr1 & 1) == 0)) {
3393
                    /* 16 bit write access */
3394
                    val = lduw_p(buf);
3395
                    io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val);
3396
                    l = 2;
3397
                } else {
3398
                    /* 8 bit write access */
3399
                    val = ldub_p(buf);
3400
                    io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val);
3401
                    l = 1;
3402
                }
3403
            } else {
3404
                unsigned long addr1;
3405
                addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3406
                /* RAM case */
3407
                ptr = qemu_get_ram_ptr(addr1);
3408
                memcpy(ptr, buf, l);
3409
                if (!cpu_physical_memory_is_dirty(addr1)) {
3410
                    /* invalidate code */
3411
                    tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3412
                    /* set dirty bit */
3413
                    cpu_physical_memory_set_dirty_flags(
3414
                        addr1, (0xff & ~CODE_DIRTY_FLAG));
3415
                }
3416
            }
3417
        } else {
3418
            if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3419
                !(pd & IO_MEM_ROMD)) {
3420
                target_phys_addr_t addr1 = addr;
3421
                /* I/O case */
3422
                io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3423
                if (p)
3424
                    addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3425
                if (l >= 4 && ((addr1 & 3) == 0)) {
3426
                    /* 32 bit read access */
3427
                    val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1);
3428
                    stl_p(buf, val);
3429
                    l = 4;
3430
                } else if (l >= 2 && ((addr1 & 1) == 0)) {
3431
                    /* 16 bit read access */
3432
                    val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1);
3433
                    stw_p(buf, val);
3434
                    l = 2;
3435
                } else {
3436
                    /* 8 bit read access */
3437
                    val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1);
3438
                    stb_p(buf, val);
3439
                    l = 1;
3440
                }
3441
            } else {
3442
                /* RAM case */
3443
                ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
3444
                    (addr & ~TARGET_PAGE_MASK);
3445
                memcpy(buf, ptr, l);
3446
            }
3447
        }
3448
        len -= l;
3449
        buf += l;
3450
        addr += l;
3451
    }
3452
}
3453

    
3454
/* used for ROM loading : can write in RAM and ROM */
3455
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
3456
                                   const uint8_t *buf, int len)
3457
{
3458
    int l;
3459
    uint8_t *ptr;
3460
    target_phys_addr_t page;
3461
    unsigned long pd;
3462
    PhysPageDesc *p;
3463

    
3464
    while (len > 0) {
3465
        page = addr & TARGET_PAGE_MASK;
3466
        l = (page + TARGET_PAGE_SIZE) - addr;
3467
        if (l > len)
3468
            l = len;
3469
        p = phys_page_find(page >> TARGET_PAGE_BITS);
3470
        if (!p) {
3471
            pd = IO_MEM_UNASSIGNED;
3472
        } else {
3473
            pd = p->phys_offset;
3474
        }
3475

    
3476
        if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
3477
            (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3478
            !(pd & IO_MEM_ROMD)) {
3479
            /* do nothing */
3480
        } else {
3481
            unsigned long addr1;
3482
            addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3483
            /* ROM/RAM case */
3484
            ptr = qemu_get_ram_ptr(addr1);
3485
            memcpy(ptr, buf, l);
3486
        }
3487
        len -= l;
3488
        buf += l;
3489
        addr += l;
3490
    }
3491
}
3492

    
3493
typedef struct {
3494
    void *buffer;
3495
    target_phys_addr_t addr;
3496
    target_phys_addr_t len;
3497
} BounceBuffer;
3498

    
3499
static BounceBuffer bounce;
3500

    
3501
typedef struct MapClient {
3502
    void *opaque;
3503
    void (*callback)(void *opaque);
3504
    QLIST_ENTRY(MapClient) link;
3505
} MapClient;
3506

    
3507
static QLIST_HEAD(map_client_list, MapClient) map_client_list
3508
    = QLIST_HEAD_INITIALIZER(map_client_list);
3509

    
3510
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
3511
{
3512
    MapClient *client = qemu_malloc(sizeof(*client));
3513

    
3514
    client->opaque = opaque;
3515
    client->callback = callback;
3516
    QLIST_INSERT_HEAD(&map_client_list, client, link);
3517
    return client;
3518
}
3519

    
3520
void cpu_unregister_map_client(void *_client)
3521
{
3522
    MapClient *client = (MapClient *)_client;
3523

    
3524
    QLIST_REMOVE(client, link);
3525
    qemu_free(client);
3526
}
3527

    
3528
static void cpu_notify_map_clients(void)
3529
{
3530
    MapClient *client;
3531

    
3532
    while (!QLIST_EMPTY(&map_client_list)) {
3533
        client = QLIST_FIRST(&map_client_list);
3534
        client->callback(client->opaque);
3535
        cpu_unregister_map_client(client);
3536
    }
3537
}
3538

    
3539
/* Map a physical memory region into a host virtual address.
3540
 * May map a subset of the requested range, given by and returned in *plen.
3541
 * May return NULL if resources needed to perform the mapping are exhausted.
3542
 * Use only for reads OR writes - not for read-modify-write operations.
3543
 * Use cpu_register_map_client() to know when retrying the map operation is
3544
 * likely to succeed.
3545
 */
3546
void *cpu_physical_memory_map(target_phys_addr_t addr,
3547
                              target_phys_addr_t *plen,
3548
                              int is_write)
3549
{
3550
    target_phys_addr_t len = *plen;
3551
    target_phys_addr_t done = 0;
3552
    int l;
3553
    uint8_t *ret = NULL;
3554
    uint8_t *ptr;
3555
    target_phys_addr_t page;
3556
    unsigned long pd;
3557
    PhysPageDesc *p;
3558
    unsigned long addr1;
3559

    
3560
    while (len > 0) {
3561
        page = addr & TARGET_PAGE_MASK;
3562
        l = (page + TARGET_PAGE_SIZE) - addr;
3563
        if (l > len)
3564
            l = len;
3565
        p = phys_page_find(page >> TARGET_PAGE_BITS);
3566
        if (!p) {
3567
            pd = IO_MEM_UNASSIGNED;
3568
        } else {
3569
            pd = p->phys_offset;
3570
        }
3571

    
3572
        if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3573
            if (done || bounce.buffer) {
3574
                break;
3575
            }
3576
            bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
3577
            bounce.addr = addr;
3578
            bounce.len = l;
3579
            if (!is_write) {
3580
                cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
3581
            }
3582
            ptr = bounce.buffer;
3583
        } else {
3584
            addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3585
            ptr = qemu_get_ram_ptr(addr1);
3586
        }
3587
        if (!done) {
3588
            ret = ptr;
3589
        } else if (ret + done != ptr) {
3590
            break;
3591
        }
3592

    
3593
        len -= l;
3594
        addr += l;
3595
        done += l;
3596
    }
3597
    *plen = done;
3598
    return ret;
3599
}
3600

    
3601
/* Unmaps a memory region previously mapped by cpu_physical_memory_map().
3602
 * Will also mark the memory as dirty if is_write == 1.  access_len gives
3603
 * the amount of memory that was actually read or written by the caller.
3604
 */
3605
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
3606
                               int is_write, target_phys_addr_t access_len)
3607
{
3608
    if (buffer != bounce.buffer) {
3609
        if (is_write) {
3610
            ram_addr_t addr1 = qemu_ram_addr_from_host(buffer);
3611
            while (access_len) {
3612
                unsigned l;
3613
                l = TARGET_PAGE_SIZE;
3614
                if (l > access_len)
3615
                    l = access_len;
3616
                if (!cpu_physical_memory_is_dirty(addr1)) {
3617
                    /* invalidate code */
3618
                    tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3619
                    /* set dirty bit */
3620
                    cpu_physical_memory_set_dirty_flags(
3621
                        addr1, (0xff & ~CODE_DIRTY_FLAG));
3622
                }
3623
                addr1 += l;
3624
                access_len -= l;
3625
            }
3626
        }
3627
        return;
3628
    }
3629
    if (is_write) {
3630
        cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
3631
    }
3632
    qemu_vfree(bounce.buffer);
3633
    bounce.buffer = NULL;
3634
    cpu_notify_map_clients();
3635
}
3636

    
3637
/* warning: addr must be aligned */
3638
uint32_t ldl_phys(target_phys_addr_t addr)
3639
{
3640
    int io_index;
3641
    uint8_t *ptr;
3642
    uint32_t val;
3643
    unsigned long pd;
3644
    PhysPageDesc *p;
3645

    
3646
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
3647
    if (!p) {
3648
        pd = IO_MEM_UNASSIGNED;
3649
    } else {
3650
        pd = p->phys_offset;
3651
    }
3652

    
3653
    if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3654
        !(pd & IO_MEM_ROMD)) {
3655
        /* I/O case */
3656
        io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3657
        if (p)
3658
            addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3659
        val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3660
    } else {
3661
        /* RAM case */
3662
        ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
3663
            (addr & ~TARGET_PAGE_MASK);
3664
        val = ldl_p(ptr);
3665
    }
3666
    return val;
3667
}
3668

    
3669
/* warning: addr must be aligned */
3670
uint64_t ldq_phys(target_phys_addr_t addr)
3671
{
3672
    int io_index;
3673
    uint8_t *ptr;
3674
    uint64_t val;
3675
    unsigned long pd;
3676
    PhysPageDesc *p;
3677

    
3678
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
3679
    if (!p) {
3680
        pd = IO_MEM_UNASSIGNED;
3681
    } else {
3682
        pd = p->phys_offset;
3683
    }
3684

    
3685
    if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3686
        !(pd & IO_MEM_ROMD)) {
3687
        /* I/O case */
3688
        io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3689
        if (p)
3690
            addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3691
#ifdef TARGET_WORDS_BIGENDIAN
3692
        val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3693
        val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3694
#else
3695
        val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3696
        val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3697
#endif
3698
    } else {
3699
        /* RAM case */
3700
        ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
3701
            (addr & ~TARGET_PAGE_MASK);
3702
        val = ldq_p(ptr);
3703
    }
3704
    return val;
3705
}
3706

    
3707
/* XXX: optimize */
3708
uint32_t ldub_phys(target_phys_addr_t addr)
3709
{
3710
    uint8_t val;
3711
    cpu_physical_memory_read(addr, &val, 1);
3712
    return val;
3713
}
3714

    
3715
/* XXX: optimize */
3716
uint32_t lduw_phys(target_phys_addr_t addr)
3717
{
3718
    uint16_t val;
3719
    cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3720
    return tswap16(val);
3721
}
3722

    
3723
/* warning: addr must be aligned. The ram page is not masked as dirty
3724
   and the code inside is not invalidated. It is useful if the dirty
3725
   bits are used to track modified PTEs */
3726
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3727
{
3728
    int io_index;
3729
    uint8_t *ptr;
3730
    unsigned long pd;
3731
    PhysPageDesc *p;
3732

    
3733
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
3734
    if (!p) {
3735
        pd = IO_MEM_UNASSIGNED;
3736
    } else {
3737
        pd = p->phys_offset;
3738
    }
3739

    
3740
    if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3741
        io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3742
        if (p)
3743
            addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3744
        io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3745
    } else {
3746
        unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3747
        ptr = qemu_get_ram_ptr(addr1);
3748
        stl_p(ptr, val);
3749

    
3750
        if (unlikely(in_migration)) {
3751
            if (!cpu_physical_memory_is_dirty(addr1)) {
3752
                /* invalidate code */
3753
                tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3754
                /* set dirty bit */
3755
                cpu_physical_memory_set_dirty_flags(
3756
                    addr1, (0xff & ~CODE_DIRTY_FLAG));
3757
            }
3758
        }
3759
    }
3760
}
3761

    
3762
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3763
{
3764
    int io_index;
3765
    uint8_t *ptr;
3766
    unsigned long pd;
3767
    PhysPageDesc *p;
3768

    
3769
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
3770
    if (!p) {
3771
        pd = IO_MEM_UNASSIGNED;
3772
    } else {
3773
        pd = p->phys_offset;
3774
    }
3775

    
3776
    if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3777
        io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3778
        if (p)
3779
            addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3780
#ifdef TARGET_WORDS_BIGENDIAN
3781
        io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3782
        io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3783
#else
3784
        io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3785
        io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3786
#endif
3787
    } else {
3788
        ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
3789
            (addr & ~TARGET_PAGE_MASK);
3790
        stq_p(ptr, val);
3791
    }
3792
}
3793

    
3794
/* warning: addr must be aligned */
3795
void stl_phys(target_phys_addr_t addr, uint32_t val)
3796
{
3797
    int io_index;
3798
    uint8_t *ptr;
3799
    unsigned long pd;
3800
    PhysPageDesc *p;
3801

    
3802
    p = phys_page_find(addr >> TARGET_PAGE_BITS);
3803
    if (!p) {
3804
        pd = IO_MEM_UNASSIGNED;
3805
    } else {
3806
        pd = p->phys_offset;
3807
    }
3808

    
3809
    if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3810
        io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3811
        if (p)
3812
            addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3813
        io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3814
    } else {
3815
        unsigned long addr1;
3816
        addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3817
        /* RAM case */
3818
        ptr = qemu_get_ram_ptr(addr1);
3819
        stl_p(ptr, val);
3820
        if (!cpu_physical_memory_is_dirty(addr1)) {
3821
            /* invalidate code */
3822
            tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3823
            /* set dirty bit */
3824
            cpu_physical_memory_set_dirty_flags(addr1,
3825
                (0xff & ~CODE_DIRTY_FLAG));
3826
        }
3827
    }
3828
}
3829

    
3830
/* XXX: optimize */
3831
void stb_phys(target_phys_addr_t addr, uint32_t val)
3832
{
3833
    uint8_t v = val;
3834
    cpu_physical_memory_write(addr, &v, 1);
3835
}
3836

    
3837
/* XXX: optimize */
3838
void stw_phys(target_phys_addr_t addr, uint32_t val)
3839
{
3840
    uint16_t v = tswap16(val);
3841
    cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3842
}
3843

    
3844
/* XXX: optimize */
3845
void stq_phys(target_phys_addr_t addr, uint64_t val)
3846
{
3847
    val = tswap64(val);
3848
    cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3849
}
3850

    
3851
/* virtual memory access for debug (includes writing to ROM) */
3852
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
3853
                        uint8_t *buf, int len, int is_write)
3854
{
3855
    int l;
3856
    target_phys_addr_t phys_addr;
3857
    target_ulong page;
3858

    
3859
    while (len > 0) {
3860
        page = addr & TARGET_PAGE_MASK;
3861
        phys_addr = cpu_get_phys_page_debug(env, page);
3862
        /* if no physical page mapped, return an error */
3863
        if (phys_addr == -1)
3864
            return -1;
3865
        l = (page + TARGET_PAGE_SIZE) - addr;
3866
        if (l > len)
3867
            l = len;
3868
        phys_addr += (addr & ~TARGET_PAGE_MASK);
3869
        if (is_write)
3870
            cpu_physical_memory_write_rom(phys_addr, buf, l);
3871
        else
3872
            cpu_physical_memory_rw(phys_addr, buf, l, is_write);
3873
        len -= l;
3874
        buf += l;
3875
        addr += l;
3876
    }
3877
    return 0;
3878
}
3879
#endif
3880

    
3881
/* in deterministic execution mode, instructions doing device I/Os
3882
   must be at the end of the TB */
3883
void cpu_io_recompile(CPUState *env, void *retaddr)
3884
{
3885
    TranslationBlock *tb;
3886
    uint32_t n, cflags;
3887
    target_ulong pc, cs_base;
3888
    uint64_t flags;
3889

    
3890
    tb = tb_find_pc((unsigned long)retaddr);
3891
    if (!tb) {
3892
        cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", 
3893
                  retaddr);
3894
    }
3895
    n = env->icount_decr.u16.low + tb->icount;
3896
    cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3897
    /* Calculate how many instructions had been executed before the fault
3898
       occurred.  */
3899
    n = n - env->icount_decr.u16.low;
3900
    /* Generate a new TB ending on the I/O insn.  */
3901
    n++;
3902
    /* On MIPS and SH, delay slot instructions can only be restarted if
3903
       they were already the first instruction in the TB.  If this is not
3904
       the first instruction in a TB then re-execute the preceding
3905
       branch.  */
3906
#if defined(TARGET_MIPS)
3907
    if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3908
        env->active_tc.PC -= 4;
3909
        env->icount_decr.u16.low++;
3910
        env->hflags &= ~MIPS_HFLAG_BMASK;
3911
    }
3912
#elif defined(TARGET_SH4)
3913
    if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3914
            && n > 1) {
3915
        env->pc -= 2;
3916
        env->icount_decr.u16.low++;
3917
        env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3918
    }
3919
#endif
3920
    /* This should never happen.  */
3921
    if (n > CF_COUNT_MASK)
3922
        cpu_abort(env, "TB too big during recompile");
3923

    
3924
    cflags = n | CF_LAST_IO;
3925
    pc = tb->pc;
3926
    cs_base = tb->cs_base;
3927
    flags = tb->flags;
3928
    tb_phys_invalidate(tb, -1);
3929
    /* FIXME: In theory this could raise an exception.  In practice
3930
       we have already translated the block once so it's probably ok.  */
3931
    tb_gen_code(env, pc, cs_base, flags, cflags);
3932
    /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
3933
       the first in the TB) then we end up generating a whole new TB and
3934
       repeating the fault, which is horribly inefficient.
3935
       Better would be to execute just this insn uncached, or generate a
3936
       second new TB.  */
3937
    cpu_resume_from_signal(env, NULL);
3938
}
3939

    
3940
#if !defined(CONFIG_USER_ONLY)
3941

    
3942
void dump_exec_info(FILE *f,
3943
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3944
{
3945
    int i, target_code_size, max_target_code_size;
3946
    int direct_jmp_count, direct_jmp2_count, cross_page;
3947
    TranslationBlock *tb;
3948

    
3949
    target_code_size = 0;
3950
    max_target_code_size = 0;
3951
    cross_page = 0;
3952
    direct_jmp_count = 0;
3953
    direct_jmp2_count = 0;
3954
    for(i = 0; i < nb_tbs; i++) {
3955
        tb = &tbs[i];
3956
        target_code_size += tb->size;
3957
        if (tb->size > max_target_code_size)
3958
            max_target_code_size = tb->size;
3959
        if (tb->page_addr[1] != -1)
3960
            cross_page++;
3961
        if (tb->tb_next_offset[0] != 0xffff) {
3962
            direct_jmp_count++;
3963
            if (tb->tb_next_offset[1] != 0xffff) {
3964
                direct_jmp2_count++;
3965
            }
3966
        }
3967
    }
3968
    /* XXX: avoid using doubles ? */
3969
    cpu_fprintf(f, "Translation buffer state:\n");
3970
    cpu_fprintf(f, "gen code size       %ld/%ld\n",
3971
                code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3972
    cpu_fprintf(f, "TB count            %d/%d\n", 
3973
                nb_tbs, code_gen_max_blocks);
3974
    cpu_fprintf(f, "TB avg target size  %d max=%d bytes\n",
3975
                nb_tbs ? target_code_size / nb_tbs : 0,
3976
                max_target_code_size);
3977
    cpu_fprintf(f, "TB avg host size    %d bytes (expansion ratio: %0.1f)\n",
3978
                nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3979
                target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
3980
    cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3981
            cross_page,
3982
            nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3983
    cpu_fprintf(f, "direct jump count   %d (%d%%) (2 jumps=%d %d%%)\n",
3984
                direct_jmp_count,
3985
                nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3986
                direct_jmp2_count,
3987
                nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
3988
    cpu_fprintf(f, "\nStatistics:\n");
3989
    cpu_fprintf(f, "TB flush count      %d\n", tb_flush_count);
3990
    cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3991
    cpu_fprintf(f, "TLB flush count     %d\n", tlb_flush_count);
3992
    tcg_dump_info(f, cpu_fprintf);
3993
}
3994

    
3995
#define MMUSUFFIX _cmmu
3996
#define GETPC() NULL
3997
#define env cpu_single_env
3998
#define SOFTMMU_CODE_ACCESS
3999

    
4000
#define SHIFT 0
4001
#include "softmmu_template.h"
4002

    
4003
#define SHIFT 1
4004
#include "softmmu_template.h"
4005

    
4006
#define SHIFT 2
4007
#include "softmmu_template.h"
4008

    
4009
#define SHIFT 3
4010
#include "softmmu_template.h"
4011

    
4012
#undef env
4013

    
4014
#endif