Revision 2ea815ca target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 311 | 311 |
tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2); |
| 312 | 312 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
| 313 | 313 |
gen_set_label(l2); |
| 314 |
tcg_temp_free(r_temp); |
|
| 314 | 315 |
} |
| 315 | 316 |
|
| 316 | 317 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 344 | 345 |
tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
| 345 | 346 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
| 346 | 347 |
gen_set_label(l1); |
| 348 |
tcg_temp_free(r_temp); |
|
| 347 | 349 |
} |
| 348 | 350 |
|
| 349 | 351 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 374 | 376 |
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
| 375 | 377 |
tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
| 376 | 378 |
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
| 379 |
tcg_temp_free(r_temp); |
|
| 377 | 380 |
tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
| 378 | 381 |
} |
| 379 | 382 |
|
| ... | ... | |
| 390 | 393 |
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
| 391 | 394 |
tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
| 392 | 395 |
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
| 396 |
tcg_temp_free(r_temp); |
|
| 393 | 397 |
tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
| 394 | 398 |
} |
| 395 | 399 |
#endif |
| 396 | 400 |
|
| 397 | 401 |
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
| 398 | 402 |
{
|
| 399 |
TCGv r_temp; |
|
| 403 |
TCGv r_temp, r_const;
|
|
| 400 | 404 |
int l1; |
| 401 | 405 |
|
| 402 | 406 |
l1 = gen_new_label(); |
| ... | ... | |
| 408 | 412 |
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| 409 | 413 |
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
| 410 | 414 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
| 411 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
|
| 415 |
r_const = tcg_const_i32(TT_TOVF); |
|
| 416 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 417 |
tcg_temp_free(r_const); |
|
| 412 | 418 |
gen_set_label(l1); |
| 419 |
tcg_temp_free(r_temp); |
|
| 413 | 420 |
} |
| 414 | 421 |
|
| 415 | 422 |
static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
| ... | ... | |
| 427 | 434 |
static inline void gen_tag_tv(TCGv src1, TCGv src2) |
| 428 | 435 |
{
|
| 429 | 436 |
int l1; |
| 437 |
TCGv r_const; |
|
| 430 | 438 |
|
| 431 | 439 |
l1 = gen_new_label(); |
| 432 | 440 |
tcg_gen_or_tl(cpu_tmp0, src1, src2); |
| 433 | 441 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); |
| 434 | 442 |
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
| 435 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
|
| 443 |
r_const = tcg_const_i32(TT_TOVF); |
|
| 444 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 445 |
tcg_temp_free(r_const); |
|
| 436 | 446 |
gen_set_label(l1); |
| 437 | 447 |
} |
| 438 | 448 |
|
| ... | ... | |
| 533 | 543 |
tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
| 534 | 544 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
| 535 | 545 |
gen_set_label(l1); |
| 546 |
tcg_temp_free(r_temp1); |
|
| 547 |
tcg_temp_free(r_temp2); |
|
| 536 | 548 |
} |
| 537 | 549 |
|
| 538 | 550 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 563 | 575 |
tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
| 564 | 576 |
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
| 565 | 577 |
tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
| 578 |
tcg_temp_free(r_temp); |
|
| 566 | 579 |
} |
| 567 | 580 |
|
| 568 | 581 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 578 | 591 |
tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
| 579 | 592 |
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
| 580 | 593 |
tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
| 594 |
tcg_temp_free(r_temp); |
|
| 581 | 595 |
} |
| 582 | 596 |
#endif |
| 583 | 597 |
|
| 584 | 598 |
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
| 585 | 599 |
{
|
| 586 |
TCGv r_temp; |
|
| 600 |
TCGv r_temp, r_const;
|
|
| 587 | 601 |
int l1; |
| 588 | 602 |
|
| 589 | 603 |
l1 = gen_new_label(); |
| ... | ... | |
| 594 | 608 |
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
| 595 | 609 |
tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
| 596 | 610 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); |
| 597 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
|
| 611 |
r_const = tcg_const_i32(TT_TOVF); |
|
| 612 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 613 |
tcg_temp_free(r_const); |
|
| 598 | 614 |
gen_set_label(l1); |
| 615 |
tcg_temp_free(r_temp); |
|
| 599 | 616 |
} |
| 600 | 617 |
|
| 601 | 618 |
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 708 | 725 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
| 709 | 726 |
tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1); |
| 710 | 727 |
tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2); |
| 728 |
tcg_temp_free(r_temp2); |
|
| 711 | 729 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
| 712 | 730 |
|
| 713 | 731 |
// b1 = N ^ V; |
| 714 | 732 |
gen_mov_reg_N(cpu_tmp0, cpu_psr); |
| 715 | 733 |
gen_mov_reg_V(r_temp, cpu_psr); |
| 716 | 734 |
tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
| 735 |
tcg_temp_free(r_temp); |
|
| 717 | 736 |
|
| 718 | 737 |
// T0 = (b1 << 31) | (T0 >> 1); |
| 719 | 738 |
// src1 = T0; |
| ... | ... | |
| 745 | 764 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 746 | 765 |
tcg_gen_trunc_i64_i32(r_temp, r_temp); |
| 747 | 766 |
tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
| 767 |
tcg_temp_free(r_temp); |
|
| 748 | 768 |
#ifdef TARGET_SPARC64 |
| 749 | 769 |
tcg_gen_mov_i64(dst, r_temp2); |
| 750 | 770 |
#else |
| 751 | 771 |
tcg_gen_trunc_i64_tl(dst, r_temp2); |
| 752 | 772 |
#endif |
| 773 |
tcg_temp_free(r_temp2); |
|
| 753 | 774 |
} |
| 754 | 775 |
|
| 755 | 776 |
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
| ... | ... | |
| 766 | 787 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 767 | 788 |
tcg_gen_trunc_i64_i32(r_temp, r_temp); |
| 768 | 789 |
tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
| 790 |
tcg_temp_free(r_temp); |
|
| 769 | 791 |
#ifdef TARGET_SPARC64 |
| 770 | 792 |
tcg_gen_mov_i64(dst, r_temp2); |
| 771 | 793 |
#else |
| 772 | 794 |
tcg_gen_trunc_i64_tl(dst, r_temp2); |
| 773 | 795 |
#endif |
| 796 |
tcg_temp_free(r_temp2); |
|
| 774 | 797 |
} |
| 775 | 798 |
|
| 776 | 799 |
#ifdef TARGET_SPARC64 |
| 777 | 800 |
static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
| 778 | 801 |
{
|
| 802 |
TCGv r_const; |
|
| 779 | 803 |
int l1; |
| 780 | 804 |
|
| 781 | 805 |
l1 = gen_new_label(); |
| 782 | 806 |
tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1); |
| 783 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO)); |
|
| 807 |
r_const = tcg_const_i32(TT_DIV_ZERO); |
|
| 808 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 809 |
tcg_temp_free(r_const); |
|
| 784 | 810 |
gen_set_label(l1); |
| 785 | 811 |
} |
| 786 | 812 |
|
| ... | ... | |
| 1563 | 1589 |
|
| 1564 | 1590 |
static inline void gen_op_fpexception_im(int fsr_flags) |
| 1565 | 1591 |
{
|
| 1592 |
TCGv r_const; |
|
| 1593 |
|
|
| 1566 | 1594 |
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
| 1567 | 1595 |
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
| 1568 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP)); |
|
| 1596 |
r_const = tcg_const_i32(TT_FP_EXCP); |
|
| 1597 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 1598 |
tcg_temp_free(r_const); |
|
| 1569 | 1599 |
} |
| 1570 | 1600 |
|
| 1571 | 1601 |
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
| 1572 | 1602 |
{
|
| 1573 | 1603 |
#if !defined(CONFIG_USER_ONLY) |
| 1574 | 1604 |
if (!dc->fpu_enabled) {
|
| 1605 |
TCGv r_const; |
|
| 1606 |
|
|
| 1575 | 1607 |
save_state(dc, r_cond); |
| 1576 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN)); |
|
| 1608 |
r_const = tcg_const_i32(TT_NFPU_INSN); |
|
| 1609 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 1610 |
tcg_temp_free(r_const); |
|
| 1577 | 1611 |
dc->is_br = 1; |
| 1578 | 1612 |
return 1; |
| 1579 | 1613 |
} |
| ... | ... | |
| 1613 | 1647 |
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
| 1614 | 1648 |
int sign) |
| 1615 | 1649 |
{
|
| 1616 |
TCGv r_asi; |
|
| 1650 |
TCGv r_asi, r_size, r_sign;
|
|
| 1617 | 1651 |
|
| 1618 | 1652 |
r_asi = gen_get_asi(insn, addr); |
| 1619 |
tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, |
|
| 1620 |
tcg_const_i32(size), tcg_const_i32(sign)); |
|
| 1653 |
r_size = tcg_const_i32(size); |
|
| 1654 |
r_sign = tcg_const_i32(sign); |
|
| 1655 |
tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign); |
|
| 1656 |
tcg_temp_free(r_sign); |
|
| 1657 |
tcg_temp_free(r_size); |
|
| 1658 |
tcg_temp_free(r_asi); |
|
| 1621 | 1659 |
} |
| 1622 | 1660 |
|
| 1623 | 1661 |
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
| 1624 | 1662 |
{
|
| 1625 |
TCGv r_asi; |
|
| 1663 |
TCGv r_asi, r_size;
|
|
| 1626 | 1664 |
|
| 1627 | 1665 |
r_asi = gen_get_asi(insn, addr); |
| 1628 |
tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size)); |
|
| 1666 |
r_size = tcg_const_i32(size); |
|
| 1667 |
tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size); |
|
| 1668 |
tcg_temp_free(r_size); |
|
| 1669 |
tcg_temp_free(r_asi); |
|
| 1629 | 1670 |
} |
| 1630 | 1671 |
|
| 1631 | 1672 |
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
| 1632 | 1673 |
{
|
| 1633 |
TCGv r_asi; |
|
| 1674 |
TCGv r_asi, r_size, r_rd;
|
|
| 1634 | 1675 |
|
| 1635 | 1676 |
r_asi = gen_get_asi(insn, addr); |
| 1636 |
tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size), |
|
| 1637 |
tcg_const_i32(rd)); |
|
| 1677 |
r_size = tcg_const_i32(size); |
|
| 1678 |
r_rd = tcg_const_i32(rd); |
|
| 1679 |
tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd); |
|
| 1680 |
tcg_temp_free(r_rd); |
|
| 1681 |
tcg_temp_free(r_size); |
|
| 1682 |
tcg_temp_free(r_asi); |
|
| 1638 | 1683 |
} |
| 1639 | 1684 |
|
| 1640 | 1685 |
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
| 1641 | 1686 |
{
|
| 1642 |
TCGv r_asi; |
|
| 1687 |
TCGv r_asi, r_size, r_rd;
|
|
| 1643 | 1688 |
|
| 1644 | 1689 |
r_asi = gen_get_asi(insn, addr); |
| 1645 |
tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size), |
|
| 1646 |
tcg_const_i32(rd)); |
|
| 1690 |
r_size = tcg_const_i32(size); |
|
| 1691 |
r_rd = tcg_const_i32(rd); |
|
| 1692 |
tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd); |
|
| 1693 |
tcg_temp_free(r_rd); |
|
| 1694 |
tcg_temp_free(r_size); |
|
| 1695 |
tcg_temp_free(r_asi); |
|
| 1647 | 1696 |
} |
| 1648 | 1697 |
|
| 1649 | 1698 |
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
| 1650 | 1699 |
{
|
| 1651 |
TCGv r_asi; |
|
| 1700 |
TCGv r_asi, r_size, r_sign;
|
|
| 1652 | 1701 |
|
| 1653 | 1702 |
r_asi = gen_get_asi(insn, addr); |
| 1654 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, |
|
| 1655 |
tcg_const_i32(4), tcg_const_i32(0)); |
|
| 1656 |
tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, |
|
| 1657 |
tcg_const_i32(4)); |
|
| 1703 |
r_size = tcg_const_i32(4); |
|
| 1704 |
r_sign = tcg_const_i32(0); |
|
| 1705 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
|
| 1706 |
tcg_temp_free(r_sign); |
|
| 1707 |
tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); |
|
| 1708 |
tcg_temp_free(r_size); |
|
| 1709 |
tcg_temp_free(r_asi); |
|
| 1658 | 1710 |
tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
| 1659 | 1711 |
} |
| 1660 | 1712 |
|
| 1661 | 1713 |
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn) |
| 1662 | 1714 |
{
|
| 1663 |
TCGv r_asi; |
|
| 1715 |
TCGv r_asi, r_size, r_sign;
|
|
| 1664 | 1716 |
|
| 1665 | 1717 |
r_asi = gen_get_asi(insn, addr); |
| 1666 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, |
|
| 1667 |
tcg_const_i32(8), tcg_const_i32(0)); |
|
| 1718 |
r_size = tcg_const_i32(8); |
|
| 1719 |
r_sign = tcg_const_i32(0); |
|
| 1720 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
|
| 1721 |
tcg_temp_free(r_sign); |
|
| 1722 |
tcg_temp_free(r_size); |
|
| 1723 |
tcg_temp_free(r_asi); |
|
| 1668 | 1724 |
tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL); |
| 1669 | 1725 |
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
| 1670 | 1726 |
tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL); |
| ... | ... | |
| 1672 | 1728 |
|
| 1673 | 1729 |
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
| 1674 | 1730 |
{
|
| 1675 |
TCGv r_temp, r_asi; |
|
| 1731 |
TCGv r_temp, r_asi, r_size;
|
|
| 1676 | 1732 |
|
| 1677 | 1733 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
| 1678 | 1734 |
gen_movl_reg_TN(rd + 1, r_temp); |
| 1679 | 1735 |
tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, |
| 1680 | 1736 |
r_temp); |
| 1737 |
tcg_temp_free(r_temp); |
|
| 1681 | 1738 |
r_asi = gen_get_asi(insn, addr); |
| 1682 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, |
|
| 1683 |
tcg_const_i32(8)); |
|
| 1739 |
r_size = tcg_const_i32(8); |
|
| 1740 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
|
| 1741 |
tcg_temp_free(r_size); |
|
| 1742 |
tcg_temp_free(r_asi); |
|
| 1684 | 1743 |
} |
| 1685 | 1744 |
|
| 1686 | 1745 |
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
| ... | ... | |
| 1692 | 1751 |
gen_movl_reg_TN(rd, r_val1); |
| 1693 | 1752 |
r_asi = gen_get_asi(insn, addr); |
| 1694 | 1753 |
tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); |
| 1754 |
tcg_temp_free(r_asi); |
|
| 1755 |
tcg_temp_free(r_val1); |
|
| 1695 | 1756 |
} |
| 1696 | 1757 |
|
| 1697 | 1758 |
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
| ... | ... | |
| 1702 | 1763 |
gen_movl_reg_TN(rd, cpu_tmp64); |
| 1703 | 1764 |
r_asi = gen_get_asi(insn, addr); |
| 1704 | 1765 |
tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi); |
| 1766 |
tcg_temp_free(r_asi); |
|
| 1705 | 1767 |
} |
| 1706 | 1768 |
|
| 1707 | 1769 |
#elif !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 1709 | 1771 |
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
| 1710 | 1772 |
int sign) |
| 1711 | 1773 |
{
|
| 1712 |
int asi;
|
|
| 1774 |
TCGv r_asi, r_size, r_sign;
|
|
| 1713 | 1775 |
|
| 1714 |
asi = GET_FIELD(insn, 19, 26); |
|
| 1715 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi), |
|
| 1716 |
tcg_const_i32(size), tcg_const_i32(sign)); |
|
| 1776 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
|
| 1777 |
r_size = tcg_const_i32(size); |
|
| 1778 |
r_sign = tcg_const_i32(sign); |
|
| 1779 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
|
| 1780 |
tcg_temp_free(r_sign); |
|
| 1781 |
tcg_temp_free(r_size); |
|
| 1782 |
tcg_temp_free(r_asi); |
|
| 1717 | 1783 |
tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
| 1718 | 1784 |
} |
| 1719 | 1785 |
|
| 1720 | 1786 |
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
| 1721 | 1787 |
{
|
| 1722 |
int asi;
|
|
| 1788 |
TCGv r_asi, r_size;
|
|
| 1723 | 1789 |
|
| 1724 | 1790 |
tcg_gen_extu_tl_i64(cpu_tmp64, src); |
| 1725 |
asi = GET_FIELD(insn, 19, 26); |
|
| 1726 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi), |
|
| 1727 |
tcg_const_i32(size)); |
|
| 1791 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
|
| 1792 |
r_size = tcg_const_i32(size); |
|
| 1793 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
|
| 1794 |
tcg_temp_free(r_size); |
|
| 1795 |
tcg_temp_free(r_asi); |
|
| 1728 | 1796 |
} |
| 1729 | 1797 |
|
| 1730 | 1798 |
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
| 1731 | 1799 |
{
|
| 1732 |
int asi;
|
|
| 1800 |
TCGv r_asi, r_size, r_sign;
|
|
| 1733 | 1801 |
|
| 1734 |
asi = GET_FIELD(insn, 19, 26); |
|
| 1735 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi), |
|
| 1736 |
tcg_const_i32(4), tcg_const_i32(0)); |
|
| 1737 |
tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi), |
|
| 1738 |
tcg_const_i32(4)); |
|
| 1802 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
|
| 1803 |
r_size = tcg_const_i32(4); |
|
| 1804 |
r_sign = tcg_const_i32(0); |
|
| 1805 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
|
| 1806 |
tcg_temp_free(r_sign); |
|
| 1807 |
tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); |
|
| 1808 |
tcg_temp_free(r_size); |
|
| 1809 |
tcg_temp_free(r_asi); |
|
| 1739 | 1810 |
tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
| 1740 | 1811 |
} |
| 1741 | 1812 |
|
| 1742 | 1813 |
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn) |
| 1743 | 1814 |
{
|
| 1744 |
int asi;
|
|
| 1815 |
TCGv r_asi, r_size, r_sign;
|
|
| 1745 | 1816 |
|
| 1746 |
asi = GET_FIELD(insn, 19, 26); |
|
| 1747 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi), |
|
| 1748 |
tcg_const_i32(8), tcg_const_i32(0)); |
|
| 1817 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
|
| 1818 |
r_size = tcg_const_i32(8); |
|
| 1819 |
r_sign = tcg_const_i32(0); |
|
| 1820 |
tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); |
|
| 1821 |
tcg_temp_free(r_sign); |
|
| 1822 |
tcg_temp_free(r_size); |
|
| 1823 |
tcg_temp_free(r_asi); |
|
| 1749 | 1824 |
tcg_gen_trunc_i64_tl(lo, cpu_tmp64); |
| 1750 | 1825 |
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); |
| 1751 | 1826 |
tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
| ... | ... | |
| 1753 | 1828 |
|
| 1754 | 1829 |
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
| 1755 | 1830 |
{
|
| 1756 |
int asi; |
|
| 1757 |
TCGv r_temp; |
|
| 1831 |
TCGv r_temp, r_asi, r_size; |
|
| 1758 | 1832 |
|
| 1759 | 1833 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
| 1760 | 1834 |
gen_movl_reg_TN(rd + 1, r_temp); |
| 1761 | 1835 |
tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp); |
| 1762 |
asi = GET_FIELD(insn, 19, 26); |
|
| 1763 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi), |
|
| 1764 |
tcg_const_i32(8)); |
|
| 1836 |
tcg_temp_free(r_temp); |
|
| 1837 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
|
| 1838 |
r_size = tcg_const_i32(8); |
|
| 1839 |
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); |
|
| 1840 |
tcg_temp_free(r_size); |
|
| 1841 |
tcg_temp_free(r_asi); |
|
| 1765 | 1842 |
} |
| 1766 | 1843 |
#endif |
| 1767 | 1844 |
|
| 1768 | 1845 |
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
| 1769 | 1846 |
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
| 1770 | 1847 |
{
|
| 1771 |
int asi;
|
|
| 1848 |
TCGv r_val, r_asi, r_size;
|
|
| 1772 | 1849 |
|
| 1773 | 1850 |
gen_ld_asi(dst, addr, insn, 1, 0); |
| 1774 | 1851 |
|
| 1775 |
asi = GET_FIELD(insn, 19, 26); |
|
| 1776 |
tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL), |
|
| 1777 |
tcg_const_i32(asi), tcg_const_i32(1)); |
|
| 1852 |
r_val = tcg_const_i64(0xffULL); |
|
| 1853 |
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
|
| 1854 |
r_size = tcg_const_i32(1); |
|
| 1855 |
tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size); |
|
| 1856 |
tcg_temp_free(r_size); |
|
| 1857 |
tcg_temp_free(r_asi); |
|
| 1858 |
tcg_temp_free(r_val); |
|
| 1778 | 1859 |
} |
| 1779 | 1860 |
#endif |
| 1780 | 1861 |
|
| ... | ... | |
| 1802 | 1883 |
|
| 1803 | 1884 |
if (IS_IMM) { /* immediate */
|
| 1804 | 1885 |
rs2 = GET_FIELDs(insn, 19, 31); |
| 1805 |
r_rs2 = tcg_const_tl((int)rs2); |
|
| 1886 |
r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
|
|
| 1806 | 1887 |
} else { /* register */
|
| 1807 | 1888 |
rs2 = GET_FIELD(insn, 27, 31); |
| 1808 | 1889 |
if (rs2 == 0) |
| 1809 |
r_rs2 = tcg_const_tl(0); |
|
| 1890 |
r_rs2 = tcg_const_tl(0); // XXX how to free?
|
|
| 1810 | 1891 |
else if (rs2 < 8) |
| 1811 | 1892 |
r_rs2 = cpu_gregs[rs2]; |
| 1812 | 1893 |
else |
| ... | ... | |
| 1913 | 1994 |
case 0x4: /* SETHI */ |
| 1914 | 1995 |
if (rd) { // nop
|
| 1915 | 1996 |
uint32_t value = GET_FIELD(insn, 10, 31); |
| 1916 |
gen_movl_TN_reg(rd, tcg_const_tl(value << 10)); |
|
| 1997 |
TCGv r_const; |
|
| 1998 |
|
|
| 1999 |
r_const = tcg_const_tl(value << 10); |
|
| 2000 |
gen_movl_TN_reg(rd, r_const); |
|
| 2001 |
tcg_temp_free(r_const); |
|
| 1917 | 2002 |
} |
| 1918 | 2003 |
break; |
| 1919 | 2004 |
case 0x0: /* UNIMPL */ |
| ... | ... | |
| 1926 | 2011 |
case 1: |
| 1927 | 2012 |
/*CALL*/ {
|
| 1928 | 2013 |
target_long target = GET_FIELDs(insn, 2, 31) << 2; |
| 2014 |
TCGv r_const; |
|
| 1929 | 2015 |
|
| 1930 |
gen_movl_TN_reg(15, tcg_const_tl(dc->pc)); |
|
| 2016 |
r_const = tcg_const_tl(dc->pc); |
|
| 2017 |
gen_movl_TN_reg(15, r_const); |
|
| 2018 |
tcg_temp_free(r_const); |
|
| 1931 | 2019 |
target += dc->pc; |
| 1932 | 2020 |
gen_mov_pc_npc(dc, cpu_cond); |
| 1933 | 2021 |
dc->npc = target; |
| ... | ... | |
| 1973 | 2061 |
gen_cond(r_cond, 0, cond); |
| 1974 | 2062 |
#endif |
| 1975 | 2063 |
tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond); |
| 2064 |
tcg_temp_free(r_cond); |
|
| 1976 | 2065 |
} |
| 1977 | 2066 |
gen_op_next_insn(); |
| 1978 | 2067 |
tcg_gen_exit_tb(0); |
| ... | ... | |
| 2016 | 2105 |
offsetof(CPUState, tick)); |
| 2017 | 2106 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
| 2018 | 2107 |
r_tickptr); |
| 2108 |
tcg_temp_free(r_tickptr); |
|
| 2019 | 2109 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2020 | 2110 |
} |
| 2021 | 2111 |
break; |
| 2022 | 2112 |
case 0x5: /* V9 rdpc */ |
| 2023 |
gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); |
|
| 2113 |
{
|
|
| 2114 |
TCGv r_const; |
|
| 2115 |
|
|
| 2116 |
r_const = tcg_const_tl(dc->pc); |
|
| 2117 |
gen_movl_TN_reg(rd, r_const); |
|
| 2118 |
tcg_temp_free(r_const); |
|
| 2119 |
} |
|
| 2024 | 2120 |
break; |
| 2025 | 2121 |
case 0x6: /* V9 rdfprs */ |
| 2026 | 2122 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
| ... | ... | |
| 2051 | 2147 |
offsetof(CPUState, stick)); |
| 2052 | 2148 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
| 2053 | 2149 |
r_tickptr); |
| 2150 |
tcg_temp_free(r_tickptr); |
|
| 2054 | 2151 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2055 | 2152 |
} |
| 2056 | 2153 |
break; |
| ... | ... | |
| 2127 | 2224 |
offsetof(CPUState, tsptr)); |
| 2128 | 2225 |
tcg_gen_ld_tl(cpu_dst, r_tsptr, |
| 2129 | 2226 |
offsetof(trap_state, tpc)); |
| 2227 |
tcg_temp_free(r_tsptr); |
|
| 2130 | 2228 |
} |
| 2131 | 2229 |
break; |
| 2132 | 2230 |
case 1: // tnpc |
| ... | ... | |
| 2138 | 2236 |
offsetof(CPUState, tsptr)); |
| 2139 | 2237 |
tcg_gen_ld_tl(cpu_dst, r_tsptr, |
| 2140 | 2238 |
offsetof(trap_state, tnpc)); |
| 2239 |
tcg_temp_free(r_tsptr); |
|
| 2141 | 2240 |
} |
| 2142 | 2241 |
break; |
| 2143 | 2242 |
case 2: // tstate |
| ... | ... | |
| 2149 | 2248 |
offsetof(CPUState, tsptr)); |
| 2150 | 2249 |
tcg_gen_ld_tl(cpu_dst, r_tsptr, |
| 2151 | 2250 |
offsetof(trap_state, tstate)); |
| 2251 |
tcg_temp_free(r_tsptr); |
|
| 2152 | 2252 |
} |
| 2153 | 2253 |
break; |
| 2154 | 2254 |
case 3: // tt |
| ... | ... | |
| 2160 | 2260 |
offsetof(CPUState, tsptr)); |
| 2161 | 2261 |
tcg_gen_ld_i32(cpu_dst, r_tsptr, |
| 2162 | 2262 |
offsetof(trap_state, tt)); |
| 2263 |
tcg_temp_free(r_tsptr); |
|
| 2163 | 2264 |
} |
| 2164 | 2265 |
break; |
| 2165 | 2266 |
case 4: // tick |
| ... | ... | |
| 2172 | 2273 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, |
| 2173 | 2274 |
r_tickptr); |
| 2174 | 2275 |
gen_movl_TN_reg(rd, cpu_dst); |
| 2276 |
tcg_temp_free(r_tickptr); |
|
| 2175 | 2277 |
} |
| 2176 | 2278 |
break; |
| 2177 | 2279 |
case 5: // tba |
| ... | ... | |
| 2653 | 2755 |
glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ |
| 2654 | 2756 |
(glue(size_FDQ, FPREG(rd))); \ |
| 2655 | 2757 |
gen_set_label(l1); \ |
| 2758 |
tcg_temp_free(r_cond); \ |
|
| 2656 | 2759 |
} |
| 2657 | 2760 |
case 0x001: /* V9 fmovscc %fcc0 */ |
| 2658 | 2761 |
FMOVCC(F, 0); |
| ... | ... | |
| 2711 | 2814 |
glue(glue(gen_op_store_, size_FDQ), T0_fpr) \ |
| 2712 | 2815 |
(glue(size_FDQ, FPREG(rd))); \ |
| 2713 | 2816 |
gen_set_label(l1); \ |
| 2817 |
tcg_temp_free(r_cond); \ |
|
| 2714 | 2818 |
} |
| 2715 | 2819 |
|
| 2716 | 2820 |
case 0x101: /* V9 fmovscc %icc */ |
| ... | ... | |
| 2776 | 2880 |
if (rs1 == 0) {
|
| 2777 | 2881 |
// or %g0, x, y -> mov T0, x; mov y, T0 |
| 2778 | 2882 |
if (IS_IMM) { /* immediate */
|
| 2883 |
TCGv r_const; |
|
| 2884 |
|
|
| 2779 | 2885 |
rs2 = GET_FIELDs(insn, 19, 31); |
| 2780 |
gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); |
|
| 2886 |
r_const = tcg_const_tl((int)rs2); |
|
| 2887 |
gen_movl_TN_reg(rd, r_const); |
|
| 2888 |
tcg_temp_free(r_const); |
|
| 2781 | 2889 |
} else { /* register */
|
| 2782 | 2890 |
rs2 = GET_FIELD(insn, 27, 31); |
| 2783 | 2891 |
gen_movl_reg_TN(rs2, cpu_dst); |
| ... | ... | |
| 3107 | 3215 |
offsetof(CPUState, tick)); |
| 3108 | 3216 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
| 3109 | 3217 |
r_tickptr, cpu_dst); |
| 3218 |
tcg_temp_free(r_tickptr); |
|
| 3110 | 3219 |
} |
| 3111 | 3220 |
break; |
| 3112 | 3221 |
case 0x18: /* System tick */ |
| ... | ... | |
| 3124 | 3233 |
offsetof(CPUState, stick)); |
| 3125 | 3234 |
tcg_gen_helper_0_2(helper_tick_set_count, |
| 3126 | 3235 |
r_tickptr, cpu_dst); |
| 3236 |
tcg_temp_free(r_tickptr); |
|
| 3127 | 3237 |
} |
| 3128 | 3238 |
break; |
| 3129 | 3239 |
case 0x19: /* System tick compare */ |
| ... | ... | |
| 3144 | 3254 |
offsetof(CPUState, stick)); |
| 3145 | 3255 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
| 3146 | 3256 |
r_tickptr, cpu_dst); |
| 3257 |
tcg_temp_free(r_tickptr); |
|
| 3147 | 3258 |
} |
| 3148 | 3259 |
break; |
| 3149 | 3260 |
|
| ... | ... | |
| 3207 | 3318 |
offsetof(CPUState, tsptr)); |
| 3208 | 3319 |
tcg_gen_st_tl(cpu_dst, r_tsptr, |
| 3209 | 3320 |
offsetof(trap_state, tpc)); |
| 3321 |
tcg_temp_free(r_tsptr); |
|
| 3210 | 3322 |
} |
| 3211 | 3323 |
break; |
| 3212 | 3324 |
case 1: // tnpc |
| ... | ... | |
| 3218 | 3330 |
offsetof(CPUState, tsptr)); |
| 3219 | 3331 |
tcg_gen_st_tl(cpu_dst, r_tsptr, |
| 3220 | 3332 |
offsetof(trap_state, tnpc)); |
| 3333 |
tcg_temp_free(r_tsptr); |
|
| 3221 | 3334 |
} |
| 3222 | 3335 |
break; |
| 3223 | 3336 |
case 2: // tstate |
| ... | ... | |
| 3230 | 3343 |
tcg_gen_st_tl(cpu_dst, r_tsptr, |
| 3231 | 3344 |
offsetof(trap_state, |
| 3232 | 3345 |
tstate)); |
| 3346 |
tcg_temp_free(r_tsptr); |
|
| 3233 | 3347 |
} |
| 3234 | 3348 |
break; |
| 3235 | 3349 |
case 3: // tt |
| ... | ... | |
| 3241 | 3355 |
offsetof(CPUState, tsptr)); |
| 3242 | 3356 |
tcg_gen_st_i32(cpu_dst, r_tsptr, |
| 3243 | 3357 |
offsetof(trap_state, tt)); |
| 3358 |
tcg_temp_free(r_tsptr); |
|
| 3244 | 3359 |
} |
| 3245 | 3360 |
break; |
| 3246 | 3361 |
case 4: // tick |
| ... | ... | |
| 3252 | 3367 |
offsetof(CPUState, tick)); |
| 3253 | 3368 |
tcg_gen_helper_0_2(helper_tick_set_count, |
| 3254 | 3369 |
r_tickptr, cpu_dst); |
| 3370 |
tcg_temp_free(r_tickptr); |
|
| 3255 | 3371 |
} |
| 3256 | 3372 |
break; |
| 3257 | 3373 |
case 5: // tba |
| ... | ... | |
| 3378 | 3494 |
offsetof(CPUState, hstick)); |
| 3379 | 3495 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
| 3380 | 3496 |
r_tickptr, cpu_dst); |
| 3497 |
tcg_temp_free(r_tickptr); |
|
| 3381 | 3498 |
} |
| 3382 | 3499 |
break; |
| 3383 | 3500 |
case 6: // hver readonly |
| ... | ... | |
| 3412 | 3529 |
|
| 3413 | 3530 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
| 3414 | 3531 |
if (IS_IMM) { /* immediate */
|
| 3532 |
TCGv r_const; |
|
| 3533 |
|
|
| 3415 | 3534 |
rs2 = GET_FIELD_SPs(insn, 0, 10); |
| 3416 |
gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); |
|
| 3535 |
r_const = tcg_const_tl((int)rs2); |
|
| 3536 |
gen_movl_TN_reg(rd, r_const); |
|
| 3537 |
tcg_temp_free(r_const); |
|
| 3417 | 3538 |
} else {
|
| 3418 | 3539 |
rs2 = GET_FIELD_SP(insn, 0, 4); |
| 3419 | 3540 |
gen_movl_reg_TN(rs2, cpu_tmp0); |
| 3420 | 3541 |
gen_movl_TN_reg(rd, cpu_tmp0); |
| 3421 | 3542 |
} |
| 3422 | 3543 |
gen_set_label(l1); |
| 3544 |
tcg_temp_free(r_cond); |
|
| 3423 | 3545 |
break; |
| 3424 | 3546 |
} |
| 3425 | 3547 |
case 0x2d: /* V9 sdivx */ |
| ... | ... | |
| 3445 | 3567 |
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
| 3446 | 3568 |
cpu_src1, 0, l1); |
| 3447 | 3569 |
if (IS_IMM) { /* immediate */
|
| 3570 |
TCGv r_const; |
|
| 3571 |
|
|
| 3448 | 3572 |
rs2 = GET_FIELD_SPs(insn, 0, 9); |
| 3449 |
gen_movl_TN_reg(rd, tcg_const_tl((int)rs2)); |
|
| 3573 |
r_const = tcg_const_tl((int)rs2); |
|
| 3574 |
gen_movl_TN_reg(rd, r_const); |
|
| 3575 |
tcg_temp_free(r_const); |
|
| 3450 | 3576 |
} else {
|
| 3451 | 3577 |
rs2 = GET_FIELD_SP(insn, 0, 4); |
| 3452 | 3578 |
gen_movl_reg_TN(rs2, cpu_tmp0); |
| ... | ... | |
| 3934 | 4060 |
#endif |
| 3935 | 4061 |
#ifdef TARGET_SPARC64 |
| 3936 | 4062 |
} else if (xop == 0x39) { /* V9 return */
|
| 4063 |
TCGv r_const; |
|
| 4064 |
|
|
| 3937 | 4065 |
save_state(dc, cpu_cond); |
| 3938 | 4066 |
cpu_src1 = get_src1(insn, cpu_src1); |
| 3939 | 4067 |
if (IS_IMM) { /* immediate */
|
| ... | ... | |
| 3949 | 4077 |
} |
| 3950 | 4078 |
tcg_gen_helper_0_0(helper_restore); |
| 3951 | 4079 |
gen_mov_pc_npc(dc, cpu_cond); |
| 3952 |
tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
|
| 3953 |
tcg_const_i32(3)); |
|
| 4080 |
r_const = tcg_const_i32(3); |
|
| 4081 |
tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const); |
|
| 4082 |
tcg_temp_free(r_const); |
|
| 3954 | 4083 |
tcg_gen_mov_tl(cpu_npc, cpu_dst); |
| 3955 | 4084 |
dc->npc = DYNAMIC_PC; |
| 3956 | 4085 |
goto jmp_insn; |
| ... | ... | |
| 3971 | 4100 |
switch (xop) {
|
| 3972 | 4101 |
case 0x38: /* jmpl */ |
| 3973 | 4102 |
{
|
| 3974 |
gen_movl_TN_reg(rd, tcg_const_tl(dc->pc)); |
|
| 4103 |
TCGv r_const; |
|
| 4104 |
|
|
| 4105 |
r_const = tcg_const_tl(dc->pc); |
|
| 4106 |
gen_movl_TN_reg(rd, r_const); |
|
| 4107 |
tcg_temp_free(r_const); |
|
| 3975 | 4108 |
gen_mov_pc_npc(dc, cpu_cond); |
| 4109 |
r_const = tcg_const_i32(3); |
|
| 3976 | 4110 |
tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
| 3977 |
tcg_const_i32(3)); |
|
| 4111 |
r_const); |
|
| 4112 |
tcg_temp_free(r_const); |
|
| 3978 | 4113 |
tcg_gen_mov_tl(cpu_npc, cpu_dst); |
| 3979 | 4114 |
dc->npc = DYNAMIC_PC; |
| 3980 | 4115 |
} |
| ... | ... | |
| 3982 | 4117 |
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) |
| 3983 | 4118 |
case 0x39: /* rett, V9 return */ |
| 3984 | 4119 |
{
|
| 4120 |
TCGv r_const; |
|
| 4121 |
|
|
| 3985 | 4122 |
if (!supervisor(dc)) |
| 3986 | 4123 |
goto priv_insn; |
| 3987 | 4124 |
gen_mov_pc_npc(dc, cpu_cond); |
| 4125 |
r_const = tcg_const_i32(3); |
|
| 3988 | 4126 |
tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
| 3989 |
tcg_const_i32(3)); |
|
| 4127 |
r_const); |
|
| 4128 |
tcg_temp_free(r_const); |
|
| 3990 | 4129 |
tcg_gen_mov_tl(cpu_npc, cpu_dst); |
| 3991 | 4130 |
dc->npc = DYNAMIC_PC; |
| 3992 | 4131 |
tcg_gen_helper_0_0(helper_rett); |
| ... | ... | |
| 4080 | 4219 |
if (rd & 1) |
| 4081 | 4220 |
goto illegal_insn; |
| 4082 | 4221 |
else {
|
| 4222 |
TCGv r_const; |
|
| 4223 |
|
|
| 4083 | 4224 |
save_state(dc, cpu_cond); |
| 4084 |
tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
|
| 4085 |
tcg_const_i32(7)); // XXX remove |
|
| 4225 |
r_const = tcg_const_i32(7); |
|
| 4226 |
tcg_gen_helper_0_2(helper_check_align, cpu_dst, |
|
| 4227 |
r_const); // XXX remove |
|
| 4228 |
tcg_temp_free(r_const); |
|
| 4086 | 4229 |
ABI32_MASK(cpu_addr); |
| 4087 | 4230 |
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
| 4088 | 4231 |
tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
| ... | ... | |
| 4102 | 4245 |
tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
| 4103 | 4246 |
break; |
| 4104 | 4247 |
case 0xd: /* ldstub -- XXX: should be atomically */ |
| 4105 |
ABI32_MASK(cpu_addr); |
|
| 4106 |
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
|
| 4107 |
tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, |
|
| 4108 |
dc->mem_idx); |
|
| 4248 |
{
|
|
| 4249 |
TCGv r_const; |
|
| 4250 |
|
|
| 4251 |
ABI32_MASK(cpu_addr); |
|
| 4252 |
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
|
| 4253 |
r_const = tcg_const_tl(0xff); |
|
| 4254 |
tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
|
| 4255 |
tcg_temp_free(r_const); |
|
| 4256 |
} |
|
| 4109 | 4257 |
break; |
| 4110 | 4258 |
case 0x0f: /* swap register with memory. Also |
| 4111 | 4259 |
atomically */ |
| ... | ... | |
| 4272 | 4420 |
tcg_gen_helper_0_0(helper_ldfsr); |
| 4273 | 4421 |
break; |
| 4274 | 4422 |
case 0x22: /* load quad fpreg */ |
| 4275 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
|
| 4276 |
tcg_gen_helper_0_2(helper_ldqf, cpu_addr, |
|
| 4277 |
tcg_const_i32(dc->mem_idx)); |
|
| 4278 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 4423 |
{
|
|
| 4424 |
TCGv r_const; |
|
| 4425 |
|
|
| 4426 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
|
| 4427 |
r_const = tcg_const_i32(dc->mem_idx); |
|
| 4428 |
tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const); |
|
| 4429 |
tcg_temp_free(r_const); |
|
| 4430 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
|
| 4431 |
} |
|
| 4279 | 4432 |
break; |
| 4280 | 4433 |
case 0x23: /* load double fpreg */ |
| 4281 |
tcg_gen_helper_0_2(helper_lddf, cpu_addr, |
|
| 4282 |
tcg_const_i32(dc->mem_idx)); |
|
| 4283 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
|
| 4434 |
{
|
|
| 4435 |
TCGv r_const; |
|
| 4436 |
|
|
| 4437 |
r_const = tcg_const_i32(dc->mem_idx); |
|
| 4438 |
tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const); |
|
| 4439 |
tcg_temp_free(r_const); |
|
| 4440 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
|
| 4441 |
} |
|
| 4284 | 4442 |
break; |
| 4285 | 4443 |
default: |
| 4286 | 4444 |
goto illegal_insn; |
| ... | ... | |
| 4305 | 4463 |
if (rd & 1) |
| 4306 | 4464 |
goto illegal_insn; |
| 4307 | 4465 |
else {
|
| 4308 |
TCGv r_low; |
|
| 4466 |
TCGv r_low, r_const;
|
|
| 4309 | 4467 |
|
| 4310 | 4468 |
save_state(dc, cpu_cond); |
| 4311 | 4469 |
ABI32_MASK(cpu_addr); |
| 4470 |
r_const = tcg_const_i32(7); |
|
| 4312 | 4471 |
tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
| 4313 |
tcg_const_i32(7)); // XXX remove |
|
| 4472 |
r_const); // XXX remove |
|
| 4473 |
tcg_temp_free(r_const); |
|
| 4314 | 4474 |
r_low = tcg_temp_new(TCG_TYPE_TL); |
| 4315 | 4475 |
gen_movl_reg_TN(rd + 1, r_low); |
| 4316 | 4476 |
tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val, |
| 4317 | 4477 |
r_low); |
| 4478 |
tcg_temp_free(r_low); |
|
| 4318 | 4479 |
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
| 4319 | 4480 |
} |
| 4320 | 4481 |
break; |
| ... | ... | |
| 4398 | 4559 |
case 0x26: |
| 4399 | 4560 |
#ifdef TARGET_SPARC64 |
| 4400 | 4561 |
/* V9 stqf, store quad fpreg */ |
| 4401 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
|
| 4402 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 4403 |
tcg_gen_helper_0_2(helper_stqf, cpu_addr, |
|
| 4404 |
tcg_const_i32(dc->mem_idx)); |
|
| 4562 |
{
|
|
| 4563 |
TCGv r_const; |
|
| 4564 |
|
|
| 4565 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
|
| 4566 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 4567 |
r_const = tcg_const_i32(dc->mem_idx); |
|
| 4568 |
tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const); |
|
| 4569 |
tcg_temp_free(r_const); |
|
| 4570 |
} |
|
| 4405 | 4571 |
break; |
| 4406 | 4572 |
#else /* !TARGET_SPARC64 */ |
| 4407 | 4573 |
/* stdfq, store floating point queue */ |
| ... | ... | |
| 4416 | 4582 |
#endif |
| 4417 | 4583 |
#endif |
| 4418 | 4584 |
case 0x27: /* store double fpreg */ |
| 4419 |
gen_op_load_fpr_DT0(DFPREG(rd)); |
|
| 4420 |
tcg_gen_helper_0_2(helper_stdf, cpu_addr, |
|
| 4421 |
tcg_const_i32(dc->mem_idx)); |
|
| 4585 |
{
|
|
| 4586 |
TCGv r_const; |
|
| 4587 |
|
|
| 4588 |
gen_op_load_fpr_DT0(DFPREG(rd)); |
|
| 4589 |
r_const = tcg_const_i32(dc->mem_idx); |
|
| 4590 |
tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const); |
|
| 4591 |
tcg_temp_free(r_const); |
|
| 4592 |
} |
|
| 4422 | 4593 |
break; |
| 4423 | 4594 |
default: |
| 4424 | 4595 |
goto illegal_insn; |
| ... | ... | |
| 4432 | 4603 |
gen_stf_asi(cpu_addr, insn, 4, rd); |
| 4433 | 4604 |
break; |
| 4434 | 4605 |
case 0x36: /* V9 stqfa */ |
| 4435 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
|
| 4436 |
tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
|
| 4437 |
tcg_const_i32(7)); |
|
| 4438 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 4439 |
gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); |
|
| 4606 |
{
|
|
| 4607 |
TCGv r_const; |
|
| 4608 |
|
|
| 4609 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
|
| 4610 |
r_const = tcg_const_i32(7); |
|
| 4611 |
tcg_gen_helper_0_2(helper_check_align, cpu_addr, |
|
| 4612 |
r_const); |
|
| 4613 |
tcg_temp_free(r_const); |
|
| 4614 |
gen_op_load_fpr_QT0(QFPREG(rd)); |
|
| 4615 |
gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); |
|
| 4616 |
} |
|
| 4440 | 4617 |
break; |
| 4441 | 4618 |
case 0x37: /* V9 stdfa */ |
| 4442 | 4619 |
gen_op_load_fpr_DT0(DFPREG(rd)); |
| ... | ... | |
| 4481 | 4658 |
jmp_insn: |
| 4482 | 4659 |
return; |
| 4483 | 4660 |
illegal_insn: |
| 4484 |
save_state(dc, cpu_cond); |
|
| 4485 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN)); |
|
| 4486 |
dc->is_br = 1; |
|
| 4661 |
{
|
|
| 4662 |
TCGv r_const; |
|
| 4663 |
|
|
| 4664 |
save_state(dc, cpu_cond); |
|
| 4665 |
r_const = tcg_const_i32(TT_ILL_INSN); |
|
| 4666 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 4667 |
tcg_temp_free(r_const); |
|
| 4668 |
dc->is_br = 1; |
|
| 4669 |
} |
|
| 4487 | 4670 |
return; |
| 4488 | 4671 |
unimp_flush: |
| 4489 |
save_state(dc, cpu_cond); |
|
| 4490 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_UNIMP_FLUSH)); |
|
| 4491 |
dc->is_br = 1; |
|
| 4672 |
{
|
|
| 4673 |
TCGv r_const; |
|
| 4674 |
|
|
| 4675 |
save_state(dc, cpu_cond); |
|
| 4676 |
r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
|
| 4677 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 4678 |
tcg_temp_free(r_const); |
|
| 4679 |
dc->is_br = 1; |
|
| 4680 |
} |
|
| 4492 | 4681 |
return; |
| 4493 | 4682 |
#if !defined(CONFIG_USER_ONLY) |
| 4494 | 4683 |
priv_insn: |
| 4495 |
save_state(dc, cpu_cond); |
|
| 4496 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN)); |
|
| 4497 |
dc->is_br = 1; |
|
| 4684 |
{
|
|
| 4685 |
TCGv r_const; |
|
| 4686 |
|
|
| 4687 |
save_state(dc, cpu_cond); |
|
| 4688 |
r_const = tcg_const_i32(TT_PRIV_INSN); |
|
| 4689 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 4690 |
tcg_temp_free(r_const); |
|
| 4691 |
dc->is_br = 1; |
|
| 4692 |
} |
|
| 4498 | 4693 |
return; |
| 4499 | 4694 |
#endif |
| 4500 | 4695 |
nfpu_insn: |
| ... | ... | |
| 4511 | 4706 |
#endif |
| 4512 | 4707 |
#ifndef TARGET_SPARC64 |
| 4513 | 4708 |
ncp_insn: |
| 4514 |
save_state(dc, cpu_cond); |
|
| 4515 |
tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN)); |
|
| 4516 |
dc->is_br = 1; |
|
| 4709 |
{
|
|
| 4710 |
TCGv r_const; |
|
| 4711 |
|
|
| 4712 |
save_state(dc, cpu_cond); |
|
| 4713 |
r_const = tcg_const_i32(TT_NCP_INSN); |
|
| 4714 |
tcg_gen_helper_0_1(raise_exception, r_const); |
|
| 4715 |
tcg_temp_free(r_const); |
|
| 4716 |
dc->is_br = 1; |
|
| 4717 |
} |
|
| 4517 | 4718 |
return; |
| 4518 | 4719 |
#endif |
| 4519 | 4720 |
} |
| ... | ... | |
| 4596 | 4797 |
(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32)); |
| 4597 | 4798 |
|
| 4598 | 4799 |
exit_gen_loop: |
| 4800 |
tcg_temp_free(cpu_tmp64); |
|
| 4801 |
tcg_temp_free(cpu_tmp32); |
|
| 4802 |
tcg_temp_free(cpu_tmp0); |
|
| 4599 | 4803 |
if (!dc->is_br) {
|
| 4600 | 4804 |
if (dc->pc != DYNAMIC_PC && |
| 4601 | 4805 |
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
|
Also available in: Unified diff