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/*
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 * i386 virtual CPU header
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#define TARGET_LONG_BITS 32
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#include "cpu-defs.h"
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#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
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#define USE_CODE_COPY
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#endif
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
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#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C           0x0001
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#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000 
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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/* hidden flags - used internally by qemu to represent additionnal cpu
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   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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   with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
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#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
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#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
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#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
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#define CR0_PG_MASK  (1 << 31)
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#define CR4_VME_MASK  (1 << 0)
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#define CR4_PVI_MASK  (1 << 1)
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#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_PGE_MASK  (1 << 7)
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#define PG_PRESENT_BIT        0
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#define PG_RW_BIT        1
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#define PG_USER_BIT        2
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#define PG_PWT_BIT        3
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#define PG_PCD_BIT        4
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#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
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#define PG_PSE_BIT        7
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#define PG_GLOBAL_BIT        8
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
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#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
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#define PG_ERROR_W_BIT     1
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#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK    0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define MSR_IA32_APICBASE               0x1b
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#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define EXCP00_DIVZ        0
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#define EXCP01_SSTP        1
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#define EXCP02_NMI        2
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#define EXCP03_INT3        3
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#define EXCP04_INTO        4
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#define EXCP05_BOUND        5
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#define EXCP06_ILLOP        6
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#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
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#define EXCP09_XERR        9
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#define EXCP0A_TSS        10
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#define EXCP0B_NOSEG        11
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#define EXCP0C_STACK        12
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#define EXCP0D_GPF        13
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#define EXCP0E_PAGE        14
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#define EXCP10_COPR        16
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#define EXCP11_ALGN        17
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#define EXCP12_MCHK        18
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enum {
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    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
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    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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    CC_OP_MULW,
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    CC_OP_MULL,
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    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADDW,
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    CC_OP_ADDL,
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    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADCW,
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    CC_OP_ADCL,
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    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUBW,
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    CC_OP_SUBL,
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    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SBBW,
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    CC_OP_SBBL,
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    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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    CC_OP_LOGICW,
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    CC_OP_LOGICL,
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    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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    CC_OP_INCW,
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    CC_OP_INCL,
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    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
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    CC_OP_DECW,
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    CC_OP_DECL,
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    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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    CC_OP_SHLW,
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    CC_OP_SHLL,
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    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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    CC_OP_SARW,
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    CC_OP_SARL,
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    CC_OP_NB,
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};
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#if defined(__i386__) || defined(__x86_64__)
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#define USE_X86LDOUBLE
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#endif
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#ifdef USE_X86LDOUBLE
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typedef long double CPU86_LDouble;
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#else
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typedef double CPU86_LDouble;
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#endif
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typedef struct SegmentCache {
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    uint32_t selector;
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    uint8_t *base;
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    uint32_t limit;
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    uint32_t flags;
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} SegmentCache;
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typedef struct CPUX86State {
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    /* standard registers */
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    uint32_t regs[8];
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    uint32_t eip;
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    uint32_t eflags; /* eflags register. During CPU emulation, CC
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                        flags and DF are set to zero because they are
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                        stored elsewhere */
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    /* emulator internal eflags handling */
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    uint32_t cc_src;
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    uint32_t cc_dst;
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    uint32_t cc_op;
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    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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    uint32_t hflags; /* hidden flags, see HF_xxx constants */
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    /* FPU state */
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    unsigned int fpstt; /* top of stack index */
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    unsigned int fpus;
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    unsigned int fpuc;
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    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
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    CPU86_LDouble fpregs[8];
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    /* emulator internal variables */
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    CPU86_LDouble ft0;
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    union {
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        float f;
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        double d;
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        int i32;
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        int64_t i64;
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    } fp_convert;
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    /* segments */
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    SegmentCache segs[6]; /* selector values */
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    SegmentCache ldt;
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    SegmentCache tr;
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    SegmentCache gdt; /* only base and limit are used */
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    SegmentCache idt; /* only base and limit are used */
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    /* sysenter registers */
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    uint32_t sysenter_cs;
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    uint32_t sysenter_esp;
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    uint32_t sysenter_eip;
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    /* temporary data for USE_CODE_COPY mode */
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#ifdef USE_CODE_COPY
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    uint32_t tmp0;
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    uint32_t saved_esp;
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    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
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#endif
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    /* exception/interrupt handling */
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    jmp_buf jmp_env;
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    int exception_index;
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    int error_code;
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    int exception_is_int;
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    int exception_next_eip;
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    struct TranslationBlock *current_tb; /* currently executing TB */
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    uint32_t cr[5]; /* NOTE: cr1 is unused */
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    uint32_t dr[8]; /* debug registers */
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    int interrupt_request; 
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    int user_mode_only; /* user mode only simulation */
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    uint32_t a20_mask;
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    /* soft mmu support */
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* 0 = kernel, 1 = user */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    /* ice debug support */
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    uint32_t breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled;
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    /* user data */
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    void *opaque;
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} CPUX86State;
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#ifndef IN_OP_I386
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void cpu_x86_outb(CPUX86State *env, int addr, int val);
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void cpu_x86_outw(CPUX86State *env, int addr, int val);
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void cpu_x86_outl(CPUX86State *env, int addr, int val);
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int cpu_x86_inb(CPUX86State *env, int addr);
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int cpu_x86_inw(CPUX86State *env, int addr);
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int cpu_x86_inl(CPUX86State *env, int addr);
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#endif
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CPUX86State *cpu_x86_init(void);
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int cpu_x86_exec(CPUX86State *s);
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void cpu_x86_close(CPUX86State *s);
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int cpu_get_pic_interrupt(CPUX86State *s);
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/* MSDOS compatibility mode FPU exception support */
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void cpu_set_ferr(CPUX86State *s);
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/* this function must always be used to load data in the segment
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   cache: it synchronizes the hflags with the segment cache values */
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static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
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                                          int seg_reg, unsigned int selector,
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                                          uint8_t *base, unsigned int limit, 
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                                          unsigned int flags)
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{
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    SegmentCache *sc;
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    unsigned int new_hflags;
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    sc = &env->segs[seg_reg];
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    sc->selector = selector;
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    sc->base = base;
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    sc->limit = limit;
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    sc->flags = flags;
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    /* update the hidden flags */
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    new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
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        >> (DESC_B_SHIFT - HF_CS32_SHIFT);
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    new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
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        >> (DESC_B_SHIFT - HF_SS32_SHIFT);
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    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
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        /* XXX: try to avoid this test. The problem comes from the
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           fact that is real mode or vm86 mode we only modify the
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           'base' and 'selector' fields of the segment cache to go
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           faster. A solution may be to force addseg to one in
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           translate-i386.c. */
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        new_hflags |= HF_ADDSEG_MASK;
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    } else {
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        new_hflags |= (((unsigned long)env->segs[R_DS].base | 
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                        (unsigned long)env->segs[R_ES].base |
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                        (unsigned long)env->segs[R_SS].base) != 0) << 
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            HF_ADDSEG_SHIFT;
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    }
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    env->hflags = (env->hflags & 
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                   ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
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}
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/* wrapper, just in case memory mappings must be changed */
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static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
420
{
421
#if HF_CPL_MASK == 3
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    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
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#else
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#error HF_CPL_MASK is hardcoded
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#endif
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}
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/* used for debug or cpu save/restore */
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void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
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CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
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/* the following helpers are only usable in user mode simulation as
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   they can trigger unexpected exceptions */
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void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
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void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
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void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
440
   is returned if the signal was handled by the virtual CPU.  */
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struct siginfo;
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
443
                           void *puc);
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void cpu_x86_set_a20(CPUX86State *env, int a20_state);
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/* will be suppressed */
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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/* used to debug */
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#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
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#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
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void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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457
#endif /* CPU_I386_H */