Revision 2f062c72 hw/sh7750.c
b/hw/sh7750.c | ||
---|---|---|
27 | 27 |
#include "sh7750_regs.h" |
28 | 28 |
#include "sh7750_regnames.h" |
29 | 29 |
|
30 |
typedef struct { |
|
31 |
uint8_t data[16]; |
|
32 |
uint8_t length; /* Number of characters in the FIFO */ |
|
33 |
uint8_t write_idx; /* Index of first character to write */ |
|
34 |
uint8_t read_idx; /* Index of first character to read */ |
|
35 |
} fifo; |
|
36 |
|
|
37 | 30 |
#define NB_DEVICES 4 |
38 | 31 |
|
39 | 32 |
typedef struct SH7750State { |
... | ... | |
43 | 36 |
uint32_t periph_freq; |
44 | 37 |
/* SDRAM controller */ |
45 | 38 |
uint16_t rfcr; |
46 |
/* First serial port */ |
|
47 |
CharDriverState *serial1; |
|
48 |
uint8_t scscr1; |
|
49 |
uint8_t scsmr1; |
|
50 |
uint8_t scbrr1; |
|
51 |
uint8_t scssr1; |
|
52 |
uint8_t scssr1_read; |
|
53 |
uint8_t sctsr1; |
|
54 |
uint8_t sctsr1_loaded; |
|
55 |
uint8_t sctdr1; |
|
56 |
uint8_t scrdr1; |
|
57 |
/* Second serial port */ |
|
58 |
CharDriverState *serial2; |
|
59 |
uint16_t sclsr2; |
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60 |
uint16_t scscr2; |
|
61 |
uint16_t scfcr2; |
|
62 |
uint16_t scfsr2; |
|
63 |
uint16_t scsmr2; |
|
64 |
uint8_t scbrr2; |
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65 |
fifo serial2_receive_fifo; |
|
66 |
fifo serial2_transmit_fifo; |
|
67 | 39 |
/* IO ports */ |
68 | 40 |
uint16_t gpioic; |
69 | 41 |
uint32_t pctra; |
... | ... | |
84 | 56 |
|
85 | 57 |
} SH7750State; |
86 | 58 |
|
87 |
/********************************************************************** |
|
88 |
First serial port |
|
89 |
**********************************************************************/ |
|
90 |
|
|
91 |
static int serial1_can_receive(void *opaque) |
|
92 |
{ |
|
93 |
SH7750State *s = opaque; |
|
94 |
|
|
95 |
return s->scscr1 & SH7750_SCSCR_RE; |
|
96 |
} |
|
97 |
|
|
98 |
static void serial1_receive_char(SH7750State * s, uint8_t c) |
|
99 |
{ |
|
100 |
if (s->scssr1 & SH7750_SCSSR1_RDRF) { |
|
101 |
s->scssr1 |= SH7750_SCSSR1_ORER; |
|
102 |
return; |
|
103 |
} |
|
104 |
|
|
105 |
s->scrdr1 = c; |
|
106 |
s->scssr1 |= SH7750_SCSSR1_RDRF; |
|
107 |
} |
|
108 |
|
|
109 |
static void serial1_receive(void *opaque, const uint8_t * buf, int size) |
|
110 |
{ |
|
111 |
SH7750State *s = opaque; |
|
112 |
int i; |
|
113 |
|
|
114 |
for (i = 0; i < size; i++) { |
|
115 |
serial1_receive_char(s, buf[i]); |
|
116 |
} |
|
117 |
} |
|
118 |
|
|
119 |
static void serial1_event(void *opaque, int event) |
|
120 |
{ |
|
121 |
assert(0); |
|
122 |
} |
|
123 |
|
|
124 |
static void serial1_maybe_send(SH7750State * s) |
|
125 |
{ |
|
126 |
uint8_t c; |
|
127 |
|
|
128 |
if (s->scssr1 & SH7750_SCSSR1_TDRE) |
|
129 |
return; |
|
130 |
c = s->sctdr1; |
|
131 |
s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND; |
|
132 |
if (s->scscr1 & SH7750_SCSCR_TIE) { |
|
133 |
fprintf(stderr, "interrupts for serial port 1 not implemented\n"); |
|
134 |
assert(0); |
|
135 |
} |
|
136 |
/* XXXXX Check for errors in write */ |
|
137 |
qemu_chr_write(s->serial1, &c, 1); |
|
138 |
} |
|
139 |
|
|
140 |
static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value) |
|
141 |
{ |
|
142 |
uint8_t new_flags; |
|
143 |
|
|
144 |
/* If transmit disable, TDRE and TEND stays up */ |
|
145 |
if ((s->scscr1 & SH7750_SCSCR_TE) == 0) { |
|
146 |
mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND; |
|
147 |
} |
|
148 |
|
|
149 |
/* Only clear bits which have been read before and do not set any bit |
|
150 |
in the flags */ |
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151 |
new_flags = s->scssr1 & ~s->scssr1_read; /* Preserve unread flags */ |
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152 |
new_flags &= mem_value | ~s->scssr1_read; /* Clear read flags */ |
|
153 |
|
|
154 |
s->scssr1 = (new_flags & 0xf8) | (mem_value & 1); |
|
155 |
s->scssr1_read &= mem_value; |
|
156 |
|
|
157 |
/* If TDRE has been cleared, TEND will also be cleared */ |
|
158 |
if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) { |
|
159 |
s->scssr1 &= ~SH7750_SCSSR1_TEND; |
|
160 |
} |
|
161 |
|
|
162 |
/* Check for transmission to start */ |
|
163 |
serial1_maybe_send(s); |
|
164 |
} |
|
165 |
|
|
166 |
static void serial1_update_parameters(SH7750State * s) |
|
167 |
{ |
|
168 |
QEMUSerialSetParams ssp; |
|
169 |
|
|
170 |
if (s->scsmr1 & SH7750_SCSMR_CHR_7) |
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171 |
ssp.data_bits = 7; |
|
172 |
else |
|
173 |
ssp.data_bits = 8; |
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174 |
if (s->scsmr1 & SH7750_SCSMR_PE) { |
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175 |
if (s->scsmr1 & SH7750_SCSMR_PM_ODD) |
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176 |
ssp.parity = 'O'; |
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177 |
else |
|
178 |
ssp.parity = 'E'; |
|
179 |
} else |
|
180 |
ssp.parity = 'N'; |
|
181 |
if (s->scsmr1 & SH7750_SCSMR_STOP_2) |
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182 |
ssp.stop_bits = 2; |
|
183 |
else |
|
184 |
ssp.stop_bits = 1; |
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185 |
fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1); |
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186 |
ssp.speed = s->periph_freq / |
|
187 |
(32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1; |
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188 |
fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n", |
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189 |
ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed); |
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190 |
qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
|
191 |
} |
|
192 |
|
|
193 |
static void scscr1_changed(SH7750State * s) |
|
194 |
{ |
|
195 |
if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) { |
|
196 |
if (!s->serial1) { |
|
197 |
fprintf(stderr, "serial port 1 not bound to anything\n"); |
|
198 |
assert(0); |
|
199 |
} |
|
200 |
serial1_update_parameters(s); |
|
201 |
} |
|
202 |
if ((s->scscr1 & SH7750_SCSCR_RE) == 0) { |
|
203 |
s->scssr1 |= SH7750_SCSSR1_TDRE; |
|
204 |
} |
|
205 |
} |
|
206 |
|
|
207 |
static void init_serial1(SH7750State * s, int serial_nb) |
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208 |
{ |
|
209 |
CharDriverState *chr; |
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210 |
|
|
211 |
s->scssr1 = 0x84; |
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212 |
chr = serial_hds[serial_nb]; |
|
213 |
if (!chr) { |
|
214 |
fprintf(stderr, |
|
215 |
"no serial port associated to SH7750 first serial port\n"); |
|
216 |
return; |
|
217 |
} |
|
218 |
|
|
219 |
s->serial1 = chr; |
|
220 |
qemu_chr_add_handlers(chr, serial1_can_receive, |
|
221 |
serial1_receive, serial1_event, s); |
|
222 |
} |
|
223 |
|
|
224 |
/********************************************************************** |
|
225 |
Second serial port |
|
226 |
**********************************************************************/ |
|
227 |
|
|
228 |
static int serial2_can_receive(void *opaque) |
|
229 |
{ |
|
230 |
SH7750State *s = opaque; |
|
231 |
static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 }; |
|
232 |
|
|
233 |
return s->serial2_receive_fifo.length < |
|
234 |
max_fifo_size[(s->scfcr2 >> 9) & 7]; |
|
235 |
} |
|
236 |
|
|
237 |
static void serial2_adjust_receive_flags(SH7750State * s) |
|
238 |
{ |
|
239 |
static uint8_t max_fifo_size[] = { 1, 4, 8, 14 }; |
|
240 |
|
|
241 |
/* XXXXX Add interrupt generation */ |
|
242 |
if (s->serial2_receive_fifo.length >= |
|
243 |
max_fifo_size[(s->scfcr2 >> 7) & 3]) { |
|
244 |
s->scfsr2 |= SH7750_SCFSR2_RDF; |
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245 |
s->scfsr2 &= ~SH7750_SCFSR2_DR; |
|
246 |
} else { |
|
247 |
s->scfsr2 &= ~SH7750_SCFSR2_RDF; |
|
248 |
if (s->serial2_receive_fifo.length > 0) |
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249 |
s->scfsr2 |= SH7750_SCFSR2_DR; |
|
250 |
else |
|
251 |
s->scfsr2 &= ~SH7750_SCFSR2_DR; |
|
252 |
} |
|
253 |
} |
|
254 |
|
|
255 |
static void serial2_append_char(SH7750State * s, uint8_t c) |
|
256 |
{ |
|
257 |
if (s->serial2_receive_fifo.length == 16) { |
|
258 |
/* Overflow */ |
|
259 |
s->sclsr2 |= SH7750_SCLSR2_ORER; |
|
260 |
return; |
|
261 |
} |
|
262 |
|
|
263 |
s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c; |
|
264 |
s->serial2_receive_fifo.length++; |
|
265 |
serial2_adjust_receive_flags(s); |
|
266 |
} |
|
267 |
|
|
268 |
static void serial2_receive(void *opaque, const uint8_t * buf, int size) |
|
269 |
{ |
|
270 |
SH7750State *s = opaque; |
|
271 |
int i; |
|
272 |
|
|
273 |
for (i = 0; i < size; i++) |
|
274 |
serial2_append_char(s, buf[i]); |
|
275 |
} |
|
276 |
|
|
277 |
static void serial2_event(void *opaque, int event) |
|
278 |
{ |
|
279 |
/* XXXXX */ |
|
280 |
assert(0); |
|
281 |
} |
|
282 |
|
|
283 |
static void serial2_update_parameters(SH7750State * s) |
|
284 |
{ |
|
285 |
QEMUSerialSetParams ssp; |
|
286 |
|
|
287 |
if (s->scsmr2 & SH7750_SCSMR_CHR_7) |
|
288 |
ssp.data_bits = 7; |
|
289 |
else |
|
290 |
ssp.data_bits = 8; |
|
291 |
if (s->scsmr2 & SH7750_SCSMR_PE) { |
|
292 |
if (s->scsmr2 & SH7750_SCSMR_PM_ODD) |
|
293 |
ssp.parity = 'O'; |
|
294 |
else |
|
295 |
ssp.parity = 'E'; |
|
296 |
} else |
|
297 |
ssp.parity = 'N'; |
|
298 |
if (s->scsmr2 & SH7750_SCSMR_STOP_2) |
|
299 |
ssp.stop_bits = 2; |
|
300 |
else |
|
301 |
ssp.stop_bits = 1; |
|
302 |
fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2); |
|
303 |
ssp.speed = s->periph_freq / |
|
304 |
(32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1; |
|
305 |
fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n", |
|
306 |
ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed); |
|
307 |
qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
|
308 |
} |
|
309 |
|
|
310 |
static void scscr2_changed(SH7750State * s) |
|
311 |
{ |
|
312 |
if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) { |
|
313 |
if (!s->serial2) { |
|
314 |
fprintf(stderr, "serial port 2 not bound to anything\n"); |
|
315 |
assert(0); |
|
316 |
} |
|
317 |
serial2_update_parameters(s); |
|
318 |
} |
|
319 |
} |
|
320 |
|
|
321 |
static void init_serial2(SH7750State * s, int serial_nb) |
|
322 |
{ |
|
323 |
CharDriverState *chr; |
|
324 |
|
|
325 |
s->scfsr2 = 0x0060; |
|
326 |
|
|
327 |
chr = serial_hds[serial_nb]; |
|
328 |
if (!chr) { |
|
329 |
fprintf(stderr, |
|
330 |
"no serial port associated to SH7750 second serial port\n"); |
|
331 |
return; |
|
332 |
} |
|
333 |
|
|
334 |
s->serial2 = chr; |
|
335 |
qemu_chr_add_handlers(chr, serial2_can_receive, |
|
336 |
serial2_receive, serial1_event, s); |
|
337 |
} |
|
338 |
|
|
339 |
static void init_serial_ports(SH7750State * s) |
|
340 |
{ |
|
341 |
init_serial1(s, 0); |
|
342 |
init_serial2(s, 1); |
|
343 |
} |
|
344 | 59 |
|
345 | 60 |
/********************************************************************** |
346 | 61 |
I/O ports |
... | ... | |
472 | 187 |
|
473 | 188 |
static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr) |
474 | 189 |
{ |
475 |
SH7750State *s = opaque; |
|
476 |
uint8_t r; |
|
477 |
|
|
478 | 190 |
switch (addr) { |
479 |
case SH7750_SCSSR1_A7: |
|
480 |
r = s->scssr1; |
|
481 |
s->scssr1_read |= r; |
|
482 |
return s->scssr1; |
|
483 |
case SH7750_SCRDR1_A7: |
|
484 |
s->scssr1 &= ~SH7750_SCSSR1_RDRF; |
|
485 |
return s->scrdr1; |
|
486 | 191 |
default: |
487 | 192 |
error_access("byte read", addr); |
488 | 193 |
assert(0); |
... | ... | |
492 | 197 |
static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) |
493 | 198 |
{ |
494 | 199 |
SH7750State *s = opaque; |
495 |
uint16_t r; |
|
496 | 200 |
|
497 | 201 |
switch (addr) { |
498 | 202 |
case SH7750_RFCR_A7: |
499 | 203 |
fprintf(stderr, |
500 | 204 |
"Read access to refresh count register, incrementing\n"); |
501 | 205 |
return s->rfcr++; |
502 |
case SH7750_SCLSR2_A7: |
|
503 |
/* Read and clear overflow bit */ |
|
504 |
r = s->sclsr2; |
|
505 |
s->sclsr2 = 0; |
|
506 |
return r; |
|
507 |
case SH7750_SCSFR2_A7: |
|
508 |
return s->scfsr2; |
|
509 | 206 |
case SH7750_PDTRA_A7: |
510 | 207 |
return porta_lines(s); |
511 | 208 |
case SH7750_PDTRB_A7: |
... | ... | |
554 | 251 |
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
555 | 252 |
uint32_t mem_value) |
556 | 253 |
{ |
557 |
SH7750State *s = opaque; |
|
558 |
|
|
559 | 254 |
switch (addr) { |
560 | 255 |
/* PRECHARGE ? XXXXX */ |
561 | 256 |
case SH7750_PRECHARGE0_A7: |
562 | 257 |
case SH7750_PRECHARGE1_A7: |
563 | 258 |
ignore_access("byte write", addr); |
564 | 259 |
return; |
565 |
case SH7750_SCBRR2_A7: |
|
566 |
s->scbrr2 = mem_value; |
|
567 |
return; |
|
568 |
case SH7750_SCSCR1_A7: |
|
569 |
s->scscr1 = mem_value; |
|
570 |
scscr1_changed(s); |
|
571 |
return; |
|
572 |
case SH7750_SCSMR1_A7: |
|
573 |
s->scsmr1 = mem_value; |
|
574 |
return; |
|
575 |
case SH7750_SCBRR1_A7: |
|
576 |
s->scbrr1 = mem_value; |
|
577 |
return; |
|
578 |
case SH7750_SCTDR1_A7: |
|
579 |
s->scssr1 &= ~SH7750_SCSSR1_TEND; |
|
580 |
s->sctdr1 = mem_value; |
|
581 |
return; |
|
582 |
case SH7750_SCSSR1_A7: |
|
583 |
serial1_change_scssr1(s, mem_value); |
|
584 |
return; |
|
585 | 260 |
default: |
586 | 261 |
error_access("byte write", addr); |
587 | 262 |
assert(0); |
... | ... | |
596 | 271 |
|
597 | 272 |
switch (addr) { |
598 | 273 |
/* SDRAM controller */ |
599 |
case SH7750_SCBRR1_A7: |
|
600 |
case SH7750_SCBRR2_A7: |
|
601 | 274 |
case SH7750_BCR2_A7: |
602 | 275 |
case SH7750_BCR3_A7: |
603 | 276 |
case SH7750_RTCOR_A7: |
... | ... | |
620 | 293 |
fprintf(stderr, "Write access to refresh count register\n"); |
621 | 294 |
s->rfcr = mem_value; |
622 | 295 |
return; |
623 |
case SH7750_SCLSR2_A7: |
|
624 |
s->sclsr2 = mem_value; |
|
625 |
return; |
|
626 |
case SH7750_SCSCR2_A7: |
|
627 |
s->scscr2 = mem_value; |
|
628 |
scscr2_changed(s); |
|
629 |
return; |
|
630 |
case SH7750_SCFCR2_A7: |
|
631 |
s->scfcr2 = mem_value; |
|
632 |
return; |
|
633 |
case SH7750_SCSMR2_A7: |
|
634 |
s->scsmr2 = mem_value; |
|
635 |
return; |
|
636 | 296 |
case SH7750_GPIOIC_A7: |
637 | 297 |
s->gpioic = mem_value; |
638 | 298 |
if (mem_value != 0) { |
... | ... | |
734 | 394 |
sh7750_mem_read, |
735 | 395 |
sh7750_mem_write, s); |
736 | 396 |
cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory); |
737 |
init_serial_ports(s); |
|
397 |
|
|
398 |
sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]); |
|
399 |
sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF, |
|
400 |
s->periph_freq, serial_hds[1]); |
|
738 | 401 |
|
739 | 402 |
tmu012_init(0x1fd80000, |
740 | 403 |
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
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