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/*
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 *  PowerPC emulation special registers manipulation helpers for qemu.
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 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#if !defined(__HELPER_REGS_H__)
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#define __HELPER_REGS_H__
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static always_inline target_ulong hreg_load_xer (CPUPPCState *env)
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{
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    return (xer_so << XER_SO) |
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        (xer_ov << XER_OV) |
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        (xer_ca << XER_CA) |
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        (xer_bc << XER_BC) |
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        (xer_cmp << XER_CMP);
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}
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static always_inline void hreg_store_xer (CPUPPCState *env, target_ulong value)
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{
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    xer_so = (value >> XER_SO) & 0x01;
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    xer_ov = (value >> XER_OV) & 0x01;
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    xer_ca = (value >> XER_CA) & 0x01;
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    xer_cmp = (value >> XER_CMP) & 0xFF;
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    xer_bc = (value >> XER_BC) & 0x7F;
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}
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/* Swap temporary saved registers with GPRs */
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static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
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{
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    ppc_gpr_t tmp;
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    tmp = env->gpr[0];
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    env->gpr[0] = env->tgpr[0];
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    env->tgpr[0] = tmp;
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    tmp = env->gpr[1];
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    env->gpr[1] = env->tgpr[1];
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    env->tgpr[1] = tmp;
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    tmp = env->gpr[2];
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    env->gpr[2] = env->tgpr[2];
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    env->tgpr[2] = tmp;
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    tmp = env->gpr[3];
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    env->gpr[3] = env->tgpr[3];
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    env->tgpr[3] = tmp;
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}
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static always_inline void hreg_compute_hflags (CPUPPCState *env)
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{
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    target_ulong hflags_mask;
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    /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
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    hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
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        (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
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        (1 << MSR_LE);
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#if defined (TARGET_PPC64)
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    hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF);
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#if defined (TARGET_PPC64H)
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    hflags_mask |= 1ULL << MSR_HV;
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    /* Precompute MMU index */
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    if (msr_pr == 0 && msr_hv != 0)
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        env->mmu_idx = 2;
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    else
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#endif
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#endif
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        env->mmu_idx = 1 - msr_pr;
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    env->hflags = env->msr & hflags_mask;
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}
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static always_inline int hreg_store_msr (CPUPPCState *env, target_ulong value)
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{
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    int excp;
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    excp = 0;
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    value &= env->msr_mask;
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#if !defined (CONFIG_USER_ONLY)
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    if (((value >> MSR_IR) & 1) != msr_ir ||
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        ((value >> MSR_DR) & 1) != msr_dr) {
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        /* Flush all tlb when changing translation mode */
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        tlb_flush(env, 1);
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        excp = POWERPC_EXCP_NONE;
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        env->interrupt_request |= CPU_INTERRUPT_EXITTB;
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    }
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    if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
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                 ((value ^ env->msr) & (1 << MSR_TGPR)))) {
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        /* Swap temporary saved registers with GPRs */
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        hreg_swap_gpr_tgpr(env);
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    }
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    if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
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        /* Change the exception prefix on PowerPC 601 */
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        env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
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    }
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#endif
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    env->msr = value;
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    hreg_compute_hflags(env);
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#if !defined (CONFIG_USER_ONLY)
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    if (unlikely(msr_pow == 1)) {
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        if ((*env->check_pow)(env)) {
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            env->halted = 1;
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            excp = EXCP_HALTED;
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        }
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    }
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#endif
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    return excp;
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}
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#endif /* !defined(__HELPER_REGS_H__) */