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1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* A lot of PowerPC definition have been included here.
22
 * Most of them are not usable for now but have been kept
23
 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24
 */
25

    
26
#include "dis-asm.h"
27

    
28
//#define PPC_DUMP_CPU
29
//#define PPC_DEBUG_SPR
30
//#define PPC_DEBUG_IRQ
31

    
32
struct ppc_def_t {
33
    const unsigned char *name;
34
    uint32_t pvr;
35
    uint32_t pvr_mask;
36
    uint64_t insns_flags;
37
    uint64_t msr_mask;
38
    uint8_t mmu_model;
39
    uint8_t excp_model;
40
    uint8_t bus_model;
41
    uint8_t pad;
42
    uint32_t flags;
43
    int bfd_mach;
44
    void (*init_proc)(CPUPPCState *env);
45
    int (*check_pow)(CPUPPCState *env);
46
};
47

    
48
/* For user-mode emulation, we don't emulate any IRQ controller */
49
#if defined(CONFIG_USER_ONLY)
50
#define PPC_IRQ_INIT_FN(name)                                                 \
51
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
52
{                                                                             \
53
}
54
#else
55
#define PPC_IRQ_INIT_FN(name)                                                 \
56
void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
57
#endif
58

    
59
PPC_IRQ_INIT_FN(40x);
60
PPC_IRQ_INIT_FN(6xx);
61
PPC_IRQ_INIT_FN(970);
62

    
63
/* Generic callbacks:
64
 * do nothing but store/retrieve spr value
65
 */
66
#ifdef PPC_DUMP_SPR_ACCESSES
67
static void spr_read_generic (void *opaque, int sprn)
68
{
69
    gen_op_load_dump_spr(sprn);
70
}
71

    
72
static void spr_write_generic (void *opaque, int sprn)
73
{
74
    gen_op_store_dump_spr(sprn);
75
}
76
#else
77
static void spr_read_generic (void *opaque, int sprn)
78
{
79
    gen_op_load_spr(sprn);
80
}
81

    
82
static void spr_write_generic (void *opaque, int sprn)
83
{
84
    gen_op_store_spr(sprn);
85
}
86
#endif
87

    
88
#if !defined(CONFIG_USER_ONLY)
89
static void spr_write_clear (void *opaque, int sprn)
90
{
91
    gen_op_mask_spr(sprn);
92
}
93
#endif
94

    
95
/* SPR common to all PowerPC */
96
/* XER */
97
static void spr_read_xer (void *opaque, int sprn)
98
{
99
    gen_op_load_xer();
100
}
101

    
102
static void spr_write_xer (void *opaque, int sprn)
103
{
104
    gen_op_store_xer();
105
}
106

    
107
/* LR */
108
static void spr_read_lr (void *opaque, int sprn)
109
{
110
    gen_op_load_lr();
111
}
112

    
113
static void spr_write_lr (void *opaque, int sprn)
114
{
115
    gen_op_store_lr();
116
}
117

    
118
/* CTR */
119
static void spr_read_ctr (void *opaque, int sprn)
120
{
121
    gen_op_load_ctr();
122
}
123

    
124
static void spr_write_ctr (void *opaque, int sprn)
125
{
126
    gen_op_store_ctr();
127
}
128

    
129
/* User read access to SPR */
130
/* USPRx */
131
/* UMMCRx */
132
/* UPMCx */
133
/* USIA */
134
/* UDECR */
135
static void spr_read_ureg (void *opaque, int sprn)
136
{
137
    gen_op_load_spr(sprn + 0x10);
138
}
139

    
140
/* SPR common to all non-embedded PowerPC */
141
/* DECR */
142
#if !defined(CONFIG_USER_ONLY)
143
static void spr_read_decr (void *opaque, int sprn)
144
{
145
    gen_op_load_decr();
146
}
147

    
148
static void spr_write_decr (void *opaque, int sprn)
149
{
150
    gen_op_store_decr();
151
}
152
#endif
153

    
154
/* SPR common to all non-embedded PowerPC, except 601 */
155
/* Time base */
156
static void spr_read_tbl (void *opaque, int sprn)
157
{
158
    gen_op_load_tbl();
159
}
160

    
161
static void spr_read_tbu (void *opaque, int sprn)
162
{
163
    gen_op_load_tbu();
164
}
165

    
166
__attribute__ (( unused ))
167
static void spr_read_atbl (void *opaque, int sprn)
168
{
169
    gen_op_load_atbl();
170
}
171

    
172
__attribute__ (( unused ))
173
static void spr_read_atbu (void *opaque, int sprn)
174
{
175
    gen_op_load_atbu();
176
}
177

    
178
#if !defined(CONFIG_USER_ONLY)
179
static void spr_write_tbl (void *opaque, int sprn)
180
{
181
    gen_op_store_tbl();
182
}
183

    
184
static void spr_write_tbu (void *opaque, int sprn)
185
{
186
    gen_op_store_tbu();
187
}
188

    
189
__attribute__ (( unused ))
190
static void spr_write_atbl (void *opaque, int sprn)
191
{
192
    gen_op_store_atbl();
193
}
194

    
195
__attribute__ (( unused ))
196
static void spr_write_atbu (void *opaque, int sprn)
197
{
198
    gen_op_store_atbu();
199
}
200
#endif
201

    
202
#if !defined(CONFIG_USER_ONLY)
203
/* IBAT0U...IBAT0U */
204
/* IBAT0L...IBAT7L */
205
static void spr_read_ibat (void *opaque, int sprn)
206
{
207
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
208
}
209

    
210
static void spr_read_ibat_h (void *opaque, int sprn)
211
{
212
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
213
}
214

    
215
static void spr_write_ibatu (void *opaque, int sprn)
216
{
217
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
218
}
219

    
220
static void spr_write_ibatu_h (void *opaque, int sprn)
221
{
222
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
223
}
224

    
225
static void spr_write_ibatl (void *opaque, int sprn)
226
{
227
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
228
}
229

    
230
static void spr_write_ibatl_h (void *opaque, int sprn)
231
{
232
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
233
}
234

    
235
/* DBAT0U...DBAT7U */
236
/* DBAT0L...DBAT7L */
237
static void spr_read_dbat (void *opaque, int sprn)
238
{
239
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
240
}
241

    
242
static void spr_read_dbat_h (void *opaque, int sprn)
243
{
244
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
245
}
246

    
247
static void spr_write_dbatu (void *opaque, int sprn)
248
{
249
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
250
}
251

    
252
static void spr_write_dbatu_h (void *opaque, int sprn)
253
{
254
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
255
}
256

    
257
static void spr_write_dbatl (void *opaque, int sprn)
258
{
259
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
260
}
261

    
262
static void spr_write_dbatl_h (void *opaque, int sprn)
263
{
264
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
265
}
266

    
267
/* SDR1 */
268
static void spr_read_sdr1 (void *opaque, int sprn)
269
{
270
    gen_op_load_sdr1();
271
}
272

    
273
static void spr_write_sdr1 (void *opaque, int sprn)
274
{
275
    gen_op_store_sdr1();
276
}
277

    
278
/* 64 bits PowerPC specific SPRs */
279
/* ASR */
280
#if defined(TARGET_PPC64)
281
__attribute__ (( unused ))
282
static void spr_read_asr (void *opaque, int sprn)
283
{
284
    gen_op_load_asr();
285
}
286

    
287
__attribute__ (( unused ))
288
static void spr_write_asr (void *opaque, int sprn)
289
{
290
    gen_op_store_asr();
291
}
292
#endif
293
#endif
294

    
295
/* PowerPC 601 specific registers */
296
/* RTC */
297
static void spr_read_601_rtcl (void *opaque, int sprn)
298
{
299
    gen_op_load_601_rtcl();
300
}
301

    
302
static void spr_read_601_rtcu (void *opaque, int sprn)
303
{
304
    gen_op_load_601_rtcu();
305
}
306

    
307
#if !defined(CONFIG_USER_ONLY)
308
static void spr_write_601_rtcu (void *opaque, int sprn)
309
{
310
    gen_op_store_601_rtcu();
311
}
312

    
313
static void spr_write_601_rtcl (void *opaque, int sprn)
314
{
315
    gen_op_store_601_rtcl();
316
}
317
#endif
318

    
319
/* Unified bats */
320
#if !defined(CONFIG_USER_ONLY)
321
static void spr_read_601_ubat (void *opaque, int sprn)
322
{
323
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
324
}
325

    
326
static void spr_write_601_ubatu (void *opaque, int sprn)
327
{
328
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
329
}
330

    
331
static void spr_write_601_ubatl (void *opaque, int sprn)
332
{
333
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
334
}
335
#endif
336

    
337
/* PowerPC 40x specific registers */
338
#if !defined(CONFIG_USER_ONLY)
339
static void spr_read_40x_pit (void *opaque, int sprn)
340
{
341
    gen_op_load_40x_pit();
342
}
343

    
344
static void spr_write_40x_pit (void *opaque, int sprn)
345
{
346
    gen_op_store_40x_pit();
347
}
348

    
349
static void spr_write_40x_dbcr0 (void *opaque, int sprn)
350
{
351
    DisasContext *ctx = opaque;
352

    
353
    gen_op_store_40x_dbcr0();
354
    /* We must stop translation as we may have rebooted */
355
    GEN_STOP(ctx);
356
}
357

    
358
static void spr_write_40x_sler (void *opaque, int sprn)
359
{
360
    gen_op_store_40x_sler();
361
}
362

    
363
static void spr_write_booke_tcr (void *opaque, int sprn)
364
{
365
    gen_op_store_booke_tcr();
366
}
367

    
368
static void spr_write_booke_tsr (void *opaque, int sprn)
369
{
370
    gen_op_store_booke_tsr();
371
}
372
#endif
373

    
374
/* PowerPC 403 specific registers */
375
/* PBL1 / PBU1 / PBL2 / PBU2 */
376
#if !defined(CONFIG_USER_ONLY)
377
static void spr_read_403_pbr (void *opaque, int sprn)
378
{
379
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
380
}
381

    
382
static void spr_write_403_pbr (void *opaque, int sprn)
383
{
384
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
385
}
386

    
387
static void spr_write_pir (void *opaque, int sprn)
388
{
389
    gen_op_store_pir();
390
}
391
#endif
392

    
393
#if !defined(CONFIG_USER_ONLY)
394
/* Callback used to write the exception vector base */
395
static void spr_write_excp_prefix (void *opaque, int sprn)
396
{
397
    gen_op_store_excp_prefix();
398
    gen_op_store_spr(sprn);
399
}
400

    
401
static void spr_write_excp_vector (void *opaque, int sprn)
402
{
403
    DisasContext *ctx = opaque;
404

    
405
    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
406
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
407
        gen_op_store_spr(sprn);
408
    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
409
        gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
410
        gen_op_store_spr(sprn);
411
    } else {
412
        printf("Trying to write an unknown exception vector %d %03x\n",
413
               sprn, sprn);
414
        GEN_EXCP_PRIVREG(ctx);
415
    }
416
}
417
#endif
418

    
419
#if defined(CONFIG_USER_ONLY)
420
#define spr_register(env, num, name, uea_read, uea_write,                     \
421
                     oea_read, oea_write, initial_value)                      \
422
do {                                                                          \
423
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
424
} while (0)
425
static inline void _spr_register (CPUPPCState *env, int num,
426
                                  const unsigned char *name,
427
                                  void (*uea_read)(void *opaque, int sprn),
428
                                  void (*uea_write)(void *opaque, int sprn),
429
                                  target_ulong initial_value)
430
#else
431
static inline void spr_register (CPUPPCState *env, int num,
432
                                 const unsigned char *name,
433
                                 void (*uea_read)(void *opaque, int sprn),
434
                                 void (*uea_write)(void *opaque, int sprn),
435
                                 void (*oea_read)(void *opaque, int sprn),
436
                                 void (*oea_write)(void *opaque, int sprn),
437
                                 target_ulong initial_value)
438
#endif
439
{
440
    ppc_spr_t *spr;
441

    
442
    spr = &env->spr_cb[num];
443
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
444
#if !defined(CONFIG_USER_ONLY)
445
        spr->oea_read != NULL || spr->oea_write != NULL ||
446
#endif
447
        spr->uea_read != NULL || spr->uea_write != NULL) {
448
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
449
        exit(1);
450
    }
451
#if defined(PPC_DEBUG_SPR)
452
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
453
           initial_value);
454
#endif
455
    spr->name = name;
456
    spr->uea_read = uea_read;
457
    spr->uea_write = uea_write;
458
#if !defined(CONFIG_USER_ONLY)
459
    spr->oea_read = oea_read;
460
    spr->oea_write = oea_write;
461
#endif
462
    env->spr[num] = initial_value;
463
}
464

    
465
/* Generic PowerPC SPRs */
466
static void gen_spr_generic (CPUPPCState *env)
467
{
468
    /* Integer processing */
469
    spr_register(env, SPR_XER, "XER",
470
                 &spr_read_xer, &spr_write_xer,
471
                 &spr_read_xer, &spr_write_xer,
472
                 0x00000000);
473
    /* Branch contol */
474
    spr_register(env, SPR_LR, "LR",
475
                 &spr_read_lr, &spr_write_lr,
476
                 &spr_read_lr, &spr_write_lr,
477
                 0x00000000);
478
    spr_register(env, SPR_CTR, "CTR",
479
                 &spr_read_ctr, &spr_write_ctr,
480
                 &spr_read_ctr, &spr_write_ctr,
481
                 0x00000000);
482
    /* Interrupt processing */
483
    spr_register(env, SPR_SRR0, "SRR0",
484
                 SPR_NOACCESS, SPR_NOACCESS,
485
                 &spr_read_generic, &spr_write_generic,
486
                 0x00000000);
487
    spr_register(env, SPR_SRR1, "SRR1",
488
                 SPR_NOACCESS, SPR_NOACCESS,
489
                 &spr_read_generic, &spr_write_generic,
490
                 0x00000000);
491
    /* Processor control */
492
    spr_register(env, SPR_SPRG0, "SPRG0",
493
                 SPR_NOACCESS, SPR_NOACCESS,
494
                 &spr_read_generic, &spr_write_generic,
495
                 0x00000000);
496
    spr_register(env, SPR_SPRG1, "SPRG1",
497
                 SPR_NOACCESS, SPR_NOACCESS,
498
                 &spr_read_generic, &spr_write_generic,
499
                 0x00000000);
500
    spr_register(env, SPR_SPRG2, "SPRG2",
501
                 SPR_NOACCESS, SPR_NOACCESS,
502
                 &spr_read_generic, &spr_write_generic,
503
                 0x00000000);
504
    spr_register(env, SPR_SPRG3, "SPRG3",
505
                 SPR_NOACCESS, SPR_NOACCESS,
506
                 &spr_read_generic, &spr_write_generic,
507
                 0x00000000);
508
}
509

    
510
/* SPR common to all non-embedded PowerPC, including 601 */
511
static void gen_spr_ne_601 (CPUPPCState *env)
512
{
513
    /* Exception processing */
514
    spr_register(env, SPR_DSISR, "DSISR",
515
                 SPR_NOACCESS, SPR_NOACCESS,
516
                 &spr_read_generic, &spr_write_generic,
517
                 0x00000000);
518
    spr_register(env, SPR_DAR, "DAR",
519
                 SPR_NOACCESS, SPR_NOACCESS,
520
                 &spr_read_generic, &spr_write_generic,
521
                 0x00000000);
522
    /* Timer */
523
    spr_register(env, SPR_DECR, "DECR",
524
                 SPR_NOACCESS, SPR_NOACCESS,
525
                 &spr_read_decr, &spr_write_decr,
526
                 0x00000000);
527
    /* Memory management */
528
    spr_register(env, SPR_SDR1, "SDR1",
529
                 SPR_NOACCESS, SPR_NOACCESS,
530
                 &spr_read_sdr1, &spr_write_sdr1,
531
                 0x00000000);
532
}
533

    
534
/* BATs 0-3 */
535
static void gen_low_BATs (CPUPPCState *env)
536
{
537
#if !defined(CONFIG_USER_ONLY)
538
    spr_register(env, SPR_IBAT0U, "IBAT0U",
539
                 SPR_NOACCESS, SPR_NOACCESS,
540
                 &spr_read_ibat, &spr_write_ibatu,
541
                 0x00000000);
542
    spr_register(env, SPR_IBAT0L, "IBAT0L",
543
                 SPR_NOACCESS, SPR_NOACCESS,
544
                 &spr_read_ibat, &spr_write_ibatl,
545
                 0x00000000);
546
    spr_register(env, SPR_IBAT1U, "IBAT1U",
547
                 SPR_NOACCESS, SPR_NOACCESS,
548
                 &spr_read_ibat, &spr_write_ibatu,
549
                 0x00000000);
550
    spr_register(env, SPR_IBAT1L, "IBAT1L",
551
                 SPR_NOACCESS, SPR_NOACCESS,
552
                 &spr_read_ibat, &spr_write_ibatl,
553
                 0x00000000);
554
    spr_register(env, SPR_IBAT2U, "IBAT2U",
555
                 SPR_NOACCESS, SPR_NOACCESS,
556
                 &spr_read_ibat, &spr_write_ibatu,
557
                 0x00000000);
558
    spr_register(env, SPR_IBAT2L, "IBAT2L",
559
                 SPR_NOACCESS, SPR_NOACCESS,
560
                 &spr_read_ibat, &spr_write_ibatl,
561
                 0x00000000);
562
    spr_register(env, SPR_IBAT3U, "IBAT3U",
563
                 SPR_NOACCESS, SPR_NOACCESS,
564
                 &spr_read_ibat, &spr_write_ibatu,
565
                 0x00000000);
566
    spr_register(env, SPR_IBAT3L, "IBAT3L",
567
                 SPR_NOACCESS, SPR_NOACCESS,
568
                 &spr_read_ibat, &spr_write_ibatl,
569
                 0x00000000);
570
    spr_register(env, SPR_DBAT0U, "DBAT0U",
571
                 SPR_NOACCESS, SPR_NOACCESS,
572
                 &spr_read_dbat, &spr_write_dbatu,
573
                 0x00000000);
574
    spr_register(env, SPR_DBAT0L, "DBAT0L",
575
                 SPR_NOACCESS, SPR_NOACCESS,
576
                 &spr_read_dbat, &spr_write_dbatl,
577
                 0x00000000);
578
    spr_register(env, SPR_DBAT1U, "DBAT1U",
579
                 SPR_NOACCESS, SPR_NOACCESS,
580
                 &spr_read_dbat, &spr_write_dbatu,
581
                 0x00000000);
582
    spr_register(env, SPR_DBAT1L, "DBAT1L",
583
                 SPR_NOACCESS, SPR_NOACCESS,
584
                 &spr_read_dbat, &spr_write_dbatl,
585
                 0x00000000);
586
    spr_register(env, SPR_DBAT2U, "DBAT2U",
587
                 SPR_NOACCESS, SPR_NOACCESS,
588
                 &spr_read_dbat, &spr_write_dbatu,
589
                 0x00000000);
590
    spr_register(env, SPR_DBAT2L, "DBAT2L",
591
                 SPR_NOACCESS, SPR_NOACCESS,
592
                 &spr_read_dbat, &spr_write_dbatl,
593
                 0x00000000);
594
    spr_register(env, SPR_DBAT3U, "DBAT3U",
595
                 SPR_NOACCESS, SPR_NOACCESS,
596
                 &spr_read_dbat, &spr_write_dbatu,
597
                 0x00000000);
598
    spr_register(env, SPR_DBAT3L, "DBAT3L",
599
                 SPR_NOACCESS, SPR_NOACCESS,
600
                 &spr_read_dbat, &spr_write_dbatl,
601
                 0x00000000);
602
    env->nb_BATs += 4;
603
#endif
604
}
605

    
606
/* BATs 4-7 */
607
static void gen_high_BATs (CPUPPCState *env)
608
{
609
#if !defined(CONFIG_USER_ONLY)
610
    spr_register(env, SPR_IBAT4U, "IBAT4U",
611
                 SPR_NOACCESS, SPR_NOACCESS,
612
                 &spr_read_ibat_h, &spr_write_ibatu_h,
613
                 0x00000000);
614
    spr_register(env, SPR_IBAT4L, "IBAT4L",
615
                 SPR_NOACCESS, SPR_NOACCESS,
616
                 &spr_read_ibat_h, &spr_write_ibatl_h,
617
                 0x00000000);
618
    spr_register(env, SPR_IBAT5U, "IBAT5U",
619
                 SPR_NOACCESS, SPR_NOACCESS,
620
                 &spr_read_ibat_h, &spr_write_ibatu_h,
621
                 0x00000000);
622
    spr_register(env, SPR_IBAT5L, "IBAT5L",
623
                 SPR_NOACCESS, SPR_NOACCESS,
624
                 &spr_read_ibat_h, &spr_write_ibatl_h,
625
                 0x00000000);
626
    spr_register(env, SPR_IBAT6U, "IBAT6U",
627
                 SPR_NOACCESS, SPR_NOACCESS,
628
                 &spr_read_ibat_h, &spr_write_ibatu_h,
629
                 0x00000000);
630
    spr_register(env, SPR_IBAT6L, "IBAT6L",
631
                 SPR_NOACCESS, SPR_NOACCESS,
632
                 &spr_read_ibat_h, &spr_write_ibatl_h,
633
                 0x00000000);
634
    spr_register(env, SPR_IBAT7U, "IBAT7U",
635
                 SPR_NOACCESS, SPR_NOACCESS,
636
                 &spr_read_ibat_h, &spr_write_ibatu_h,
637
                 0x00000000);
638
    spr_register(env, SPR_IBAT7L, "IBAT7L",
639
                 SPR_NOACCESS, SPR_NOACCESS,
640
                 &spr_read_ibat_h, &spr_write_ibatl_h,
641
                 0x00000000);
642
    spr_register(env, SPR_DBAT4U, "DBAT4U",
643
                 SPR_NOACCESS, SPR_NOACCESS,
644
                 &spr_read_dbat_h, &spr_write_dbatu_h,
645
                 0x00000000);
646
    spr_register(env, SPR_DBAT4L, "DBAT4L",
647
                 SPR_NOACCESS, SPR_NOACCESS,
648
                 &spr_read_dbat_h, &spr_write_dbatl_h,
649
                 0x00000000);
650
    spr_register(env, SPR_DBAT5U, "DBAT5U",
651
                 SPR_NOACCESS, SPR_NOACCESS,
652
                 &spr_read_dbat_h, &spr_write_dbatu_h,
653
                 0x00000000);
654
    spr_register(env, SPR_DBAT5L, "DBAT5L",
655
                 SPR_NOACCESS, SPR_NOACCESS,
656
                 &spr_read_dbat_h, &spr_write_dbatl_h,
657
                 0x00000000);
658
    spr_register(env, SPR_DBAT6U, "DBAT6U",
659
                 SPR_NOACCESS, SPR_NOACCESS,
660
                 &spr_read_dbat_h, &spr_write_dbatu_h,
661
                 0x00000000);
662
    spr_register(env, SPR_DBAT6L, "DBAT6L",
663
                 SPR_NOACCESS, SPR_NOACCESS,
664
                 &spr_read_dbat_h, &spr_write_dbatl_h,
665
                 0x00000000);
666
    spr_register(env, SPR_DBAT7U, "DBAT7U",
667
                 SPR_NOACCESS, SPR_NOACCESS,
668
                 &spr_read_dbat_h, &spr_write_dbatu_h,
669
                 0x00000000);
670
    spr_register(env, SPR_DBAT7L, "DBAT7L",
671
                 SPR_NOACCESS, SPR_NOACCESS,
672
                 &spr_read_dbat_h, &spr_write_dbatl_h,
673
                 0x00000000);
674
    env->nb_BATs += 4;
675
#endif
676
}
677

    
678
/* Generic PowerPC time base */
679
static void gen_tbl (CPUPPCState *env)
680
{
681
    spr_register(env, SPR_VTBL,  "TBL",
682
                 &spr_read_tbl, SPR_NOACCESS,
683
                 &spr_read_tbl, SPR_NOACCESS,
684
                 0x00000000);
685
    spr_register(env, SPR_TBL,   "TBL",
686
                 SPR_NOACCESS, SPR_NOACCESS,
687
                 SPR_NOACCESS, &spr_write_tbl,
688
                 0x00000000);
689
    spr_register(env, SPR_VTBU,  "TBU",
690
                 &spr_read_tbu, SPR_NOACCESS,
691
                 &spr_read_tbu, SPR_NOACCESS,
692
                 0x00000000);
693
    spr_register(env, SPR_TBU,   "TBU",
694
                 SPR_NOACCESS, SPR_NOACCESS,
695
                 SPR_NOACCESS, &spr_write_tbu,
696
                 0x00000000);
697
}
698

    
699
/* Softare table search registers */
700
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
701
{
702
#if !defined(CONFIG_USER_ONLY)
703
    env->nb_tlb = nb_tlbs;
704
    env->nb_ways = nb_ways;
705
    env->id_tlbs = 1;
706
    spr_register(env, SPR_DMISS, "DMISS",
707
                 SPR_NOACCESS, SPR_NOACCESS,
708
                 &spr_read_generic, SPR_NOACCESS,
709
                 0x00000000);
710
    spr_register(env, SPR_DCMP, "DCMP",
711
                 SPR_NOACCESS, SPR_NOACCESS,
712
                 &spr_read_generic, SPR_NOACCESS,
713
                 0x00000000);
714
    spr_register(env, SPR_HASH1, "HASH1",
715
                 SPR_NOACCESS, SPR_NOACCESS,
716
                 &spr_read_generic, SPR_NOACCESS,
717
                 0x00000000);
718
    spr_register(env, SPR_HASH2, "HASH2",
719
                 SPR_NOACCESS, SPR_NOACCESS,
720
                 &spr_read_generic, SPR_NOACCESS,
721
                 0x00000000);
722
    spr_register(env, SPR_IMISS, "IMISS",
723
                 SPR_NOACCESS, SPR_NOACCESS,
724
                 &spr_read_generic, SPR_NOACCESS,
725
                 0x00000000);
726
    spr_register(env, SPR_ICMP, "ICMP",
727
                 SPR_NOACCESS, SPR_NOACCESS,
728
                 &spr_read_generic, SPR_NOACCESS,
729
                 0x00000000);
730
    spr_register(env, SPR_RPA, "RPA",
731
                 SPR_NOACCESS, SPR_NOACCESS,
732
                 &spr_read_generic, &spr_write_generic,
733
                 0x00000000);
734
#endif
735
}
736

    
737
/* SPR common to MPC755 and G2 */
738
static void gen_spr_G2_755 (CPUPPCState *env)
739
{
740
    /* SGPRs */
741
    spr_register(env, SPR_SPRG4, "SPRG4",
742
                 SPR_NOACCESS, SPR_NOACCESS,
743
                 &spr_read_generic, &spr_write_generic,
744
                 0x00000000);
745
    spr_register(env, SPR_SPRG5, "SPRG5",
746
                 SPR_NOACCESS, SPR_NOACCESS,
747
                 &spr_read_generic, &spr_write_generic,
748
                 0x00000000);
749
    spr_register(env, SPR_SPRG6, "SPRG6",
750
                 SPR_NOACCESS, SPR_NOACCESS,
751
                 &spr_read_generic, &spr_write_generic,
752
                 0x00000000);
753
    spr_register(env, SPR_SPRG7, "SPRG7",
754
                 SPR_NOACCESS, SPR_NOACCESS,
755
                 &spr_read_generic, &spr_write_generic,
756
                 0x00000000);
757
    /* External access control */
758
    /* XXX : not implemented */
759
    spr_register(env, SPR_EAR, "EAR",
760
                 SPR_NOACCESS, SPR_NOACCESS,
761
                 &spr_read_generic, &spr_write_generic,
762
                 0x00000000);
763
}
764

    
765
/* SPR common to all 7xx PowerPC implementations */
766
static void gen_spr_7xx (CPUPPCState *env)
767
{
768
    /* Breakpoints */
769
    /* XXX : not implemented */
770
    spr_register(env, SPR_DABR, "DABR",
771
                 SPR_NOACCESS, SPR_NOACCESS,
772
                 &spr_read_generic, &spr_write_generic,
773
                 0x00000000);
774
    /* XXX : not implemented */
775
    spr_register(env, SPR_IABR, "IABR",
776
                 SPR_NOACCESS, SPR_NOACCESS,
777
                 &spr_read_generic, &spr_write_generic,
778
                 0x00000000);
779
    /* Cache management */
780
    /* XXX : not implemented */
781
    spr_register(env, SPR_ICTC, "ICTC",
782
                 SPR_NOACCESS, SPR_NOACCESS,
783
                 &spr_read_generic, &spr_write_generic,
784
                 0x00000000);
785
    /* XXX : not implemented */
786
    spr_register(env, SPR_L2CR, "L2CR",
787
                 SPR_NOACCESS, SPR_NOACCESS,
788
                 &spr_read_generic, &spr_write_generic,
789
                 0x00000000);
790
    /* Performance monitors */
791
    /* XXX : not implemented */
792
    spr_register(env, SPR_MMCR0, "MMCR0",
793
                 SPR_NOACCESS, SPR_NOACCESS,
794
                 &spr_read_generic, &spr_write_generic,
795
                 0x00000000);
796
    /* XXX : not implemented */
797
    spr_register(env, SPR_MMCR1, "MMCR1",
798
                 SPR_NOACCESS, SPR_NOACCESS,
799
                 &spr_read_generic, &spr_write_generic,
800
                 0x00000000);
801
    /* XXX : not implemented */
802
    spr_register(env, SPR_PMC1, "PMC1",
803
                 SPR_NOACCESS, SPR_NOACCESS,
804
                 &spr_read_generic, &spr_write_generic,
805
                 0x00000000);
806
    /* XXX : not implemented */
807
    spr_register(env, SPR_PMC2, "PMC2",
808
                 SPR_NOACCESS, SPR_NOACCESS,
809
                 &spr_read_generic, &spr_write_generic,
810
                 0x00000000);
811
    /* XXX : not implemented */
812
    spr_register(env, SPR_PMC3, "PMC3",
813
                 SPR_NOACCESS, SPR_NOACCESS,
814
                 &spr_read_generic, &spr_write_generic,
815
                 0x00000000);
816
    /* XXX : not implemented */
817
    spr_register(env, SPR_PMC4, "PMC4",
818
                 SPR_NOACCESS, SPR_NOACCESS,
819
                 &spr_read_generic, &spr_write_generic,
820
                 0x00000000);
821
    /* XXX : not implemented */
822
    spr_register(env, SPR_SIAR, "SIAR",
823
                 SPR_NOACCESS, SPR_NOACCESS,
824
                 &spr_read_generic, SPR_NOACCESS,
825
                 0x00000000);
826
    /* XXX : not implemented */
827
    spr_register(env, SPR_UMMCR0, "UMMCR0",
828
                 &spr_read_ureg, SPR_NOACCESS,
829
                 &spr_read_ureg, SPR_NOACCESS,
830
                 0x00000000);
831
    /* XXX : not implemented */
832
    spr_register(env, SPR_UMMCR1, "UMMCR1",
833
                 &spr_read_ureg, SPR_NOACCESS,
834
                 &spr_read_ureg, SPR_NOACCESS,
835
                 0x00000000);
836
    /* XXX : not implemented */
837
    spr_register(env, SPR_UPMC1, "UPMC1",
838
                 &spr_read_ureg, SPR_NOACCESS,
839
                 &spr_read_ureg, SPR_NOACCESS,
840
                 0x00000000);
841
    /* XXX : not implemented */
842
    spr_register(env, SPR_UPMC2, "UPMC2",
843
                 &spr_read_ureg, SPR_NOACCESS,
844
                 &spr_read_ureg, SPR_NOACCESS,
845
                 0x00000000);
846
    /* XXX : not implemented */
847
    spr_register(env, SPR_UPMC3, "UPMC3",
848
                 &spr_read_ureg, SPR_NOACCESS,
849
                 &spr_read_ureg, SPR_NOACCESS,
850
                 0x00000000);
851
    /* XXX : not implemented */
852
    spr_register(env, SPR_UPMC4, "UPMC4",
853
                 &spr_read_ureg, SPR_NOACCESS,
854
                 &spr_read_ureg, SPR_NOACCESS,
855
                 0x00000000);
856
    /* XXX : not implemented */
857
    spr_register(env, SPR_USIAR, "USIAR",
858
                 &spr_read_ureg, SPR_NOACCESS,
859
                 &spr_read_ureg, SPR_NOACCESS,
860
                 0x00000000);
861
    /* External access control */
862
    /* XXX : not implemented */
863
    spr_register(env, SPR_EAR, "EAR",
864
                 SPR_NOACCESS, SPR_NOACCESS,
865
                 &spr_read_generic, &spr_write_generic,
866
                 0x00000000);
867
}
868

    
869
static void gen_spr_thrm (CPUPPCState *env)
870
{
871
    /* Thermal management */
872
    /* XXX : not implemented */
873
    spr_register(env, SPR_THRM1, "THRM1",
874
                 SPR_NOACCESS, SPR_NOACCESS,
875
                 &spr_read_generic, &spr_write_generic,
876
                 0x00000000);
877
    /* XXX : not implemented */
878
    spr_register(env, SPR_THRM2, "THRM2",
879
                 SPR_NOACCESS, SPR_NOACCESS,
880
                 &spr_read_generic, &spr_write_generic,
881
                 0x00000000);
882
    /* XXX : not implemented */
883
    spr_register(env, SPR_THRM3, "THRM3",
884
                 SPR_NOACCESS, SPR_NOACCESS,
885
                 &spr_read_generic, &spr_write_generic,
886
                 0x00000000);
887
}
888

    
889
/* SPR specific to PowerPC 604 implementation */
890
static void gen_spr_604 (CPUPPCState *env)
891
{
892
    /* Processor identification */
893
    spr_register(env, SPR_PIR, "PIR",
894
                 SPR_NOACCESS, SPR_NOACCESS,
895
                 &spr_read_generic, &spr_write_pir,
896
                 0x00000000);
897
    /* Breakpoints */
898
    /* XXX : not implemented */
899
    spr_register(env, SPR_IABR, "IABR",
900
                 SPR_NOACCESS, SPR_NOACCESS,
901
                 &spr_read_generic, &spr_write_generic,
902
                 0x00000000);
903
    /* XXX : not implemented */
904
    spr_register(env, SPR_DABR, "DABR",
905
                 SPR_NOACCESS, SPR_NOACCESS,
906
                 &spr_read_generic, &spr_write_generic,
907
                 0x00000000);
908
    /* Performance counters */
909
    /* XXX : not implemented */
910
    spr_register(env, SPR_MMCR0, "MMCR0",
911
                 SPR_NOACCESS, SPR_NOACCESS,
912
                 &spr_read_generic, &spr_write_generic,
913
                 0x00000000);
914
    /* XXX : not implemented */
915
    spr_register(env, SPR_MMCR1, "MMCR1",
916
                 SPR_NOACCESS, SPR_NOACCESS,
917
                 &spr_read_generic, &spr_write_generic,
918
                 0x00000000);
919
    /* XXX : not implemented */
920
    spr_register(env, SPR_PMC1, "PMC1",
921
                 SPR_NOACCESS, SPR_NOACCESS,
922
                 &spr_read_generic, &spr_write_generic,
923
                 0x00000000);
924
    /* XXX : not implemented */
925
    spr_register(env, SPR_PMC2, "PMC2",
926
                 SPR_NOACCESS, SPR_NOACCESS,
927
                 &spr_read_generic, &spr_write_generic,
928
                 0x00000000);
929
    /* XXX : not implemented */
930
    spr_register(env, SPR_PMC3, "PMC3",
931
                 SPR_NOACCESS, SPR_NOACCESS,
932
                 &spr_read_generic, &spr_write_generic,
933
                 0x00000000);
934
    /* XXX : not implemented */
935
    spr_register(env, SPR_PMC4, "PMC4",
936
                 SPR_NOACCESS, SPR_NOACCESS,
937
                 &spr_read_generic, &spr_write_generic,
938
                 0x00000000);
939
    /* XXX : not implemented */
940
    spr_register(env, SPR_SIAR, "SIAR",
941
                 SPR_NOACCESS, SPR_NOACCESS,
942
                 &spr_read_generic, SPR_NOACCESS,
943
                 0x00000000);
944
    /* XXX : not implemented */
945
    spr_register(env, SPR_SDA, "SDA",
946
                 SPR_NOACCESS, SPR_NOACCESS,
947
                 &spr_read_generic, SPR_NOACCESS,
948
                 0x00000000);
949
    /* External access control */
950
    /* XXX : not implemented */
951
    spr_register(env, SPR_EAR, "EAR",
952
                 SPR_NOACCESS, SPR_NOACCESS,
953
                 &spr_read_generic, &spr_write_generic,
954
                 0x00000000);
955
}
956

    
957
/* SPR specific to PowerPC 603 implementation */
958
static void gen_spr_603 (CPUPPCState *env)
959
{
960
    /* External access control */
961
    /* XXX : not implemented */
962
    spr_register(env, SPR_EAR, "EAR",
963
                 SPR_NOACCESS, SPR_NOACCESS,
964
                 &spr_read_generic, &spr_write_generic,
965
                 0x00000000);
966
}
967

    
968
/* SPR specific to PowerPC G2 implementation */
969
static void gen_spr_G2 (CPUPPCState *env)
970
{
971
    /* Memory base address */
972
    /* MBAR */
973
    /* XXX : not implemented */
974
    spr_register(env, SPR_MBAR, "MBAR",
975
                 SPR_NOACCESS, SPR_NOACCESS,
976
                 &spr_read_generic, &spr_write_generic,
977
                 0x00000000);
978
    /* System version register */
979
    /* SVR */
980
    /* XXX : TODO: initialize it to an appropriate value */
981
    spr_register(env, SPR_SVR, "SVR",
982
                 SPR_NOACCESS, SPR_NOACCESS,
983
                 &spr_read_generic, SPR_NOACCESS,
984
                 0x00000000);
985
    /* Exception processing */
986
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
987
                 SPR_NOACCESS, SPR_NOACCESS,
988
                 &spr_read_generic, &spr_write_generic,
989
                 0x00000000);
990
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
991
                 SPR_NOACCESS, SPR_NOACCESS,
992
                 &spr_read_generic, &spr_write_generic,
993
                 0x00000000);
994
    /* Breakpoints */
995
    /* XXX : not implemented */
996
    spr_register(env, SPR_DABR, "DABR",
997
                 SPR_NOACCESS, SPR_NOACCESS,
998
                 &spr_read_generic, &spr_write_generic,
999
                 0x00000000);
1000
    /* XXX : not implemented */
1001
    spr_register(env, SPR_DABR2, "DABR2",
1002
                 SPR_NOACCESS, SPR_NOACCESS,
1003
                 &spr_read_generic, &spr_write_generic,
1004
                 0x00000000);
1005
    /* XXX : not implemented */
1006
    spr_register(env, SPR_IABR, "IABR",
1007
                 SPR_NOACCESS, SPR_NOACCESS,
1008
                 &spr_read_generic, &spr_write_generic,
1009
                 0x00000000);
1010
    /* XXX : not implemented */
1011
    spr_register(env, SPR_IABR2, "IABR2",
1012
                 SPR_NOACCESS, SPR_NOACCESS,
1013
                 &spr_read_generic, &spr_write_generic,
1014
                 0x00000000);
1015
    /* XXX : not implemented */
1016
    spr_register(env, SPR_IBCR, "IBCR",
1017
                 SPR_NOACCESS, SPR_NOACCESS,
1018
                 &spr_read_generic, &spr_write_generic,
1019
                 0x00000000);
1020
    /* XXX : not implemented */
1021
    spr_register(env, SPR_DBCR, "DBCR",
1022
                 SPR_NOACCESS, SPR_NOACCESS,
1023
                 &spr_read_generic, &spr_write_generic,
1024
                 0x00000000);
1025
}
1026

    
1027
/* SPR specific to PowerPC 602 implementation */
1028
static void gen_spr_602 (CPUPPCState *env)
1029
{
1030
    /* ESA registers */
1031
    /* XXX : not implemented */
1032
    spr_register(env, SPR_SER, "SER",
1033
                 SPR_NOACCESS, SPR_NOACCESS,
1034
                 &spr_read_generic, &spr_write_generic,
1035
                 0x00000000);
1036
    /* XXX : not implemented */
1037
    spr_register(env, SPR_SEBR, "SEBR",
1038
                 SPR_NOACCESS, SPR_NOACCESS,
1039
                 &spr_read_generic, &spr_write_generic,
1040
                 0x00000000);
1041
    /* XXX : not implemented */
1042
    spr_register(env, SPR_ESASRR, "ESASRR",
1043
                 SPR_NOACCESS, SPR_NOACCESS,
1044
                 &spr_read_generic, &spr_write_generic,
1045
                 0x00000000);
1046
    /* Floating point status */
1047
    /* XXX : not implemented */
1048
    spr_register(env, SPR_SP, "SP",
1049
                 SPR_NOACCESS, SPR_NOACCESS,
1050
                 &spr_read_generic, &spr_write_generic,
1051
                 0x00000000);
1052
    /* XXX : not implemented */
1053
    spr_register(env, SPR_LT, "LT",
1054
                 SPR_NOACCESS, SPR_NOACCESS,
1055
                 &spr_read_generic, &spr_write_generic,
1056
                 0x00000000);
1057
    /* Watchdog timer */
1058
    /* XXX : not implemented */
1059
    spr_register(env, SPR_TCR, "TCR",
1060
                 SPR_NOACCESS, SPR_NOACCESS,
1061
                 &spr_read_generic, &spr_write_generic,
1062
                 0x00000000);
1063
    /* Interrupt base */
1064
    spr_register(env, SPR_IBR, "IBR",
1065
                 SPR_NOACCESS, SPR_NOACCESS,
1066
                 &spr_read_generic, &spr_write_generic,
1067
                 0x00000000);
1068
    /* XXX : not implemented */
1069
    spr_register(env, SPR_IABR, "IABR",
1070
                 SPR_NOACCESS, SPR_NOACCESS,
1071
                 &spr_read_generic, &spr_write_generic,
1072
                 0x00000000);
1073
}
1074

    
1075
/* SPR specific to PowerPC 601 implementation */
1076
static void gen_spr_601 (CPUPPCState *env)
1077
{
1078
    /* Multiplication/division register */
1079
    /* MQ */
1080
    spr_register(env, SPR_MQ, "MQ",
1081
                 &spr_read_generic, &spr_write_generic,
1082
                 &spr_read_generic, &spr_write_generic,
1083
                 0x00000000);
1084
    /* RTC registers */
1085
    spr_register(env, SPR_601_RTCU, "RTCU",
1086
                 SPR_NOACCESS, SPR_NOACCESS,
1087
                 SPR_NOACCESS, &spr_write_601_rtcu,
1088
                 0x00000000);
1089
    spr_register(env, SPR_601_VRTCU, "RTCU",
1090
                 &spr_read_601_rtcu, SPR_NOACCESS,
1091
                 &spr_read_601_rtcu, SPR_NOACCESS,
1092
                 0x00000000);
1093
    spr_register(env, SPR_601_RTCL, "RTCL",
1094
                 SPR_NOACCESS, SPR_NOACCESS,
1095
                 SPR_NOACCESS, &spr_write_601_rtcl,
1096
                 0x00000000);
1097
    spr_register(env, SPR_601_VRTCL, "RTCL",
1098
                 &spr_read_601_rtcl, SPR_NOACCESS,
1099
                 &spr_read_601_rtcl, SPR_NOACCESS,
1100
                 0x00000000);
1101
    /* Timer */
1102
#if 0 /* ? */
1103
    spr_register(env, SPR_601_UDECR, "UDECR",
1104
                 &spr_read_decr, SPR_NOACCESS,
1105
                 &spr_read_decr, SPR_NOACCESS,
1106
                 0x00000000);
1107
#endif
1108
    /* External access control */
1109
    /* XXX : not implemented */
1110
    spr_register(env, SPR_EAR, "EAR",
1111
                 SPR_NOACCESS, SPR_NOACCESS,
1112
                 &spr_read_generic, &spr_write_generic,
1113
                 0x00000000);
1114
    /* Memory management */
1115
#if !defined(CONFIG_USER_ONLY)
1116
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1117
                 SPR_NOACCESS, SPR_NOACCESS,
1118
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1119
                 0x00000000);
1120
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1121
                 SPR_NOACCESS, SPR_NOACCESS,
1122
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1123
                 0x00000000);
1124
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1125
                 SPR_NOACCESS, SPR_NOACCESS,
1126
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1127
                 0x00000000);
1128
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1129
                 SPR_NOACCESS, SPR_NOACCESS,
1130
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1131
                 0x00000000);
1132
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1133
                 SPR_NOACCESS, SPR_NOACCESS,
1134
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1135
                 0x00000000);
1136
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1137
                 SPR_NOACCESS, SPR_NOACCESS,
1138
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1139
                 0x00000000);
1140
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1141
                 SPR_NOACCESS, SPR_NOACCESS,
1142
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1143
                 0x00000000);
1144
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1145
                 SPR_NOACCESS, SPR_NOACCESS,
1146
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1147
                 0x00000000);
1148
    env->nb_BATs = 4;
1149
#endif
1150
}
1151

    
1152
static void gen_spr_74xx (CPUPPCState *env)
1153
{
1154
    /* Processor identification */
1155
    spr_register(env, SPR_PIR, "PIR",
1156
                 SPR_NOACCESS, SPR_NOACCESS,
1157
                 &spr_read_generic, &spr_write_pir,
1158
                 0x00000000);
1159
    /* XXX : not implemented */
1160
    spr_register(env, SPR_MMCR2, "MMCR2",
1161
                 SPR_NOACCESS, SPR_NOACCESS,
1162
                 &spr_read_generic, &spr_write_generic,
1163
                 0x00000000);
1164
    /* XXX : not implemented */
1165
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1166
                 &spr_read_ureg, SPR_NOACCESS,
1167
                 &spr_read_ureg, SPR_NOACCESS,
1168
                 0x00000000);
1169
    /* XXX: not implemented */
1170
    spr_register(env, SPR_BAMR, "BAMR",
1171
                 SPR_NOACCESS, SPR_NOACCESS,
1172
                 &spr_read_generic, &spr_write_generic,
1173
                 0x00000000);
1174
    /* XXX : not implemented */
1175
    spr_register(env, SPR_UBAMR, "UBAMR",
1176
                 &spr_read_ureg, SPR_NOACCESS,
1177
                 &spr_read_ureg, SPR_NOACCESS,
1178
                 0x00000000);
1179
    /* XXX : not implemented */
1180
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1181
                 SPR_NOACCESS, SPR_NOACCESS,
1182
                 &spr_read_generic, &spr_write_generic,
1183
                 0x00000000);
1184
    /* Hardware implementation registers */
1185
    /* XXX : not implemented */
1186
    spr_register(env, SPR_HID0, "HID0",
1187
                 SPR_NOACCESS, SPR_NOACCESS,
1188
                 &spr_read_generic, &spr_write_generic,
1189
                 0x00000000);
1190
    /* XXX : not implemented */
1191
    spr_register(env, SPR_HID1, "HID1",
1192
                 SPR_NOACCESS, SPR_NOACCESS,
1193
                 &spr_read_generic, &spr_write_generic,
1194
                 0x00000000);
1195
    /* Altivec */
1196
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1197
                 &spr_read_generic, &spr_write_generic,
1198
                 &spr_read_generic, &spr_write_generic,
1199
                 0x00000000);
1200
}
1201

    
1202
static void gen_l3_ctrl (CPUPPCState *env)
1203
{
1204
    /* L3CR */
1205
    /* XXX : not implemented */
1206
    spr_register(env, SPR_L3CR, "L3CR",
1207
                 SPR_NOACCESS, SPR_NOACCESS,
1208
                 &spr_read_generic, &spr_write_generic,
1209
                 0x00000000);
1210
    /* L3ITCR0 */
1211
    /* XXX : not implemented */
1212
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1213
                 SPR_NOACCESS, SPR_NOACCESS,
1214
                 &spr_read_generic, &spr_write_generic,
1215
                 0x00000000);
1216
    /* L3ITCR1 */
1217
    /* XXX : not implemented */
1218
    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1219
                 SPR_NOACCESS, SPR_NOACCESS,
1220
                 &spr_read_generic, &spr_write_generic,
1221
                 0x00000000);
1222
    /* L3ITCR2 */
1223
    /* XXX : not implemented */
1224
    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1225
                 SPR_NOACCESS, SPR_NOACCESS,
1226
                 &spr_read_generic, &spr_write_generic,
1227
                 0x00000000);
1228
    /* L3ITCR3 */
1229
    /* XXX : not implemented */
1230
    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1231
                 SPR_NOACCESS, SPR_NOACCESS,
1232
                 &spr_read_generic, &spr_write_generic,
1233
                 0x00000000);
1234
    /* L3OHCR */
1235
    /* XXX : not implemented */
1236
    spr_register(env, SPR_L3OHCR, "L3OHCR",
1237
                 SPR_NOACCESS, SPR_NOACCESS,
1238
                 &spr_read_generic, &spr_write_generic,
1239
                 0x00000000);
1240
    /* L3PM */
1241
    /* XXX : not implemented */
1242
    spr_register(env, SPR_L3PM, "L3PM",
1243
                 SPR_NOACCESS, SPR_NOACCESS,
1244
                 &spr_read_generic, &spr_write_generic,
1245
                 0x00000000);
1246
}
1247

    
1248
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1249
{
1250
#if !defined(CONFIG_USER_ONLY)
1251
    env->nb_tlb = nb_tlbs;
1252
    env->nb_ways = nb_ways;
1253
    env->id_tlbs = 1;
1254
    /* XXX : not implemented */
1255
    spr_register(env, SPR_PTEHI, "PTEHI",
1256
                 SPR_NOACCESS, SPR_NOACCESS,
1257
                 &spr_read_generic, &spr_write_generic,
1258
                 0x00000000);
1259
    /* XXX : not implemented */
1260
    spr_register(env, SPR_PTELO, "PTELO",
1261
                 SPR_NOACCESS, SPR_NOACCESS,
1262
                 &spr_read_generic, &spr_write_generic,
1263
                 0x00000000);
1264
    /* XXX : not implemented */
1265
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1266
                 SPR_NOACCESS, SPR_NOACCESS,
1267
                 &spr_read_generic, &spr_write_generic,
1268
                 0x00000000);
1269
#endif
1270
}
1271

    
1272
/* PowerPC BookE SPR */
1273
static void gen_spr_BookE (CPUPPCState *env)
1274
{
1275
    /* Processor identification */
1276
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1277
                 SPR_NOACCESS, SPR_NOACCESS,
1278
                 &spr_read_generic, &spr_write_pir,
1279
                 0x00000000);
1280
    /* Interrupt processing */
1281
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1282
                 SPR_NOACCESS, SPR_NOACCESS,
1283
                 &spr_read_generic, &spr_write_generic,
1284
                 0x00000000);
1285
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1286
                 SPR_NOACCESS, SPR_NOACCESS,
1287
                 &spr_read_generic, &spr_write_generic,
1288
                 0x00000000);
1289
#if 0
1290
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1291
                 SPR_NOACCESS, SPR_NOACCESS,
1292
                 &spr_read_generic, &spr_write_generic,
1293
                 0x00000000);
1294
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1295
                 SPR_NOACCESS, SPR_NOACCESS,
1296
                 &spr_read_generic, &spr_write_generic,
1297
                 0x00000000);
1298
#endif
1299
    /* Debug */
1300
    /* XXX : not implemented */
1301
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1302
                 SPR_NOACCESS, SPR_NOACCESS,
1303
                 &spr_read_generic, &spr_write_generic,
1304
                 0x00000000);
1305
    /* XXX : not implemented */
1306
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1307
                 SPR_NOACCESS, SPR_NOACCESS,
1308
                 &spr_read_generic, &spr_write_generic,
1309
                 0x00000000);
1310
    /* XXX : not implemented */
1311
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1312
                 SPR_NOACCESS, SPR_NOACCESS,
1313
                 &spr_read_generic, &spr_write_generic,
1314
                 0x00000000);
1315
    /* XXX : not implemented */
1316
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1317
                 SPR_NOACCESS, SPR_NOACCESS,
1318
                 &spr_read_generic, &spr_write_generic,
1319
                 0x00000000);
1320
    /* XXX : not implemented */
1321
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1322
                 SPR_NOACCESS, SPR_NOACCESS,
1323
                 &spr_read_generic, &spr_write_generic,
1324
                 0x00000000);
1325
    /* XXX : not implemented */
1326
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1327
                 SPR_NOACCESS, SPR_NOACCESS,
1328
                 &spr_read_generic, &spr_write_generic,
1329
                 0x00000000);
1330
    /* XXX : not implemented */
1331
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1332
                 SPR_NOACCESS, SPR_NOACCESS,
1333
                 &spr_read_generic, &spr_write_generic,
1334
                 0x00000000);
1335
    /* XXX : not implemented */
1336
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1337
                 SPR_NOACCESS, SPR_NOACCESS,
1338
                 &spr_read_generic, &spr_write_generic,
1339
                 0x00000000);
1340
    /* XXX : not implemented */
1341
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1342
                 SPR_NOACCESS, SPR_NOACCESS,
1343
                 &spr_read_generic, &spr_write_generic,
1344
                 0x00000000);
1345
    /* XXX : not implemented */
1346
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1347
                 SPR_NOACCESS, SPR_NOACCESS,
1348
                 &spr_read_generic, &spr_write_generic,
1349
                 0x00000000);
1350
    /* XXX : not implemented */
1351
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1352
                 SPR_NOACCESS, SPR_NOACCESS,
1353
                 &spr_read_generic, &spr_write_generic,
1354
                 0x00000000);
1355
    /* XXX : not implemented */
1356
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1357
                 SPR_NOACCESS, SPR_NOACCESS,
1358
                 &spr_read_generic, &spr_write_clear,
1359
                 0x00000000);
1360
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1361
                 SPR_NOACCESS, SPR_NOACCESS,
1362
                 &spr_read_generic, &spr_write_generic,
1363
                 0x00000000);
1364
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1365
                 SPR_NOACCESS, SPR_NOACCESS,
1366
                 &spr_read_generic, &spr_write_generic,
1367
                 0x00000000);
1368
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1369
                 SPR_NOACCESS, SPR_NOACCESS,
1370
                 &spr_read_generic, &spr_write_excp_prefix,
1371
                 0x00000000);
1372
    /* Exception vectors */
1373
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1374
                 SPR_NOACCESS, SPR_NOACCESS,
1375
                 &spr_read_generic, &spr_write_excp_vector,
1376
                 0x00000000);
1377
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1378
                 SPR_NOACCESS, SPR_NOACCESS,
1379
                 &spr_read_generic, &spr_write_excp_vector,
1380
                 0x00000000);
1381
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1382
                 SPR_NOACCESS, SPR_NOACCESS,
1383
                 &spr_read_generic, &spr_write_excp_vector,
1384
                 0x00000000);
1385
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1386
                 SPR_NOACCESS, SPR_NOACCESS,
1387
                 &spr_read_generic, &spr_write_excp_vector,
1388
                 0x00000000);
1389
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1390
                 SPR_NOACCESS, SPR_NOACCESS,
1391
                 &spr_read_generic, &spr_write_excp_vector,
1392
                 0x00000000);
1393
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1394
                 SPR_NOACCESS, SPR_NOACCESS,
1395
                 &spr_read_generic, &spr_write_excp_vector,
1396
                 0x00000000);
1397
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1398
                 SPR_NOACCESS, SPR_NOACCESS,
1399
                 &spr_read_generic, &spr_write_excp_vector,
1400
                 0x00000000);
1401
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1402
                 SPR_NOACCESS, SPR_NOACCESS,
1403
                 &spr_read_generic, &spr_write_excp_vector,
1404
                 0x00000000);
1405
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1406
                 SPR_NOACCESS, SPR_NOACCESS,
1407
                 &spr_read_generic, &spr_write_excp_vector,
1408
                 0x00000000);
1409
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1410
                 SPR_NOACCESS, SPR_NOACCESS,
1411
                 &spr_read_generic, &spr_write_excp_vector,
1412
                 0x00000000);
1413
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1414
                 SPR_NOACCESS, SPR_NOACCESS,
1415
                 &spr_read_generic, &spr_write_excp_vector,
1416
                 0x00000000);
1417
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1418
                 SPR_NOACCESS, SPR_NOACCESS,
1419
                 &spr_read_generic, &spr_write_excp_vector,
1420
                 0x00000000);
1421
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1422
                 SPR_NOACCESS, SPR_NOACCESS,
1423
                 &spr_read_generic, &spr_write_excp_vector,
1424
                 0x00000000);
1425
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1426
                 SPR_NOACCESS, SPR_NOACCESS,
1427
                 &spr_read_generic, &spr_write_excp_vector,
1428
                 0x00000000);
1429
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1430
                 SPR_NOACCESS, SPR_NOACCESS,
1431
                 &spr_read_generic, &spr_write_excp_vector,
1432
                 0x00000000);
1433
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1434
                 SPR_NOACCESS, SPR_NOACCESS,
1435
                 &spr_read_generic, &spr_write_excp_vector,
1436
                 0x00000000);
1437
#if 0
1438
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1439
                 SPR_NOACCESS, SPR_NOACCESS,
1440
                 &spr_read_generic, &spr_write_excp_vector,
1441
                 0x00000000);
1442
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1443
                 SPR_NOACCESS, SPR_NOACCESS,
1444
                 &spr_read_generic, &spr_write_excp_vector,
1445
                 0x00000000);
1446
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1447
                 SPR_NOACCESS, SPR_NOACCESS,
1448
                 &spr_read_generic, &spr_write_excp_vector,
1449
                 0x00000000);
1450
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1451
                 SPR_NOACCESS, SPR_NOACCESS,
1452
                 &spr_read_generic, &spr_write_excp_vector,
1453
                 0x00000000);
1454
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1455
                 SPR_NOACCESS, SPR_NOACCESS,
1456
                 &spr_read_generic, &spr_write_excp_vector,
1457
                 0x00000000);
1458
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1459
                 SPR_NOACCESS, SPR_NOACCESS,
1460
                 &spr_read_generic, &spr_write_excp_vector,
1461
                 0x00000000);
1462
#endif
1463
    spr_register(env, SPR_BOOKE_PID, "PID",
1464
                 SPR_NOACCESS, SPR_NOACCESS,
1465
                 &spr_read_generic, &spr_write_generic,
1466
                 0x00000000);
1467
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1468
                 SPR_NOACCESS, SPR_NOACCESS,
1469
                 &spr_read_generic, &spr_write_booke_tcr,
1470
                 0x00000000);
1471
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1472
                 SPR_NOACCESS, SPR_NOACCESS,
1473
                 &spr_read_generic, &spr_write_booke_tsr,
1474
                 0x00000000);
1475
    /* Timer */
1476
    spr_register(env, SPR_DECR, "DECR",
1477
                 SPR_NOACCESS, SPR_NOACCESS,
1478
                 &spr_read_decr, &spr_write_decr,
1479
                 0x00000000);
1480
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1481
                 SPR_NOACCESS, SPR_NOACCESS,
1482
                 SPR_NOACCESS, &spr_write_generic,
1483
                 0x00000000);
1484
    /* SPRGs */
1485
    spr_register(env, SPR_USPRG0, "USPRG0",
1486
                 &spr_read_generic, &spr_write_generic,
1487
                 &spr_read_generic, &spr_write_generic,
1488
                 0x00000000);
1489
    spr_register(env, SPR_SPRG4, "SPRG4",
1490
                 SPR_NOACCESS, SPR_NOACCESS,
1491
                 &spr_read_generic, &spr_write_generic,
1492
                 0x00000000);
1493
    spr_register(env, SPR_USPRG4, "USPRG4",
1494
                 &spr_read_ureg, SPR_NOACCESS,
1495
                 &spr_read_ureg, SPR_NOACCESS,
1496
                 0x00000000);
1497
    spr_register(env, SPR_SPRG5, "SPRG5",
1498
                 SPR_NOACCESS, SPR_NOACCESS,
1499
                 &spr_read_generic, &spr_write_generic,
1500
                 0x00000000);
1501
    spr_register(env, SPR_USPRG5, "USPRG5",
1502
                 &spr_read_ureg, SPR_NOACCESS,
1503
                 &spr_read_ureg, SPR_NOACCESS,
1504
                 0x00000000);
1505
    spr_register(env, SPR_SPRG6, "SPRG6",
1506
                 SPR_NOACCESS, SPR_NOACCESS,
1507
                 &spr_read_generic, &spr_write_generic,
1508
                 0x00000000);
1509
    spr_register(env, SPR_USPRG6, "USPRG6",
1510
                 &spr_read_ureg, SPR_NOACCESS,
1511
                 &spr_read_ureg, SPR_NOACCESS,
1512
                 0x00000000);
1513
    spr_register(env, SPR_SPRG7, "SPRG7",
1514
                 SPR_NOACCESS, SPR_NOACCESS,
1515
                 &spr_read_generic, &spr_write_generic,
1516
                 0x00000000);
1517
    spr_register(env, SPR_USPRG7, "USPRG7",
1518
                 &spr_read_ureg, SPR_NOACCESS,
1519
                 &spr_read_ureg, SPR_NOACCESS,
1520
                 0x00000000);
1521
}
1522

    
1523
/* FSL storage control registers */
1524
static void gen_spr_BookE_FSL (CPUPPCState *env)
1525
{
1526
#if !defined(CONFIG_USER_ONLY)
1527
    /* TLB assist registers */
1528
    /* XXX : not implemented */
1529
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1530
                 SPR_NOACCESS, SPR_NOACCESS,
1531
                 &spr_read_generic, &spr_write_generic,
1532
                 0x00000000);
1533
    /* XXX : not implemented */
1534
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1535
                 SPR_NOACCESS, SPR_NOACCESS,
1536
                 &spr_read_generic, &spr_write_generic,
1537
                 0x00000000);
1538
    /* XXX : not implemented */
1539
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1540
                 SPR_NOACCESS, SPR_NOACCESS,
1541
                 &spr_read_generic, &spr_write_generic,
1542
                 0x00000000);
1543
    /* XXX : not implemented */
1544
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1545
                 SPR_NOACCESS, SPR_NOACCESS,
1546
                 &spr_read_generic, &spr_write_generic,
1547
                 0x00000000);
1548
    /* XXX : not implemented */
1549
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1550
                 SPR_NOACCESS, SPR_NOACCESS,
1551
                 &spr_read_generic, &spr_write_generic,
1552
                 0x00000000);
1553
    /* XXX : not implemented */
1554
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1555
                 SPR_NOACCESS, SPR_NOACCESS,
1556
                 &spr_read_generic, &spr_write_generic,
1557
                 0x00000000);
1558
    /* XXX : not implemented */
1559
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1560
                 SPR_NOACCESS, SPR_NOACCESS,
1561
                 &spr_read_generic, &spr_write_generic,
1562
                 0x00000000);
1563
    if (env->nb_pids > 1) {
1564
        /* XXX : not implemented */
1565
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1566
                     SPR_NOACCESS, SPR_NOACCESS,
1567
                     &spr_read_generic, &spr_write_generic,
1568
                     0x00000000);
1569
    }
1570
    if (env->nb_pids > 2) {
1571
        /* XXX : not implemented */
1572
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1573
                     SPR_NOACCESS, SPR_NOACCESS,
1574
                     &spr_read_generic, &spr_write_generic,
1575
                     0x00000000);
1576
    }
1577
    /* XXX : not implemented */
1578
    spr_register(env, SPR_MMUCFG, "MMUCFG",
1579
                 SPR_NOACCESS, SPR_NOACCESS,
1580
                 &spr_read_generic, SPR_NOACCESS,
1581
                 0x00000000); /* TOFIX */
1582
    /* XXX : not implemented */
1583
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1584
                 SPR_NOACCESS, SPR_NOACCESS,
1585
                 &spr_read_generic, &spr_write_generic,
1586
                 0x00000000); /* TOFIX */
1587
    switch (env->nb_ways) {
1588
    case 4:
1589
        /* XXX : not implemented */
1590
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1591
                     SPR_NOACCESS, SPR_NOACCESS,
1592
                     &spr_read_generic, SPR_NOACCESS,
1593
                     0x00000000); /* TOFIX */
1594
        /* Fallthru */
1595
    case 3:
1596
        /* XXX : not implemented */
1597
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1598
                     SPR_NOACCESS, SPR_NOACCESS,
1599
                     &spr_read_generic, SPR_NOACCESS,
1600
                     0x00000000); /* TOFIX */
1601
        /* Fallthru */
1602
    case 2:
1603
        /* XXX : not implemented */
1604
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1605
                     SPR_NOACCESS, SPR_NOACCESS,
1606
                     &spr_read_generic, SPR_NOACCESS,
1607
                     0x00000000); /* TOFIX */
1608
        /* Fallthru */
1609
    case 1:
1610
        /* XXX : not implemented */
1611
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1612
                     SPR_NOACCESS, SPR_NOACCESS,
1613
                     &spr_read_generic, SPR_NOACCESS,
1614
                     0x00000000); /* TOFIX */
1615
        /* Fallthru */
1616
    case 0:
1617
    default:
1618
        break;
1619
    }
1620
#endif
1621
}
1622

    
1623
/* SPR specific to PowerPC 440 implementation */
1624
static void gen_spr_440 (CPUPPCState *env)
1625
{
1626
    /* Cache control */
1627
    /* XXX : not implemented */
1628
    spr_register(env, SPR_440_DNV0, "DNV0",
1629
                 SPR_NOACCESS, SPR_NOACCESS,
1630
                 &spr_read_generic, &spr_write_generic,
1631
                 0x00000000);
1632
    /* XXX : not implemented */
1633
    spr_register(env, SPR_440_DNV1, "DNV1",
1634
                 SPR_NOACCESS, SPR_NOACCESS,
1635
                 &spr_read_generic, &spr_write_generic,
1636
                 0x00000000);
1637
    /* XXX : not implemented */
1638
    spr_register(env, SPR_440_DNV2, "DNV2",
1639
                 SPR_NOACCESS, SPR_NOACCESS,
1640
                 &spr_read_generic, &spr_write_generic,
1641
                 0x00000000);
1642
    /* XXX : not implemented */
1643
    spr_register(env, SPR_440_DNV3, "DNV3",
1644
                 SPR_NOACCESS, SPR_NOACCESS,
1645
                 &spr_read_generic, &spr_write_generic,
1646
                 0x00000000);
1647
    /* XXX : not implemented */
1648
    spr_register(env, SPR_440_DTV0, "DTV0",
1649
                 SPR_NOACCESS, SPR_NOACCESS,
1650
                 &spr_read_generic, &spr_write_generic,
1651
                 0x00000000);
1652
    /* XXX : not implemented */
1653
    spr_register(env, SPR_440_DTV1, "DTV1",
1654
                 SPR_NOACCESS, SPR_NOACCESS,
1655
                 &spr_read_generic, &spr_write_generic,
1656
                 0x00000000);
1657
    /* XXX : not implemented */
1658
    spr_register(env, SPR_440_DTV2, "DTV2",
1659
                 SPR_NOACCESS, SPR_NOACCESS,
1660
                 &spr_read_generic, &spr_write_generic,
1661
                 0x00000000);
1662
    /* XXX : not implemented */
1663
    spr_register(env, SPR_440_DTV3, "DTV3",
1664
                 SPR_NOACCESS, SPR_NOACCESS,
1665
                 &spr_read_generic, &spr_write_generic,
1666
                 0x00000000);
1667
    /* XXX : not implemented */
1668
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1669
                 SPR_NOACCESS, SPR_NOACCESS,
1670
                 &spr_read_generic, &spr_write_generic,
1671
                 0x00000000);
1672
    /* XXX : not implemented */
1673
    spr_register(env, SPR_440_INV0, "INV0",
1674
                 SPR_NOACCESS, SPR_NOACCESS,
1675
                 &spr_read_generic, &spr_write_generic,
1676
                 0x00000000);
1677
    /* XXX : not implemented */
1678
    spr_register(env, SPR_440_INV1, "INV1",
1679
                 SPR_NOACCESS, SPR_NOACCESS,
1680
                 &spr_read_generic, &spr_write_generic,
1681
                 0x00000000);
1682
    /* XXX : not implemented */
1683
    spr_register(env, SPR_440_INV2, "INV2",
1684
                 SPR_NOACCESS, SPR_NOACCESS,
1685
                 &spr_read_generic, &spr_write_generic,
1686
                 0x00000000);
1687
    /* XXX : not implemented */
1688
    spr_register(env, SPR_440_INV3, "INV3",
1689
                 SPR_NOACCESS, SPR_NOACCESS,
1690
                 &spr_read_generic, &spr_write_generic,
1691
                 0x00000000);
1692
    /* XXX : not implemented */
1693
    spr_register(env, SPR_440_ITV0, "ITV0",
1694
                 SPR_NOACCESS, SPR_NOACCESS,
1695
                 &spr_read_generic, &spr_write_generic,
1696
                 0x00000000);
1697
    /* XXX : not implemented */
1698
    spr_register(env, SPR_440_ITV1, "ITV1",
1699
                 SPR_NOACCESS, SPR_NOACCESS,
1700
                 &spr_read_generic, &spr_write_generic,
1701
                 0x00000000);
1702
    /* XXX : not implemented */
1703
    spr_register(env, SPR_440_ITV2, "ITV2",
1704
                 SPR_NOACCESS, SPR_NOACCESS,
1705
                 &spr_read_generic, &spr_write_generic,
1706
                 0x00000000);
1707
    /* XXX : not implemented */
1708
    spr_register(env, SPR_440_ITV3, "ITV3",
1709
                 SPR_NOACCESS, SPR_NOACCESS,
1710
                 &spr_read_generic, &spr_write_generic,
1711
                 0x00000000);
1712
    /* XXX : not implemented */
1713
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1714
                 SPR_NOACCESS, SPR_NOACCESS,
1715
                 &spr_read_generic, &spr_write_generic,
1716
                 0x00000000);
1717
    /* Cache debug */
1718
    /* XXX : not implemented */
1719
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1720
                 SPR_NOACCESS, SPR_NOACCESS,
1721
                 &spr_read_generic, SPR_NOACCESS,
1722
                 0x00000000);
1723
    /* XXX : not implemented */
1724
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1725
                 SPR_NOACCESS, SPR_NOACCESS,
1726
                 &spr_read_generic, SPR_NOACCESS,
1727
                 0x00000000);
1728
    /* XXX : not implemented */
1729
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1730
                 SPR_NOACCESS, SPR_NOACCESS,
1731
                 &spr_read_generic, SPR_NOACCESS,
1732
                 0x00000000);
1733
    /* XXX : not implemented */
1734
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1735
                 SPR_NOACCESS, SPR_NOACCESS,
1736
                 &spr_read_generic, SPR_NOACCESS,
1737
                 0x00000000);
1738
    /* XXX : not implemented */
1739
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1740
                 SPR_NOACCESS, SPR_NOACCESS,
1741
                 &spr_read_generic, SPR_NOACCESS,
1742
                 0x00000000);
1743
    /* XXX : not implemented */
1744
    spr_register(env, SPR_440_DBDR, "DBDR",
1745
                 SPR_NOACCESS, SPR_NOACCESS,
1746
                 &spr_read_generic, &spr_write_generic,
1747
                 0x00000000);
1748
    /* Processor control */
1749
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1750
                 SPR_NOACCESS, SPR_NOACCESS,
1751
                 &spr_read_generic, &spr_write_generic,
1752
                 0x00000000);
1753
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1754
                 SPR_NOACCESS, SPR_NOACCESS,
1755
                 &spr_read_generic, SPR_NOACCESS,
1756
                 0x00000000);
1757
    /* Storage control */
1758
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1759
                 SPR_NOACCESS, SPR_NOACCESS,
1760
                 &spr_read_generic, &spr_write_generic,
1761
                 0x00000000);
1762
}
1763

    
1764
/* SPR shared between PowerPC 40x implementations */
1765
static void gen_spr_40x (CPUPPCState *env)
1766
{
1767
    /* Cache */
1768
    /* not emulated, as Qemu do not emulate caches */
1769
    spr_register(env, SPR_40x_DCCR, "DCCR",
1770
                 SPR_NOACCESS, SPR_NOACCESS,
1771
                 &spr_read_generic, &spr_write_generic,
1772
                 0x00000000);
1773
    /* not emulated, as Qemu do not emulate caches */
1774
    spr_register(env, SPR_40x_ICCR, "ICCR",
1775
                 SPR_NOACCESS, SPR_NOACCESS,
1776
                 &spr_read_generic, &spr_write_generic,
1777
                 0x00000000);
1778
    /* not emulated, as Qemu do not emulate caches */
1779
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1780
                 SPR_NOACCESS, SPR_NOACCESS,
1781
                 &spr_read_generic, SPR_NOACCESS,
1782
                 0x00000000);
1783
    /* Exception */
1784
    spr_register(env, SPR_40x_DEAR, "DEAR",
1785
                 SPR_NOACCESS, SPR_NOACCESS,
1786
                 &spr_read_generic, &spr_write_generic,
1787
                 0x00000000);
1788
    spr_register(env, SPR_40x_ESR, "ESR",
1789
                 SPR_NOACCESS, SPR_NOACCESS,
1790
                 &spr_read_generic, &spr_write_generic,
1791
                 0x00000000);
1792
    spr_register(env, SPR_40x_EVPR, "EVPR",
1793
                 SPR_NOACCESS, SPR_NOACCESS,
1794
                 &spr_read_generic, &spr_write_excp_prefix,
1795
                 0x00000000);
1796
    spr_register(env, SPR_40x_SRR2, "SRR2",
1797
                 &spr_read_generic, &spr_write_generic,
1798
                 &spr_read_generic, &spr_write_generic,
1799
                 0x00000000);
1800
    spr_register(env, SPR_40x_SRR3, "SRR3",
1801
                 &spr_read_generic, &spr_write_generic,
1802
                 &spr_read_generic, &spr_write_generic,
1803
                 0x00000000);
1804
    /* Timers */
1805
    spr_register(env, SPR_40x_PIT, "PIT",
1806
                 SPR_NOACCESS, SPR_NOACCESS,
1807
                 &spr_read_40x_pit, &spr_write_40x_pit,
1808
                 0x00000000);
1809
    spr_register(env, SPR_40x_TCR, "TCR",
1810
                 SPR_NOACCESS, SPR_NOACCESS,
1811
                 &spr_read_generic, &spr_write_booke_tcr,
1812
                 0x00000000);
1813
    spr_register(env, SPR_40x_TSR, "TSR",
1814
                 SPR_NOACCESS, SPR_NOACCESS,
1815
                 &spr_read_generic, &spr_write_booke_tsr,
1816
                 0x00000000);
1817
}
1818

    
1819
/* SPR specific to PowerPC 405 implementation */
1820
static void gen_spr_405 (CPUPPCState *env)
1821
{
1822
    /* MMU */
1823
    spr_register(env, SPR_40x_PID, "PID",
1824
                 SPR_NOACCESS, SPR_NOACCESS,
1825
                 &spr_read_generic, &spr_write_generic,
1826
                 0x00000000);
1827
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1828
                 SPR_NOACCESS, SPR_NOACCESS,
1829
                 &spr_read_generic, &spr_write_generic,
1830
                 0x00700000);
1831
    /* Debug interface */
1832
    /* XXX : not implemented */
1833
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1834
                 SPR_NOACCESS, SPR_NOACCESS,
1835
                 &spr_read_generic, &spr_write_40x_dbcr0,
1836
                 0x00000000);
1837
    /* XXX : not implemented */
1838
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1839
                 SPR_NOACCESS, SPR_NOACCESS,
1840
                 &spr_read_generic, &spr_write_generic,
1841
                 0x00000000);
1842
    /* XXX : not implemented */
1843
    spr_register(env, SPR_40x_DBSR, "DBSR",
1844
                 SPR_NOACCESS, SPR_NOACCESS,
1845
                 &spr_read_generic, &spr_write_clear,
1846
                 /* Last reset was system reset */
1847
                 0x00000300);
1848
    /* XXX : not implemented */
1849
    spr_register(env, SPR_40x_DAC1, "DAC1",
1850
                 SPR_NOACCESS, SPR_NOACCESS,
1851
                 &spr_read_generic, &spr_write_generic,
1852
                 0x00000000);
1853
    spr_register(env, SPR_40x_DAC2, "DAC2",
1854
                 SPR_NOACCESS, SPR_NOACCESS,
1855
                 &spr_read_generic, &spr_write_generic,
1856
                 0x00000000);
1857
    /* XXX : not implemented */
1858
    spr_register(env, SPR_405_DVC1, "DVC1",
1859
                 SPR_NOACCESS, SPR_NOACCESS,
1860
                 &spr_read_generic, &spr_write_generic,
1861
                 0x00000000);
1862
    /* XXX : not implemented */
1863
    spr_register(env, SPR_405_DVC2, "DVC2",
1864
                 SPR_NOACCESS, SPR_NOACCESS,
1865
                 &spr_read_generic, &spr_write_generic,
1866
                 0x00000000);
1867
    /* XXX : not implemented */
1868
    spr_register(env, SPR_40x_IAC1, "IAC1",
1869
                 SPR_NOACCESS, SPR_NOACCESS,
1870
                 &spr_read_generic, &spr_write_generic,
1871
                 0x00000000);
1872
    spr_register(env, SPR_40x_IAC2, "IAC2",
1873
                 SPR_NOACCESS, SPR_NOACCESS,
1874
                 &spr_read_generic, &spr_write_generic,
1875
                 0x00000000);
1876
    /* XXX : not implemented */
1877
    spr_register(env, SPR_405_IAC3, "IAC3",
1878
                 SPR_NOACCESS, SPR_NOACCESS,
1879
                 &spr_read_generic, &spr_write_generic,
1880
                 0x00000000);
1881
    /* XXX : not implemented */
1882
    spr_register(env, SPR_405_IAC4, "IAC4",
1883
                 SPR_NOACCESS, SPR_NOACCESS,
1884
                 &spr_read_generic, &spr_write_generic,
1885
                 0x00000000);
1886
    /* Storage control */
1887
    /* XXX: TODO: not implemented */
1888
    spr_register(env, SPR_405_SLER, "SLER",
1889
                 SPR_NOACCESS, SPR_NOACCESS,
1890
                 &spr_read_generic, &spr_write_40x_sler,
1891
                 0x00000000);
1892
    spr_register(env, SPR_40x_ZPR, "ZPR",
1893
                 SPR_NOACCESS, SPR_NOACCESS,
1894
                 &spr_read_generic, &spr_write_generic,
1895
                 0x00000000);
1896
    /* XXX : not implemented */
1897
    spr_register(env, SPR_405_SU0R, "SU0R",
1898
                 SPR_NOACCESS, SPR_NOACCESS,
1899
                 &spr_read_generic, &spr_write_generic,
1900
                 0x00000000);
1901
    /* SPRG */
1902
    spr_register(env, SPR_USPRG0, "USPRG0",
1903
                 &spr_read_ureg, SPR_NOACCESS,
1904
                 &spr_read_ureg, SPR_NOACCESS,
1905
                 0x00000000);
1906
    spr_register(env, SPR_SPRG4, "SPRG4",
1907
                 SPR_NOACCESS, SPR_NOACCESS,
1908
                 &spr_read_generic, &spr_write_generic,
1909
                 0x00000000);
1910
    spr_register(env, SPR_USPRG4, "USPRG4",
1911
                 &spr_read_ureg, SPR_NOACCESS,
1912
                 &spr_read_ureg, SPR_NOACCESS,
1913
                 0x00000000);
1914
    spr_register(env, SPR_SPRG5, "SPRG5",
1915
                 SPR_NOACCESS, SPR_NOACCESS,
1916
                 spr_read_generic, &spr_write_generic,
1917
                 0x00000000);
1918
    spr_register(env, SPR_USPRG5, "USPRG5",
1919
                 &spr_read_ureg, SPR_NOACCESS,
1920
                 &spr_read_ureg, SPR_NOACCESS,
1921
                 0x00000000);
1922
    spr_register(env, SPR_SPRG6, "SPRG6",
1923
                 SPR_NOACCESS, SPR_NOACCESS,
1924
                 spr_read_generic, &spr_write_generic,
1925
                 0x00000000);
1926
    spr_register(env, SPR_USPRG6, "USPRG6",
1927
                 &spr_read_ureg, SPR_NOACCESS,
1928
                 &spr_read_ureg, SPR_NOACCESS,
1929
                 0x00000000);
1930
    spr_register(env, SPR_SPRG7, "SPRG7",
1931
                 SPR_NOACCESS, SPR_NOACCESS,
1932
                 spr_read_generic, &spr_write_generic,
1933
                 0x00000000);
1934
    spr_register(env, SPR_USPRG7, "USPRG7",
1935
                 &spr_read_ureg, SPR_NOACCESS,
1936
                 &spr_read_ureg, SPR_NOACCESS,
1937
                 0x00000000);
1938
}
1939

    
1940
/* SPR shared between PowerPC 401 & 403 implementations */
1941
static void gen_spr_401_403 (CPUPPCState *env)
1942
{
1943
    /* Time base */
1944
    spr_register(env, SPR_403_VTBL,  "TBL",
1945
                 &spr_read_tbl, SPR_NOACCESS,
1946
                 &spr_read_tbl, SPR_NOACCESS,
1947
                 0x00000000);
1948
    spr_register(env, SPR_403_TBL,   "TBL",
1949
                 SPR_NOACCESS, SPR_NOACCESS,
1950
                 SPR_NOACCESS, &spr_write_tbl,
1951
                 0x00000000);
1952
    spr_register(env, SPR_403_VTBU,  "TBU",
1953
                 &spr_read_tbu, SPR_NOACCESS,
1954
                 &spr_read_tbu, SPR_NOACCESS,
1955
                 0x00000000);
1956
    spr_register(env, SPR_403_TBU,   "TBU",
1957
                 SPR_NOACCESS, SPR_NOACCESS,
1958
                 SPR_NOACCESS, &spr_write_tbu,
1959
                 0x00000000);
1960
    /* Debug */
1961
    /* not emulated, as Qemu do not emulate caches */
1962
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1963
                 SPR_NOACCESS, SPR_NOACCESS,
1964
                 &spr_read_generic, &spr_write_generic,
1965
                 0x00000000);
1966
}
1967

    
1968
/* SPR specific to PowerPC 401 implementation */
1969
static void gen_spr_401 (CPUPPCState *env)
1970
{
1971
    /* Debug interface */
1972
    /* XXX : not implemented */
1973
    spr_register(env, SPR_40x_DBCR0, "DBCR",
1974
                 SPR_NOACCESS, SPR_NOACCESS,
1975
                 &spr_read_generic, &spr_write_40x_dbcr0,
1976
                 0x00000000);
1977
    /* XXX : not implemented */
1978
    spr_register(env, SPR_40x_DBSR, "DBSR",
1979
                 SPR_NOACCESS, SPR_NOACCESS,
1980
                 &spr_read_generic, &spr_write_clear,
1981
                 /* Last reset was system reset */
1982
                 0x00000300);
1983
    /* XXX : not implemented */
1984
    spr_register(env, SPR_40x_DAC1, "DAC",
1985
                 SPR_NOACCESS, SPR_NOACCESS,
1986
                 &spr_read_generic, &spr_write_generic,
1987
                 0x00000000);
1988
    /* XXX : not implemented */
1989
    spr_register(env, SPR_40x_IAC1, "IAC",
1990
                 SPR_NOACCESS, SPR_NOACCESS,
1991
                 &spr_read_generic, &spr_write_generic,
1992
                 0x00000000);
1993
    /* Storage control */
1994
    /* XXX: TODO: not implemented */
1995
    spr_register(env, SPR_405_SLER, "SLER",
1996
                 SPR_NOACCESS, SPR_NOACCESS,
1997
                 &spr_read_generic, &spr_write_40x_sler,
1998
                 0x00000000);
1999
    /* not emulated, as Qemu never does speculative access */
2000
    spr_register(env, SPR_40x_SGR, "SGR",
2001
                 SPR_NOACCESS, SPR_NOACCESS,
2002
                 &spr_read_generic, &spr_write_generic,
2003
                 0xFFFFFFFF);
2004
    /* not emulated, as Qemu do not emulate caches */
2005
    spr_register(env, SPR_40x_DCWR, "DCWR",
2006
                 SPR_NOACCESS, SPR_NOACCESS,
2007
                 &spr_read_generic, &spr_write_generic,
2008
                 0x00000000);
2009
}
2010

    
2011
static void gen_spr_401x2 (CPUPPCState *env)
2012
{
2013
    gen_spr_401(env);
2014
    spr_register(env, SPR_40x_PID, "PID",
2015
                 SPR_NOACCESS, SPR_NOACCESS,
2016
                 &spr_read_generic, &spr_write_generic,
2017
                 0x00000000);
2018
    spr_register(env, SPR_40x_ZPR, "ZPR",
2019
                 SPR_NOACCESS, SPR_NOACCESS,
2020
                 &spr_read_generic, &spr_write_generic,
2021
                 0x00000000);
2022
}
2023

    
2024
/* SPR specific to PowerPC 403 implementation */
2025
static void gen_spr_403 (CPUPPCState *env)
2026
{
2027
    /* Debug interface */
2028
    /* XXX : not implemented */
2029
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2030
                 SPR_NOACCESS, SPR_NOACCESS,
2031
                 &spr_read_generic, &spr_write_40x_dbcr0,
2032
                 0x00000000);
2033
    /* XXX : not implemented */
2034
    spr_register(env, SPR_40x_DBSR, "DBSR",
2035
                 SPR_NOACCESS, SPR_NOACCESS,
2036
                 &spr_read_generic, &spr_write_clear,
2037
                 /* Last reset was system reset */
2038
                 0x00000300);
2039
    /* XXX : not implemented */
2040
    spr_register(env, SPR_40x_DAC1, "DAC1",
2041
                 SPR_NOACCESS, SPR_NOACCESS,
2042
                 &spr_read_generic, &spr_write_generic,
2043
                 0x00000000);
2044
    /* XXX : not implemented */
2045
    spr_register(env, SPR_40x_DAC2, "DAC2",
2046
                 SPR_NOACCESS, SPR_NOACCESS,
2047
                 &spr_read_generic, &spr_write_generic,
2048
                 0x00000000);
2049
    /* XXX : not implemented */
2050
    spr_register(env, SPR_40x_IAC1, "IAC1",
2051
                 SPR_NOACCESS, SPR_NOACCESS,
2052
                 &spr_read_generic, &spr_write_generic,
2053
                 0x00000000);
2054
    /* XXX : not implemented */
2055
    spr_register(env, SPR_40x_IAC2, "IAC2",
2056
                 SPR_NOACCESS, SPR_NOACCESS,
2057
                 &spr_read_generic, &spr_write_generic,
2058
                 0x00000000);
2059
}
2060

    
2061
static void gen_spr_403_real (CPUPPCState *env)
2062
{
2063
    spr_register(env, SPR_403_PBL1,  "PBL1",
2064
                 SPR_NOACCESS, SPR_NOACCESS,
2065
                 &spr_read_403_pbr, &spr_write_403_pbr,
2066
                 0x00000000);
2067
    spr_register(env, SPR_403_PBU1,  "PBU1",
2068
                 SPR_NOACCESS, SPR_NOACCESS,
2069
                 &spr_read_403_pbr, &spr_write_403_pbr,
2070
                 0x00000000);
2071
    spr_register(env, SPR_403_PBL2,  "PBL2",
2072
                 SPR_NOACCESS, SPR_NOACCESS,
2073
                 &spr_read_403_pbr, &spr_write_403_pbr,
2074
                 0x00000000);
2075
    spr_register(env, SPR_403_PBU2,  "PBU2",
2076
                 SPR_NOACCESS, SPR_NOACCESS,
2077
                 &spr_read_403_pbr, &spr_write_403_pbr,
2078
                 0x00000000);
2079
}
2080

    
2081
static void gen_spr_403_mmu (CPUPPCState *env)
2082
{
2083
    /* MMU */
2084
    spr_register(env, SPR_40x_PID, "PID",
2085
                 SPR_NOACCESS, SPR_NOACCESS,
2086
                 &spr_read_generic, &spr_write_generic,
2087
                 0x00000000);
2088
    spr_register(env, SPR_40x_ZPR, "ZPR",
2089
                 SPR_NOACCESS, SPR_NOACCESS,
2090
                 &spr_read_generic, &spr_write_generic,
2091
                 0x00000000);
2092
}
2093

    
2094
/* SPR specific to PowerPC compression coprocessor extension */
2095
static void gen_spr_compress (CPUPPCState *env)
2096
{
2097
    /* XXX : not implemented */
2098
    spr_register(env, SPR_401_SKR, "SKR",
2099
                 SPR_NOACCESS, SPR_NOACCESS,
2100
                 &spr_read_generic, &spr_write_generic,
2101
                 0x00000000);
2102
}
2103

    
2104
#if defined (TARGET_PPC64)
2105
/* SPR specific to PowerPC 620 */
2106
static void gen_spr_620 (CPUPPCState *env)
2107
{
2108
    /* XXX : not implemented */
2109
    spr_register(env, SPR_620_PMR0, "PMR0",
2110
                 SPR_NOACCESS, SPR_NOACCESS,
2111
                 &spr_read_generic, &spr_write_generic,
2112
                 0x00000000);
2113
    /* XXX : not implemented */
2114
    spr_register(env, SPR_620_PMR1, "PMR1",
2115
                 SPR_NOACCESS, SPR_NOACCESS,
2116
                 &spr_read_generic, &spr_write_generic,
2117
                 0x00000000);
2118
    /* XXX : not implemented */
2119
    spr_register(env, SPR_620_PMR2, "PMR2",
2120
                 SPR_NOACCESS, SPR_NOACCESS,
2121
                 &spr_read_generic, &spr_write_generic,
2122
                 0x00000000);
2123
    /* XXX : not implemented */
2124
    spr_register(env, SPR_620_PMR3, "PMR3",
2125
                 SPR_NOACCESS, SPR_NOACCESS,
2126
                 &spr_read_generic, &spr_write_generic,
2127
                 0x00000000);
2128
    /* XXX : not implemented */
2129
    spr_register(env, SPR_620_PMR4, "PMR4",
2130
                 SPR_NOACCESS, SPR_NOACCESS,
2131
                 &spr_read_generic, &spr_write_generic,
2132
                 0x00000000);
2133
    /* XXX : not implemented */
2134
    spr_register(env, SPR_620_PMR5, "PMR5",
2135
                 SPR_NOACCESS, SPR_NOACCESS,
2136
                 &spr_read_generic, &spr_write_generic,
2137
                 0x00000000);
2138
    /* XXX : not implemented */
2139
    spr_register(env, SPR_620_PMR6, "PMR6",
2140
                 SPR_NOACCESS, SPR_NOACCESS,
2141
                 &spr_read_generic, &spr_write_generic,
2142
                 0x00000000);
2143
    /* XXX : not implemented */
2144
    spr_register(env, SPR_620_PMR7, "PMR7",
2145
                 SPR_NOACCESS, SPR_NOACCESS,
2146
                 &spr_read_generic, &spr_write_generic,
2147
                 0x00000000);
2148
    /* XXX : not implemented */
2149
    spr_register(env, SPR_620_PMR8, "PMR8",
2150
                 SPR_NOACCESS, SPR_NOACCESS,
2151
                 &spr_read_generic, &spr_write_generic,
2152
                 0x00000000);
2153
    /* XXX : not implemented */
2154
    spr_register(env, SPR_620_PMR9, "PMR9",
2155
                 SPR_NOACCESS, SPR_NOACCESS,
2156
                 &spr_read_generic, &spr_write_generic,
2157
                 0x00000000);
2158
    /* XXX : not implemented */
2159
    spr_register(env, SPR_620_PMRA, "PMR10",
2160
                 SPR_NOACCESS, SPR_NOACCESS,
2161
                 &spr_read_generic, &spr_write_generic,
2162
                 0x00000000);
2163
    /* XXX : not implemented */
2164
    spr_register(env, SPR_620_PMRB, "PMR11",
2165
                 SPR_NOACCESS, SPR_NOACCESS,
2166
                 &spr_read_generic, &spr_write_generic,
2167
                 0x00000000);
2168
    /* XXX : not implemented */
2169
    spr_register(env, SPR_620_PMRC, "PMR12",
2170
                 SPR_NOACCESS, SPR_NOACCESS,
2171
                 &spr_read_generic, &spr_write_generic,
2172
                 0x00000000);
2173
    /* XXX : not implemented */
2174
    spr_register(env, SPR_620_PMRD, "PMR13",
2175
                 SPR_NOACCESS, SPR_NOACCESS,
2176
                 &spr_read_generic, &spr_write_generic,
2177
                 0x00000000);
2178
    /* XXX : not implemented */
2179
    spr_register(env, SPR_620_PMRE, "PMR14",
2180
                 SPR_NOACCESS, SPR_NOACCESS,
2181
                 &spr_read_generic, &spr_write_generic,
2182
                 0x00000000);
2183
    /* XXX : not implemented */
2184
    spr_register(env, SPR_620_PMRF, "PMR15",
2185
                 SPR_NOACCESS, SPR_NOACCESS,
2186
                 &spr_read_generic, &spr_write_generic,
2187
                 0x00000000);
2188
    /* XXX : not implemented */
2189
    spr_register(env, SPR_620_HID8, "HID8",
2190
                 SPR_NOACCESS, SPR_NOACCESS,
2191
                 &spr_read_generic, &spr_write_generic,
2192
                 0x00000000);
2193
    /* XXX : not implemented */
2194
    spr_register(env, SPR_620_HID9, "HID9",
2195
                 SPR_NOACCESS, SPR_NOACCESS,
2196
                 &spr_read_generic, &spr_write_generic,
2197
                 0x00000000);
2198
}
2199
#endif /* defined (TARGET_PPC64) */
2200

    
2201
// XXX: TODO
2202
/*
2203
 * AMR     => SPR 29 (Power 2.04)
2204
 * CTRL    => SPR 136 (Power 2.04)
2205
 * CTRL    => SPR 152 (Power 2.04)
2206
 * SCOMC   => SPR 276 (64 bits ?)
2207
 * SCOMD   => SPR 277 (64 bits ?)
2208
 * TBU40   => SPR 286 (Power 2.04 hypv)
2209
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2210
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2211
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2212
 * HDAR    => SPR 307 (Power 2.04 hypv)
2213
 * PURR    => SPR 309 (Power 2.04 hypv)
2214
 * HDEC    => SPR 310 (Power 2.04 hypv)
2215
 * HIOR    => SPR 311 (hypv)
2216
 * RMOR    => SPR 312 (970)
2217
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2218
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2219
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2220
 * LPCR    => SPR 316 (970)
2221
 * LPIDR   => SPR 317 (970)
2222
 * SPEFSCR => SPR 512 (Power 2.04 emb)
2223
 * EPR     => SPR 702 (Power 2.04 emb)
2224
 * perf    => 768-783 (Power 2.04)
2225
 * perf    => 784-799 (Power 2.04)
2226
 * PPR     => SPR 896 (Power 2.04)
2227
 * EPLC    => SPR 947 (Power 2.04 emb)
2228
 * EPSC    => SPR 948 (Power 2.04 emb)
2229
 * DABRX   => 1015    (Power 2.04 hypv)
2230
 * FPECR   => SPR 1022 (?)
2231
 * ... and more (thermal management, performance counters, ...)
2232
 */
2233

    
2234
/*****************************************************************************/
2235
/* Exception vectors models                                                  */
2236
static void init_excp_4xx_real (CPUPPCState *env)
2237
{
2238
#if !defined(CONFIG_USER_ONLY)
2239
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2240
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2241
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2242
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2243
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2244
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2245
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2246
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2247
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2248
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2249
    env->excp_prefix = 0x00000000;
2250
    env->ivor_mask = 0x0000FFF0;
2251
    env->ivpr_mask = 0xFFFF0000;
2252
    /* Hardware reset vector */
2253
    env->hreset_vector = 0xFFFFFFFCUL;
2254
#endif
2255
}
2256

    
2257
static void init_excp_4xx_softmmu (CPUPPCState *env)
2258
{
2259
#if !defined(CONFIG_USER_ONLY)
2260
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2261
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2262
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2263
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2264
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2265
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2266
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2267
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2268
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2269
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2270
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2271
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2272
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2273
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2274
    env->excp_prefix = 0x00000000;
2275
    env->ivor_mask = 0x0000FFF0;
2276
    env->ivpr_mask = 0xFFFF0000;
2277
    /* Hardware reset vector */
2278
    env->hreset_vector = 0xFFFFFFFCUL;
2279
#endif
2280
}
2281

    
2282
static void init_excp_BookE (CPUPPCState *env)
2283
{
2284
#if !defined(CONFIG_USER_ONLY)
2285
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2286
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2287
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2288
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2289
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2290
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2291
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2292
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2293
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2294
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2295
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2296
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2297
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2298
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2299
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2300
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2301
    env->excp_prefix = 0x00000000;
2302
    env->ivor_mask = 0x0000FFE0;
2303
    env->ivpr_mask = 0xFFFF0000;
2304
    /* Hardware reset vector */
2305
    env->hreset_vector = 0xFFFFFFFCUL;
2306
#endif
2307
}
2308

    
2309
static void init_excp_601 (CPUPPCState *env)
2310
{
2311
#if !defined(CONFIG_USER_ONLY)
2312
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2313
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2314
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2315
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2316
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2317
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2318
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2319
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2320
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2321
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2322
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2323
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2324
    env->excp_prefix = 0xFFF00000;
2325
    /* Hardware reset vector */
2326
    env->hreset_vector = 0x00000100UL;
2327
#endif
2328
}
2329

    
2330
static void init_excp_602 (CPUPPCState *env)
2331
{
2332
#if !defined(CONFIG_USER_ONLY)
2333
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2334
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2335
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2336
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2337
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2338
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2339
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2340
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2341
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2342
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2343
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2344
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2345
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2346
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2347
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2348
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2349
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2350
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2351
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2352
    env->excp_prefix = 0xFFF00000;
2353
    /* Hardware reset vector */
2354
    env->hreset_vector = 0xFFFFFFFCUL;
2355
#endif
2356
}
2357

    
2358
static void init_excp_603 (CPUPPCState *env)
2359
{
2360
#if !defined(CONFIG_USER_ONLY)
2361
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2362
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2363
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2364
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2365
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2366
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2367
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2368
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2369
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2370
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2371
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2372
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2373
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2374
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2375
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2376
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2377
    /* Hardware reset vector */
2378
    env->hreset_vector = 0xFFFFFFFCUL;
2379
#endif
2380
}
2381

    
2382
static void init_excp_G2 (CPUPPCState *env)
2383
{
2384
#if !defined(CONFIG_USER_ONLY)
2385
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2386
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2387
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2388
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2389
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2390
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2391
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2392
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2393
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2394
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2395
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2396
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2397
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2398
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2399
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2400
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2401
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2402
    /* Hardware reset vector */
2403
    env->hreset_vector = 0xFFFFFFFCUL;
2404
#endif
2405
}
2406

    
2407
static void init_excp_604 (CPUPPCState *env)
2408
{
2409
#if !defined(CONFIG_USER_ONLY)
2410
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2411
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2412
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2413
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2414
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2415
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2416
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2417
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2418
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2419
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2420
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2421
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2422
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2423
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2424
    /* Hardware reset vector */
2425
    env->hreset_vector = 0xFFFFFFFCUL;
2426
#endif
2427
}
2428

    
2429
#if defined(TARGET_PPC64)
2430
static void init_excp_620 (CPUPPCState *env)
2431
{
2432
#if !defined(CONFIG_USER_ONLY)
2433
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2434
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2435
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2436
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2437
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2438
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2439
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2440
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2441
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2442
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2443
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2444
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2445
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2446
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2447
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2448
    /* Hardware reset vector */
2449
    env->hreset_vector = 0x0000000000000100ULL; /* ? */
2450
#endif
2451
}
2452
#endif /* defined(TARGET_PPC64) */
2453

    
2454
static void init_excp_7x0 (CPUPPCState *env)
2455
{
2456
#if !defined(CONFIG_USER_ONLY)
2457
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2458
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2459
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2460
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2461
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2462
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2463
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2464
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2465
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2466
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2467
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2468
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2469
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2470
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2471
    /* Hardware reset vector */
2472
    env->hreset_vector = 0xFFFFFFFCUL;
2473
#endif
2474
}
2475

    
2476
static void init_excp_750FX (CPUPPCState *env)
2477
{
2478
#if !defined(CONFIG_USER_ONLY)
2479
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2480
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2481
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2482
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2483
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2484
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2485
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2486
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2487
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2488
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2489
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2490
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2491
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2492
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2493
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2494
    /* Hardware reset vector */
2495
    env->hreset_vector = 0xFFFFFFFCUL;
2496
#endif
2497
}
2498

    
2499
/* XXX: Check if this is correct */
2500
static void init_excp_7x5 (CPUPPCState *env)
2501
{
2502
#if !defined(CONFIG_USER_ONLY)
2503
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2504
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2505
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2506
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2507
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2508
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2509
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2510
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2511
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2512
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2513
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2514
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2515
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2516
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2517
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2518
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2519
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2520
    /* Hardware reset vector */
2521
    env->hreset_vector = 0xFFFFFFFCUL;
2522
#endif
2523
}
2524

    
2525
static void init_excp_7400 (CPUPPCState *env)
2526
{
2527
#if !defined(CONFIG_USER_ONLY)
2528
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2529
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2530
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2531
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2532
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2533
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2534
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2535
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2536
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2537
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2538
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2539
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2540
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2541
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2542
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2543
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2544
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2545
    /* Hardware reset vector */
2546
    env->hreset_vector = 0xFFFFFFFCUL;
2547
#endif
2548
}
2549

    
2550
static void init_excp_7450 (CPUPPCState *env)
2551
{
2552
#if !defined(CONFIG_USER_ONLY)
2553
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2554
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2555
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2556
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2557
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2558
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2559
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2560
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2561
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2562
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2563
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2564
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2565
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2566
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2567
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2568
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2569
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2570
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2571
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2572
    /* Hardware reset vector */
2573
    env->hreset_vector = 0xFFFFFFFCUL;
2574
#endif
2575
}
2576

    
2577
#if defined (TARGET_PPC64)
2578
static void init_excp_970 (CPUPPCState *env)
2579
{
2580
#if !defined(CONFIG_USER_ONLY)
2581
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2582
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2583
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2584
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2585
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2586
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2587
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2588
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2589
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2590
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2591
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2592
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2593
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2594
#endif
2595
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2596
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2597
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2598
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2599
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2600
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2601
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2602
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2603
    /* Hardware reset vector */
2604
    env->hreset_vector = 0x0000000000000100ULL;
2605
#endif
2606
}
2607
#endif
2608

    
2609
/*****************************************************************************/
2610
/* Power management enable checks                                            */
2611
static int check_pow_none (CPUPPCState *env)
2612
{
2613
    return 0;
2614
}
2615

    
2616
static int check_pow_nocheck (CPUPPCState *env)
2617
{
2618
    return 1;
2619
}
2620

    
2621
static int check_pow_hid0 (CPUPPCState *env)
2622
{
2623
    if (env->spr[SPR_HID0] & 0x00E00000)
2624
        return 1;
2625

    
2626
    return 0;
2627
}
2628

    
2629
/*****************************************************************************/
2630
/* PowerPC implementations definitions                                       */
2631

    
2632
/* PowerPC 40x instruction set                                               */
2633
#define POWERPC_INSNS_EMB    (PPC_INSNS_BASE | PPC_CACHE_DCBZ | PPC_EMB_COMMON)
2634

    
2635
/* PowerPC 401                                                               */
2636
#define POWERPC_INSNS_401    (POWERPC_INSNS_EMB |                             \
2637
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2638
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2639
#define POWERPC_MSRM_401     (0x00000000000FD201ULL)
2640
#define POWERPC_MMU_401      (POWERPC_MMU_REAL_4xx)
2641
#define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
2642
#define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
2643
#define POWERPC_BFDM_401     (bfd_mach_ppc_403)
2644
#define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2645
#define check_pow_401        check_pow_nocheck
2646

    
2647
static void init_proc_401 (CPUPPCState *env)
2648
{
2649
    gen_spr_40x(env);
2650
    gen_spr_401_403(env);
2651
    gen_spr_401(env);
2652
    init_excp_4xx_real(env);
2653
    env->dcache_line_size = 32;
2654
    env->icache_line_size = 32;
2655
    /* Allocate hardware IRQ controller */
2656
    ppc40x_irq_init(env);
2657
}
2658

    
2659
/* PowerPC 401x2                                                             */
2660
#define POWERPC_INSNS_401x2  (POWERPC_INSNS_EMB |                             \
2661
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2662
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2663
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2664
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2665
#define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
2666
#define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
2667
#define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
2668
#define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
2669
#define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
2670
#define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2671
#define check_pow_401x2      check_pow_nocheck
2672

    
2673
static void init_proc_401x2 (CPUPPCState *env)
2674
{
2675
    gen_spr_40x(env);
2676
    gen_spr_401_403(env);
2677
    gen_spr_401x2(env);
2678
    gen_spr_compress(env);
2679
    /* Memory management */
2680
#if !defined(CONFIG_USER_ONLY)
2681
    env->nb_tlb = 64;
2682
    env->nb_ways = 1;
2683
    env->id_tlbs = 0;
2684
#endif
2685
    init_excp_4xx_softmmu(env);
2686
    env->dcache_line_size = 32;
2687
    env->icache_line_size = 32;
2688
    /* Allocate hardware IRQ controller */
2689
    ppc40x_irq_init(env);
2690
}
2691

    
2692
/* PowerPC 401x3                                                             */
2693
#define POWERPC_INSNS_401x3  (POWERPC_INSNS_EMB |                             \
2694
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2695
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2696
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2697
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2698
#define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
2699
#define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
2700
#define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
2701
#define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
2702
#define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
2703
#define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2704
#define check_pow_401x3      check_pow_nocheck
2705

    
2706
__attribute__ (( unused ))
2707
static void init_proc_401x3 (CPUPPCState *env)
2708
{
2709
    gen_spr_40x(env);
2710
    gen_spr_401_403(env);
2711
    gen_spr_401(env);
2712
    gen_spr_401x2(env);
2713
    gen_spr_compress(env);
2714
    init_excp_4xx_softmmu(env);
2715
    env->dcache_line_size = 32;
2716
    env->icache_line_size = 32;
2717
    /* Allocate hardware IRQ controller */
2718
    ppc40x_irq_init(env);
2719
}
2720

    
2721
/* IOP480                                                                    */
2722
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB |                             \
2723
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2724
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2725
                              PPC_CACHE_DCBA |                                \
2726
                              PPC_4xx_COMMON | PPC_40x_EXCP |  PPC_40x_ICBT)
2727
#define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
2728
#define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
2729
#define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
2730
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2731
#define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
2732
#define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2733
#define check_pow_IOP480     check_pow_nocheck
2734

    
2735
static void init_proc_IOP480 (CPUPPCState *env)
2736
{
2737
    gen_spr_40x(env);
2738
    gen_spr_401_403(env);
2739
    gen_spr_401x2(env);
2740
    gen_spr_compress(env);
2741
    /* Memory management */
2742
#if !defined(CONFIG_USER_ONLY)
2743
    env->nb_tlb = 64;
2744
    env->nb_ways = 1;
2745
    env->id_tlbs = 0;
2746
#endif
2747
    init_excp_4xx_softmmu(env);
2748
    env->dcache_line_size = 32;
2749
    env->icache_line_size = 32;
2750
    /* Allocate hardware IRQ controller */
2751
    ppc40x_irq_init(env);
2752
}
2753

    
2754
/* PowerPC 403                                                               */
2755
#define POWERPC_INSNS_403    (POWERPC_INSNS_EMB |                             \
2756
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2757
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2758
#define POWERPC_MSRM_403     (0x000000000007D00DULL)
2759
#define POWERPC_MMU_403      (POWERPC_MMU_REAL_4xx)
2760
#define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
2761
#define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
2762
#define POWERPC_BFDM_403     (bfd_mach_ppc_403)
2763
#define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2764
#define check_pow_403        check_pow_nocheck
2765

    
2766
static void init_proc_403 (CPUPPCState *env)
2767
{
2768
    gen_spr_40x(env);
2769
    gen_spr_401_403(env);
2770
    gen_spr_403(env);
2771
    gen_spr_403_real(env);
2772
    init_excp_4xx_real(env);
2773
    env->dcache_line_size = 32;
2774
    env->icache_line_size = 32;
2775
    /* Allocate hardware IRQ controller */
2776
    ppc40x_irq_init(env);
2777
#if !defined(CONFIG_USER_ONLY)
2778
    /* Hardware reset vector */
2779
    env->hreset_vector = 0xFFFFFFFCUL;
2780
#endif
2781
}
2782

    
2783
/* PowerPC 403 GCX                                                           */
2784
#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB |                             \
2785
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2786
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2787
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2788
#define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
2789
#define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
2790
#define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
2791
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2792
#define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
2793
#define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2794
#define check_pow_403GCX     check_pow_nocheck
2795

    
2796
static void init_proc_403GCX (CPUPPCState *env)
2797
{
2798
    gen_spr_40x(env);
2799
    gen_spr_401_403(env);
2800
    gen_spr_403(env);
2801
    gen_spr_403_real(env);
2802
    gen_spr_403_mmu(env);
2803
    /* Bus access control */
2804
    /* not emulated, as Qemu never does speculative access */
2805
    spr_register(env, SPR_40x_SGR, "SGR",
2806
                 SPR_NOACCESS, SPR_NOACCESS,
2807
                 &spr_read_generic, &spr_write_generic,
2808
                 0xFFFFFFFF);
2809
    /* not emulated, as Qemu do not emulate caches */
2810
    spr_register(env, SPR_40x_DCWR, "DCWR",
2811
                 SPR_NOACCESS, SPR_NOACCESS,
2812
                 &spr_read_generic, &spr_write_generic,
2813
                 0x00000000);
2814
    /* Memory management */
2815
#if !defined(CONFIG_USER_ONLY)
2816
    env->nb_tlb = 64;
2817
    env->nb_ways = 1;
2818
    env->id_tlbs = 0;
2819
#endif
2820
    init_excp_4xx_softmmu(env);
2821
    env->dcache_line_size = 32;
2822
    env->icache_line_size = 32;
2823
    /* Allocate hardware IRQ controller */
2824
    ppc40x_irq_init(env);
2825
}
2826

    
2827
/* PowerPC 405                                                               */
2828
#define POWERPC_INSNS_405    (POWERPC_INSNS_EMB | PPC_MFTB |                  \
2829
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2830
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2831
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT |  \
2832
                              PPC_405_MAC)
2833
#define POWERPC_MSRM_405     (0x000000000006E630ULL)
2834
#define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
2835
#define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
2836
#define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
2837
#define POWERPC_BFDM_405     (bfd_mach_ppc_403)
2838
#define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2839
                              POWERPC_FLAG_DE)
2840
#define check_pow_405        check_pow_nocheck
2841

    
2842
static void init_proc_405 (CPUPPCState *env)
2843
{
2844
    /* Time base */
2845
    gen_tbl(env);
2846
    gen_spr_40x(env);
2847
    gen_spr_405(env);
2848
    /* Bus access control */
2849
    /* not emulated, as Qemu never does speculative access */
2850
    spr_register(env, SPR_40x_SGR, "SGR",
2851
                 SPR_NOACCESS, SPR_NOACCESS,
2852
                 &spr_read_generic, &spr_write_generic,
2853
                 0xFFFFFFFF);
2854
    /* not emulated, as Qemu do not emulate caches */
2855
    spr_register(env, SPR_40x_DCWR, "DCWR",
2856
                 SPR_NOACCESS, SPR_NOACCESS,
2857
                 &spr_read_generic, &spr_write_generic,
2858
                 0x00000000);
2859
    /* Memory management */
2860
#if !defined(CONFIG_USER_ONLY)
2861
    env->nb_tlb = 64;
2862
    env->nb_ways = 1;
2863
    env->id_tlbs = 0;
2864
#endif
2865
    init_excp_4xx_softmmu(env);
2866
    env->dcache_line_size = 32;
2867
    env->icache_line_size = 32;
2868
    /* Allocate hardware IRQ controller */
2869
    ppc40x_irq_init(env);
2870
}
2871

    
2872
/* PowerPC 440 EP                                                            */
2873
#define POWERPC_INSNS_440EP  (POWERPC_INSNS_EMB |                             \
2874
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2875
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2876
                              PPC_440_SPEC | PPC_RFMCI)
2877
#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
2878
#define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
2879
#define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
2880
#define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
2881
#define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
2882
#define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2883
                              POWERPC_FLAG_DE)
2884
#define check_pow_440EP      check_pow_nocheck
2885

    
2886
static void init_proc_440EP (CPUPPCState *env)
2887
{
2888
    /* Time base */
2889
    gen_tbl(env);
2890
    gen_spr_BookE(env);
2891
    gen_spr_440(env);
2892
    /* XXX : not implemented */
2893
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2894
                 SPR_NOACCESS, SPR_NOACCESS,
2895
                 &spr_read_generic, &spr_write_generic,
2896
                 0x00000000);
2897
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2898
                 SPR_NOACCESS, SPR_NOACCESS,
2899
                 &spr_read_generic, &spr_write_generic,
2900
                 0x00000000);
2901
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2902
                 SPR_NOACCESS, SPR_NOACCESS,
2903
                 &spr_read_generic, &spr_write_generic,
2904
                 0x00000000);
2905
    /* XXX : not implemented */
2906
    spr_register(env, SPR_440_CCR1, "CCR1",
2907
                 SPR_NOACCESS, SPR_NOACCESS,
2908
                 &spr_read_generic, &spr_write_generic,
2909
                 0x00000000);
2910
    /* Memory management */
2911
#if !defined(CONFIG_USER_ONLY)
2912
    env->nb_tlb = 64;
2913
    env->nb_ways = 1;
2914
    env->id_tlbs = 0;
2915
#endif
2916
    init_excp_BookE(env);
2917
    env->dcache_line_size = 32;
2918
    env->icache_line_size = 32;
2919
    /* XXX: TODO: allocate internal IRQ controller */
2920
}
2921

    
2922
/* PowerPC 440 GP                                                            */
2923
#define POWERPC_INSNS_440GP  (POWERPC_INSNS_EMB |                             \
2924
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2925
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2926
                              PPC_405_MAC | PPC_440_SPEC)
2927
#define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
2928
#define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
2929
#define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
2930
#define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
2931
#define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
2932
#define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2933
                              POWERPC_FLAG_DE)
2934
#define check_pow_440GP      check_pow_nocheck
2935

    
2936
static void init_proc_440GP (CPUPPCState *env)
2937
{
2938
    /* Time base */
2939
    gen_tbl(env);
2940
    gen_spr_BookE(env);
2941
    gen_spr_440(env);
2942
    /* Memory management */
2943
#if !defined(CONFIG_USER_ONLY)
2944
    env->nb_tlb = 64;
2945
    env->nb_ways = 1;
2946
    env->id_tlbs = 0;
2947
#endif
2948
    init_excp_BookE(env);
2949
    env->dcache_line_size = 32;
2950
    env->icache_line_size = 32;
2951
    /* XXX: TODO: allocate internal IRQ controller */
2952
}
2953

    
2954
/* PowerPC 440x4                                                             */
2955
#define POWERPC_INSNS_440x4  (POWERPC_INSNS_EMB |                             \
2956
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2957
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2958
                              PPC_440_SPEC)
2959
#define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
2960
#define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
2961
#define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
2962
#define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
2963
#define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
2964
#define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
2965
                              POWERPC_FLAG_DE)
2966
#define check_pow_440x4      check_pow_nocheck
2967

    
2968
__attribute__ (( unused ))
2969
static void init_proc_440x4 (CPUPPCState *env)
2970
{
2971
    /* Time base */
2972
    gen_tbl(env);
2973
    gen_spr_BookE(env);
2974
    gen_spr_440(env);
2975
    /* Memory management */
2976
#if !defined(CONFIG_USER_ONLY)
2977
    env->nb_tlb = 64;
2978
    env->nb_ways = 1;
2979
    env->id_tlbs = 0;
2980
#endif
2981
    init_excp_BookE(env);
2982
    env->dcache_line_size = 32;
2983
    env->icache_line_size = 32;
2984
    /* XXX: TODO: allocate internal IRQ controller */
2985
}
2986

    
2987
/* PowerPC 440x5                                                             */
2988
#define POWERPC_INSNS_440x5  (POWERPC_INSNS_EMB |                             \
2989
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2990
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2991
                              PPC_440_SPEC | PPC_RFMCI)
2992
#define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
2993
#define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
2994
#define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
2995
#define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
2996
#define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
2997
#define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
2998
                              POWERPC_FLAG_DE)
2999
#define check_pow_440x5      check_pow_nocheck
3000

    
3001
static void init_proc_440x5 (CPUPPCState *env)
3002
{
3003
    /* Time base */
3004
    gen_tbl(env);
3005
    gen_spr_BookE(env);
3006
    gen_spr_440(env);
3007
    /* XXX : not implemented */
3008
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3009
                 SPR_NOACCESS, SPR_NOACCESS,
3010
                 &spr_read_generic, &spr_write_generic,
3011
                 0x00000000);
3012
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3013
                 SPR_NOACCESS, SPR_NOACCESS,
3014
                 &spr_read_generic, &spr_write_generic,
3015
                 0x00000000);
3016
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3017
                 SPR_NOACCESS, SPR_NOACCESS,
3018
                 &spr_read_generic, &spr_write_generic,
3019
                 0x00000000);
3020
    /* XXX : not implemented */
3021
    spr_register(env, SPR_440_CCR1, "CCR1",
3022
                 SPR_NOACCESS, SPR_NOACCESS,
3023
                 &spr_read_generic, &spr_write_generic,
3024
                 0x00000000);
3025
    /* Memory management */
3026
#if !defined(CONFIG_USER_ONLY)
3027
    env->nb_tlb = 64;
3028
    env->nb_ways = 1;
3029
    env->id_tlbs = 0;
3030
#endif
3031
    init_excp_BookE(env);
3032
    env->dcache_line_size = 32;
3033
    env->icache_line_size = 32;
3034
    /* XXX: TODO: allocate internal IRQ controller */
3035
}
3036

    
3037
/* PowerPC 460 (guessed)                                                     */
3038
#define POWERPC_INSNS_460    (POWERPC_INSNS_EMB |                             \
3039
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3040
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
3041
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3042
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3043
#define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3044
#define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3045
#define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3046
#define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3047
#define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3048
                              POWERPC_FLAG_DE)
3049
#define check_pow_460        check_pow_nocheck
3050

    
3051
__attribute__ (( unused ))
3052
static void init_proc_460 (CPUPPCState *env)
3053
{
3054
    /* Time base */
3055
    gen_tbl(env);
3056
    gen_spr_BookE(env);
3057
    gen_spr_440(env);
3058
    /* XXX : not implemented */
3059
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3060
                 SPR_NOACCESS, SPR_NOACCESS,
3061
                 &spr_read_generic, &spr_write_generic,
3062
                 0x00000000);
3063
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3064
                 SPR_NOACCESS, SPR_NOACCESS,
3065
                 &spr_read_generic, &spr_write_generic,
3066
                 0x00000000);
3067
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3068
                 SPR_NOACCESS, SPR_NOACCESS,
3069
                 &spr_read_generic, &spr_write_generic,
3070
                 0x00000000);
3071
    /* XXX : not implemented */
3072
    spr_register(env, SPR_440_CCR1, "CCR1",
3073
                 SPR_NOACCESS, SPR_NOACCESS,
3074
                 &spr_read_generic, &spr_write_generic,
3075
                 0x00000000);
3076
    /* XXX : not implemented */
3077
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3078
                 &spr_read_generic, &spr_write_generic,
3079
                 &spr_read_generic, &spr_write_generic,
3080
                 0x00000000);
3081
    /* Memory management */
3082
#if !defined(CONFIG_USER_ONLY)
3083
    env->nb_tlb = 64;
3084
    env->nb_ways = 1;
3085
    env->id_tlbs = 0;
3086
#endif
3087
    init_excp_BookE(env);
3088
    env->dcache_line_size = 32;
3089
    env->icache_line_size = 32;
3090
    /* XXX: TODO: allocate internal IRQ controller */
3091
}
3092

    
3093
/* PowerPC 460F (guessed)                                                    */
3094
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
3095
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
3096
                              PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES |  \
3097
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |            \
3098
                              PPC_FLOAT_STFIWX |                              \
3099
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
3100
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3101
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3102
#define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3103
#define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3104
#define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3105
#define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3106
#define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3107
                              POWERPC_FLAG_DE)
3108
#define check_pow_460F       check_pow_nocheck
3109

    
3110
__attribute__ (( unused ))
3111
static void init_proc_460F (CPUPPCState *env)
3112
{
3113
    /* Time base */
3114
    gen_tbl(env);
3115
    gen_spr_BookE(env);
3116
    gen_spr_440(env);
3117
    /* XXX : not implemented */
3118
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3119
                 SPR_NOACCESS, SPR_NOACCESS,
3120
                 &spr_read_generic, &spr_write_generic,
3121
                 0x00000000);
3122
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3123
                 SPR_NOACCESS, SPR_NOACCESS,
3124
                 &spr_read_generic, &spr_write_generic,
3125
                 0x00000000);
3126
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3127
                 SPR_NOACCESS, SPR_NOACCESS,
3128
                 &spr_read_generic, &spr_write_generic,
3129
                 0x00000000);
3130
    /* XXX : not implemented */
3131
    spr_register(env, SPR_440_CCR1, "CCR1",
3132
                 SPR_NOACCESS, SPR_NOACCESS,
3133
                 &spr_read_generic, &spr_write_generic,
3134
                 0x00000000);
3135
    /* XXX : not implemented */
3136
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3137
                 &spr_read_generic, &spr_write_generic,
3138
                 &spr_read_generic, &spr_write_generic,
3139
                 0x00000000);
3140
    /* Memory management */
3141
#if !defined(CONFIG_USER_ONLY)
3142
    env->nb_tlb = 64;
3143
    env->nb_ways = 1;
3144
    env->id_tlbs = 0;
3145
#endif
3146
    init_excp_BookE(env);
3147
    env->dcache_line_size = 32;
3148
    env->icache_line_size = 32;
3149
    /* XXX: TODO: allocate internal IRQ controller */
3150
}
3151

    
3152
/* Generic BookE PowerPC                                                     */
3153
#define POWERPC_INSNS_BookE  (POWERPC_INSNS_EMB |                             \
3154
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3155
                              PPC_CACHE_DCBA |                                \
3156
                              PPC_FLOAT | PPC_FLOAT_FSQRT |                   \
3157
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3158
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIW |              \
3159
                              PPC_BOOKE)
3160
#define POWERPC_MSRM_BookE   (0x000000000006D630ULL)
3161
#define POWERPC_MMU_BookE    (POWERPC_MMU_BOOKE)
3162
#define POWERPC_EXCP_BookE   (POWERPC_EXCP_BOOKE)
3163
#define POWERPC_INPUT_BookE  (PPC_FLAGS_INPUT_BookE)
3164
#define POWERPC_BFDM_BookE   (bfd_mach_ppc_403)
3165
#define POWERPC_FLAG_BookE   (POWERPC_FLAG_NONE)
3166
#define check_pow_BookE      check_pow_nocheck
3167

    
3168
__attribute__ (( unused ))
3169
static void init_proc_BookE (CPUPPCState *env)
3170
{
3171
    init_excp_BookE(env);
3172
    env->dcache_line_size = 32;
3173
    env->icache_line_size = 32;
3174
}
3175

    
3176
/* e200 core                                                                 */
3177

    
3178
/* e300 core                                                                 */
3179

    
3180
/* e500 core                                                                 */
3181
#define POWERPC_INSNS_e500   (POWERPC_INSNS_EMB |                             \
3182
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
3183
                              PPC_CACHE_DCBA |                                \
3184
                              PPC_BOOKE | PPC_E500_VECTOR)
3185
#define POWERPC_MMU_e500     (POWERPC_MMU_SOFT_4xx)
3186
#define POWERPC_EXCP_e500    (POWERPC_EXCP_40x)
3187
#define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
3188
#define POWERPC_BFDM_e500    (bfd_mach_ppc_403)
3189
#define POWERPC_FLAG_e500    (POWERPC_FLAG_SPE)
3190
#define check_pow_e500       check_pow_hid0
3191

    
3192
__attribute__ (( unused ))
3193
static void init_proc_e500 (CPUPPCState *env)
3194
{
3195
    /* Time base */
3196
    gen_tbl(env);
3197
    gen_spr_BookE(env);
3198
    /* Memory management */
3199
    gen_spr_BookE_FSL(env);
3200
#if !defined(CONFIG_USER_ONLY)
3201
    env->nb_tlb = 64;
3202
    env->nb_ways = 1;
3203
    env->id_tlbs = 0;
3204
#endif
3205
    init_excp_BookE(env);
3206
    env->dcache_line_size = 32;
3207
    env->icache_line_size = 32;
3208
    /* XXX: TODO: allocate internal IRQ controller */
3209
}
3210

    
3211
/* e600 core                                                                 */
3212

    
3213
/* Non-embedded PowerPC                                                      */
3214
/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC                    */
3215
#define POWERPC_INSNS_6xx    (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |     \
3216
                              PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3217
/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602      */
3218
#define POWERPC_INSNS_WORKS  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |           \
3219
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3220
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3221
                              PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB |   \
3222
                              PPC_SEGMENT)
3223

    
3224
/* POWER : same as 601, without mfmsr, mfsr                                  */
3225
#if defined(TODO)
3226
#define POWERPC_INSNS_POWER  (XXX_TODO)
3227
/* POWER RSC (from RAD6000) */
3228
#define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
3229
#endif /* TODO */
3230

    
3231
/* PowerPC 601                                                               */
3232
#define POWERPC_INSNS_601    (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ |            \
3233
                              PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3234
#define POWERPC_MSRM_601     (0x000000000000FD70ULL)
3235
#define POWERPC_MMU_601      (POWERPC_MMU_32B)
3236
//#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
3237
#define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
3238
#define POWERPC_BFDM_601     (bfd_mach_ppc_601)
3239
#define POWERPC_FLAG_601     (POWERPC_FLAG_SE)
3240
#define check_pow_601        check_pow_none
3241

    
3242
static void init_proc_601 (CPUPPCState *env)
3243
{
3244
    gen_spr_ne_601(env);
3245
    gen_spr_601(env);
3246
    /* Hardware implementation registers */
3247
    /* XXX : not implemented */
3248
    spr_register(env, SPR_HID0, "HID0",
3249
                 SPR_NOACCESS, SPR_NOACCESS,
3250
                 &spr_read_generic, &spr_write_generic,
3251
                 0x00000000);
3252
    /* XXX : not implemented */
3253
    spr_register(env, SPR_HID1, "HID1",
3254
                 SPR_NOACCESS, SPR_NOACCESS,
3255
                 &spr_read_generic, &spr_write_generic,
3256
                 0x00000000);
3257
    /* XXX : not implemented */
3258
    spr_register(env, SPR_601_HID2, "HID2",
3259
                 SPR_NOACCESS, SPR_NOACCESS,
3260
                 &spr_read_generic, &spr_write_generic,
3261
                 0x00000000);
3262
    /* XXX : not implemented */
3263
    spr_register(env, SPR_601_HID5, "HID5",
3264
                 SPR_NOACCESS, SPR_NOACCESS,
3265
                 &spr_read_generic, &spr_write_generic,
3266
                 0x00000000);
3267
    /* XXX : not implemented */
3268
    spr_register(env, SPR_601_HID15, "HID15",
3269
                 SPR_NOACCESS, SPR_NOACCESS,
3270
                 &spr_read_generic, &spr_write_generic,
3271
                 0x00000000);
3272
    /* Memory management */
3273
#if !defined(CONFIG_USER_ONLY)
3274
    env->nb_tlb = 64;
3275
    env->nb_ways = 2;
3276
    env->id_tlbs = 0;
3277
#endif
3278
    init_excp_601(env);
3279
    env->dcache_line_size = 64;
3280
    env->icache_line_size = 64;
3281
    /* XXX: TODO: allocate internal IRQ controller */
3282
}
3283

    
3284
/* PowerPC 602                                                               */
3285
#define POWERPC_INSNS_602    (POWERPC_INSNS_6xx | PPC_MFTB |                  \
3286
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3287
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3288
                              PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3289
                              PPC_SEGMENT | PPC_602_SPEC)
3290
#define POWERPC_MSRM_602     (0x000000000033FF73ULL)
3291
#define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
3292
//#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
3293
#define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
3294
#define POWERPC_BFDM_602     (bfd_mach_ppc_602)
3295
#define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3296
                              POWERPC_FLAG_BE)
3297
#define check_pow_602        check_pow_hid0
3298

    
3299
static void init_proc_602 (CPUPPCState *env)
3300
{
3301
    gen_spr_ne_601(env);
3302
    gen_spr_602(env);
3303
    /* Time base */
3304
    gen_tbl(env);
3305
    /* hardware implementation registers */
3306
    /* XXX : not implemented */
3307
    spr_register(env, SPR_HID0, "HID0",
3308
                 SPR_NOACCESS, SPR_NOACCESS,
3309
                 &spr_read_generic, &spr_write_generic,
3310
                 0x00000000);
3311
    /* XXX : not implemented */
3312
    spr_register(env, SPR_HID1, "HID1",
3313
                 SPR_NOACCESS, SPR_NOACCESS,
3314
                 &spr_read_generic, &spr_write_generic,
3315
                 0x00000000);
3316
    /* Memory management */
3317
    gen_low_BATs(env);
3318
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3319
    init_excp_602(env);
3320
    env->dcache_line_size = 32;
3321
    env->icache_line_size = 32;
3322
    /* Allocate hardware IRQ controller */
3323
    ppc6xx_irq_init(env);
3324
}
3325

    
3326
/* PowerPC 603                                                               */
3327
#define POWERPC_INSNS_603    (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3328
#define POWERPC_MSRM_603     (0x000000000007FF73ULL)
3329
#define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
3330
//#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
3331
#define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
3332
#define POWERPC_BFDM_603     (bfd_mach_ppc_603)
3333
#define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3334
                              POWERPC_FLAG_BE)
3335
#define check_pow_603        check_pow_hid0
3336

    
3337
static void init_proc_603 (CPUPPCState *env)
3338
{
3339
    gen_spr_ne_601(env);
3340
    gen_spr_603(env);
3341
    /* Time base */
3342
    gen_tbl(env);
3343
    /* hardware implementation registers */
3344
    /* XXX : not implemented */
3345
    spr_register(env, SPR_HID0, "HID0",
3346
                 SPR_NOACCESS, SPR_NOACCESS,
3347
                 &spr_read_generic, &spr_write_generic,
3348
                 0x00000000);
3349
    /* XXX : not implemented */
3350
    spr_register(env, SPR_HID1, "HID1",
3351
                 SPR_NOACCESS, SPR_NOACCESS,
3352
                 &spr_read_generic, &spr_write_generic,
3353
                 0x00000000);
3354
    /* Memory management */
3355
    gen_low_BATs(env);
3356
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3357
    init_excp_603(env);
3358
    env->dcache_line_size = 32;
3359
    env->icache_line_size = 32;
3360
    /* Allocate hardware IRQ controller */
3361
    ppc6xx_irq_init(env);
3362
}
3363

    
3364
/* PowerPC 603e                                                              */
3365
#define POWERPC_INSNS_603E   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3366
#define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
3367
#define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
3368
//#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
3369
#define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
3370
#define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
3371
#define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3372
                              POWERPC_FLAG_BE)
3373
#define check_pow_603E       check_pow_hid0
3374

    
3375
static void init_proc_603E (CPUPPCState *env)
3376
{
3377
    gen_spr_ne_601(env);
3378
    gen_spr_603(env);
3379
    /* Time base */
3380
    gen_tbl(env);
3381
    /* hardware implementation registers */
3382
    /* XXX : not implemented */
3383
    spr_register(env, SPR_HID0, "HID0",
3384
                 SPR_NOACCESS, SPR_NOACCESS,
3385
                 &spr_read_generic, &spr_write_generic,
3386
                 0x00000000);
3387
    /* XXX : not implemented */
3388
    spr_register(env, SPR_HID1, "HID1",
3389
                 SPR_NOACCESS, SPR_NOACCESS,
3390
                 &spr_read_generic, &spr_write_generic,
3391
                 0x00000000);
3392
    /* XXX : not implemented */
3393
    spr_register(env, SPR_IABR, "IABR",
3394
                 SPR_NOACCESS, SPR_NOACCESS,
3395
                 &spr_read_generic, &spr_write_generic,
3396
                 0x00000000);
3397
    /* Memory management */
3398
    gen_low_BATs(env);
3399
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3400
    init_excp_603(env);
3401
    env->dcache_line_size = 32;
3402
    env->icache_line_size = 32;
3403
    /* Allocate hardware IRQ controller */
3404
    ppc6xx_irq_init(env);
3405
}
3406

    
3407
/* PowerPC G2                                                                */
3408
#define POWERPC_INSNS_G2     (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3409
#define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3410
#define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3411
//#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3412
#define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3413
#define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3414
#define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3415
                              POWERPC_FLAG_BE)
3416
#define check_pow_G2         check_pow_hid0
3417

    
3418
static void init_proc_G2 (CPUPPCState *env)
3419
{
3420
    gen_spr_ne_601(env);
3421
    gen_spr_G2_755(env);
3422
    gen_spr_G2(env);
3423
    /* Time base */
3424
    gen_tbl(env);
3425
    /* Hardware implementation register */
3426
    /* XXX : not implemented */
3427
    spr_register(env, SPR_HID0, "HID0",
3428
                 SPR_NOACCESS, SPR_NOACCESS,
3429
                 &spr_read_generic, &spr_write_generic,
3430
                 0x00000000);
3431
    /* XXX : not implemented */
3432
    spr_register(env, SPR_HID1, "HID1",
3433
                 SPR_NOACCESS, SPR_NOACCESS,
3434
                 &spr_read_generic, &spr_write_generic,
3435
                 0x00000000);
3436
    /* XXX : not implemented */
3437
    spr_register(env, SPR_HID2, "HID2",
3438
                 SPR_NOACCESS, SPR_NOACCESS,
3439
                 &spr_read_generic, &spr_write_generic,
3440
                 0x00000000);
3441
    /* Memory management */
3442
    gen_low_BATs(env);
3443
    gen_high_BATs(env);
3444
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3445
    init_excp_G2(env);
3446
    env->dcache_line_size = 32;
3447
    env->icache_line_size = 32;
3448
    /* Allocate hardware IRQ controller */
3449
    ppc6xx_irq_init(env);
3450
}
3451

    
3452
/* PowerPC G2LE                                                              */
3453
#define POWERPC_INSNS_G2LE   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3454
#define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3455
#define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3456
#define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3457
#define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3458
#define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3459
#define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3460
                              POWERPC_FLAG_BE)
3461
#define check_pow_G2LE       check_pow_hid0
3462

    
3463
static void init_proc_G2LE (CPUPPCState *env)
3464
{
3465
    gen_spr_ne_601(env);
3466
    gen_spr_G2_755(env);
3467
    gen_spr_G2(env);
3468
    /* Time base */
3469
    gen_tbl(env);
3470
    /* Hardware implementation register */
3471
    /* XXX : not implemented */
3472
    spr_register(env, SPR_HID0, "HID0",
3473
                 SPR_NOACCESS, SPR_NOACCESS,
3474
                 &spr_read_generic, &spr_write_generic,
3475
                 0x00000000);
3476
    /* XXX : not implemented */
3477
    spr_register(env, SPR_HID1, "HID1",
3478
                 SPR_NOACCESS, SPR_NOACCESS,
3479
                 &spr_read_generic, &spr_write_generic,
3480
                 0x00000000);
3481
    /* XXX : not implemented */
3482
    spr_register(env, SPR_HID2, "HID2",
3483
                 SPR_NOACCESS, SPR_NOACCESS,
3484
                 &spr_read_generic, &spr_write_generic,
3485
                 0x00000000);
3486
    /* Memory management */
3487
    gen_low_BATs(env);
3488
    gen_high_BATs(env);
3489
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3490
    init_excp_G2(env);
3491
    env->dcache_line_size = 32;
3492
    env->icache_line_size = 32;
3493
    /* Allocate hardware IRQ controller */
3494
    ppc6xx_irq_init(env);
3495
}
3496

    
3497
/* PowerPC 604                                                               */
3498
#define POWERPC_INSNS_604    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3499
#define POWERPC_MSRM_604     (0x000000000005FF77ULL)
3500
#define POWERPC_MMU_604      (POWERPC_MMU_32B)
3501
//#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
3502
#define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
3503
#define POWERPC_BFDM_604     (bfd_mach_ppc_604)
3504
#define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3505
                              POWERPC_FLAG_PMM)
3506
#define check_pow_604        check_pow_nocheck
3507

    
3508
static void init_proc_604 (CPUPPCState *env)
3509
{
3510
    gen_spr_ne_601(env);
3511
    gen_spr_604(env);
3512
    /* Time base */
3513
    gen_tbl(env);
3514
    /* Hardware implementation registers */
3515
    /* XXX : not implemented */
3516
    spr_register(env, SPR_HID0, "HID0",
3517
                 SPR_NOACCESS, SPR_NOACCESS,
3518
                 &spr_read_generic, &spr_write_generic,
3519
                 0x00000000);
3520
    /* XXX : not implemented */
3521
    spr_register(env, SPR_HID1, "HID1",
3522
                 SPR_NOACCESS, SPR_NOACCESS,
3523
                 &spr_read_generic, &spr_write_generic,
3524
                 0x00000000);
3525
    /* Memory management */
3526
    gen_low_BATs(env);
3527
    init_excp_604(env);
3528
    env->dcache_line_size = 32;
3529
    env->icache_line_size = 32;
3530
    /* Allocate hardware IRQ controller */
3531
    ppc6xx_irq_init(env);
3532
}
3533

    
3534
/* PowerPC 740/750 (aka G3)                                                  */
3535
#define POWERPC_INSNS_7x0    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3536
#define POWERPC_MSRM_7x0     (0x000000000005FF77ULL)
3537
#define POWERPC_MMU_7x0      (POWERPC_MMU_32B)
3538
//#define POWERPC_EXCP_7x0     (POWERPC_EXCP_7x0)
3539
#define POWERPC_INPUT_7x0    (PPC_FLAGS_INPUT_6xx)
3540
#define POWERPC_BFDM_7x0     (bfd_mach_ppc_750)
3541
#define POWERPC_FLAG_7x0     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3542
                              POWERPC_FLAG_PMM)
3543
#define check_pow_7x0        check_pow_hid0
3544

    
3545
static void init_proc_7x0 (CPUPPCState *env)
3546
{
3547
    gen_spr_ne_601(env);
3548
    gen_spr_7xx(env);
3549
    /* Time base */
3550
    gen_tbl(env);
3551
    /* Thermal management */
3552
    gen_spr_thrm(env);
3553
    /* Hardware implementation registers */
3554
    /* XXX : not implemented */
3555
    spr_register(env, SPR_HID0, "HID0",
3556
                 SPR_NOACCESS, SPR_NOACCESS,
3557
                 &spr_read_generic, &spr_write_generic,
3558
                 0x00000000);
3559
    /* XXX : not implemented */
3560
    spr_register(env, SPR_HID1, "HID1",
3561
                 SPR_NOACCESS, SPR_NOACCESS,
3562
                 &spr_read_generic, &spr_write_generic,
3563
                 0x00000000);
3564
    /* Memory management */
3565
    gen_low_BATs(env);
3566
    init_excp_7x0(env);
3567
    env->dcache_line_size = 32;
3568
    env->icache_line_size = 32;
3569
    /* Allocate hardware IRQ controller */
3570
    ppc6xx_irq_init(env);
3571
}
3572

    
3573
/* PowerPC 750FX/GX                                                          */
3574
#define POWERPC_INSNS_750fx  (POWERPC_INSNS_WORKS | PPC_EXTERN)
3575
#define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
3576
#define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
3577
#define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
3578
#define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
3579
#define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
3580
#define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3581
                              POWERPC_FLAG_PMM)
3582
#define check_pow_750fx      check_pow_hid0
3583

    
3584
static void init_proc_750fx (CPUPPCState *env)
3585
{
3586
    gen_spr_ne_601(env);
3587
    gen_spr_7xx(env);
3588
    /* Time base */
3589
    gen_tbl(env);
3590
    /* Thermal management */
3591
    gen_spr_thrm(env);
3592
    /* Hardware implementation registers */
3593
    /* XXX : not implemented */
3594
    spr_register(env, SPR_HID0, "HID0",
3595
                 SPR_NOACCESS, SPR_NOACCESS,
3596
                 &spr_read_generic, &spr_write_generic,
3597
                 0x00000000);
3598
    /* XXX : not implemented */
3599
    spr_register(env, SPR_HID1, "HID1",
3600
                 SPR_NOACCESS, SPR_NOACCESS,
3601
                 &spr_read_generic, &spr_write_generic,
3602
                 0x00000000);
3603
    /* XXX : not implemented */
3604
    spr_register(env, SPR_750_HID2, "HID2",
3605
                 SPR_NOACCESS, SPR_NOACCESS,
3606
                 &spr_read_generic, &spr_write_generic,
3607
                 0x00000000);
3608
    /* Memory management */
3609
    gen_low_BATs(env);
3610
    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3611
    gen_high_BATs(env);
3612
    init_excp_750FX(env);
3613
    env->dcache_line_size = 32;
3614
    env->icache_line_size = 32;
3615
    /* Allocate hardware IRQ controller */
3616
    ppc6xx_irq_init(env);
3617
}
3618

    
3619
/* PowerPC 745/755                                                           */
3620
#define POWERPC_INSNS_7x5    (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3621
#define POWERPC_MSRM_7x5     (0x000000000005FF77ULL)
3622
#define POWERPC_MMU_7x5      (POWERPC_MMU_SOFT_6xx)
3623
//#define POWERPC_EXCP_7x5     (POWERPC_EXCP_7x5)
3624
#define POWERPC_INPUT_7x5    (PPC_FLAGS_INPUT_6xx)
3625
#define POWERPC_BFDM_7x5     (bfd_mach_ppc_750)
3626
#define POWERPC_FLAG_7x5     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3627
                              POWERPC_FLAG_PMM)
3628
#define check_pow_7x5        check_pow_hid0
3629

    
3630
static void init_proc_7x5 (CPUPPCState *env)
3631
{
3632
    gen_spr_ne_601(env);
3633
    gen_spr_G2_755(env);
3634
    /* Time base */
3635
    gen_tbl(env);
3636
    /* L2 cache control */
3637
    /* XXX : not implemented */
3638
    spr_register(env, SPR_ICTC, "ICTC",
3639
                 SPR_NOACCESS, SPR_NOACCESS,
3640
                 &spr_read_generic, &spr_write_generic,
3641
                 0x00000000);
3642
    /* XXX : not implemented */
3643
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3644
                 SPR_NOACCESS, SPR_NOACCESS,
3645
                 &spr_read_generic, &spr_write_generic,
3646
                 0x00000000);
3647
    /* Hardware implementation registers */
3648
    /* XXX : not implemented */
3649
    spr_register(env, SPR_HID0, "HID0",
3650
                 SPR_NOACCESS, SPR_NOACCESS,
3651
                 &spr_read_generic, &spr_write_generic,
3652
                 0x00000000);
3653
    /* XXX : not implemented */
3654
    spr_register(env, SPR_HID1, "HID1",
3655
                 SPR_NOACCESS, SPR_NOACCESS,
3656
                 &spr_read_generic, &spr_write_generic,
3657
                 0x00000000);
3658
    /* XXX : not implemented */
3659
    spr_register(env, SPR_HID2, "HID2",
3660
                 SPR_NOACCESS, SPR_NOACCESS,
3661
                 &spr_read_generic, &spr_write_generic,
3662
                 0x00000000);
3663
    /* Memory management */
3664
    gen_low_BATs(env);
3665
    gen_high_BATs(env);
3666
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3667
    init_excp_7x5(env);
3668
    env->dcache_line_size = 32;
3669
    env->icache_line_size = 32;
3670
    /* Allocate hardware IRQ controller */
3671
    ppc6xx_irq_init(env);
3672
#if !defined(CONFIG_USER_ONLY)
3673
    /* Hardware reset vector */
3674
    env->hreset_vector = 0xFFFFFFFCUL;
3675
#endif
3676
}
3677

    
3678
/* PowerPC 7400 (aka G4)                                                     */
3679
#define POWERPC_INSNS_7400   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3680
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3681
                              PPC_ALTIVEC)
3682
#define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
3683
#define POWERPC_MMU_7400     (POWERPC_MMU_32B)
3684
#define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
3685
#define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
3686
#define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
3687
#define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3688
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3689
#define check_pow_7400       check_pow_hid0
3690

    
3691
static void init_proc_7400 (CPUPPCState *env)
3692
{
3693
    gen_spr_ne_601(env);
3694
    gen_spr_7xx(env);
3695
    /* Time base */
3696
    gen_tbl(env);
3697
    /* 74xx specific SPR */
3698
    gen_spr_74xx(env);
3699
    /* Thermal management */
3700
    gen_spr_thrm(env);
3701
    /* Memory management */
3702
    gen_low_BATs(env);
3703
    init_excp_7400(env);
3704
    env->dcache_line_size = 32;
3705
    env->icache_line_size = 32;
3706
    /* Allocate hardware IRQ controller */
3707
    ppc6xx_irq_init(env);
3708
}
3709

    
3710
/* PowerPC 7410 (aka G4)                                                     */
3711
#define POWERPC_INSNS_7410   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3712
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3713
                              PPC_ALTIVEC)
3714
#define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
3715
#define POWERPC_MMU_7410     (POWERPC_MMU_32B)
3716
#define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
3717
#define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
3718
#define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
3719
#define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3720
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3721
#define check_pow_7410       check_pow_hid0
3722

    
3723
static void init_proc_7410 (CPUPPCState *env)
3724
{
3725
    gen_spr_ne_601(env);
3726
    gen_spr_7xx(env);
3727
    /* Time base */
3728
    gen_tbl(env);
3729
    /* 74xx specific SPR */
3730
    gen_spr_74xx(env);
3731
    /* Thermal management */
3732
    gen_spr_thrm(env);
3733
    /* L2PMCR */
3734
    /* XXX : not implemented */
3735
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3736
                 SPR_NOACCESS, SPR_NOACCESS,
3737
                 &spr_read_generic, &spr_write_generic,
3738
                 0x00000000);
3739
    /* LDSTDB */
3740
    /* XXX : not implemented */
3741
    spr_register(env, SPR_LDSTDB, "LDSTDB",
3742
                 SPR_NOACCESS, SPR_NOACCESS,
3743
                 &spr_read_generic, &spr_write_generic,
3744
                 0x00000000);
3745
    /* Memory management */
3746
    gen_low_BATs(env);
3747
    init_excp_7400(env);
3748
    env->dcache_line_size = 32;
3749
    env->icache_line_size = 32;
3750
    /* Allocate hardware IRQ controller */
3751
    ppc6xx_irq_init(env);
3752
}
3753

    
3754
/* PowerPC 7440 (aka G4)                                                     */
3755
#define POWERPC_INSNS_7440   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3756
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3757
                              PPC_ALTIVEC)
3758
#define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
3759
#define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
3760
#define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
3761
#define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
3762
#define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
3763
#define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3764
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3765
#define check_pow_7440       check_pow_hid0
3766

    
3767
__attribute__ (( unused ))
3768
static void init_proc_7440 (CPUPPCState *env)
3769
{
3770
    gen_spr_ne_601(env);
3771
    gen_spr_7xx(env);
3772
    /* Time base */
3773
    gen_tbl(env);
3774
    /* 74xx specific SPR */
3775
    gen_spr_74xx(env);
3776
    /* LDSTCR */
3777
    /* XXX : not implemented */
3778
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3779
                 SPR_NOACCESS, SPR_NOACCESS,
3780
                 &spr_read_generic, &spr_write_generic,
3781
                 0x00000000);
3782
    /* ICTRL */
3783
    /* XXX : not implemented */
3784
    spr_register(env, SPR_ICTRL, "ICTRL",
3785
                 SPR_NOACCESS, SPR_NOACCESS,
3786
                 &spr_read_generic, &spr_write_generic,
3787
                 0x00000000);
3788
    /* MSSSR0 */
3789
    /* XXX : not implemented */
3790
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3791
                 SPR_NOACCESS, SPR_NOACCESS,
3792
                 &spr_read_generic, &spr_write_generic,
3793
                 0x00000000);
3794
    /* PMC */
3795
    /* XXX : not implemented */
3796
    spr_register(env, SPR_PMC5, "PMC5",
3797
                 SPR_NOACCESS, SPR_NOACCESS,
3798
                 &spr_read_generic, &spr_write_generic,
3799
                 0x00000000);
3800
    /* XXX : not implemented */
3801
    spr_register(env, SPR_UPMC5, "UPMC5",
3802
                 &spr_read_ureg, SPR_NOACCESS,
3803
                 &spr_read_ureg, SPR_NOACCESS,
3804
                 0x00000000);
3805
    /* XXX : not implemented */
3806
    spr_register(env, SPR_PMC6, "PMC6",
3807
                 SPR_NOACCESS, SPR_NOACCESS,
3808
                 &spr_read_generic, &spr_write_generic,
3809
                 0x00000000);
3810
    /* XXX : not implemented */
3811
    spr_register(env, SPR_UPMC6, "UPMC6",
3812
                 &spr_read_ureg, SPR_NOACCESS,
3813
                 &spr_read_ureg, SPR_NOACCESS,
3814
                 0x00000000);
3815
    /* Memory management */
3816
    gen_low_BATs(env);
3817
    gen_74xx_soft_tlb(env, 128, 2);
3818
    init_excp_7450(env);
3819
    env->dcache_line_size = 32;
3820
    env->icache_line_size = 32;
3821
    /* Allocate hardware IRQ controller */
3822
    ppc6xx_irq_init(env);
3823
}
3824

    
3825
/* PowerPC 7450 (aka G4)                                                     */
3826
#define POWERPC_INSNS_7450   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3827
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3828
                              PPC_ALTIVEC)
3829
#define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
3830
#define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
3831
#define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
3832
#define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
3833
#define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
3834
#define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3835
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3836
#define check_pow_7450       check_pow_hid0
3837

    
3838
__attribute__ (( unused ))
3839
static void init_proc_7450 (CPUPPCState *env)
3840
{
3841
    gen_spr_ne_601(env);
3842
    gen_spr_7xx(env);
3843
    /* Time base */
3844
    gen_tbl(env);
3845
    /* 74xx specific SPR */
3846
    gen_spr_74xx(env);
3847
    /* Level 3 cache control */
3848
    gen_l3_ctrl(env);
3849
    /* LDSTCR */
3850
    /* XXX : not implemented */
3851
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3852
                 SPR_NOACCESS, SPR_NOACCESS,
3853
                 &spr_read_generic, &spr_write_generic,
3854
                 0x00000000);
3855
    /* ICTRL */
3856
    /* XXX : not implemented */
3857
    spr_register(env, SPR_ICTRL, "ICTRL",
3858
                 SPR_NOACCESS, SPR_NOACCESS,
3859
                 &spr_read_generic, &spr_write_generic,
3860
                 0x00000000);
3861
    /* MSSSR0 */
3862
    /* XXX : not implemented */
3863
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3864
                 SPR_NOACCESS, SPR_NOACCESS,
3865
                 &spr_read_generic, &spr_write_generic,
3866
                 0x00000000);
3867
    /* PMC */
3868
    /* XXX : not implemented */
3869
    spr_register(env, SPR_PMC5, "PMC5",
3870
                 SPR_NOACCESS, SPR_NOACCESS,
3871
                 &spr_read_generic, &spr_write_generic,
3872
                 0x00000000);
3873
    /* XXX : not implemented */
3874
    spr_register(env, SPR_UPMC5, "UPMC5",
3875
                 &spr_read_ureg, SPR_NOACCESS,
3876
                 &spr_read_ureg, SPR_NOACCESS,
3877
                 0x00000000);
3878
    /* XXX : not implemented */
3879
    spr_register(env, SPR_PMC6, "PMC6",
3880
                 SPR_NOACCESS, SPR_NOACCESS,
3881
                 &spr_read_generic, &spr_write_generic,
3882
                 0x00000000);
3883
    /* XXX : not implemented */
3884
    spr_register(env, SPR_UPMC6, "UPMC6",
3885
                 &spr_read_ureg, SPR_NOACCESS,
3886
                 &spr_read_ureg, SPR_NOACCESS,
3887
                 0x00000000);
3888
    /* Memory management */
3889
    gen_low_BATs(env);
3890
    gen_74xx_soft_tlb(env, 128, 2);
3891
    init_excp_7450(env);
3892
    env->dcache_line_size = 32;
3893
    env->icache_line_size = 32;
3894
    /* Allocate hardware IRQ controller */
3895
    ppc6xx_irq_init(env);
3896
}
3897

    
3898
/* PowerPC 7445 (aka G4)                                                     */
3899
#define POWERPC_INSNS_7445   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3900
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3901
                              PPC_ALTIVEC)
3902
#define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
3903
#define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
3904
#define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
3905
#define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
3906
#define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
3907
#define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
3908
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3909
#define check_pow_7445       check_pow_hid0
3910

    
3911
__attribute__ (( unused ))
3912
static void init_proc_7445 (CPUPPCState *env)
3913
{
3914
    gen_spr_ne_601(env);
3915
    gen_spr_7xx(env);
3916
    /* Time base */
3917
    gen_tbl(env);
3918
    /* 74xx specific SPR */
3919
    gen_spr_74xx(env);
3920
    /* LDSTCR */
3921
    /* XXX : not implemented */
3922
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3923
                 SPR_NOACCESS, SPR_NOACCESS,
3924
                 &spr_read_generic, &spr_write_generic,
3925
                 0x00000000);
3926
    /* ICTRL */
3927
    /* XXX : not implemented */
3928
    spr_register(env, SPR_ICTRL, "ICTRL",
3929
                 SPR_NOACCESS, SPR_NOACCESS,
3930
                 &spr_read_generic, &spr_write_generic,
3931
                 0x00000000);
3932
    /* MSSSR0 */
3933
    /* XXX : not implemented */
3934
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3935
                 SPR_NOACCESS, SPR_NOACCESS,
3936
                 &spr_read_generic, &spr_write_generic,
3937
                 0x00000000);
3938
    /* PMC */
3939
    /* XXX : not implemented */
3940
    spr_register(env, SPR_PMC5, "PMC5",
3941
                 SPR_NOACCESS, SPR_NOACCESS,
3942
                 &spr_read_generic, &spr_write_generic,
3943
                 0x00000000);
3944
    /* XXX : not implemented */
3945
    spr_register(env, SPR_UPMC5, "UPMC5",
3946
                 &spr_read_ureg, SPR_NOACCESS,
3947
                 &spr_read_ureg, SPR_NOACCESS,
3948
                 0x00000000);
3949
    /* XXX : not implemented */
3950
    spr_register(env, SPR_PMC6, "PMC6",
3951
                 SPR_NOACCESS, SPR_NOACCESS,
3952
                 &spr_read_generic, &spr_write_generic,
3953
                 0x00000000);
3954
    /* XXX : not implemented */
3955
    spr_register(env, SPR_UPMC6, "UPMC6",
3956
                 &spr_read_ureg, SPR_NOACCESS,
3957
                 &spr_read_ureg, SPR_NOACCESS,
3958
                 0x00000000);
3959
    /* SPRGs */
3960
    spr_register(env, SPR_SPRG4, "SPRG4",
3961
                 SPR_NOACCESS, SPR_NOACCESS,
3962
                 &spr_read_generic, &spr_write_generic,
3963
                 0x00000000);
3964
    spr_register(env, SPR_USPRG4, "USPRG4",
3965
                 &spr_read_ureg, SPR_NOACCESS,
3966
                 &spr_read_ureg, SPR_NOACCESS,
3967
                 0x00000000);
3968
    spr_register(env, SPR_SPRG5, "SPRG5",
3969
                 SPR_NOACCESS, SPR_NOACCESS,
3970
                 &spr_read_generic, &spr_write_generic,
3971
                 0x00000000);
3972
    spr_register(env, SPR_USPRG5, "USPRG5",
3973
                 &spr_read_ureg, SPR_NOACCESS,
3974
                 &spr_read_ureg, SPR_NOACCESS,
3975
                 0x00000000);
3976
    spr_register(env, SPR_SPRG6, "SPRG6",
3977
                 SPR_NOACCESS, SPR_NOACCESS,
3978
                 &spr_read_generic, &spr_write_generic,
3979
                 0x00000000);
3980
    spr_register(env, SPR_USPRG6, "USPRG6",
3981
                 &spr_read_ureg, SPR_NOACCESS,
3982
                 &spr_read_ureg, SPR_NOACCESS,
3983
                 0x00000000);
3984
    spr_register(env, SPR_SPRG7, "SPRG7",
3985
                 SPR_NOACCESS, SPR_NOACCESS,
3986
                 &spr_read_generic, &spr_write_generic,
3987
                 0x00000000);
3988
    spr_register(env, SPR_USPRG7, "USPRG7",
3989
                 &spr_read_ureg, SPR_NOACCESS,
3990
                 &spr_read_ureg, SPR_NOACCESS,
3991
                 0x00000000);
3992
    /* Memory management */
3993
    gen_low_BATs(env);
3994
    gen_high_BATs(env);
3995
    gen_74xx_soft_tlb(env, 128, 2);
3996
    init_excp_7450(env);
3997
    env->dcache_line_size = 32;
3998
    env->icache_line_size = 32;
3999
    /* Allocate hardware IRQ controller */
4000
    ppc6xx_irq_init(env);
4001
}
4002

    
4003
/* PowerPC 7455 (aka G4)                                                     */
4004
#define POWERPC_INSNS_7455   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
4005
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
4006
                              PPC_ALTIVEC)
4007
#define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
4008
#define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
4009
#define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
4010
#define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
4011
#define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
4012
#define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4013
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4014
#define check_pow_7455       check_pow_hid0
4015

    
4016
__attribute__ (( unused ))
4017
static void init_proc_7455 (CPUPPCState *env)
4018
{
4019
    gen_spr_ne_601(env);
4020
    gen_spr_7xx(env);
4021
    /* Time base */
4022
    gen_tbl(env);
4023
    /* 74xx specific SPR */
4024
    gen_spr_74xx(env);
4025
    /* Level 3 cache control */
4026
    gen_l3_ctrl(env);
4027
    /* LDSTCR */
4028
    /* XXX : not implemented */
4029
    spr_register(env, SPR_LDSTCR, "LDSTCR",
4030
                 SPR_NOACCESS, SPR_NOACCESS,
4031
                 &spr_read_generic, &spr_write_generic,
4032
                 0x00000000);
4033
    /* ICTRL */
4034
    /* XXX : not implemented */
4035
    spr_register(env, SPR_ICTRL, "ICTRL",
4036
                 SPR_NOACCESS, SPR_NOACCESS,
4037
                 &spr_read_generic, &spr_write_generic,
4038
                 0x00000000);
4039
    /* MSSSR0 */
4040
    /* XXX : not implemented */
4041
    spr_register(env, SPR_MSSSR0, "MSSSR0",
4042
                 SPR_NOACCESS, SPR_NOACCESS,
4043
                 &spr_read_generic, &spr_write_generic,
4044
                 0x00000000);
4045
    /* PMC */
4046
    /* XXX : not implemented */
4047
    spr_register(env, SPR_PMC5, "PMC5",
4048
                 SPR_NOACCESS, SPR_NOACCESS,
4049
                 &spr_read_generic, &spr_write_generic,
4050
                 0x00000000);
4051
    /* XXX : not implemented */
4052
    spr_register(env, SPR_UPMC5, "UPMC5",
4053
                 &spr_read_ureg, SPR_NOACCESS,
4054
                 &spr_read_ureg, SPR_NOACCESS,
4055
                 0x00000000);
4056
    /* XXX : not implemented */
4057
    spr_register(env, SPR_PMC6, "PMC6",
4058
                 SPR_NOACCESS, SPR_NOACCESS,
4059
                 &spr_read_generic, &spr_write_generic,
4060
                 0x00000000);
4061
    /* XXX : not implemented */
4062
    spr_register(env, SPR_UPMC6, "UPMC6",
4063
                 &spr_read_ureg, SPR_NOACCESS,
4064
                 &spr_read_ureg, SPR_NOACCESS,
4065
                 0x00000000);
4066
    /* SPRGs */
4067
    spr_register(env, SPR_SPRG4, "SPRG4",
4068
                 SPR_NOACCESS, SPR_NOACCESS,
4069
                 &spr_read_generic, &spr_write_generic,
4070
                 0x00000000);
4071
    spr_register(env, SPR_USPRG4, "USPRG4",
4072
                 &spr_read_ureg, SPR_NOACCESS,
4073
                 &spr_read_ureg, SPR_NOACCESS,
4074
                 0x00000000);
4075
    spr_register(env, SPR_SPRG5, "SPRG5",
4076
                 SPR_NOACCESS, SPR_NOACCESS,
4077
                 &spr_read_generic, &spr_write_generic,
4078
                 0x00000000);
4079
    spr_register(env, SPR_USPRG5, "USPRG5",
4080
                 &spr_read_ureg, SPR_NOACCESS,
4081
                 &spr_read_ureg, SPR_NOACCESS,
4082
                 0x00000000);
4083
    spr_register(env, SPR_SPRG6, "SPRG6",
4084
                 SPR_NOACCESS, SPR_NOACCESS,
4085
                 &spr_read_generic, &spr_write_generic,
4086
                 0x00000000);
4087
    spr_register(env, SPR_USPRG6, "USPRG6",
4088
                 &spr_read_ureg, SPR_NOACCESS,
4089
                 &spr_read_ureg, SPR_NOACCESS,
4090
                 0x00000000);
4091
    spr_register(env, SPR_SPRG7, "SPRG7",
4092
                 SPR_NOACCESS, SPR_NOACCESS,
4093
                 &spr_read_generic, &spr_write_generic,
4094
                 0x00000000);
4095
    spr_register(env, SPR_USPRG7, "USPRG7",
4096
                 &spr_read_ureg, SPR_NOACCESS,
4097
                 &spr_read_ureg, SPR_NOACCESS,
4098
                 0x00000000);
4099
    /* Memory management */
4100
    gen_low_BATs(env);
4101
    gen_high_BATs(env);
4102
    gen_74xx_soft_tlb(env, 128, 2);
4103
    init_excp_7450(env);
4104
    env->dcache_line_size = 32;
4105
    env->icache_line_size = 32;
4106
    /* Allocate hardware IRQ controller */
4107
    ppc6xx_irq_init(env);
4108
}
4109

    
4110
#if defined (TARGET_PPC64)
4111
#define POWERPC_INSNS_WORK64  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |          \
4112
                               PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |           \
4113
                               PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |            \
4114
                               PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4115
/* PowerPC 970                                                               */
4116
#define POWERPC_INSNS_970    (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4117
                              PPC_64B | PPC_ALTIVEC |                         \
4118
                              PPC_SEGMENT_64B | PPC_SLBI)
4119
#define POWERPC_MSRM_970     (0x900000000204FF36ULL)
4120
#define POWERPC_MMU_970      (POWERPC_MMU_64B)
4121
//#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
4122
#define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
4123
#define POWERPC_BFDM_970     (bfd_mach_ppc64)
4124
#define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4125
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4126

    
4127
#if defined(CONFIG_USER_ONLY)
4128
#define POWERPC970_HID5_INIT 0x00000080
4129
#else
4130
#define POWERPC970_HID5_INIT 0x00000000
4131
#endif
4132

    
4133
static int check_pow_970 (CPUPPCState *env)
4134
{
4135
    if (env->spr[SPR_HID0] & 0x00600000)
4136
        return 1;
4137

    
4138
    return 0;
4139
}
4140

    
4141
static void init_proc_970 (CPUPPCState *env)
4142
{
4143
    gen_spr_ne_601(env);
4144
    gen_spr_7xx(env);
4145
    /* Time base */
4146
    gen_tbl(env);
4147
    /* Hardware implementation registers */
4148
    /* XXX : not implemented */
4149
    spr_register(env, SPR_HID0, "HID0",
4150
                 SPR_NOACCESS, SPR_NOACCESS,
4151
                 &spr_read_generic, &spr_write_clear,
4152
                 0x60000000);
4153
    /* XXX : not implemented */
4154
    spr_register(env, SPR_HID1, "HID1",
4155
                 SPR_NOACCESS, SPR_NOACCESS,
4156
                 &spr_read_generic, &spr_write_generic,
4157
                 0x00000000);
4158
    /* XXX : not implemented */
4159
    spr_register(env, SPR_750_HID2, "HID2",
4160
                 SPR_NOACCESS, SPR_NOACCESS,
4161
                 &spr_read_generic, &spr_write_generic,
4162
                 0x00000000);
4163
    /* XXX : not implemented */
4164
    spr_register(env, SPR_970_HID5, "HID5",
4165
                 SPR_NOACCESS, SPR_NOACCESS,
4166
                 &spr_read_generic, &spr_write_generic,
4167
                 POWERPC970_HID5_INIT);
4168
    /* Memory management */
4169
    /* XXX: not correct */
4170
    gen_low_BATs(env);
4171
    /* XXX : not implemented */
4172
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4173
                 SPR_NOACCESS, SPR_NOACCESS,
4174
                 &spr_read_generic, SPR_NOACCESS,
4175
                 0x00000000); /* TOFIX */
4176
    /* XXX : not implemented */
4177
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4178
                 SPR_NOACCESS, SPR_NOACCESS,
4179
                 &spr_read_generic, &spr_write_generic,
4180
                 0x00000000); /* TOFIX */
4181
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4182
                 SPR_NOACCESS, SPR_NOACCESS,
4183
                 &spr_read_generic, &spr_write_generic,
4184
                 0xFFF00000); /* XXX: This is a hack */
4185
#if !defined(CONFIG_USER_ONLY)
4186
    env->excp_prefix = 0xFFF00000;
4187
#endif
4188
#if !defined(CONFIG_USER_ONLY)
4189
    env->slb_nr = 32;
4190
#endif
4191
    init_excp_970(env);
4192
    env->dcache_line_size = 128;
4193
    env->icache_line_size = 128;
4194
    /* Allocate hardware IRQ controller */
4195
    ppc970_irq_init(env);
4196
}
4197

    
4198
/* PowerPC 970FX (aka G5)                                                    */
4199
#define POWERPC_INSNS_970FX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4200
                              PPC_64B | PPC_ALTIVEC |                         \
4201
                              PPC_SEGMENT_64B | PPC_SLBI)
4202
#define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
4203
#define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
4204
#define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
4205
#define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
4206
#define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
4207
#define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4208
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4209

    
4210
static int check_pow_970FX (CPUPPCState *env)
4211
{
4212
    if (env->spr[SPR_HID0] & 0x00600000)
4213
        return 1;
4214

    
4215
    return 0;
4216
}
4217

    
4218
static void init_proc_970FX (CPUPPCState *env)
4219
{
4220
    gen_spr_ne_601(env);
4221
    gen_spr_7xx(env);
4222
    /* Time base */
4223
    gen_tbl(env);
4224
    /* Hardware implementation registers */
4225
    /* XXX : not implemented */
4226
    spr_register(env, SPR_HID0, "HID0",
4227
                 SPR_NOACCESS, SPR_NOACCESS,
4228
                 &spr_read_generic, &spr_write_clear,
4229
                 0x60000000);
4230
    /* XXX : not implemented */
4231
    spr_register(env, SPR_HID1, "HID1",
4232
                 SPR_NOACCESS, SPR_NOACCESS,
4233
                 &spr_read_generic, &spr_write_generic,
4234
                 0x00000000);
4235
    /* XXX : not implemented */
4236
    spr_register(env, SPR_750_HID2, "HID2",
4237
                 SPR_NOACCESS, SPR_NOACCESS,
4238
                 &spr_read_generic, &spr_write_generic,
4239
                 0x00000000);
4240
    /* XXX : not implemented */
4241
    spr_register(env, SPR_970_HID5, "HID5",
4242
                 SPR_NOACCESS, SPR_NOACCESS,
4243
                 &spr_read_generic, &spr_write_generic,
4244
                 POWERPC970_HID5_INIT);
4245
    /* Memory management */
4246
    /* XXX: not correct */
4247
    gen_low_BATs(env);
4248
    /* XXX : not implemented */
4249
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4250
                 SPR_NOACCESS, SPR_NOACCESS,
4251
                 &spr_read_generic, SPR_NOACCESS,
4252
                 0x00000000); /* TOFIX */
4253
    /* XXX : not implemented */
4254
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4255
                 SPR_NOACCESS, SPR_NOACCESS,
4256
                 &spr_read_generic, &spr_write_generic,
4257
                 0x00000000); /* TOFIX */
4258
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4259
                 SPR_NOACCESS, SPR_NOACCESS,
4260
                 &spr_read_generic, &spr_write_generic,
4261
                 0xFFF00000); /* XXX: This is a hack */
4262
#if !defined(CONFIG_USER_ONLY)
4263
    env->excp_prefix = 0xFFF00000;
4264
#endif
4265
#if !defined(CONFIG_USER_ONLY)
4266
    env->slb_nr = 32;
4267
#endif
4268
    init_excp_970(env);
4269
    env->dcache_line_size = 128;
4270
    env->icache_line_size = 128;
4271
    /* Allocate hardware IRQ controller */
4272
    ppc970_irq_init(env);
4273
}
4274

    
4275
/* PowerPC 970 GX                                                            */
4276
#define POWERPC_INSNS_970GX  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4277
                              PPC_64B | PPC_ALTIVEC |                         \
4278
                              PPC_SEGMENT_64B | PPC_SLBI)
4279
#define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
4280
#define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
4281
#define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
4282
#define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
4283
#define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
4284
#define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4285
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4286

    
4287
static int check_pow_970GX (CPUPPCState *env)
4288
{
4289
    if (env->spr[SPR_HID0] & 0x00600000)
4290
        return 1;
4291

    
4292
    return 0;
4293
}
4294

    
4295
static void init_proc_970GX (CPUPPCState *env)
4296
{
4297
    gen_spr_ne_601(env);
4298
    gen_spr_7xx(env);
4299
    /* Time base */
4300
    gen_tbl(env);
4301
    /* Hardware implementation registers */
4302
    /* XXX : not implemented */
4303
    spr_register(env, SPR_HID0, "HID0",
4304
                 SPR_NOACCESS, SPR_NOACCESS,
4305
                 &spr_read_generic, &spr_write_clear,
4306
                 0x60000000);
4307
    /* XXX : not implemented */
4308
    spr_register(env, SPR_HID1, "HID1",
4309
                 SPR_NOACCESS, SPR_NOACCESS,
4310
                 &spr_read_generic, &spr_write_generic,
4311
                 0x00000000);
4312
    /* XXX : not implemented */
4313
    spr_register(env, SPR_750_HID2, "HID2",
4314
                 SPR_NOACCESS, SPR_NOACCESS,
4315
                 &spr_read_generic, &spr_write_generic,
4316
                 0x00000000);
4317
    /* XXX : not implemented */
4318
    spr_register(env, SPR_970_HID5, "HID5",
4319
                 SPR_NOACCESS, SPR_NOACCESS,
4320
                 &spr_read_generic, &spr_write_generic,
4321
                 POWERPC970_HID5_INIT);
4322
    /* Memory management */
4323
    /* XXX: not correct */
4324
    gen_low_BATs(env);
4325
    /* XXX : not implemented */
4326
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4327
                 SPR_NOACCESS, SPR_NOACCESS,
4328
                 &spr_read_generic, SPR_NOACCESS,
4329
                 0x00000000); /* TOFIX */
4330
    /* XXX : not implemented */
4331
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4332
                 SPR_NOACCESS, SPR_NOACCESS,
4333
                 &spr_read_generic, &spr_write_generic,
4334
                 0x00000000); /* TOFIX */
4335
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4336
                 SPR_NOACCESS, SPR_NOACCESS,
4337
                 &spr_read_generic, &spr_write_generic,
4338
                 0xFFF00000); /* XXX: This is a hack */
4339
#if !defined(CONFIG_USER_ONLY)
4340
    env->excp_prefix = 0xFFF00000;
4341
#endif
4342
#if !defined(CONFIG_USER_ONLY)
4343
    env->slb_nr = 32;
4344
#endif
4345
    init_excp_970(env);
4346
    env->dcache_line_size = 128;
4347
    env->icache_line_size = 128;
4348
    /* Allocate hardware IRQ controller */
4349
    ppc970_irq_init(env);
4350
}
4351

    
4352
/* PowerPC 970 MP                                                            */
4353
#define POWERPC_INSNS_970MP  (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT |        \
4354
                              PPC_64B | PPC_ALTIVEC |                         \
4355
                              PPC_SEGMENT_64B | PPC_SLBI)
4356
#define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
4357
#define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
4358
#define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
4359
#define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
4360
#define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
4361
#define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
4362
                              POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4363

    
4364
static int check_pow_970MP (CPUPPCState *env)
4365
{
4366
    if (env->spr[SPR_HID0] & 0x01C00000)
4367
        return 1;
4368

    
4369
    return 0;
4370
}
4371

    
4372
static void init_proc_970MP (CPUPPCState *env)
4373
{
4374
    gen_spr_ne_601(env);
4375
    gen_spr_7xx(env);
4376
    /* Time base */
4377
    gen_tbl(env);
4378
    /* Hardware implementation registers */
4379
    /* XXX : not implemented */
4380
    spr_register(env, SPR_HID0, "HID0",
4381
                 SPR_NOACCESS, SPR_NOACCESS,
4382
                 &spr_read_generic, &spr_write_clear,
4383
                 0x60000000);
4384
    /* XXX : not implemented */
4385
    spr_register(env, SPR_HID1, "HID1",
4386
                 SPR_NOACCESS, SPR_NOACCESS,
4387
                 &spr_read_generic, &spr_write_generic,
4388
                 0x00000000);
4389
    /* XXX : not implemented */
4390
    spr_register(env, SPR_750_HID2, "HID2",
4391
                 SPR_NOACCESS, SPR_NOACCESS,
4392
                 &spr_read_generic, &spr_write_generic,
4393
                 0x00000000);
4394
    /* XXX : not implemented */
4395
    spr_register(env, SPR_970_HID5, "HID5",
4396
                 SPR_NOACCESS, SPR_NOACCESS,
4397
                 &spr_read_generic, &spr_write_generic,
4398
                 POWERPC970_HID5_INIT);
4399
    /* Memory management */
4400
    /* XXX: not correct */
4401
    gen_low_BATs(env);
4402
    /* XXX : not implemented */
4403
    spr_register(env, SPR_MMUCFG, "MMUCFG",
4404
                 SPR_NOACCESS, SPR_NOACCESS,
4405
                 &spr_read_generic, SPR_NOACCESS,
4406
                 0x00000000); /* TOFIX */
4407
    /* XXX : not implemented */
4408
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4409
                 SPR_NOACCESS, SPR_NOACCESS,
4410
                 &spr_read_generic, &spr_write_generic,
4411
                 0x00000000); /* TOFIX */
4412
    spr_register(env, SPR_HIOR, "SPR_HIOR",
4413
                 SPR_NOACCESS, SPR_NOACCESS,
4414
                 &spr_read_generic, &spr_write_generic,
4415
                 0xFFF00000); /* XXX: This is a hack */
4416
#if !defined(CONFIG_USER_ONLY)
4417
    env->excp_prefix = 0xFFF00000;
4418
#endif
4419
#if !defined(CONFIG_USER_ONLY)
4420
    env->slb_nr = 32;
4421
#endif
4422
    init_excp_970(env);
4423
    env->dcache_line_size = 128;
4424
    env->icache_line_size = 128;
4425
    /* Allocate hardware IRQ controller */
4426
    ppc970_irq_init(env);
4427
}
4428

    
4429
/* PowerPC 620                                                               */
4430
#define POWERPC_INSNS_620    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
4431
                              PPC_64B | PPC_SLBI)
4432
#define POWERPC_MSRM_620     (0x800000000005FF73ULL)
4433
#define POWERPC_MMU_620      (POWERPC_MMU_64B)
4434
#define POWERPC_EXCP_620     (POWERPC_EXCP_970)
4435
#define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_970)
4436
#define POWERPC_BFDM_620     (bfd_mach_ppc64)
4437
#define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
4438
#define check_pow_620        check_pow_nocheck /* Check this */
4439

    
4440
__attribute__ (( unused ))
4441
static void init_proc_620 (CPUPPCState *env)
4442
{
4443
    gen_spr_ne_601(env);
4444
    gen_spr_620(env);
4445
    /* Time base */
4446
    gen_tbl(env);
4447
    /* Hardware implementation registers */
4448
    /* XXX : not implemented */
4449
    spr_register(env, SPR_HID0, "HID0",
4450
                 SPR_NOACCESS, SPR_NOACCESS,
4451
                 &spr_read_generic, &spr_write_generic,
4452
                 0x00000000);
4453
    /* Memory management */
4454
    gen_low_BATs(env);
4455
    gen_high_BATs(env);
4456
    init_excp_620(env);
4457
    env->dcache_line_size = 64;
4458
    env->icache_line_size = 64;
4459
    /* XXX: TODO: initialize internal interrupt controller */
4460
}
4461
#endif /* defined (TARGET_PPC64) */
4462

    
4463
/* Default 32 bits PowerPC target will be 604 */
4464
#define CPU_POWERPC_PPC32     CPU_POWERPC_604
4465
#define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
4466
#define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
4467
#define POWERPC_MMU_PPC32     POWERPC_MMU_604
4468
#define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
4469
#define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
4470
#define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
4471
#define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
4472
#define check_pow_PPC32       check_pow_604
4473
#define init_proc_PPC32       init_proc_604
4474

    
4475
/* Default 64 bits PowerPC target will be 970 FX */
4476
#define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
4477
#define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
4478
#define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
4479
#define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
4480
#define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
4481
#define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
4482
#define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
4483
#define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
4484
#define check_pow_PPC64       check_pow_970FX
4485
#define init_proc_PPC64       init_proc_970FX
4486

    
4487
/* Default PowerPC target will be PowerPC 32 */
4488
#if defined (TARGET_PPC64) && 0 // XXX: TODO
4489
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
4490
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4491
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
4492
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
4493
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
4494
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4495
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
4496
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
4497
#define check_pow_DEFAULT     check_pow_PPC64
4498
#define init_proc_DEFAULT     init_proc_PPC64
4499
#else
4500
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
4501
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4502
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
4503
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
4504
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
4505
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4506
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
4507
#define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
4508
#define check_pow_DEFAULT     check_pow_PPC32
4509
#define init_proc_DEFAULT     init_proc_PPC32
4510
#endif
4511

    
4512
/*****************************************************************************/
4513
/* PVR definitions for most known PowerPC                                    */
4514
enum {
4515
    /* PowerPC 401 family */
4516
    /* Generic PowerPC 401 */
4517
#define CPU_POWERPC_401       CPU_POWERPC_401G2
4518
    /* PowerPC 401 cores */
4519
    CPU_POWERPC_401A1       = 0x00210000,
4520
    CPU_POWERPC_401B2       = 0x00220000,
4521
#if 0
4522
    CPU_POWERPC_401B3       = xxx,
4523
#endif
4524
    CPU_POWERPC_401C2       = 0x00230000,
4525
    CPU_POWERPC_401D2       = 0x00240000,
4526
    CPU_POWERPC_401E2       = 0x00250000,
4527
    CPU_POWERPC_401F2       = 0x00260000,
4528
    CPU_POWERPC_401G2       = 0x00270000,
4529
    /* PowerPC 401 microcontrolers */
4530
#if 0
4531
    CPU_POWERPC_401GF       = xxx,
4532
#endif
4533
#define CPU_POWERPC_IOP480    CPU_POWERPC_401B2
4534
    /* IBM Processor for Network Resources */
4535
    CPU_POWERPC_COBRA       = 0x10100000, /* XXX: 405 ? */
4536
#if 0
4537
    CPU_POWERPC_XIPCHIP     = xxx,
4538
#endif
4539
    /* PowerPC 403 family */
4540
    /* Generic PowerPC 403 */
4541
#define CPU_POWERPC_403       CPU_POWERPC_403GC
4542
    /* PowerPC 403 microcontrollers */
4543
    CPU_POWERPC_403GA       = 0x00200011,
4544
    CPU_POWERPC_403GB       = 0x00200100,
4545
    CPU_POWERPC_403GC       = 0x00200200,
4546
    CPU_POWERPC_403GCX      = 0x00201400,
4547
#if 0
4548
    CPU_POWERPC_403GP       = xxx,
4549
#endif
4550
    /* PowerPC 405 family */
4551
    /* Generic PowerPC 405 */
4552
#define CPU_POWERPC_405       CPU_POWERPC_405D4
4553
    /* PowerPC 405 cores */
4554
#if 0
4555
    CPU_POWERPC_405A3       = xxx,
4556
#endif
4557
#if 0
4558
    CPU_POWERPC_405A4       = xxx,
4559
#endif
4560
#if 0
4561
    CPU_POWERPC_405B3       = xxx,
4562
#endif
4563
#if 0
4564
    CPU_POWERPC_405B4       = xxx,
4565
#endif
4566
#if 0
4567
    CPU_POWERPC_405C3       = xxx,
4568
#endif
4569
#if 0
4570
    CPU_POWERPC_405C4       = xxx,
4571
#endif
4572
    CPU_POWERPC_405D2       = 0x20010000,
4573
#if 0
4574
    CPU_POWERPC_405D3       = xxx,
4575
#endif
4576
    CPU_POWERPC_405D4       = 0x41810000,
4577
#if 0
4578
    CPU_POWERPC_405D5       = xxx,
4579
#endif
4580
#if 0
4581
    CPU_POWERPC_405E4       = xxx,
4582
#endif
4583
#if 0
4584
    CPU_POWERPC_405F4       = xxx,
4585
#endif
4586
#if 0
4587
    CPU_POWERPC_405F5       = xxx,
4588
#endif
4589
#if 0
4590
    CPU_POWERPC_405F6       = xxx,
4591
#endif
4592
    /* PowerPC 405 microcontrolers */
4593
    /* XXX: missing 0x200108a0 */
4594
#define CPU_POWERPC_405CR     CPU_POWERPC_405CRc
4595
    CPU_POWERPC_405CRa      = 0x40110041,
4596
    CPU_POWERPC_405CRb      = 0x401100C5,
4597
    CPU_POWERPC_405CRc      = 0x40110145,
4598
    CPU_POWERPC_405EP       = 0x51210950,
4599
#if 0
4600
    CPU_POWERPC_405EXr      = xxx,
4601
#endif
4602
    CPU_POWERPC_405EZ       = 0x41511460, /* 0x51210950 ? */
4603
#if 0
4604
    CPU_POWERPC_405FX       = xxx,
4605
#endif
4606
#define CPU_POWERPC_405GP     CPU_POWERPC_405GPd
4607
    CPU_POWERPC_405GPa      = 0x40110000,
4608
    CPU_POWERPC_405GPb      = 0x40110040,
4609
    CPU_POWERPC_405GPc      = 0x40110082,
4610
    CPU_POWERPC_405GPd      = 0x401100C4,
4611
#define CPU_POWERPC_405GPe    CPU_POWERPC_405CRc
4612
    CPU_POWERPC_405GPR      = 0x50910951,
4613
#if 0
4614
    CPU_POWERPC_405H        = xxx,
4615
#endif
4616
#if 0
4617
    CPU_POWERPC_405L        = xxx,
4618
#endif
4619
    CPU_POWERPC_405LP       = 0x41F10000,
4620
#if 0
4621
    CPU_POWERPC_405PM       = xxx,
4622
#endif
4623
#if 0
4624
    CPU_POWERPC_405PS       = xxx,
4625
#endif
4626
#if 0
4627
    CPU_POWERPC_405S        = xxx,
4628
#endif
4629
    /* IBM network processors */
4630
    CPU_POWERPC_NPE405H     = 0x414100C0,
4631
    CPU_POWERPC_NPE405H2    = 0x41410140,
4632
    CPU_POWERPC_NPE405L     = 0x416100C0,
4633
    CPU_POWERPC_NPE4GS3     = 0x40B10000,
4634
#if 0
4635
    CPU_POWERPC_NPCxx1      = xxx,
4636
#endif
4637
#if 0
4638
    CPU_POWERPC_NPR161      = xxx,
4639
#endif
4640
#if 0
4641
    CPU_POWERPC_LC77700     = xxx,
4642
#endif
4643
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4644
#if 0
4645
    CPU_POWERPC_STB01000    = xxx,
4646
#endif
4647
#if 0
4648
    CPU_POWERPC_STB01010    = xxx,
4649
#endif
4650
#if 0
4651
    CPU_POWERPC_STB0210     = xxx, /* 401B3 */
4652
#endif
4653
    CPU_POWERPC_STB03       = 0x40310000, /* 0x40130000 ? */
4654
#if 0
4655
    CPU_POWERPC_STB043      = xxx,
4656
#endif
4657
#if 0
4658
    CPU_POWERPC_STB045      = xxx,
4659
#endif
4660
    CPU_POWERPC_STB04       = 0x41810000,
4661
    CPU_POWERPC_STB25       = 0x51510950,
4662
#if 0
4663
    CPU_POWERPC_STB130      = xxx,
4664
#endif
4665
    /* Xilinx cores */
4666
    CPU_POWERPC_X2VP4       = 0x20010820,
4667
#define CPU_POWERPC_X2VP7     CPU_POWERPC_X2VP4
4668
    CPU_POWERPC_X2VP20      = 0x20010860,
4669
#define CPU_POWERPC_X2VP50    CPU_POWERPC_X2VP20
4670
#if 0
4671
    CPU_POWERPC_ZL10310     = xxx,
4672
#endif
4673
#if 0
4674
    CPU_POWERPC_ZL10311     = xxx,
4675
#endif
4676
#if 0
4677
    CPU_POWERPC_ZL10320     = xxx,
4678
#endif
4679
#if 0
4680
    CPU_POWERPC_ZL10321     = xxx,
4681
#endif
4682
    /* PowerPC 440 family */
4683
    /* Generic PowerPC 440 */
4684
#define CPU_POWERPC_440       CPU_POWERPC_440GXf
4685
    /* PowerPC 440 cores */
4686
#if 0
4687
    CPU_POWERPC_440A4       = xxx,
4688
#endif
4689
#if 0
4690
    CPU_POWERPC_440A5       = xxx,
4691
#endif
4692
#if 0
4693
    CPU_POWERPC_440B4       = xxx,
4694
#endif
4695
#if 0
4696
    CPU_POWERPC_440F5       = xxx,
4697
#endif
4698
#if 0
4699
    CPU_POWERPC_440G5       = xxx,
4700
#endif
4701
#if 0
4702
    CPU_POWERPC_440H4       = xxx,
4703
#endif
4704
#if 0
4705
    CPU_POWERPC_440H6       = xxx,
4706
#endif
4707
    /* PowerPC 440 microcontrolers */
4708
#define CPU_POWERPC_440EP     CPU_POWERPC_440EPb
4709
    CPU_POWERPC_440EPa      = 0x42221850,
4710
    CPU_POWERPC_440EPb      = 0x422218D3,
4711
#define CPU_POWERPC_440GP     CPU_POWERPC_440GPc
4712
    CPU_POWERPC_440GPb      = 0x40120440,
4713
    CPU_POWERPC_440GPc      = 0x40120481,
4714
#define CPU_POWERPC_440GR     CPU_POWERPC_440GRa
4715
#define CPU_POWERPC_440GRa    CPU_POWERPC_440EPb
4716
    CPU_POWERPC_440GRX      = 0x200008D0,
4717
#define CPU_POWERPC_440EPX    CPU_POWERPC_440GRX
4718
#define CPU_POWERPC_440GX     CPU_POWERPC_440GXf
4719
    CPU_POWERPC_440GXa      = 0x51B21850,
4720
    CPU_POWERPC_440GXb      = 0x51B21851,
4721
    CPU_POWERPC_440GXc      = 0x51B21892,
4722
    CPU_POWERPC_440GXf      = 0x51B21894,
4723
#if 0
4724
    CPU_POWERPC_440S        = xxx,
4725
#endif
4726
    CPU_POWERPC_440SP       = 0x53221850,
4727
    CPU_POWERPC_440SP2      = 0x53221891,
4728
    CPU_POWERPC_440SPE      = 0x53421890,
4729
    /* PowerPC 460 family */
4730
#if 0
4731
    /* Generic PowerPC 464 */