Revision 2f644545

b/target-mips/translate.c
5435 5435 
    env->hflags |= MIPS_HFLAG_UM;
5436 5436 
    env->user_mode_only = 1;
5437 5437 
#endif
5438 
    /* XXX some guesswork here, values are CPU specific */
5439 
    env->SYNCI_Step = 16;
5440 
    env->CCRes = 2;
5441 5438 
}
5442 5439 

  		





  5443
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#include "translate_init.c"


  		












  

    
      b/target-mips/translate_init.c
    
  






  67
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    int32_t CP0_Config3;


  		





  68
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    int32_t CP0_Config6;


  		





  69
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    int32_t CP0_Config7;


  		





  
  70
  
    
    int32_t SYNCI_Step;


  		





  
  71
  
    
    int32_t CCRes;


  		





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    int32_t CP1_fcr0;


  		





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};


  		





  72
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  ......




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        .CP0_Config1 = MIPS_CONFIG1,


  		





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        .CP0_Config2 = MIPS_CONFIG2,


  		





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        .CP0_Config3 = MIPS_CONFIG3,


  		





  
  87
  
    
        .SYNCI_Step = 32,


  		





  
  88
  
    
        .CCRes = 2,


  		





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        .CP1_fcr0 = MIPS_FCR0,


  		





  86
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    },


  		





  87
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    {


  		





  ......




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        .CP0_Config1 = MIPS_CONFIG1,


  		





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        .CP0_Config2 = MIPS_CONFIG2,


  		





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        .CP0_Config3 = MIPS_CONFIG3,


  		





  
  98
  
    
        .SYNCI_Step = 32,


  		





  
  99
  
    
        .CCRes = 2,


  		





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        .CP1_fcr0 = MIPS_FCR0,


  		





  95
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    },


  		





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    {


  		





  ......




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        .CP0_Config1 = MIPS_CONFIG1,


  		





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        .CP0_Config2 = MIPS_CONFIG2,


  		





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        .CP0_Config3 = MIPS_CONFIG3,


  		





  
  109
  
    
        .SYNCI_Step = 32,


  		





  
  110
  
    
        .CCRes = 2,


  		





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        .CP1_fcr0 = MIPS_FCR0,


  		





  104
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    },


  		





  105
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    {


  		





  ......




  109
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        .CP0_Config1 = MIPS_CONFIG1,


  		





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        .CP0_Config2 = MIPS_CONFIG2,


  		





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        .CP0_Config3 = MIPS_CONFIG3,


  		





  
  120
  
    
        .SYNCI_Step = 32,


  		





  
  121
  
    
        .CCRes = 2,


  		





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        .CP1_fcr0 = MIPS_FCR0,


  		





  113
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    },


  		





  114
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    {


  		





  ......




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        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),


  		





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        .CP0_Config2 = MIPS_CONFIG2,


  		





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        .CP0_Config3 = MIPS_CONFIG3,


  		





  
  131
  
    
        .SYNCI_Step = 32,


  		





  
  132
  
    
        .CCRes = 2,


  		





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  133
  
    
        .CP1_fcr0 = MIPS_FCR0,


  		





  122
  134
  
    
    },


  		





  123
  135
  
    
#else


  		





  ......




  128
  140
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),


  		





  129
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        .CP0_Config2 = MIPS_CONFIG2,


  		





  130
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        .CP0_Config3 = MIPS_CONFIG3,


  		





  
  143
  
    
        .SYNCI_Step = 16,


  		





  
  144
  
    
        .CCRes = 2,


  		





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        .CP1_fcr0 = MIPS_FCR0,


  		





  132
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    },


  		





  133
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#endif


  		





  ......




  175
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    env->CP0_Config3 = def->CP0_Config3;


  		





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    env->CP0_Config6 = def->CP0_Config6;


  		





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    env->CP0_Config7 = def->CP0_Config7;


  		





  
  192
  
    
    env->SYNCI_Step = def->SYNCI_Step;


  		





  
  193
  
    
    env->CCRes = def->CCRes;


  		





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    env->fcr0 = def->CP1_fcr0;


  		





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    return 0;


  		





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}


  		












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