Revision 2f937732 gdbstub.c

b/gdbstub.c
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#elif defined (TARGET_SH4)
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/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
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/* FIXME: We should use XML for this.  */
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#include "target-sh4/gdbstub.c"
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static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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{
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    switch (n) {
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    case 0 ... 7:
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        if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
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            GET_REGL(env->gregs[n + 16]);
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        } else {
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            GET_REGL(env->gregs[n]);
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        }
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    case 8 ... 15:
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        GET_REGL(env->gregs[n]);
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    case 16:
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        GET_REGL(env->pc);
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    case 17:
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        GET_REGL(env->pr);
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    case 18:
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        GET_REGL(env->gbr);
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    case 19:
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        GET_REGL(env->vbr);
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    case 20:
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        GET_REGL(env->mach);
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    case 21:
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        GET_REGL(env->macl);
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    case 22:
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        GET_REGL(env->sr);
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    case 23:
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        GET_REGL(env->fpul);
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    case 24:
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        GET_REGL(env->fpscr);
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    case 25 ... 40:
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        if (env->fpscr & FPSCR_FR) {
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            stfl_p(mem_buf, env->fregs[n - 9]);
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        } else {
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            stfl_p(mem_buf, env->fregs[n - 25]);
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        }
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        return 4;
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    case 41:
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        GET_REGL(env->ssr);
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    case 42:
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        GET_REGL(env->spc);
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    case 43 ... 50:
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        GET_REGL(env->gregs[n - 43]);
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    case 51 ... 58:
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        GET_REGL(env->gregs[n - (51 - 16)]);
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    }
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    return 0;
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}
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static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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{
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    switch (n) {
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    case 0 ... 7:
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        if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
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            env->gregs[n + 16] = ldl_p(mem_buf);
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        } else {
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            env->gregs[n] = ldl_p(mem_buf);
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        }
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        break;
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    case 8 ... 15:
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        env->gregs[n] = ldl_p(mem_buf);
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        break;
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    case 16:
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        env->pc = ldl_p(mem_buf);
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        break;
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    case 17:
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        env->pr = ldl_p(mem_buf);
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        break;
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    case 18:
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        env->gbr = ldl_p(mem_buf);
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        break;
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    case 19:
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        env->vbr = ldl_p(mem_buf);
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        break;
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    case 20:
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        env->mach = ldl_p(mem_buf);
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        break;
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    case 21:
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        env->macl = ldl_p(mem_buf);
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        break;
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    case 22:
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        env->sr = ldl_p(mem_buf);
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        break;
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    case 23:
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        env->fpul = ldl_p(mem_buf);
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        break;
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    case 24:
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        env->fpscr = ldl_p(mem_buf);
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        break;
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    case 25 ... 40:
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        if (env->fpscr & FPSCR_FR) {
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            env->fregs[n - 9] = ldfl_p(mem_buf);
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        } else {
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            env->fregs[n - 25] = ldfl_p(mem_buf);
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        }
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        break;
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    case 41:
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        env->ssr = ldl_p(mem_buf);
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        break;
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    case 42:
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        env->spc = ldl_p(mem_buf);
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        break;
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    case 43 ... 50:
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        env->gregs[n - 43] = ldl_p(mem_buf);
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        break;
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    case 51 ... 58:
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        env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
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        break;
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    default:
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        return 0;
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    }
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    return 4;
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}
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#elif defined (TARGET_MICROBLAZE)
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static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)

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