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/*
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* ARM kernel loader.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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|
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#include "config.h" |
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#include "hw/hw.h" |
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#include "hw/arm/arm.h" |
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#include "sysemu/sysemu.h" |
14 |
#include "hw/boards.h" |
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#include "hw/loader.h" |
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#include "elf.h" |
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#include "sysemu/device_tree.h" |
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#include "qemu/config-file.h" |
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|
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#define KERNEL_ARGS_ADDR 0x100 |
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#define KERNEL_LOAD_ADDR 0x00010000 |
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|
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/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
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static uint32_t bootloader[] = {
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0xe3a00000, /* mov r0, #0 */ |
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0xe59f1004, /* ldr r1, [pc, #4] */ |
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0xe59f2004, /* ldr r2, [pc, #4] */ |
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0xe59ff004, /* ldr pc, [pc, #4] */ |
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0, /* Board ID */ |
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0, /* Address of kernel args. Set by integratorcp_init. */ |
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0 /* Kernel entry point. Set by integratorcp_init. */ |
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}; |
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|
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/* Handling for secondary CPU boot in a multicore system.
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* Unlike the uniprocessor/primary CPU boot, this is platform
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* dependent. The default code here is based on the secondary
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* CPU boot protocol used on realview/vexpress boards, with
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* some parameterisation to increase its flexibility.
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* QEMU platform models for which this code is not appropriate
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* should override write_secondary_boot and secondary_cpu_reset_hook
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* instead.
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*
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* This code enables the interrupt controllers for the secondary
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* CPUs and then puts all the secondary CPUs into a loop waiting
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* for an interprocessor interrupt and polling a configurable
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* location for the kernel secondary CPU entry point.
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*/
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#define DSB_INSN 0xf57ff04f |
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#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ |
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static uint32_t smpboot[] = {
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0xe59f2028, /* ldr r2, gic_cpu_if */ |
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0xe59f0028, /* ldr r0, startaddr */ |
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0xe3a01001, /* mov r1, #1 */ |
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0xe5821000, /* str r1, [r2] - set GICC_CTLR.Enable */ |
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0xe3a010ff, /* mov r1, #0xff */ |
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0xe5821004, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ |
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DSB_INSN, /* dsb */
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0xe320f003, /* wfi */ |
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0xe5901000, /* ldr r1, [r0] */ |
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0xe1110001, /* tst r1, r1 */ |
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0x0afffffb, /* beq <wfi> */ |
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0xe12fff11, /* bx r1 */ |
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0, /* gic_cpu_if: base address of GIC CPU interface */ |
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0 /* bootreg: Boot register address is held here */ |
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}; |
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|
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static void default_write_secondary(ARMCPU *cpu, |
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const struct arm_boot_info *info) |
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{ |
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int n;
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smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
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smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
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for (n = 0; n < ARRAY_SIZE(smpboot); n++) { |
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/* Replace DSB with the pre-v7 DSB if necessary. */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V7) &&
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smpboot[n] == DSB_INSN) { |
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smpboot[n] = CP15_DSB_INSN; |
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} |
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smpboot[n] = tswap32(smpboot[n]); |
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} |
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rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), |
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info->smp_loader_start); |
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} |
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|
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static void default_reset_secondary(ARMCPU *cpu, |
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const struct arm_boot_info *info) |
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{ |
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CPUARMState *env = &cpu->env; |
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stl_phys_notdirty(info->smp_bootreg_addr, 0);
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env->regs[15] = info->smp_loader_start;
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} |
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|
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#define WRITE_WORD(p, value) do { \ |
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stl_phys_notdirty(p, value); \ |
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p += 4; \
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} while (0) |
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static void set_kernel_args(const struct arm_boot_info *info) |
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{ |
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int initrd_size = info->initrd_size;
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hwaddr base = info->loader_start; |
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hwaddr p; |
105 |
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p = base + KERNEL_ARGS_ADDR; |
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/* ATAG_CORE */
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WRITE_WORD(p, 5);
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WRITE_WORD(p, 0x54410001);
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WRITE_WORD(p, 1);
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WRITE_WORD(p, 0x1000);
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WRITE_WORD(p, 0);
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/* ATAG_MEM */
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/* TODO: handle multiple chips on one ATAG list */
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WRITE_WORD(p, 4);
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WRITE_WORD(p, 0x54410002);
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WRITE_WORD(p, info->ram_size); |
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WRITE_WORD(p, info->loader_start); |
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if (initrd_size) {
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/* ATAG_INITRD2 */
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WRITE_WORD(p, 4);
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WRITE_WORD(p, 0x54420005);
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WRITE_WORD(p, info->initrd_start); |
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WRITE_WORD(p, initrd_size); |
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} |
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if (info->kernel_cmdline && *info->kernel_cmdline) {
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/* ATAG_CMDLINE */
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int cmdline_size;
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|
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cmdline_size = strlen(info->kernel_cmdline); |
131 |
cpu_physical_memory_write(p + 8, info->kernel_cmdline,
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cmdline_size + 1);
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cmdline_size = (cmdline_size >> 2) + 1; |
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WRITE_WORD(p, cmdline_size + 2);
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WRITE_WORD(p, 0x54410009);
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p += cmdline_size * 4;
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} |
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if (info->atag_board) {
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/* ATAG_BOARD */
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int atag_board_len;
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uint8_t atag_board_buf[0x1000];
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|
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atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; |
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WRITE_WORD(p, (atag_board_len + 8) >> 2); |
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WRITE_WORD(p, 0x414f4d50);
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cpu_physical_memory_write(p, atag_board_buf, atag_board_len); |
147 |
p += atag_board_len; |
148 |
} |
149 |
/* ATAG_END */
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WRITE_WORD(p, 0);
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WRITE_WORD(p, 0);
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} |
153 |
|
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static void set_kernel_args_old(const struct arm_boot_info *info) |
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{ |
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hwaddr p; |
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const char *s; |
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int initrd_size = info->initrd_size;
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hwaddr base = info->loader_start; |
160 |
|
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/* see linux/include/asm-arm/setup.h */
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p = base + KERNEL_ARGS_ADDR; |
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/* page_size */
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WRITE_WORD(p, 4096);
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/* nr_pages */
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WRITE_WORD(p, info->ram_size / 4096);
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/* ramdisk_size */
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WRITE_WORD(p, 0);
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#define FLAG_READONLY 1 |
170 |
#define FLAG_RDLOAD 4 |
171 |
#define FLAG_RDPROMPT 8 |
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/* flags */
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WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); |
174 |
/* rootdev */
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WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ |
176 |
/* video_num_cols */
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WRITE_WORD(p, 0);
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/* video_num_rows */
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WRITE_WORD(p, 0);
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180 |
/* video_x */
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WRITE_WORD(p, 0);
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/* video_y */
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WRITE_WORD(p, 0);
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/* memc_control_reg */
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WRITE_WORD(p, 0);
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/* unsigned char sounddefault */
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/* unsigned char adfsdrives */
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/* unsigned char bytes_per_char_h */
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/* unsigned char bytes_per_char_v */
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WRITE_WORD(p, 0);
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/* pages_in_bank[4] */
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WRITE_WORD(p, 0);
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WRITE_WORD(p, 0);
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WRITE_WORD(p, 0);
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WRITE_WORD(p, 0);
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/* pages_in_vram */
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WRITE_WORD(p, 0);
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/* initrd_start */
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if (initrd_size) {
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WRITE_WORD(p, info->initrd_start); |
201 |
} else {
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WRITE_WORD(p, 0);
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} |
204 |
/* initrd_size */
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WRITE_WORD(p, initrd_size); |
206 |
/* rd_start */
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WRITE_WORD(p, 0);
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/* system_rev */
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WRITE_WORD(p, 0);
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/* system_serial_low */
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WRITE_WORD(p, 0);
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/* system_serial_high */
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WRITE_WORD(p, 0);
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/* mem_fclk_21285 */
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WRITE_WORD(p, 0);
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/* zero unused fields */
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while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { |
218 |
WRITE_WORD(p, 0);
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} |
220 |
s = info->kernel_cmdline; |
221 |
if (s) {
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cpu_physical_memory_write(p, s, strlen(s) + 1);
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} else {
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WRITE_WORD(p, 0);
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225 |
} |
226 |
} |
227 |
|
228 |
static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo) |
229 |
{ |
230 |
uint32_t *mem_reg_property; |
231 |
uint32_t mem_reg_propsize; |
232 |
void *fdt = NULL; |
233 |
char *filename;
|
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int size, rc;
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235 |
uint32_t acells, scells, hival; |
236 |
|
237 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); |
238 |
if (!filename) {
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fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
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goto fail;
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241 |
} |
242 |
|
243 |
fdt = load_device_tree(filename, &size); |
244 |
if (!fdt) {
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245 |
fprintf(stderr, "Couldn't open dtb file %s\n", filename);
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246 |
g_free(filename); |
247 |
goto fail;
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248 |
} |
249 |
g_free(filename); |
250 |
|
251 |
acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells"); |
252 |
scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells"); |
253 |
if (acells == 0 || scells == 0) { |
254 |
fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
|
255 |
goto fail;
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256 |
} |
257 |
|
258 |
mem_reg_propsize = acells + scells; |
259 |
mem_reg_property = g_new0(uint32_t, mem_reg_propsize); |
260 |
mem_reg_property[acells - 1] = cpu_to_be32(binfo->loader_start);
|
261 |
hival = cpu_to_be32(binfo->loader_start >> 32);
|
262 |
if (acells > 1) { |
263 |
mem_reg_property[acells - 2] = hival;
|
264 |
} else if (hival != 0) { |
265 |
fprintf(stderr, "qemu: dtb file not compatible with "
|
266 |
"RAM start address > 4GB\n");
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267 |
goto fail;
|
268 |
} |
269 |
mem_reg_property[acells + scells - 1] = cpu_to_be32(binfo->ram_size);
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270 |
hival = cpu_to_be32(binfo->ram_size >> 32);
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271 |
if (scells > 1) { |
272 |
mem_reg_property[acells + scells - 2] = hival;
|
273 |
} else if (hival != 0) { |
274 |
fprintf(stderr, "qemu: dtb file not compatible with "
|
275 |
"RAM size > 4GB\n");
|
276 |
goto fail;
|
277 |
} |
278 |
|
279 |
rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
280 |
mem_reg_propsize * sizeof(uint32_t));
|
281 |
if (rc < 0) { |
282 |
fprintf(stderr, "couldn't set /memory/reg\n");
|
283 |
goto fail;
|
284 |
} |
285 |
|
286 |
if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
|
287 |
rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", |
288 |
binfo->kernel_cmdline); |
289 |
if (rc < 0) { |
290 |
fprintf(stderr, "couldn't set /chosen/bootargs\n");
|
291 |
goto fail;
|
292 |
} |
293 |
} |
294 |
|
295 |
if (binfo->initrd_size) {
|
296 |
rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
297 |
binfo->initrd_start); |
298 |
if (rc < 0) { |
299 |
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
|
300 |
goto fail;
|
301 |
} |
302 |
|
303 |
rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
304 |
binfo->initrd_start + binfo->initrd_size); |
305 |
if (rc < 0) { |
306 |
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
|
307 |
goto fail;
|
308 |
} |
309 |
} |
310 |
qemu_devtree_dumpdtb(fdt, size); |
311 |
|
312 |
cpu_physical_memory_write(addr, fdt, size); |
313 |
|
314 |
g_free(fdt); |
315 |
|
316 |
return 0; |
317 |
|
318 |
fail:
|
319 |
g_free(fdt); |
320 |
return -1; |
321 |
} |
322 |
|
323 |
static void do_cpu_reset(void *opaque) |
324 |
{ |
325 |
ARMCPU *cpu = opaque; |
326 |
CPUARMState *env = &cpu->env; |
327 |
const struct arm_boot_info *info = env->boot_info; |
328 |
|
329 |
cpu_reset(CPU(cpu)); |
330 |
if (info) {
|
331 |
if (!info->is_linux) {
|
332 |
/* Jump to the entry point. */
|
333 |
env->regs[15] = info->entry & 0xfffffffe; |
334 |
env->thumb = info->entry & 1;
|
335 |
} else {
|
336 |
if (env == first_cpu) {
|
337 |
env->regs[15] = info->loader_start;
|
338 |
if (!info->dtb_filename) {
|
339 |
if (old_param) {
|
340 |
set_kernel_args_old(info); |
341 |
} else {
|
342 |
set_kernel_args(info); |
343 |
} |
344 |
} |
345 |
} else {
|
346 |
info->secondary_cpu_reset_hook(cpu, info); |
347 |
} |
348 |
} |
349 |
} |
350 |
} |
351 |
|
352 |
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
353 |
{ |
354 |
CPUARMState *env = &cpu->env; |
355 |
int kernel_size;
|
356 |
int initrd_size;
|
357 |
int n;
|
358 |
int is_linux = 0; |
359 |
uint64_t elf_entry; |
360 |
hwaddr entry; |
361 |
int big_endian;
|
362 |
|
363 |
/* Load the kernel. */
|
364 |
if (!info->kernel_filename) {
|
365 |
fprintf(stderr, "Kernel image must be specified\n");
|
366 |
exit(1);
|
367 |
} |
368 |
|
369 |
info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
|
370 |
|
371 |
if (!info->secondary_cpu_reset_hook) {
|
372 |
info->secondary_cpu_reset_hook = default_reset_secondary; |
373 |
} |
374 |
if (!info->write_secondary_boot) {
|
375 |
info->write_secondary_boot = default_write_secondary; |
376 |
} |
377 |
|
378 |
if (info->nb_cpus == 0) |
379 |
info->nb_cpus = 1;
|
380 |
|
381 |
#ifdef TARGET_WORDS_BIGENDIAN
|
382 |
big_endian = 1;
|
383 |
#else
|
384 |
big_endian = 0;
|
385 |
#endif
|
386 |
|
387 |
/* We want to put the initrd far enough into RAM that when the
|
388 |
* kernel is uncompressed it will not clobber the initrd. However
|
389 |
* on boards without much RAM we must ensure that we still leave
|
390 |
* enough room for a decent sized initrd, and on boards with large
|
391 |
* amounts of RAM we must avoid the initrd being so far up in RAM
|
392 |
* that it is outside lowmem and inaccessible to the kernel.
|
393 |
* So for boards with less than 256MB of RAM we put the initrd
|
394 |
* halfway into RAM, and for boards with 256MB of RAM or more we put
|
395 |
* the initrd at 128MB.
|
396 |
*/
|
397 |
info->initrd_start = info->loader_start + |
398 |
MIN(info->ram_size / 2, 128 * 1024 * 1024); |
399 |
|
400 |
/* Assume that raw images are linux kernels, and ELF images are not. */
|
401 |
kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry, |
402 |
NULL, NULL, big_endian, ELF_MACHINE, 1); |
403 |
entry = elf_entry; |
404 |
if (kernel_size < 0) { |
405 |
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
|
406 |
&is_linux); |
407 |
} |
408 |
if (kernel_size < 0) { |
409 |
entry = info->loader_start + KERNEL_LOAD_ADDR; |
410 |
kernel_size = load_image_targphys(info->kernel_filename, entry, |
411 |
info->ram_size - KERNEL_LOAD_ADDR); |
412 |
is_linux = 1;
|
413 |
} |
414 |
if (kernel_size < 0) { |
415 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
416 |
info->kernel_filename); |
417 |
exit(1);
|
418 |
} |
419 |
info->entry = entry; |
420 |
if (is_linux) {
|
421 |
if (info->initrd_filename) {
|
422 |
initrd_size = load_image_targphys(info->initrd_filename, |
423 |
info->initrd_start, |
424 |
info->ram_size - |
425 |
info->initrd_start); |
426 |
if (initrd_size < 0) { |
427 |
fprintf(stderr, "qemu: could not load initrd '%s'\n",
|
428 |
info->initrd_filename); |
429 |
exit(1);
|
430 |
} |
431 |
} else {
|
432 |
initrd_size = 0;
|
433 |
} |
434 |
info->initrd_size = initrd_size; |
435 |
|
436 |
bootloader[4] = info->board_id;
|
437 |
|
438 |
/* for device tree boot, we pass the DTB directly in r2. Otherwise
|
439 |
* we point to the kernel args.
|
440 |
*/
|
441 |
if (info->dtb_filename) {
|
442 |
/* Place the DTB after the initrd in memory. Note that some
|
443 |
* kernels will trash anything in the 4K page the initrd
|
444 |
* ends in, so make sure the DTB isn't caught up in that.
|
445 |
*/
|
446 |
hwaddr dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, |
447 |
4096);
|
448 |
if (load_dtb(dtb_start, info)) {
|
449 |
exit(1);
|
450 |
} |
451 |
bootloader[5] = dtb_start;
|
452 |
} else {
|
453 |
bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
|
454 |
if (info->ram_size >= (1ULL << 32)) { |
455 |
fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
|
456 |
" Linux kernel using ATAGS (try passing a device tree"
|
457 |
" using -dtb)\n");
|
458 |
exit(1);
|
459 |
} |
460 |
} |
461 |
bootloader[6] = entry;
|
462 |
for (n = 0; n < sizeof(bootloader) / 4; n++) { |
463 |
bootloader[n] = tswap32(bootloader[n]); |
464 |
} |
465 |
rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader), |
466 |
info->loader_start); |
467 |
if (info->nb_cpus > 1) { |
468 |
info->write_secondary_boot(cpu, info); |
469 |
} |
470 |
} |
471 |
info->is_linux = is_linux; |
472 |
|
473 |
for (; env; env = env->next_cpu) {
|
474 |
cpu = arm_env_get_cpu(env); |
475 |
env->boot_info = info; |
476 |
qemu_register_reset(do_cpu_reset, cpu); |
477 |
} |
478 |
} |