root / hw / ppc / e500.c @ 2ff3de68
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/*
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* QEMU PowerPC e500-based platforms
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "config.h" |
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#include "qemu-common.h" |
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#include "e500.h" |
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#include "e500-ccsr.h" |
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#include "net/net.h" |
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#include "qemu/config-file.h" |
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#include "hw/hw.h" |
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#include "hw/char/serial.h" |
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#include "hw/pci/pci.h" |
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#include "hw/boards.h" |
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#include "sysemu/sysemu.h" |
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#include "sysemu/kvm.h" |
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#include "kvm_ppc.h" |
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#include "sysemu/device_tree.h" |
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#include "hw/ppc/openpic.h" |
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#include "hw/ppc/ppc.h" |
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#include "hw/loader.h" |
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#include "elf.h" |
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#include "hw/sysbus.h" |
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#include "exec/address-spaces.h" |
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#include "qemu/host-utils.h" |
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#include "hw/pci-host/ppce500.h" |
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|
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#define EPAPR_MAGIC (0x45504150) |
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#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
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#define UIMAGE_LOAD_BASE 0 |
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#define DTC_LOAD_PAD 0x1800000 |
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#define DTC_PAD_MASK 0xFFFFF |
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#define DTB_MAX_SIZE (8 * 1024 * 1024) |
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#define INITRD_LOAD_PAD 0x2000000 |
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#define INITRD_PAD_MASK 0xFFFFFF |
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|
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#define RAM_SIZES_ALIGN (64UL << 20) |
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|
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/* TODO: parameterize */
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#define MPC8544_CCSRBAR_BASE 0xE0000000ULL |
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#define MPC8544_CCSRBAR_SIZE 0x00100000ULL |
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#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL |
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#define MPC8544_MSI_REGS_OFFSET 0x41600ULL |
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#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL |
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#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL |
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#define MPC8544_PCI_REGS_OFFSET 0x8000ULL |
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#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
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MPC8544_PCI_REGS_OFFSET) |
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#define MPC8544_PCI_REGS_SIZE 0x1000ULL |
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#define MPC8544_PCI_IO 0xE1000000ULL |
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#define MPC8544_UTIL_OFFSET 0xe0000ULL |
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#define MPC8544_SPIN_BASE 0xEF000000ULL |
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struct boot_info
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{ |
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uint32_t dt_base; |
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uint32_t dt_size; |
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uint32_t entry; |
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}; |
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static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, |
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int nr_slots, int *len) |
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{ |
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int i = 0; |
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int slot;
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int pci_irq;
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int host_irq;
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int last_slot = first_slot + nr_slots;
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uint32_t *pci_map; |
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*len = nr_slots * 4 * 7 * sizeof(uint32_t); |
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pci_map = g_malloc(*len); |
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for (slot = first_slot; slot < last_slot; slot++) {
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for (pci_irq = 0; pci_irq < 4; pci_irq++) { |
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pci_map[i++] = cpu_to_be32(slot << 11);
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pci_map[i++] = cpu_to_be32(0x0);
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pci_map[i++] = cpu_to_be32(0x0);
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pci_map[i++] = cpu_to_be32(pci_irq + 1);
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pci_map[i++] = cpu_to_be32(mpic); |
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host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); |
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pci_map[i++] = cpu_to_be32(host_irq + 1);
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pci_map[i++] = cpu_to_be32(0x1);
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} |
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} |
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assert((i * sizeof(uint32_t)) == *len);
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return pci_map;
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} |
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static void dt_serial_create(void *fdt, unsigned long long offset, |
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const char *soc, const char *mpic, |
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const char *alias, int idx, bool defcon) |
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{ |
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char ser[128]; |
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snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); |
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qemu_devtree_add_subnode(fdt, ser); |
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qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); |
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qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); |
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qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); |
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qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
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qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); |
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qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); |
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qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
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qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
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if (defcon) {
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qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); |
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} |
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} |
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static int ppce500_load_device_tree(CPUPPCState *env, |
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PPCE500Params *params, |
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hwaddr addr, |
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hwaddr initrd_base, |
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hwaddr initrd_size) |
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{ |
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int ret = -1; |
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uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
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int fdt_size;
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void *fdt;
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uint8_t hypercall[16];
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uint32_t clock_freq = 400000000;
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uint32_t tb_freq = 400000000;
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int i;
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char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; |
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char soc[128]; |
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char mpic[128]; |
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uint32_t mpic_ph; |
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uint32_t msi_ph; |
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char gutil[128]; |
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char pci[128]; |
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char msi[128]; |
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uint32_t *pci_map = NULL;
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int len;
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uint32_t pci_ranges[14] =
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{ |
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0x2000000, 0x0, 0xc0000000, |
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0x0, 0xc0000000, |
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0x0, 0x20000000, |
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0x1000000, 0x0, 0x0, |
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0x0, 0xe1000000, |
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0x0, 0x10000, |
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}; |
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QemuOpts *machine_opts = qemu_get_machine_opts(); |
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const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); |
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const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); |
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if (dtb_file) {
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char *filename;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); |
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if (!filename) {
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goto out;
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} |
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fdt = load_device_tree(filename, &fdt_size); |
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if (!fdt) {
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goto out;
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} |
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goto done;
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} |
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fdt = create_device_tree(&fdt_size); |
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if (fdt == NULL) { |
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goto out;
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} |
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/* Manipulate device tree in memory. */
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qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); |
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qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); |
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qemu_devtree_add_subnode(fdt, "/memory");
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qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); |
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qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
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sizeof(mem_reg_property));
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qemu_devtree_add_subnode(fdt, "/chosen");
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if (initrd_size) {
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
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initrd_base); |
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if (ret < 0) { |
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fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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} |
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
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(initrd_base + initrd_size)); |
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if (ret < 0) { |
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fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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} |
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} |
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ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", |
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params->kernel_cmdline); |
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if (ret < 0) |
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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if (kvm_enabled()) {
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/* Read out host's frequencies */
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clock_freq = kvmppc_get_clockfreq(); |
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tb_freq = kvmppc_get_tbfreq(); |
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/* indicate KVM hypercall interface */
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qemu_devtree_add_subnode(fdt, "/hypervisor");
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qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", |
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"linux,kvm");
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kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
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qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", |
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hypercall, sizeof(hypercall));
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/* if KVM supports the idle hcall, set property indicating this */
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if (kvmppc_get_hasidle(env)) {
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qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); |
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} |
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} |
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/* Create CPU nodes */
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qemu_devtree_add_subnode(fdt, "/cpus");
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qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); |
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qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); |
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/* We need to generate the cpu nodes in reverse order, so Linux can pick
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the first node as boot node and be happy */
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for (i = smp_cpus - 1; i >= 0; i--) { |
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CPUState *cpu; |
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char cpu_name[128]; |
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uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
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cpu = qemu_get_cpu(i); |
243 |
if (cpu == NULL) { |
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continue;
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} |
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env = cpu->env_ptr; |
247 |
|
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snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", |
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cpu->cpu_index); |
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qemu_devtree_add_subnode(fdt, cpu_name); |
251 |
qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
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qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
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qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
254 |
qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index);
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qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
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env->dcache_line_size); |
257 |
qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
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env->icache_line_size); |
259 |
qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); |
260 |
qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); |
261 |
qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); |
262 |
if (cpu->cpu_index) {
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qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); |
264 |
qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); |
265 |
qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
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cpu_release_addr); |
267 |
} else {
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qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); |
269 |
} |
270 |
} |
271 |
|
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qemu_devtree_add_subnode(fdt, "/aliases");
|
273 |
/* XXX These should go into their respective devices' code */
|
274 |
snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); |
275 |
qemu_devtree_add_subnode(fdt, soc); |
276 |
qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); |
277 |
qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
|
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sizeof(compatible_sb));
|
279 |
qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); |
280 |
qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); |
281 |
qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, |
282 |
MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
|
283 |
MPC8544_CCSRBAR_SIZE); |
284 |
/* XXX should contain a reasonable value */
|
285 |
qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); |
286 |
|
287 |
snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); |
288 |
qemu_devtree_add_subnode(fdt, mpic); |
289 |
qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); |
290 |
qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); |
291 |
qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
|
292 |
0x40000);
|
293 |
qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); |
294 |
qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); |
295 |
mpic_ph = qemu_devtree_alloc_phandle(fdt); |
296 |
qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
|
297 |
qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
|
298 |
qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); |
299 |
|
300 |
/*
|
301 |
* We have to generate ser1 first, because Linux takes the first
|
302 |
* device it finds in the dt as serial output device. And we generate
|
303 |
* devices in reverse order to the dt.
|
304 |
*/
|
305 |
dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, |
306 |
soc, mpic, "serial1", 1, false); |
307 |
dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, |
308 |
soc, mpic, "serial0", 0, true); |
309 |
|
310 |
snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, |
311 |
MPC8544_UTIL_OFFSET); |
312 |
qemu_devtree_add_subnode(fdt, gutil); |
313 |
qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); |
314 |
qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); |
315 |
qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); |
316 |
|
317 |
snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); |
318 |
qemu_devtree_add_subnode(fdt, msi); |
319 |
qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); |
320 |
qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); |
321 |
msi_ph = qemu_devtree_alloc_phandle(fdt); |
322 |
qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); |
323 |
qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
|
324 |
qemu_devtree_setprop_cells(fdt, msi, "interrupts",
|
325 |
0xe0, 0x0, |
326 |
0xe1, 0x0, |
327 |
0xe2, 0x0, |
328 |
0xe3, 0x0, |
329 |
0xe4, 0x0, |
330 |
0xe5, 0x0, |
331 |
0xe6, 0x0, |
332 |
0xe7, 0x0); |
333 |
qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
|
334 |
qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
|
335 |
|
336 |
snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); |
337 |
qemu_devtree_add_subnode(fdt, pci); |
338 |
qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); |
339 |
qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); |
340 |
qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); |
341 |
qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, |
342 |
0x0, 0x7); |
343 |
pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic), |
344 |
params->pci_first_slot, params->pci_nr_slots, |
345 |
&len); |
346 |
qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
|
347 |
qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
|
348 |
qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); |
349 |
qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); |
350 |
for (i = 0; i < 14; i++) { |
351 |
pci_ranges[i] = cpu_to_be32(pci_ranges[i]); |
352 |
} |
353 |
qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
|
354 |
qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); |
355 |
qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, |
356 |
MPC8544_PCI_REGS_BASE, 0, 0x1000); |
357 |
qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); |
358 |
qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); |
359 |
qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); |
360 |
qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); |
361 |
qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); |
362 |
|
363 |
params->fixup_devtree(params, fdt); |
364 |
|
365 |
if (toplevel_compat) {
|
366 |
qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, |
367 |
strlen(toplevel_compat) + 1);
|
368 |
} |
369 |
|
370 |
done:
|
371 |
qemu_devtree_dumpdtb(fdt, fdt_size); |
372 |
ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
373 |
if (ret < 0) { |
374 |
goto out;
|
375 |
} |
376 |
g_free(fdt); |
377 |
ret = fdt_size; |
378 |
|
379 |
out:
|
380 |
g_free(pci_map); |
381 |
|
382 |
return ret;
|
383 |
} |
384 |
|
385 |
/* Create -kernel TLB entries for BookE. */
|
386 |
static inline hwaddr booke206_page_size_to_tlb(uint64_t size) |
387 |
{ |
388 |
return 63 - clz64(size >> 10); |
389 |
} |
390 |
|
391 |
static int booke206_initial_map_tsize(CPUPPCState *env) |
392 |
{ |
393 |
struct boot_info *bi = env->load_info;
|
394 |
hwaddr dt_end; |
395 |
int ps;
|
396 |
|
397 |
/* Our initial TLB entry needs to cover everything from 0 to
|
398 |
the device tree top */
|
399 |
dt_end = bi->dt_base + bi->dt_size; |
400 |
ps = booke206_page_size_to_tlb(dt_end) + 1;
|
401 |
if (ps & 1) { |
402 |
/* e500v2 can only do even TLB size bits */
|
403 |
ps++; |
404 |
} |
405 |
return ps;
|
406 |
} |
407 |
|
408 |
static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
|
409 |
{ |
410 |
int tsize;
|
411 |
|
412 |
tsize = booke206_initial_map_tsize(env); |
413 |
return (1ULL << 10 << tsize); |
414 |
} |
415 |
|
416 |
static void mmubooke_create_initial_mapping(CPUPPCState *env) |
417 |
{ |
418 |
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
419 |
hwaddr size; |
420 |
int ps;
|
421 |
|
422 |
ps = booke206_initial_map_tsize(env); |
423 |
size = (ps << MAS1_TSIZE_SHIFT); |
424 |
tlb->mas1 = MAS1_VALID | size; |
425 |
tlb->mas2 = 0;
|
426 |
tlb->mas7_3 = 0;
|
427 |
tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
428 |
|
429 |
env->tlb_dirty = true;
|
430 |
} |
431 |
|
432 |
static void ppce500_cpu_reset_sec(void *opaque) |
433 |
{ |
434 |
PowerPCCPU *cpu = opaque; |
435 |
CPUState *cs = CPU(cpu); |
436 |
CPUPPCState *env = &cpu->env; |
437 |
|
438 |
cpu_reset(cs); |
439 |
|
440 |
/* Secondary CPU starts in halted state for now. Needs to change when
|
441 |
implementing non-kernel boot. */
|
442 |
cs->halted = 1;
|
443 |
env->exception_index = EXCP_HLT; |
444 |
} |
445 |
|
446 |
static void ppce500_cpu_reset(void *opaque) |
447 |
{ |
448 |
PowerPCCPU *cpu = opaque; |
449 |
CPUState *cs = CPU(cpu); |
450 |
CPUPPCState *env = &cpu->env; |
451 |
struct boot_info *bi = env->load_info;
|
452 |
|
453 |
cpu_reset(cs); |
454 |
|
455 |
/* Set initial guest state. */
|
456 |
cs->halted = 0;
|
457 |
env->gpr[1] = (16<<20) - 8; |
458 |
env->gpr[3] = bi->dt_base;
|
459 |
env->gpr[4] = 0; |
460 |
env->gpr[5] = 0; |
461 |
env->gpr[6] = EPAPR_MAGIC;
|
462 |
env->gpr[7] = mmubooke_initial_mapsize(env);
|
463 |
env->gpr[8] = 0; |
464 |
env->gpr[9] = 0; |
465 |
env->nip = bi->entry; |
466 |
mmubooke_create_initial_mapping(env); |
467 |
} |
468 |
|
469 |
static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
|
470 |
qemu_irq **irqs) |
471 |
{ |
472 |
DeviceState *dev; |
473 |
SysBusDevice *s; |
474 |
int i, j, k;
|
475 |
|
476 |
dev = qdev_create(NULL, TYPE_OPENPIC);
|
477 |
qdev_prop_set_uint32(dev, "model", params->mpic_version);
|
478 |
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
|
479 |
|
480 |
qdev_init_nofail(dev); |
481 |
s = SYS_BUS_DEVICE(dev); |
482 |
|
483 |
k = 0;
|
484 |
for (i = 0; i < smp_cpus; i++) { |
485 |
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { |
486 |
sysbus_connect_irq(s, k++, irqs[i][j]); |
487 |
} |
488 |
} |
489 |
|
490 |
return dev;
|
491 |
} |
492 |
|
493 |
static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
|
494 |
qemu_irq **irqs) |
495 |
{ |
496 |
DeviceState *dev; |
497 |
CPUPPCState *env; |
498 |
CPUState *cs; |
499 |
int r;
|
500 |
|
501 |
dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
|
502 |
qdev_prop_set_uint32(dev, "model", params->mpic_version);
|
503 |
|
504 |
r = qdev_init(dev); |
505 |
if (r) {
|
506 |
return NULL; |
507 |
} |
508 |
|
509 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
510 |
cs = ENV_GET_CPU(env); |
511 |
|
512 |
if (kvm_openpic_connect_vcpu(dev, cs)) {
|
513 |
fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
|
514 |
__func__); |
515 |
abort(); |
516 |
} |
517 |
} |
518 |
|
519 |
return dev;
|
520 |
} |
521 |
|
522 |
static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr,
|
523 |
qemu_irq **irqs) |
524 |
{ |
525 |
qemu_irq *mpic; |
526 |
DeviceState *dev = NULL;
|
527 |
SysBusDevice *s; |
528 |
int i;
|
529 |
|
530 |
mpic = g_new(qemu_irq, 256);
|
531 |
|
532 |
if (kvm_enabled()) {
|
533 |
QemuOpts *machine_opts = qemu_get_machine_opts(); |
534 |
bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
|
535 |
"kernel_irqchip", true); |
536 |
bool irqchip_required = qemu_opt_get_bool(machine_opts,
|
537 |
"kernel_irqchip", false); |
538 |
|
539 |
if (irqchip_allowed) {
|
540 |
dev = ppce500_init_mpic_kvm(params, irqs); |
541 |
} |
542 |
|
543 |
if (irqchip_required && !dev) {
|
544 |
fprintf(stderr, "%s: irqchip requested but unavailable\n",
|
545 |
__func__); |
546 |
abort(); |
547 |
} |
548 |
} |
549 |
|
550 |
if (!dev) {
|
551 |
dev = ppce500_init_mpic_qemu(params, irqs); |
552 |
} |
553 |
|
554 |
for (i = 0; i < 256; i++) { |
555 |
mpic[i] = qdev_get_gpio_in(dev, i); |
556 |
} |
557 |
|
558 |
s = SYS_BUS_DEVICE(dev); |
559 |
memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, |
560 |
s->mmio[0].memory);
|
561 |
|
562 |
return mpic;
|
563 |
} |
564 |
|
565 |
void ppce500_init(PPCE500Params *params)
|
566 |
{ |
567 |
MemoryRegion *address_space_mem = get_system_memory(); |
568 |
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
569 |
PCIBus *pci_bus; |
570 |
CPUPPCState *env = NULL;
|
571 |
uint64_t elf_entry; |
572 |
uint64_t elf_lowaddr; |
573 |
hwaddr entry=0;
|
574 |
hwaddr loadaddr=UIMAGE_LOAD_BASE; |
575 |
target_long kernel_size=0;
|
576 |
target_ulong dt_base = 0;
|
577 |
target_ulong initrd_base = 0;
|
578 |
target_long initrd_size = 0;
|
579 |
target_ulong cur_base = 0;
|
580 |
int i;
|
581 |
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
582 |
qemu_irq **irqs, *mpic; |
583 |
DeviceState *dev; |
584 |
CPUPPCState *firstenv = NULL;
|
585 |
MemoryRegion *ccsr_addr_space; |
586 |
SysBusDevice *s; |
587 |
PPCE500CCSRState *ccsr; |
588 |
|
589 |
/* Setup CPUs */
|
590 |
if (params->cpu_model == NULL) { |
591 |
params->cpu_model = "e500v2_v30";
|
592 |
} |
593 |
|
594 |
irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
|
595 |
irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); |
596 |
for (i = 0; i < smp_cpus; i++) { |
597 |
PowerPCCPU *cpu; |
598 |
CPUState *cs; |
599 |
qemu_irq *input; |
600 |
|
601 |
cpu = cpu_ppc_init(params->cpu_model); |
602 |
if (cpu == NULL) { |
603 |
fprintf(stderr, "Unable to initialize CPU!\n");
|
604 |
exit(1);
|
605 |
} |
606 |
env = &cpu->env; |
607 |
cs = CPU(cpu); |
608 |
|
609 |
if (!firstenv) {
|
610 |
firstenv = env; |
611 |
} |
612 |
|
613 |
irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
|
614 |
input = (qemu_irq *)env->irq_inputs; |
615 |
irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; |
616 |
irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; |
617 |
env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; |
618 |
env->mpic_iack = MPC8544_CCSRBAR_BASE + |
619 |
MPC8544_MPIC_REGS_OFFSET + 0xa0;
|
620 |
|
621 |
ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
|
622 |
|
623 |
/* Register reset handler */
|
624 |
if (!i) {
|
625 |
/* Primary CPU */
|
626 |
struct boot_info *boot_info;
|
627 |
boot_info = g_malloc0(sizeof(struct boot_info)); |
628 |
qemu_register_reset(ppce500_cpu_reset, cpu); |
629 |
env->load_info = boot_info; |
630 |
} else {
|
631 |
/* Secondary CPUs */
|
632 |
qemu_register_reset(ppce500_cpu_reset_sec, cpu); |
633 |
} |
634 |
} |
635 |
|
636 |
env = firstenv; |
637 |
|
638 |
/* Fixup Memory size on a alignment boundary */
|
639 |
ram_size &= ~(RAM_SIZES_ALIGN - 1);
|
640 |
params->ram_size = ram_size; |
641 |
|
642 |
/* Register Memory */
|
643 |
memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size); |
644 |
vmstate_register_ram_global(ram); |
645 |
memory_region_add_subregion(address_space_mem, 0, ram);
|
646 |
|
647 |
dev = qdev_create(NULL, "e500-ccsr"); |
648 |
object_property_add_child(qdev_get_machine(), "e500-ccsr",
|
649 |
OBJECT(dev), NULL);
|
650 |
qdev_init_nofail(dev); |
651 |
ccsr = CCSR(dev); |
652 |
ccsr_addr_space = &ccsr->ccsr_space; |
653 |
memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, |
654 |
ccsr_addr_space); |
655 |
|
656 |
mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); |
657 |
|
658 |
/* Serial */
|
659 |
if (serial_hds[0]) { |
660 |
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, |
661 |
0, mpic[42], 399193, |
662 |
serial_hds[0], DEVICE_BIG_ENDIAN);
|
663 |
} |
664 |
|
665 |
if (serial_hds[1]) { |
666 |
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, |
667 |
0, mpic[42], 399193, |
668 |
serial_hds[1], DEVICE_BIG_ENDIAN);
|
669 |
} |
670 |
|
671 |
/* General Utility device */
|
672 |
dev = qdev_create(NULL, "mpc8544-guts"); |
673 |
qdev_init_nofail(dev); |
674 |
s = SYS_BUS_DEVICE(dev); |
675 |
memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, |
676 |
sysbus_mmio_get_region(s, 0));
|
677 |
|
678 |
/* PCI */
|
679 |
dev = qdev_create(NULL, "e500-pcihost"); |
680 |
qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
|
681 |
qdev_init_nofail(dev); |
682 |
s = SYS_BUS_DEVICE(dev); |
683 |
sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); |
684 |
sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); |
685 |
sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); |
686 |
sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); |
687 |
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, |
688 |
sysbus_mmio_get_region(s, 0));
|
689 |
|
690 |
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
691 |
if (!pci_bus)
|
692 |
printf("couldn't create PCI controller!\n");
|
693 |
|
694 |
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
|
695 |
|
696 |
if (pci_bus) {
|
697 |
/* Register network interfaces. */
|
698 |
for (i = 0; i < nb_nics; i++) { |
699 |
pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); |
700 |
} |
701 |
} |
702 |
|
703 |
/* Register spinning region */
|
704 |
sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); |
705 |
|
706 |
/* Load kernel. */
|
707 |
if (params->kernel_filename) {
|
708 |
kernel_size = load_uimage(params->kernel_filename, &entry, |
709 |
&loadaddr, NULL);
|
710 |
if (kernel_size < 0) { |
711 |
kernel_size = load_elf(params->kernel_filename, NULL, NULL, |
712 |
&elf_entry, &elf_lowaddr, NULL, 1, |
713 |
ELF_MACHINE, 0);
|
714 |
entry = elf_entry; |
715 |
loadaddr = elf_lowaddr; |
716 |
} |
717 |
/* XXX try again as binary */
|
718 |
if (kernel_size < 0) { |
719 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
720 |
params->kernel_filename); |
721 |
exit(1);
|
722 |
} |
723 |
|
724 |
cur_base = loadaddr + kernel_size; |
725 |
|
726 |
/* Reserve space for dtb */
|
727 |
dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
728 |
cur_base += DTB_MAX_SIZE; |
729 |
} |
730 |
|
731 |
/* Load initrd. */
|
732 |
if (params->initrd_filename) {
|
733 |
initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
734 |
initrd_size = load_image_targphys(params->initrd_filename, initrd_base, |
735 |
ram_size - initrd_base); |
736 |
|
737 |
if (initrd_size < 0) { |
738 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
739 |
params->initrd_filename); |
740 |
exit(1);
|
741 |
} |
742 |
|
743 |
cur_base = initrd_base + initrd_size; |
744 |
} |
745 |
|
746 |
/* If we're loading a kernel directly, we must load the device tree too. */
|
747 |
if (params->kernel_filename) {
|
748 |
struct boot_info *boot_info;
|
749 |
int dt_size;
|
750 |
|
751 |
dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base, |
752 |
initrd_size); |
753 |
if (dt_size < 0) { |
754 |
fprintf(stderr, "couldn't load device tree\n");
|
755 |
exit(1);
|
756 |
} |
757 |
assert(dt_size < DTB_MAX_SIZE); |
758 |
|
759 |
boot_info = env->load_info; |
760 |
boot_info->entry = entry; |
761 |
boot_info->dt_base = dt_base; |
762 |
boot_info->dt_size = dt_size; |
763 |
} |
764 |
|
765 |
if (kvm_enabled()) {
|
766 |
kvmppc_init(); |
767 |
} |
768 |
} |
769 |
|
770 |
static int e500_ccsr_initfn(SysBusDevice *dev) |
771 |
{ |
772 |
PPCE500CCSRState *ccsr; |
773 |
|
774 |
ccsr = CCSR(dev); |
775 |
memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr",
|
776 |
MPC8544_CCSRBAR_SIZE); |
777 |
return 0; |
778 |
} |
779 |
|
780 |
static void e500_ccsr_class_init(ObjectClass *klass, void *data) |
781 |
{ |
782 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
783 |
k->init = e500_ccsr_initfn; |
784 |
} |
785 |
|
786 |
static const TypeInfo e500_ccsr_info = { |
787 |
.name = TYPE_CCSR, |
788 |
.parent = TYPE_SYS_BUS_DEVICE, |
789 |
.instance_size = sizeof(PPCE500CCSRState),
|
790 |
.class_init = e500_ccsr_class_init, |
791 |
}; |
792 |
|
793 |
static void e500_register_types(void) |
794 |
{ |
795 |
type_register_static(&e500_ccsr_info); |
796 |
} |
797 |
|
798 |
type_init(e500_register_types) |