Revision 3023f332 hw/pxa2xx.c
b/hw/pxa2xx.c | ||
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2010 | 2010 |
} |
2011 | 2011 |
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2012 | 2012 |
/* Initialise a PXA270 integrated chip (ARM based core). */ |
2013 |
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, |
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2014 |
DisplayState *ds, const char *revision) |
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2013 |
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision) |
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2015 | 2014 |
{ |
2016 | 2015 |
struct pxa2xx_state_s *s; |
2017 | 2016 |
struct pxa2xx_ssp_s *ssp; |
... | ... | |
2067 | 2066 |
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP], |
2068 | 2067 |
s->dma, serial_hds[i]); |
2069 | 2068 |
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2070 |
if (ds) |
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2071 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds); |
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2069 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]); |
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2072 | 2070 |
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2073 | 2071 |
s->cm_base = 0x41300000; |
2074 | 2072 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
... | ... | |
2141 | 2139 |
} |
2142 | 2140 |
|
2143 | 2141 |
/* Initialise a PXA255 integrated chip (ARM based core). */ |
2144 |
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, |
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2145 |
DisplayState *ds) |
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2142 |
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size) |
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2146 | 2143 |
{ |
2147 | 2144 |
struct pxa2xx_state_s *s; |
2148 | 2145 |
struct pxa2xx_ssp_s *ssp; |
... | ... | |
2191 | 2188 |
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP], |
2192 | 2189 |
s->dma, serial_hds[i]); |
2193 | 2190 |
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2194 |
if (ds) |
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2195 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds); |
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2191 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]); |
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2196 | 2192 |
|
2197 | 2193 |
s->cm_base = 0x41300000; |
2198 | 2194 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
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