root / target-arm / helper.c @ 30a8cac1
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#include <stdio.h> |
---|---|
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "gdbstub.h" |
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#include "helpers.h" |
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#include "qemu-common.h" |
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#include "host-utils.h" |
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|
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static uint32_t cortexa9_cp15_c0_c1[8] = |
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{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 }; |
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|
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static uint32_t cortexa9_cp15_c0_c2[8] = |
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{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 }; |
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|
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static uint32_t cortexa8_cp15_c0_c1[8] = |
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{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 }; |
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|
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static uint32_t cortexa8_cp15_c0_c2[8] = |
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{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 }; |
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|
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static uint32_t mpcore_cp15_c0_c1[8] = |
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{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 }; |
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|
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static uint32_t mpcore_cp15_c0_c2[8] = |
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{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 }; |
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|
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static uint32_t arm1136_cp15_c0_c1[8] = |
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{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 }; |
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|
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static uint32_t arm1136_cp15_c0_c2[8] = |
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{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 }; |
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|
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static uint32_t cpu_arm_find_by_name(const char *name); |
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|
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static inline void set_feature(CPUARMState *env, int feature) |
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{ |
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env->features |= 1u << feature;
|
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} |
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|
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static void cpu_reset_model_id(CPUARMState *env, uint32_t id) |
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{ |
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env->cp15.c0_cpuid = id; |
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switch (id) {
|
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case ARM_CPUID_ARM926:
|
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set_feature(env, ARM_FEATURE_VFP); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
|
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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env->cp15.c1_sys = 0x00090078;
|
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break;
|
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case ARM_CPUID_ARM946:
|
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set_feature(env, ARM_FEATURE_MPU); |
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env->cp15.c0_cachetype = 0x0f004006;
|
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env->cp15.c1_sys = 0x00000078;
|
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break;
|
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case ARM_CPUID_ARM1026:
|
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_AUXCR); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
|
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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env->cp15.c1_sys = 0x00090078;
|
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break;
|
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case ARM_CPUID_ARM1136_R2:
|
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case ARM_CPUID_ARM1136:
|
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_AUXCR); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
|
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memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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break;
|
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case ARM_CPUID_ARM11MPCORE:
|
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_V6K); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_AUXCR); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
|
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memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x1dd20d2;
|
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break;
|
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case ARM_CPUID_CORTEXA8:
|
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_V6K); |
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_AUXCR); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_VFP3); |
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set_feature(env, ARM_FEATURE_NEON); |
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set_feature(env, ARM_FEATURE_THUMB2EE); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
|
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
|
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memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x82048004;
|
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env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; |
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env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ |
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env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ |
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env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ |
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break;
|
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case ARM_CPUID_CORTEXA9:
|
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_V6K); |
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_AUXCR); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_VFP3); |
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set_feature(env, ARM_FEATURE_VFP_FP16); |
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set_feature(env, ARM_FEATURE_NEON); |
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set_feature(env, ARM_FEATURE_THUMB2EE); |
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env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */ |
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
|
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
|
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memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); |
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memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); |
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env->cp15.c0_cachetype = 0x80038003;
|
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env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; |
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env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ |
129 |
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ |
130 |
break;
|
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case ARM_CPUID_CORTEXM3:
|
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_THUMB2); |
134 |
set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_M); |
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set_feature(env, ARM_FEATURE_DIV); |
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break;
|
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case ARM_CPUID_ANY: /* For userspace emulation. */ |
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_V6K); |
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_VFP); |
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set_feature(env, ARM_FEATURE_VFP3); |
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set_feature(env, ARM_FEATURE_VFP_FP16); |
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set_feature(env, ARM_FEATURE_NEON); |
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set_feature(env, ARM_FEATURE_THUMB2EE); |
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set_feature(env, ARM_FEATURE_DIV); |
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break;
|
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case ARM_CPUID_TI915T:
|
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case ARM_CPUID_TI925T:
|
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set_feature(env, ARM_FEATURE_OMAPCP); |
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env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
|
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env->cp15.c0_cachetype = 0x5109149;
|
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env->cp15.c1_sys = 0x00000070;
|
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env->cp15.c15_i_max = 0x000;
|
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env->cp15.c15_i_min = 0xff0;
|
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break;
|
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case ARM_CPUID_PXA250:
|
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case ARM_CPUID_PXA255:
|
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case ARM_CPUID_PXA260:
|
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case ARM_CPUID_PXA261:
|
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case ARM_CPUID_PXA262:
|
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set_feature(env, ARM_FEATURE_XSCALE); |
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/* JTAG_ID is ((id << 28) | 0x09265013) */
|
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env->cp15.c0_cachetype = 0xd172172;
|
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env->cp15.c1_sys = 0x00000078;
|
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break;
|
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case ARM_CPUID_PXA270_A0:
|
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case ARM_CPUID_PXA270_A1:
|
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case ARM_CPUID_PXA270_B0:
|
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case ARM_CPUID_PXA270_B1:
|
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case ARM_CPUID_PXA270_C0:
|
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case ARM_CPUID_PXA270_C5:
|
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set_feature(env, ARM_FEATURE_XSCALE); |
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/* JTAG_ID is ((id << 28) | 0x09265013) */
|
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set_feature(env, ARM_FEATURE_IWMMXT); |
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
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env->cp15.c0_cachetype = 0xd172172;
|
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env->cp15.c1_sys = 0x00000078;
|
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break;
|
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default:
|
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cpu_abort(env, "Bad CPU ID: %x\n", id);
|
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break;
|
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} |
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} |
187 |
|
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void cpu_reset(CPUARMState *env)
|
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{ |
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uint32_t id; |
191 |
|
192 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
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log_cpu_state(env, 0);
|
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} |
196 |
|
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id = env->cp15.c0_cpuid; |
198 |
memset(env, 0, offsetof(CPUARMState, breakpoints));
|
199 |
if (id)
|
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cpu_reset_model_id(env, id); |
201 |
#if defined (CONFIG_USER_ONLY)
|
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
203 |
env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
204 |
#else
|
205 |
/* SVC mode with interrupts disabled. */
|
206 |
env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
207 |
/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
|
208 |
clear at reset. */
|
209 |
if (IS_M(env))
|
210 |
env->uncached_cpsr &= ~CPSR_I; |
211 |
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
|
212 |
env->cp15.c2_base_mask = 0xffffc000u;
|
213 |
#endif
|
214 |
env->regs[15] = 0; |
215 |
tlb_flush(env, 1);
|
216 |
} |
217 |
|
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static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg) |
219 |
{ |
220 |
int nregs;
|
221 |
|
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/* VFP data registers are always little-endian. */
|
223 |
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
224 |
if (reg < nregs) {
|
225 |
stfq_le_p(buf, env->vfp.regs[reg]); |
226 |
return 8; |
227 |
} |
228 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
229 |
/* Aliases for Q regs. */
|
230 |
nregs += 16;
|
231 |
if (reg < nregs) {
|
232 |
stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); |
233 |
stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); |
234 |
return 16; |
235 |
} |
236 |
} |
237 |
switch (reg - nregs) {
|
238 |
case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; |
239 |
case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; |
240 |
case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
241 |
} |
242 |
return 0; |
243 |
} |
244 |
|
245 |
static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg) |
246 |
{ |
247 |
int nregs;
|
248 |
|
249 |
nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; |
250 |
if (reg < nregs) {
|
251 |
env->vfp.regs[reg] = ldfq_le_p(buf); |
252 |
return 8; |
253 |
} |
254 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
255 |
nregs += 16;
|
256 |
if (reg < nregs) {
|
257 |
env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); |
258 |
env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); |
259 |
return 16; |
260 |
} |
261 |
} |
262 |
switch (reg - nregs) {
|
263 |
case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; |
264 |
case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; |
265 |
case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
266 |
} |
267 |
return 0; |
268 |
} |
269 |
|
270 |
CPUARMState *cpu_arm_init(const char *cpu_model) |
271 |
{ |
272 |
CPUARMState *env; |
273 |
uint32_t id; |
274 |
static int inited = 0; |
275 |
|
276 |
id = cpu_arm_find_by_name(cpu_model); |
277 |
if (id == 0) |
278 |
return NULL; |
279 |
env = qemu_mallocz(sizeof(CPUARMState));
|
280 |
cpu_exec_init(env); |
281 |
if (!inited) {
|
282 |
inited = 1;
|
283 |
arm_translate_init(); |
284 |
} |
285 |
|
286 |
env->cpu_model_str = cpu_model; |
287 |
env->cp15.c0_cpuid = id; |
288 |
cpu_reset(env); |
289 |
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
290 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
291 |
51, "arm-neon.xml", 0); |
292 |
} else if (arm_feature(env, ARM_FEATURE_VFP3)) { |
293 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
294 |
35, "arm-vfp3.xml", 0); |
295 |
} else if (arm_feature(env, ARM_FEATURE_VFP)) { |
296 |
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, |
297 |
19, "arm-vfp.xml", 0); |
298 |
} |
299 |
qemu_init_vcpu(env); |
300 |
return env;
|
301 |
} |
302 |
|
303 |
struct arm_cpu_t {
|
304 |
uint32_t id; |
305 |
const char *name; |
306 |
}; |
307 |
|
308 |
static const struct arm_cpu_t arm_cpu_names[] = { |
309 |
{ ARM_CPUID_ARM926, "arm926"},
|
310 |
{ ARM_CPUID_ARM946, "arm946"},
|
311 |
{ ARM_CPUID_ARM1026, "arm1026"},
|
312 |
{ ARM_CPUID_ARM1136, "arm1136"},
|
313 |
{ ARM_CPUID_ARM1136_R2, "arm1136-r2"},
|
314 |
{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
|
315 |
{ ARM_CPUID_CORTEXM3, "cortex-m3"},
|
316 |
{ ARM_CPUID_CORTEXA8, "cortex-a8"},
|
317 |
{ ARM_CPUID_CORTEXA9, "cortex-a9"},
|
318 |
{ ARM_CPUID_TI925T, "ti925t" },
|
319 |
{ ARM_CPUID_PXA250, "pxa250" },
|
320 |
{ ARM_CPUID_PXA255, "pxa255" },
|
321 |
{ ARM_CPUID_PXA260, "pxa260" },
|
322 |
{ ARM_CPUID_PXA261, "pxa261" },
|
323 |
{ ARM_CPUID_PXA262, "pxa262" },
|
324 |
{ ARM_CPUID_PXA270, "pxa270" },
|
325 |
{ ARM_CPUID_PXA270_A0, "pxa270-a0" },
|
326 |
{ ARM_CPUID_PXA270_A1, "pxa270-a1" },
|
327 |
{ ARM_CPUID_PXA270_B0, "pxa270-b0" },
|
328 |
{ ARM_CPUID_PXA270_B1, "pxa270-b1" },
|
329 |
{ ARM_CPUID_PXA270_C0, "pxa270-c0" },
|
330 |
{ ARM_CPUID_PXA270_C5, "pxa270-c5" },
|
331 |
{ ARM_CPUID_ANY, "any"},
|
332 |
{ 0, NULL} |
333 |
}; |
334 |
|
335 |
void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
336 |
{ |
337 |
int i;
|
338 |
|
339 |
(*cpu_fprintf)(f, "Available CPUs:\n");
|
340 |
for (i = 0; arm_cpu_names[i].name; i++) { |
341 |
(*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
|
342 |
} |
343 |
} |
344 |
|
345 |
/* return 0 if not found */
|
346 |
static uint32_t cpu_arm_find_by_name(const char *name) |
347 |
{ |
348 |
int i;
|
349 |
uint32_t id; |
350 |
|
351 |
id = 0;
|
352 |
for (i = 0; arm_cpu_names[i].name; i++) { |
353 |
if (strcmp(name, arm_cpu_names[i].name) == 0) { |
354 |
id = arm_cpu_names[i].id; |
355 |
break;
|
356 |
} |
357 |
} |
358 |
return id;
|
359 |
} |
360 |
|
361 |
void cpu_arm_close(CPUARMState *env)
|
362 |
{ |
363 |
free(env); |
364 |
} |
365 |
|
366 |
uint32_t cpsr_read(CPUARMState *env) |
367 |
{ |
368 |
int ZF;
|
369 |
ZF = (env->ZF == 0);
|
370 |
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | |
371 |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
372 |
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25) |
373 |
| ((env->condexec_bits & 0xfc) << 8) |
374 |
| (env->GE << 16);
|
375 |
} |
376 |
|
377 |
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
|
378 |
{ |
379 |
if (mask & CPSR_NZCV) {
|
380 |
env->ZF = (~val) & CPSR_Z; |
381 |
env->NF = val; |
382 |
env->CF = (val >> 29) & 1; |
383 |
env->VF = (val << 3) & 0x80000000; |
384 |
} |
385 |
if (mask & CPSR_Q)
|
386 |
env->QF = ((val & CPSR_Q) != 0);
|
387 |
if (mask & CPSR_T)
|
388 |
env->thumb = ((val & CPSR_T) != 0);
|
389 |
if (mask & CPSR_IT_0_1) {
|
390 |
env->condexec_bits &= ~3;
|
391 |
env->condexec_bits |= (val >> 25) & 3; |
392 |
} |
393 |
if (mask & CPSR_IT_2_7) {
|
394 |
env->condexec_bits &= 3;
|
395 |
env->condexec_bits |= (val >> 8) & 0xfc; |
396 |
} |
397 |
if (mask & CPSR_GE) {
|
398 |
env->GE = (val >> 16) & 0xf; |
399 |
} |
400 |
|
401 |
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
|
402 |
switch_mode(env, val & CPSR_M); |
403 |
} |
404 |
mask &= ~CACHED_CPSR_BITS; |
405 |
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
406 |
} |
407 |
|
408 |
/* Sign/zero extend */
|
409 |
uint32_t HELPER(sxtb16)(uint32_t x) |
410 |
{ |
411 |
uint32_t res; |
412 |
res = (uint16_t)(int8_t)x; |
413 |
res |= (uint32_t)(int8_t)(x >> 16) << 16; |
414 |
return res;
|
415 |
} |
416 |
|
417 |
uint32_t HELPER(uxtb16)(uint32_t x) |
418 |
{ |
419 |
uint32_t res; |
420 |
res = (uint16_t)(uint8_t)x; |
421 |
res |= (uint32_t)(uint8_t)(x >> 16) << 16; |
422 |
return res;
|
423 |
} |
424 |
|
425 |
uint32_t HELPER(clz)(uint32_t x) |
426 |
{ |
427 |
return clz32(x);
|
428 |
} |
429 |
|
430 |
int32_t HELPER(sdiv)(int32_t num, int32_t den) |
431 |
{ |
432 |
if (den == 0) |
433 |
return 0; |
434 |
if (num == INT_MIN && den == -1) |
435 |
return INT_MIN;
|
436 |
return num / den;
|
437 |
} |
438 |
|
439 |
uint32_t HELPER(udiv)(uint32_t num, uint32_t den) |
440 |
{ |
441 |
if (den == 0) |
442 |
return 0; |
443 |
return num / den;
|
444 |
} |
445 |
|
446 |
uint32_t HELPER(rbit)(uint32_t x) |
447 |
{ |
448 |
x = ((x & 0xff000000) >> 24) |
449 |
| ((x & 0x00ff0000) >> 8) |
450 |
| ((x & 0x0000ff00) << 8) |
451 |
| ((x & 0x000000ff) << 24); |
452 |
x = ((x & 0xf0f0f0f0) >> 4) |
453 |
| ((x & 0x0f0f0f0f) << 4); |
454 |
x = ((x & 0x88888888) >> 3) |
455 |
| ((x & 0x44444444) >> 1) |
456 |
| ((x & 0x22222222) << 1) |
457 |
| ((x & 0x11111111) << 3); |
458 |
return x;
|
459 |
} |
460 |
|
461 |
uint32_t HELPER(abs)(uint32_t x) |
462 |
{ |
463 |
return ((int32_t)x < 0) ? -x : x; |
464 |
} |
465 |
|
466 |
#if defined(CONFIG_USER_ONLY)
|
467 |
|
468 |
void do_interrupt (CPUState *env)
|
469 |
{ |
470 |
env->exception_index = -1;
|
471 |
} |
472 |
|
473 |
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
474 |
int mmu_idx, int is_softmmu) |
475 |
{ |
476 |
if (rw == 2) { |
477 |
env->exception_index = EXCP_PREFETCH_ABORT; |
478 |
env->cp15.c6_insn = address; |
479 |
} else {
|
480 |
env->exception_index = EXCP_DATA_ABORT; |
481 |
env->cp15.c6_data = address; |
482 |
} |
483 |
return 1; |
484 |
} |
485 |
|
486 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
487 |
{ |
488 |
return addr;
|
489 |
} |
490 |
|
491 |
/* These should probably raise undefined insn exceptions. */
|
492 |
void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
|
493 |
{ |
494 |
int op1 = (insn >> 8) & 0xf; |
495 |
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
496 |
return;
|
497 |
} |
498 |
|
499 |
uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
500 |
{ |
501 |
int op1 = (insn >> 8) & 0xf; |
502 |
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
|
503 |
return 0; |
504 |
} |
505 |
|
506 |
void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
|
507 |
{ |
508 |
cpu_abort(env, "cp15 insn %08x\n", insn);
|
509 |
} |
510 |
|
511 |
uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
512 |
{ |
513 |
cpu_abort(env, "cp15 insn %08x\n", insn);
|
514 |
} |
515 |
|
516 |
/* These should probably raise undefined insn exceptions. */
|
517 |
void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
|
518 |
{ |
519 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
520 |
} |
521 |
|
522 |
uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
523 |
{ |
524 |
cpu_abort(env, "v7m_mrs %d\n", reg);
|
525 |
return 0; |
526 |
} |
527 |
|
528 |
void switch_mode(CPUState *env, int mode) |
529 |
{ |
530 |
if (mode != ARM_CPU_MODE_USR)
|
531 |
cpu_abort(env, "Tried to switch out of user mode\n");
|
532 |
} |
533 |
|
534 |
void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
|
535 |
{ |
536 |
cpu_abort(env, "banked r13 write\n");
|
537 |
} |
538 |
|
539 |
uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
540 |
{ |
541 |
cpu_abort(env, "banked r13 read\n");
|
542 |
return 0; |
543 |
} |
544 |
|
545 |
#else
|
546 |
|
547 |
extern int semihosting_enabled; |
548 |
|
549 |
/* Map CPU modes onto saved register banks. */
|
550 |
static inline int bank_number (int mode) |
551 |
{ |
552 |
switch (mode) {
|
553 |
case ARM_CPU_MODE_USR:
|
554 |
case ARM_CPU_MODE_SYS:
|
555 |
return 0; |
556 |
case ARM_CPU_MODE_SVC:
|
557 |
return 1; |
558 |
case ARM_CPU_MODE_ABT:
|
559 |
return 2; |
560 |
case ARM_CPU_MODE_UND:
|
561 |
return 3; |
562 |
case ARM_CPU_MODE_IRQ:
|
563 |
return 4; |
564 |
case ARM_CPU_MODE_FIQ:
|
565 |
return 5; |
566 |
} |
567 |
cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
|
568 |
return -1; |
569 |
} |
570 |
|
571 |
void switch_mode(CPUState *env, int mode) |
572 |
{ |
573 |
int old_mode;
|
574 |
int i;
|
575 |
|
576 |
old_mode = env->uncached_cpsr & CPSR_M; |
577 |
if (mode == old_mode)
|
578 |
return;
|
579 |
|
580 |
if (old_mode == ARM_CPU_MODE_FIQ) {
|
581 |
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
582 |
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
583 |
} else if (mode == ARM_CPU_MODE_FIQ) { |
584 |
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
585 |
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
586 |
} |
587 |
|
588 |
i = bank_number(old_mode); |
589 |
env->banked_r13[i] = env->regs[13];
|
590 |
env->banked_r14[i] = env->regs[14];
|
591 |
env->banked_spsr[i] = env->spsr; |
592 |
|
593 |
i = bank_number(mode); |
594 |
env->regs[13] = env->banked_r13[i];
|
595 |
env->regs[14] = env->banked_r14[i];
|
596 |
env->spsr = env->banked_spsr[i]; |
597 |
} |
598 |
|
599 |
static void v7m_push(CPUARMState *env, uint32_t val) |
600 |
{ |
601 |
env->regs[13] -= 4; |
602 |
stl_phys(env->regs[13], val);
|
603 |
} |
604 |
|
605 |
static uint32_t v7m_pop(CPUARMState *env)
|
606 |
{ |
607 |
uint32_t val; |
608 |
val = ldl_phys(env->regs[13]);
|
609 |
env->regs[13] += 4; |
610 |
return val;
|
611 |
} |
612 |
|
613 |
/* Switch to V7M main or process stack pointer. */
|
614 |
static void switch_v7m_sp(CPUARMState *env, int process) |
615 |
{ |
616 |
uint32_t tmp; |
617 |
if (env->v7m.current_sp != process) {
|
618 |
tmp = env->v7m.other_sp; |
619 |
env->v7m.other_sp = env->regs[13];
|
620 |
env->regs[13] = tmp;
|
621 |
env->v7m.current_sp = process; |
622 |
} |
623 |
} |
624 |
|
625 |
static void do_v7m_exception_exit(CPUARMState *env) |
626 |
{ |
627 |
uint32_t type; |
628 |
uint32_t xpsr; |
629 |
|
630 |
type = env->regs[15];
|
631 |
if (env->v7m.exception != 0) |
632 |
armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception); |
633 |
|
634 |
/* Switch to the target stack. */
|
635 |
switch_v7m_sp(env, (type & 4) != 0); |
636 |
/* Pop registers. */
|
637 |
env->regs[0] = v7m_pop(env);
|
638 |
env->regs[1] = v7m_pop(env);
|
639 |
env->regs[2] = v7m_pop(env);
|
640 |
env->regs[3] = v7m_pop(env);
|
641 |
env->regs[12] = v7m_pop(env);
|
642 |
env->regs[14] = v7m_pop(env);
|
643 |
env->regs[15] = v7m_pop(env);
|
644 |
xpsr = v7m_pop(env); |
645 |
xpsr_write(env, xpsr, 0xfffffdff);
|
646 |
/* Undo stack alignment. */
|
647 |
if (xpsr & 0x200) |
648 |
env->regs[13] |= 4; |
649 |
/* ??? The exception return type specifies Thread/Handler mode. However
|
650 |
this is also implied by the xPSR value. Not sure what to do
|
651 |
if there is a mismatch. */
|
652 |
/* ??? Likewise for mismatches between the CONTROL register and the stack
|
653 |
pointer. */
|
654 |
} |
655 |
|
656 |
static void do_interrupt_v7m(CPUARMState *env) |
657 |
{ |
658 |
uint32_t xpsr = xpsr_read(env); |
659 |
uint32_t lr; |
660 |
uint32_t addr; |
661 |
|
662 |
lr = 0xfffffff1;
|
663 |
if (env->v7m.current_sp)
|
664 |
lr |= 4;
|
665 |
if (env->v7m.exception == 0) |
666 |
lr |= 8;
|
667 |
|
668 |
/* For exceptions we just mark as pending on the NVIC, and let that
|
669 |
handle it. */
|
670 |
/* TODO: Need to escalate if the current priority is higher than the
|
671 |
one we're raising. */
|
672 |
switch (env->exception_index) {
|
673 |
case EXCP_UDEF:
|
674 |
armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE); |
675 |
return;
|
676 |
case EXCP_SWI:
|
677 |
env->regs[15] += 2; |
678 |
armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC); |
679 |
return;
|
680 |
case EXCP_PREFETCH_ABORT:
|
681 |
case EXCP_DATA_ABORT:
|
682 |
armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM); |
683 |
return;
|
684 |
case EXCP_BKPT:
|
685 |
if (semihosting_enabled) {
|
686 |
int nr;
|
687 |
nr = lduw_code(env->regs[15]) & 0xff; |
688 |
if (nr == 0xab) { |
689 |
env->regs[15] += 2; |
690 |
env->regs[0] = do_arm_semihosting(env);
|
691 |
return;
|
692 |
} |
693 |
} |
694 |
armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG); |
695 |
return;
|
696 |
case EXCP_IRQ:
|
697 |
env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic); |
698 |
break;
|
699 |
case EXCP_EXCEPTION_EXIT:
|
700 |
do_v7m_exception_exit(env); |
701 |
return;
|
702 |
default:
|
703 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
704 |
return; /* Never happens. Keep compiler happy. */ |
705 |
} |
706 |
|
707 |
/* Align stack pointer. */
|
708 |
/* ??? Should only do this if Configuration Control Register
|
709 |
STACKALIGN bit is set. */
|
710 |
if (env->regs[13] & 4) { |
711 |
env->regs[13] -= 4; |
712 |
xpsr |= 0x200;
|
713 |
} |
714 |
/* Switch to the handler mode. */
|
715 |
v7m_push(env, xpsr); |
716 |
v7m_push(env, env->regs[15]);
|
717 |
v7m_push(env, env->regs[14]);
|
718 |
v7m_push(env, env->regs[12]);
|
719 |
v7m_push(env, env->regs[3]);
|
720 |
v7m_push(env, env->regs[2]);
|
721 |
v7m_push(env, env->regs[1]);
|
722 |
v7m_push(env, env->regs[0]);
|
723 |
switch_v7m_sp(env, 0);
|
724 |
env->uncached_cpsr &= ~CPSR_IT; |
725 |
env->regs[14] = lr;
|
726 |
addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
|
727 |
env->regs[15] = addr & 0xfffffffe; |
728 |
env->thumb = addr & 1;
|
729 |
} |
730 |
|
731 |
/* Handle a CPU exception. */
|
732 |
void do_interrupt(CPUARMState *env)
|
733 |
{ |
734 |
uint32_t addr; |
735 |
uint32_t mask; |
736 |
int new_mode;
|
737 |
uint32_t offset; |
738 |
|
739 |
if (IS_M(env)) {
|
740 |
do_interrupt_v7m(env); |
741 |
return;
|
742 |
} |
743 |
/* TODO: Vectored interrupt controller. */
|
744 |
switch (env->exception_index) {
|
745 |
case EXCP_UDEF:
|
746 |
new_mode = ARM_CPU_MODE_UND; |
747 |
addr = 0x04;
|
748 |
mask = CPSR_I; |
749 |
if (env->thumb)
|
750 |
offset = 2;
|
751 |
else
|
752 |
offset = 4;
|
753 |
break;
|
754 |
case EXCP_SWI:
|
755 |
if (semihosting_enabled) {
|
756 |
/* Check for semihosting interrupt. */
|
757 |
if (env->thumb) {
|
758 |
mask = lduw_code(env->regs[15] - 2) & 0xff; |
759 |
} else {
|
760 |
mask = ldl_code(env->regs[15] - 4) & 0xffffff; |
761 |
} |
762 |
/* Only intercept calls from privileged modes, to provide some
|
763 |
semblance of security. */
|
764 |
if (((mask == 0x123456 && !env->thumb) |
765 |
|| (mask == 0xab && env->thumb))
|
766 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
767 |
env->regs[0] = do_arm_semihosting(env);
|
768 |
return;
|
769 |
} |
770 |
} |
771 |
new_mode = ARM_CPU_MODE_SVC; |
772 |
addr = 0x08;
|
773 |
mask = CPSR_I; |
774 |
/* The PC already points to the next instruction. */
|
775 |
offset = 0;
|
776 |
break;
|
777 |
case EXCP_BKPT:
|
778 |
/* See if this is a semihosting syscall. */
|
779 |
if (env->thumb && semihosting_enabled) {
|
780 |
mask = lduw_code(env->regs[15]) & 0xff; |
781 |
if (mask == 0xab |
782 |
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { |
783 |
env->regs[15] += 2; |
784 |
env->regs[0] = do_arm_semihosting(env);
|
785 |
return;
|
786 |
} |
787 |
} |
788 |
/* Fall through to prefetch abort. */
|
789 |
case EXCP_PREFETCH_ABORT:
|
790 |
new_mode = ARM_CPU_MODE_ABT; |
791 |
addr = 0x0c;
|
792 |
mask = CPSR_A | CPSR_I; |
793 |
offset = 4;
|
794 |
break;
|
795 |
case EXCP_DATA_ABORT:
|
796 |
new_mode = ARM_CPU_MODE_ABT; |
797 |
addr = 0x10;
|
798 |
mask = CPSR_A | CPSR_I; |
799 |
offset = 8;
|
800 |
break;
|
801 |
case EXCP_IRQ:
|
802 |
new_mode = ARM_CPU_MODE_IRQ; |
803 |
addr = 0x18;
|
804 |
/* Disable IRQ and imprecise data aborts. */
|
805 |
mask = CPSR_A | CPSR_I; |
806 |
offset = 4;
|
807 |
break;
|
808 |
case EXCP_FIQ:
|
809 |
new_mode = ARM_CPU_MODE_FIQ; |
810 |
addr = 0x1c;
|
811 |
/* Disable FIQ, IRQ and imprecise data aborts. */
|
812 |
mask = CPSR_A | CPSR_I | CPSR_F; |
813 |
offset = 4;
|
814 |
break;
|
815 |
default:
|
816 |
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
|
817 |
return; /* Never happens. Keep compiler happy. */ |
818 |
} |
819 |
/* High vectors. */
|
820 |
if (env->cp15.c1_sys & (1 << 13)) { |
821 |
addr += 0xffff0000;
|
822 |
} |
823 |
switch_mode (env, new_mode); |
824 |
env->spsr = cpsr_read(env); |
825 |
/* Clear IT bits. */
|
826 |
env->condexec_bits = 0;
|
827 |
/* Switch to the new mode, and to the correct instruction set. */
|
828 |
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
829 |
env->uncached_cpsr |= mask; |
830 |
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0; |
831 |
env->regs[14] = env->regs[15] + offset; |
832 |
env->regs[15] = addr;
|
833 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
834 |
} |
835 |
|
836 |
/* Check section/page access permissions.
|
837 |
Returns the page protection flags, or zero if the access is not
|
838 |
permitted. */
|
839 |
static inline int check_ap(CPUState *env, int ap, int domain, int access_type, |
840 |
int is_user)
|
841 |
{ |
842 |
int prot_ro;
|
843 |
|
844 |
if (domain == 3) |
845 |
return PAGE_READ | PAGE_WRITE;
|
846 |
|
847 |
if (access_type == 1) |
848 |
prot_ro = 0;
|
849 |
else
|
850 |
prot_ro = PAGE_READ; |
851 |
|
852 |
switch (ap) {
|
853 |
case 0: |
854 |
if (access_type == 1) |
855 |
return 0; |
856 |
switch ((env->cp15.c1_sys >> 8) & 3) { |
857 |
case 1: |
858 |
return is_user ? 0 : PAGE_READ; |
859 |
case 2: |
860 |
return PAGE_READ;
|
861 |
default:
|
862 |
return 0; |
863 |
} |
864 |
case 1: |
865 |
return is_user ? 0 : PAGE_READ | PAGE_WRITE; |
866 |
case 2: |
867 |
if (is_user)
|
868 |
return prot_ro;
|
869 |
else
|
870 |
return PAGE_READ | PAGE_WRITE;
|
871 |
case 3: |
872 |
return PAGE_READ | PAGE_WRITE;
|
873 |
case 4: /* Reserved. */ |
874 |
return 0; |
875 |
case 5: |
876 |
return is_user ? 0 : prot_ro; |
877 |
case 6: |
878 |
return prot_ro;
|
879 |
case 7: |
880 |
if (!arm_feature (env, ARM_FEATURE_V7))
|
881 |
return 0; |
882 |
return prot_ro;
|
883 |
default:
|
884 |
abort(); |
885 |
} |
886 |
} |
887 |
|
888 |
static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
|
889 |
{ |
890 |
uint32_t table; |
891 |
|
892 |
if (address & env->cp15.c2_mask)
|
893 |
table = env->cp15.c2_base1 & 0xffffc000;
|
894 |
else
|
895 |
table = env->cp15.c2_base0 & env->cp15.c2_base_mask; |
896 |
|
897 |
table |= (address >> 18) & 0x3ffc; |
898 |
return table;
|
899 |
} |
900 |
|
901 |
static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type, |
902 |
int is_user, uint32_t *phys_ptr, int *prot) |
903 |
{ |
904 |
int code;
|
905 |
uint32_t table; |
906 |
uint32_t desc; |
907 |
int type;
|
908 |
int ap;
|
909 |
int domain;
|
910 |
uint32_t phys_addr; |
911 |
|
912 |
/* Pagetable walk. */
|
913 |
/* Lookup l1 descriptor. */
|
914 |
table = get_level1_table_address(env, address); |
915 |
desc = ldl_phys(table); |
916 |
type = (desc & 3);
|
917 |
domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3; |
918 |
if (type == 0) { |
919 |
/* Section translation fault. */
|
920 |
code = 5;
|
921 |
goto do_fault;
|
922 |
} |
923 |
if (domain == 0 || domain == 2) { |
924 |
if (type == 2) |
925 |
code = 9; /* Section domain fault. */ |
926 |
else
|
927 |
code = 11; /* Page domain fault. */ |
928 |
goto do_fault;
|
929 |
} |
930 |
if (type == 2) { |
931 |
/* 1Mb section. */
|
932 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
933 |
ap = (desc >> 10) & 3; |
934 |
code = 13;
|
935 |
} else {
|
936 |
/* Lookup l2 entry. */
|
937 |
if (type == 1) { |
938 |
/* Coarse pagetable. */
|
939 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
940 |
} else {
|
941 |
/* Fine pagetable. */
|
942 |
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); |
943 |
} |
944 |
desc = ldl_phys(table); |
945 |
switch (desc & 3) { |
946 |
case 0: /* Page translation fault. */ |
947 |
code = 7;
|
948 |
goto do_fault;
|
949 |
case 1: /* 64k page. */ |
950 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
951 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
952 |
break;
|
953 |
case 2: /* 4k page. */ |
954 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
955 |
ap = (desc >> (4 + ((address >> 13) & 6))) & 3; |
956 |
break;
|
957 |
case 3: /* 1k page. */ |
958 |
if (type == 1) { |
959 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
960 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
961 |
} else {
|
962 |
/* Page translation fault. */
|
963 |
code = 7;
|
964 |
goto do_fault;
|
965 |
} |
966 |
} else {
|
967 |
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); |
968 |
} |
969 |
ap = (desc >> 4) & 3; |
970 |
break;
|
971 |
default:
|
972 |
/* Never happens, but compiler isn't smart enough to tell. */
|
973 |
abort(); |
974 |
} |
975 |
code = 15;
|
976 |
} |
977 |
*prot = check_ap(env, ap, domain, access_type, is_user); |
978 |
if (!*prot) {
|
979 |
/* Access permission fault. */
|
980 |
goto do_fault;
|
981 |
} |
982 |
*phys_ptr = phys_addr; |
983 |
return 0; |
984 |
do_fault:
|
985 |
return code | (domain << 4); |
986 |
} |
987 |
|
988 |
static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type, |
989 |
int is_user, uint32_t *phys_ptr, int *prot) |
990 |
{ |
991 |
int code;
|
992 |
uint32_t table; |
993 |
uint32_t desc; |
994 |
uint32_t xn; |
995 |
int type;
|
996 |
int ap;
|
997 |
int domain;
|
998 |
uint32_t phys_addr; |
999 |
|
1000 |
/* Pagetable walk. */
|
1001 |
/* Lookup l1 descriptor. */
|
1002 |
table = get_level1_table_address(env, address); |
1003 |
desc = ldl_phys(table); |
1004 |
type = (desc & 3);
|
1005 |
if (type == 0) { |
1006 |
/* Section translation fault. */
|
1007 |
code = 5;
|
1008 |
domain = 0;
|
1009 |
goto do_fault;
|
1010 |
} else if (type == 2 && (desc & (1 << 18))) { |
1011 |
/* Supersection. */
|
1012 |
domain = 0;
|
1013 |
} else {
|
1014 |
/* Section or page. */
|
1015 |
domain = (desc >> 4) & 0x1e; |
1016 |
} |
1017 |
domain = (env->cp15.c3 >> domain) & 3;
|
1018 |
if (domain == 0 || domain == 2) { |
1019 |
if (type == 2) |
1020 |
code = 9; /* Section domain fault. */ |
1021 |
else
|
1022 |
code = 11; /* Page domain fault. */ |
1023 |
goto do_fault;
|
1024 |
} |
1025 |
if (type == 2) { |
1026 |
if (desc & (1 << 18)) { |
1027 |
/* Supersection. */
|
1028 |
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); |
1029 |
} else {
|
1030 |
/* Section. */
|
1031 |
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); |
1032 |
} |
1033 |
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
1034 |
xn = desc & (1 << 4); |
1035 |
code = 13;
|
1036 |
} else {
|
1037 |
/* Lookup l2 entry. */
|
1038 |
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); |
1039 |
desc = ldl_phys(table); |
1040 |
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
1041 |
switch (desc & 3) { |
1042 |
case 0: /* Page translation fault. */ |
1043 |
code = 7;
|
1044 |
goto do_fault;
|
1045 |
case 1: /* 64k page. */ |
1046 |
phys_addr = (desc & 0xffff0000) | (address & 0xffff); |
1047 |
xn = desc & (1 << 15); |
1048 |
break;
|
1049 |
case 2: case 3: /* 4k page. */ |
1050 |
phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
1051 |
xn = desc & 1;
|
1052 |
break;
|
1053 |
default:
|
1054 |
/* Never happens, but compiler isn't smart enough to tell. */
|
1055 |
abort(); |
1056 |
} |
1057 |
code = 15;
|
1058 |
} |
1059 |
if (xn && access_type == 2) |
1060 |
goto do_fault;
|
1061 |
|
1062 |
/* The simplified model uses AP[0] as an access control bit. */
|
1063 |
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) { |
1064 |
/* Access flag fault. */
|
1065 |
code = (code == 15) ? 6 : 3; |
1066 |
goto do_fault;
|
1067 |
} |
1068 |
*prot = check_ap(env, ap, domain, access_type, is_user); |
1069 |
if (!*prot) {
|
1070 |
/* Access permission fault. */
|
1071 |
goto do_fault;
|
1072 |
} |
1073 |
*phys_ptr = phys_addr; |
1074 |
return 0; |
1075 |
do_fault:
|
1076 |
return code | (domain << 4); |
1077 |
} |
1078 |
|
1079 |
static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type, |
1080 |
int is_user, uint32_t *phys_ptr, int *prot) |
1081 |
{ |
1082 |
int n;
|
1083 |
uint32_t mask; |
1084 |
uint32_t base; |
1085 |
|
1086 |
*phys_ptr = address; |
1087 |
for (n = 7; n >= 0; n--) { |
1088 |
base = env->cp15.c6_region[n]; |
1089 |
if ((base & 1) == 0) |
1090 |
continue;
|
1091 |
mask = 1 << ((base >> 1) & 0x1f); |
1092 |
/* Keep this shift separate from the above to avoid an
|
1093 |
(undefined) << 32. */
|
1094 |
mask = (mask << 1) - 1; |
1095 |
if (((base ^ address) & ~mask) == 0) |
1096 |
break;
|
1097 |
} |
1098 |
if (n < 0) |
1099 |
return 2; |
1100 |
|
1101 |
if (access_type == 2) { |
1102 |
mask = env->cp15.c5_insn; |
1103 |
} else {
|
1104 |
mask = env->cp15.c5_data; |
1105 |
} |
1106 |
mask = (mask >> (n * 4)) & 0xf; |
1107 |
switch (mask) {
|
1108 |
case 0: |
1109 |
return 1; |
1110 |
case 1: |
1111 |
if (is_user)
|
1112 |
return 1; |
1113 |
*prot = PAGE_READ | PAGE_WRITE; |
1114 |
break;
|
1115 |
case 2: |
1116 |
*prot = PAGE_READ; |
1117 |
if (!is_user)
|
1118 |
*prot |= PAGE_WRITE; |
1119 |
break;
|
1120 |
case 3: |
1121 |
*prot = PAGE_READ | PAGE_WRITE; |
1122 |
break;
|
1123 |
case 5: |
1124 |
if (is_user)
|
1125 |
return 1; |
1126 |
*prot = PAGE_READ; |
1127 |
break;
|
1128 |
case 6: |
1129 |
*prot = PAGE_READ; |
1130 |
break;
|
1131 |
default:
|
1132 |
/* Bad permission. */
|
1133 |
return 1; |
1134 |
} |
1135 |
return 0; |
1136 |
} |
1137 |
|
1138 |
static inline int get_phys_addr(CPUState *env, uint32_t address, |
1139 |
int access_type, int is_user, |
1140 |
uint32_t *phys_ptr, int *prot)
|
1141 |
{ |
1142 |
/* Fast Context Switch Extension. */
|
1143 |
if (address < 0x02000000) |
1144 |
address += env->cp15.c13_fcse; |
1145 |
|
1146 |
if ((env->cp15.c1_sys & 1) == 0) { |
1147 |
/* MMU/MPU disabled. */
|
1148 |
*phys_ptr = address; |
1149 |
*prot = PAGE_READ | PAGE_WRITE; |
1150 |
return 0; |
1151 |
} else if (arm_feature(env, ARM_FEATURE_MPU)) { |
1152 |
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
|
1153 |
prot); |
1154 |
} else if (env->cp15.c1_sys & (1 << 23)) { |
1155 |
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
|
1156 |
prot); |
1157 |
} else {
|
1158 |
return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
|
1159 |
prot); |
1160 |
} |
1161 |
} |
1162 |
|
1163 |
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
|
1164 |
int access_type, int mmu_idx, int is_softmmu) |
1165 |
{ |
1166 |
uint32_t phys_addr; |
1167 |
int prot;
|
1168 |
int ret, is_user;
|
1169 |
|
1170 |
is_user = mmu_idx == MMU_USER_IDX; |
1171 |
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot); |
1172 |
if (ret == 0) { |
1173 |
/* Map a single [sub]page. */
|
1174 |
phys_addr &= ~(uint32_t)0x3ff;
|
1175 |
address &= ~(uint32_t)0x3ff;
|
1176 |
return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
|
1177 |
is_softmmu); |
1178 |
} |
1179 |
|
1180 |
if (access_type == 2) { |
1181 |
env->cp15.c5_insn = ret; |
1182 |
env->cp15.c6_insn = address; |
1183 |
env->exception_index = EXCP_PREFETCH_ABORT; |
1184 |
} else {
|
1185 |
env->cp15.c5_data = ret; |
1186 |
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) |
1187 |
env->cp15.c5_data |= (1 << 11); |
1188 |
env->cp15.c6_data = address; |
1189 |
env->exception_index = EXCP_DATA_ABORT; |
1190 |
} |
1191 |
return 1; |
1192 |
} |
1193 |
|
1194 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
1195 |
{ |
1196 |
uint32_t phys_addr; |
1197 |
int prot;
|
1198 |
int ret;
|
1199 |
|
1200 |
ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot); |
1201 |
|
1202 |
if (ret != 0) |
1203 |
return -1; |
1204 |
|
1205 |
return phys_addr;
|
1206 |
} |
1207 |
|
1208 |
void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
|
1209 |
{ |
1210 |
int cp_num = (insn >> 8) & 0xf; |
1211 |
int cp_info = (insn >> 5) & 7; |
1212 |
int src = (insn >> 16) & 0xf; |
1213 |
int operand = insn & 0xf; |
1214 |
|
1215 |
if (env->cp[cp_num].cp_write)
|
1216 |
env->cp[cp_num].cp_write(env->cp[cp_num].opaque, |
1217 |
cp_info, src, operand, val); |
1218 |
} |
1219 |
|
1220 |
uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) |
1221 |
{ |
1222 |
int cp_num = (insn >> 8) & 0xf; |
1223 |
int cp_info = (insn >> 5) & 7; |
1224 |
int dest = (insn >> 16) & 0xf; |
1225 |
int operand = insn & 0xf; |
1226 |
|
1227 |
if (env->cp[cp_num].cp_read)
|
1228 |
return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
|
1229 |
cp_info, dest, operand); |
1230 |
return 0; |
1231 |
} |
1232 |
|
1233 |
/* Return basic MPU access permission bits. */
|
1234 |
static uint32_t simple_mpu_ap_bits(uint32_t val)
|
1235 |
{ |
1236 |
uint32_t ret; |
1237 |
uint32_t mask; |
1238 |
int i;
|
1239 |
ret = 0;
|
1240 |
mask = 3;
|
1241 |
for (i = 0; i < 16; i += 2) { |
1242 |
ret |= (val >> i) & mask; |
1243 |
mask <<= 2;
|
1244 |
} |
1245 |
return ret;
|
1246 |
} |
1247 |
|
1248 |
/* Pad basic MPU access permission bits to extended format. */
|
1249 |
static uint32_t extended_mpu_ap_bits(uint32_t val)
|
1250 |
{ |
1251 |
uint32_t ret; |
1252 |
uint32_t mask; |
1253 |
int i;
|
1254 |
ret = 0;
|
1255 |
mask = 3;
|
1256 |
for (i = 0; i < 16; i += 2) { |
1257 |
ret |= (val & mask) << i; |
1258 |
mask <<= 2;
|
1259 |
} |
1260 |
return ret;
|
1261 |
} |
1262 |
|
1263 |
void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
|
1264 |
{ |
1265 |
int op1;
|
1266 |
int op2;
|
1267 |
int crm;
|
1268 |
|
1269 |
op1 = (insn >> 21) & 7; |
1270 |
op2 = (insn >> 5) & 7; |
1271 |
crm = insn & 0xf;
|
1272 |
switch ((insn >> 16) & 0xf) { |
1273 |
case 0: |
1274 |
/* ID codes. */
|
1275 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1276 |
break;
|
1277 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1278 |
break;
|
1279 |
if (arm_feature(env, ARM_FEATURE_V7)
|
1280 |
&& op1 == 2 && crm == 0 && op2 == 0) { |
1281 |
env->cp15.c0_cssel = val & 0xf;
|
1282 |
break;
|
1283 |
} |
1284 |
goto bad_reg;
|
1285 |
case 1: /* System configuration. */ |
1286 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1287 |
op2 = 0;
|
1288 |
switch (op2) {
|
1289 |
case 0: |
1290 |
if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0) |
1291 |
env->cp15.c1_sys = val; |
1292 |
/* ??? Lots of these bits are not implemented. */
|
1293 |
/* This may enable/disable the MMU, so do a TLB flush. */
|
1294 |
tlb_flush(env, 1);
|
1295 |
break;
|
1296 |
case 1: /* Auxiliary cotrol register. */ |
1297 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1298 |
env->cp15.c1_xscaleauxcr = val; |
1299 |
break;
|
1300 |
} |
1301 |
/* Not implemented. */
|
1302 |
break;
|
1303 |
case 2: |
1304 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1305 |
goto bad_reg;
|
1306 |
if (env->cp15.c1_coproc != val) {
|
1307 |
env->cp15.c1_coproc = val; |
1308 |
/* ??? Is this safe when called from within a TB? */
|
1309 |
tb_flush(env); |
1310 |
} |
1311 |
break;
|
1312 |
default:
|
1313 |
goto bad_reg;
|
1314 |
} |
1315 |
break;
|
1316 |
case 2: /* MMU Page table control / MPU cache control. */ |
1317 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1318 |
switch (op2) {
|
1319 |
case 0: |
1320 |
env->cp15.c2_data = val; |
1321 |
break;
|
1322 |
case 1: |
1323 |
env->cp15.c2_insn = val; |
1324 |
break;
|
1325 |
default:
|
1326 |
goto bad_reg;
|
1327 |
} |
1328 |
} else {
|
1329 |
switch (op2) {
|
1330 |
case 0: |
1331 |
env->cp15.c2_base0 = val; |
1332 |
break;
|
1333 |
case 1: |
1334 |
env->cp15.c2_base1 = val; |
1335 |
break;
|
1336 |
case 2: |
1337 |
val &= 7;
|
1338 |
env->cp15.c2_control = val; |
1339 |
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
|
1340 |
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
|
1341 |
break;
|
1342 |
default:
|
1343 |
goto bad_reg;
|
1344 |
} |
1345 |
} |
1346 |
break;
|
1347 |
case 3: /* MMU Domain access control / MPU write buffer control. */ |
1348 |
env->cp15.c3 = val; |
1349 |
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ |
1350 |
break;
|
1351 |
case 4: /* Reserved. */ |
1352 |
goto bad_reg;
|
1353 |
case 5: /* MMU Fault status / MPU access permission. */ |
1354 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1355 |
op2 = 0;
|
1356 |
switch (op2) {
|
1357 |
case 0: |
1358 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
1359 |
val = extended_mpu_ap_bits(val); |
1360 |
env->cp15.c5_data = val; |
1361 |
break;
|
1362 |
case 1: |
1363 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
1364 |
val = extended_mpu_ap_bits(val); |
1365 |
env->cp15.c5_insn = val; |
1366 |
break;
|
1367 |
case 2: |
1368 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
1369 |
goto bad_reg;
|
1370 |
env->cp15.c5_data = val; |
1371 |
break;
|
1372 |
case 3: |
1373 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
1374 |
goto bad_reg;
|
1375 |
env->cp15.c5_insn = val; |
1376 |
break;
|
1377 |
default:
|
1378 |
goto bad_reg;
|
1379 |
} |
1380 |
break;
|
1381 |
case 6: /* MMU Fault address / MPU base/size. */ |
1382 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1383 |
if (crm >= 8) |
1384 |
goto bad_reg;
|
1385 |
env->cp15.c6_region[crm] = val; |
1386 |
} else {
|
1387 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1388 |
op2 = 0;
|
1389 |
switch (op2) {
|
1390 |
case 0: |
1391 |
env->cp15.c6_data = val; |
1392 |
break;
|
1393 |
case 1: /* ??? This is WFAR on armv6 */ |
1394 |
case 2: |
1395 |
env->cp15.c6_insn = val; |
1396 |
break;
|
1397 |
default:
|
1398 |
goto bad_reg;
|
1399 |
} |
1400 |
} |
1401 |
break;
|
1402 |
case 7: /* Cache control. */ |
1403 |
env->cp15.c15_i_max = 0x000;
|
1404 |
env->cp15.c15_i_min = 0xff0;
|
1405 |
/* No cache, so nothing to do. */
|
1406 |
/* ??? MPCore has VA to PA translation functions. */
|
1407 |
break;
|
1408 |
case 8: /* MMU TLB control. */ |
1409 |
switch (op2) {
|
1410 |
case 0: /* Invalidate all. */ |
1411 |
tlb_flush(env, 0);
|
1412 |
break;
|
1413 |
case 1: /* Invalidate single TLB entry. */ |
1414 |
#if 0
|
1415 |
/* ??? This is wrong for large pages and sections. */
|
1416 |
/* As an ugly hack to make linux work we always flush a 4K
|
1417 |
pages. */
|
1418 |
val &= 0xfffff000;
|
1419 |
tlb_flush_page(env, val);
|
1420 |
tlb_flush_page(env, val + 0x400);
|
1421 |
tlb_flush_page(env, val + 0x800);
|
1422 |
tlb_flush_page(env, val + 0xc00);
|
1423 |
#else
|
1424 |
tlb_flush(env, 1);
|
1425 |
#endif
|
1426 |
break;
|
1427 |
case 2: /* Invalidate on ASID. */ |
1428 |
tlb_flush(env, val == 0);
|
1429 |
break;
|
1430 |
case 3: /* Invalidate single entry on MVA. */ |
1431 |
/* ??? This is like case 1, but ignores ASID. */
|
1432 |
tlb_flush(env, 1);
|
1433 |
break;
|
1434 |
default:
|
1435 |
goto bad_reg;
|
1436 |
} |
1437 |
break;
|
1438 |
case 9: |
1439 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1440 |
break;
|
1441 |
switch (crm) {
|
1442 |
case 0: /* Cache lockdown. */ |
1443 |
switch (op1) {
|
1444 |
case 0: /* L1 cache. */ |
1445 |
switch (op2) {
|
1446 |
case 0: |
1447 |
env->cp15.c9_data = val; |
1448 |
break;
|
1449 |
case 1: |
1450 |
env->cp15.c9_insn = val; |
1451 |
break;
|
1452 |
default:
|
1453 |
goto bad_reg;
|
1454 |
} |
1455 |
break;
|
1456 |
case 1: /* L2 cache. */ |
1457 |
/* Ignore writes to L2 lockdown/auxiliary registers. */
|
1458 |
break;
|
1459 |
default:
|
1460 |
goto bad_reg;
|
1461 |
} |
1462 |
break;
|
1463 |
case 1: /* TCM memory region registers. */ |
1464 |
/* Not implemented. */
|
1465 |
goto bad_reg;
|
1466 |
default:
|
1467 |
goto bad_reg;
|
1468 |
} |
1469 |
break;
|
1470 |
case 10: /* MMU TLB lockdown. */ |
1471 |
/* ??? TLB lockdown not implemented. */
|
1472 |
break;
|
1473 |
case 12: /* Reserved. */ |
1474 |
goto bad_reg;
|
1475 |
case 13: /* Process ID. */ |
1476 |
switch (op2) {
|
1477 |
case 0: |
1478 |
/* Unlike real hardware the qemu TLB uses virtual addresses,
|
1479 |
not modified virtual addresses, so this causes a TLB flush.
|
1480 |
*/
|
1481 |
if (env->cp15.c13_fcse != val)
|
1482 |
tlb_flush(env, 1);
|
1483 |
env->cp15.c13_fcse = val; |
1484 |
break;
|
1485 |
case 1: |
1486 |
/* This changes the ASID, so do a TLB flush. */
|
1487 |
if (env->cp15.c13_context != val
|
1488 |
&& !arm_feature(env, ARM_FEATURE_MPU)) |
1489 |
tlb_flush(env, 0);
|
1490 |
env->cp15.c13_context = val; |
1491 |
break;
|
1492 |
default:
|
1493 |
goto bad_reg;
|
1494 |
} |
1495 |
break;
|
1496 |
case 14: /* Reserved. */ |
1497 |
goto bad_reg;
|
1498 |
case 15: /* Implementation specific. */ |
1499 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1500 |
if (op2 == 0 && crm == 1) { |
1501 |
if (env->cp15.c15_cpar != (val & 0x3fff)) { |
1502 |
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
|
1503 |
tb_flush(env); |
1504 |
env->cp15.c15_cpar = val & 0x3fff;
|
1505 |
} |
1506 |
break;
|
1507 |
} |
1508 |
goto bad_reg;
|
1509 |
} |
1510 |
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
1511 |
switch (crm) {
|
1512 |
case 0: |
1513 |
break;
|
1514 |
case 1: /* Set TI925T configuration. */ |
1515 |
env->cp15.c15_ticonfig = val & 0xe7;
|
1516 |
env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */ |
1517 |
ARM_CPUID_TI915T : ARM_CPUID_TI925T; |
1518 |
break;
|
1519 |
case 2: /* Set I_max. */ |
1520 |
env->cp15.c15_i_max = val; |
1521 |
break;
|
1522 |
case 3: /* Set I_min. */ |
1523 |
env->cp15.c15_i_min = val; |
1524 |
break;
|
1525 |
case 4: /* Set thread-ID. */ |
1526 |
env->cp15.c15_threadid = val & 0xffff;
|
1527 |
break;
|
1528 |
case 8: /* Wait-for-interrupt (deprecated). */ |
1529 |
cpu_interrupt(env, CPU_INTERRUPT_HALT); |
1530 |
break;
|
1531 |
default:
|
1532 |
goto bad_reg;
|
1533 |
} |
1534 |
} |
1535 |
break;
|
1536 |
} |
1537 |
return;
|
1538 |
bad_reg:
|
1539 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
1540 |
cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
|
1541 |
(insn >> 16) & 0xf, crm, op1, op2); |
1542 |
} |
1543 |
|
1544 |
uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) |
1545 |
{ |
1546 |
int op1;
|
1547 |
int op2;
|
1548 |
int crm;
|
1549 |
|
1550 |
op1 = (insn >> 21) & 7; |
1551 |
op2 = (insn >> 5) & 7; |
1552 |
crm = insn & 0xf;
|
1553 |
switch ((insn >> 16) & 0xf) { |
1554 |
case 0: /* ID codes. */ |
1555 |
switch (op1) {
|
1556 |
case 0: |
1557 |
switch (crm) {
|
1558 |
case 0: |
1559 |
switch (op2) {
|
1560 |
case 0: /* Device ID. */ |
1561 |
return env->cp15.c0_cpuid;
|
1562 |
case 1: /* Cache Type. */ |
1563 |
return env->cp15.c0_cachetype;
|
1564 |
case 2: /* TCM status. */ |
1565 |
return 0; |
1566 |
case 3: /* TLB type register. */ |
1567 |
return 0; /* No lockable TLB entries. */ |
1568 |
case 5: /* CPU ID */ |
1569 |
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
|
1570 |
return env->cpu_index | 0x80000900; |
1571 |
} else {
|
1572 |
return env->cpu_index;
|
1573 |
} |
1574 |
default:
|
1575 |
goto bad_reg;
|
1576 |
} |
1577 |
case 1: |
1578 |
if (!arm_feature(env, ARM_FEATURE_V6))
|
1579 |
goto bad_reg;
|
1580 |
return env->cp15.c0_c1[op2];
|
1581 |
case 2: |
1582 |
if (!arm_feature(env, ARM_FEATURE_V6))
|
1583 |
goto bad_reg;
|
1584 |
return env->cp15.c0_c2[op2];
|
1585 |
case 3: case 4: case 5: case 6: case 7: |
1586 |
return 0; |
1587 |
default:
|
1588 |
goto bad_reg;
|
1589 |
} |
1590 |
case 1: |
1591 |
/* These registers aren't documented on arm11 cores. However
|
1592 |
Linux looks at them anyway. */
|
1593 |
if (!arm_feature(env, ARM_FEATURE_V6))
|
1594 |
goto bad_reg;
|
1595 |
if (crm != 0) |
1596 |
goto bad_reg;
|
1597 |
if (!arm_feature(env, ARM_FEATURE_V7))
|
1598 |
return 0; |
1599 |
|
1600 |
switch (op2) {
|
1601 |
case 0: |
1602 |
return env->cp15.c0_ccsid[env->cp15.c0_cssel];
|
1603 |
case 1: |
1604 |
return env->cp15.c0_clid;
|
1605 |
case 7: |
1606 |
return 0; |
1607 |
} |
1608 |
goto bad_reg;
|
1609 |
case 2: |
1610 |
if (op2 != 0 || crm != 0) |
1611 |
goto bad_reg;
|
1612 |
return env->cp15.c0_cssel;
|
1613 |
default:
|
1614 |
goto bad_reg;
|
1615 |
} |
1616 |
case 1: /* System configuration. */ |
1617 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1618 |
op2 = 0;
|
1619 |
switch (op2) {
|
1620 |
case 0: /* Control register. */ |
1621 |
return env->cp15.c1_sys;
|
1622 |
case 1: /* Auxiliary control register. */ |
1623 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1624 |
return env->cp15.c1_xscaleauxcr;
|
1625 |
if (!arm_feature(env, ARM_FEATURE_AUXCR))
|
1626 |
goto bad_reg;
|
1627 |
switch (ARM_CPUID(env)) {
|
1628 |
case ARM_CPUID_ARM1026:
|
1629 |
return 1; |
1630 |
case ARM_CPUID_ARM1136:
|
1631 |
case ARM_CPUID_ARM1136_R2:
|
1632 |
return 7; |
1633 |
case ARM_CPUID_ARM11MPCORE:
|
1634 |
return 1; |
1635 |
case ARM_CPUID_CORTEXA8:
|
1636 |
return 2; |
1637 |
case ARM_CPUID_CORTEXA9:
|
1638 |
return 0; |
1639 |
default:
|
1640 |
goto bad_reg;
|
1641 |
} |
1642 |
case 2: /* Coprocessor access register. */ |
1643 |
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
1644 |
goto bad_reg;
|
1645 |
return env->cp15.c1_coproc;
|
1646 |
default:
|
1647 |
goto bad_reg;
|
1648 |
} |
1649 |
case 2: /* MMU Page table control / MPU cache control. */ |
1650 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1651 |
switch (op2) {
|
1652 |
case 0: |
1653 |
return env->cp15.c2_data;
|
1654 |
break;
|
1655 |
case 1: |
1656 |
return env->cp15.c2_insn;
|
1657 |
break;
|
1658 |
default:
|
1659 |
goto bad_reg;
|
1660 |
} |
1661 |
} else {
|
1662 |
switch (op2) {
|
1663 |
case 0: |
1664 |
return env->cp15.c2_base0;
|
1665 |
case 1: |
1666 |
return env->cp15.c2_base1;
|
1667 |
case 2: |
1668 |
return env->cp15.c2_control;
|
1669 |
default:
|
1670 |
goto bad_reg;
|
1671 |
} |
1672 |
} |
1673 |
case 3: /* MMU Domain access control / MPU write buffer control. */ |
1674 |
return env->cp15.c3;
|
1675 |
case 4: /* Reserved. */ |
1676 |
goto bad_reg;
|
1677 |
case 5: /* MMU Fault status / MPU access permission. */ |
1678 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1679 |
op2 = 0;
|
1680 |
switch (op2) {
|
1681 |
case 0: |
1682 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
1683 |
return simple_mpu_ap_bits(env->cp15.c5_data);
|
1684 |
return env->cp15.c5_data;
|
1685 |
case 1: |
1686 |
if (arm_feature(env, ARM_FEATURE_MPU))
|
1687 |
return simple_mpu_ap_bits(env->cp15.c5_data);
|
1688 |
return env->cp15.c5_insn;
|
1689 |
case 2: |
1690 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
1691 |
goto bad_reg;
|
1692 |
return env->cp15.c5_data;
|
1693 |
case 3: |
1694 |
if (!arm_feature(env, ARM_FEATURE_MPU))
|
1695 |
goto bad_reg;
|
1696 |
return env->cp15.c5_insn;
|
1697 |
default:
|
1698 |
goto bad_reg;
|
1699 |
} |
1700 |
case 6: /* MMU Fault address. */ |
1701 |
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
1702 |
if (crm >= 8) |
1703 |
goto bad_reg;
|
1704 |
return env->cp15.c6_region[crm];
|
1705 |
} else {
|
1706 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1707 |
op2 = 0;
|
1708 |
switch (op2) {
|
1709 |
case 0: |
1710 |
return env->cp15.c6_data;
|
1711 |
case 1: |
1712 |
if (arm_feature(env, ARM_FEATURE_V6)) {
|
1713 |
/* Watchpoint Fault Adrress. */
|
1714 |
return 0; /* Not implemented. */ |
1715 |
} else {
|
1716 |
/* Instruction Fault Adrress. */
|
1717 |
/* Arm9 doesn't have an IFAR, but implementing it anyway
|
1718 |
shouldn't do any harm. */
|
1719 |
return env->cp15.c6_insn;
|
1720 |
} |
1721 |
case 2: |
1722 |
if (arm_feature(env, ARM_FEATURE_V6)) {
|
1723 |
/* Instruction Fault Adrress. */
|
1724 |
return env->cp15.c6_insn;
|
1725 |
} else {
|
1726 |
goto bad_reg;
|
1727 |
} |
1728 |
default:
|
1729 |
goto bad_reg;
|
1730 |
} |
1731 |
} |
1732 |
case 7: /* Cache control. */ |
1733 |
/* FIXME: Should only clear Z flag if destination is r15. */
|
1734 |
env->ZF = 0;
|
1735 |
return 0; |
1736 |
case 8: /* MMU TLB control. */ |
1737 |
goto bad_reg;
|
1738 |
case 9: /* Cache lockdown. */ |
1739 |
switch (op1) {
|
1740 |
case 0: /* L1 cache. */ |
1741 |
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
1742 |
return 0; |
1743 |
switch (op2) {
|
1744 |
case 0: |
1745 |
return env->cp15.c9_data;
|
1746 |
case 1: |
1747 |
return env->cp15.c9_insn;
|
1748 |
default:
|
1749 |
goto bad_reg;
|
1750 |
} |
1751 |
case 1: /* L2 cache */ |
1752 |
if (crm != 0) |
1753 |
goto bad_reg;
|
1754 |
/* L2 Lockdown and Auxiliary control. */
|
1755 |
return 0; |
1756 |
default:
|
1757 |
goto bad_reg;
|
1758 |
} |
1759 |
case 10: /* MMU TLB lockdown. */ |
1760 |
/* ??? TLB lockdown not implemented. */
|
1761 |
return 0; |
1762 |
case 11: /* TCM DMA control. */ |
1763 |
case 12: /* Reserved. */ |
1764 |
goto bad_reg;
|
1765 |
case 13: /* Process ID. */ |
1766 |
switch (op2) {
|
1767 |
case 0: |
1768 |
return env->cp15.c13_fcse;
|
1769 |
case 1: |
1770 |
return env->cp15.c13_context;
|
1771 |
default:
|
1772 |
goto bad_reg;
|
1773 |
} |
1774 |
case 14: /* Reserved. */ |
1775 |
goto bad_reg;
|
1776 |
case 15: /* Implementation specific. */ |
1777 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
1778 |
if (op2 == 0 && crm == 1) |
1779 |
return env->cp15.c15_cpar;
|
1780 |
|
1781 |
goto bad_reg;
|
1782 |
} |
1783 |
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
1784 |
switch (crm) {
|
1785 |
case 0: |
1786 |
return 0; |
1787 |
case 1: /* Read TI925T configuration. */ |
1788 |
return env->cp15.c15_ticonfig;
|
1789 |
case 2: /* Read I_max. */ |
1790 |
return env->cp15.c15_i_max;
|
1791 |
case 3: /* Read I_min. */ |
1792 |
return env->cp15.c15_i_min;
|
1793 |
case 4: /* Read thread-ID. */ |
1794 |
return env->cp15.c15_threadid;
|
1795 |
case 8: /* TI925T_status */ |
1796 |
return 0; |
1797 |
} |
1798 |
/* TODO: Peripheral port remap register:
|
1799 |
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
|
1800 |
* controller base address at $rn & ~0xfff and map size of
|
1801 |
* 0x200 << ($rn & 0xfff), when MMU is off. */
|
1802 |
goto bad_reg;
|
1803 |
} |
1804 |
return 0; |
1805 |
} |
1806 |
bad_reg:
|
1807 |
/* ??? For debugging only. Should raise illegal instruction exception. */
|
1808 |
cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
|
1809 |
(insn >> 16) & 0xf, crm, op1, op2); |
1810 |
return 0; |
1811 |
} |
1812 |
|
1813 |
void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
|
1814 |
{ |
1815 |
env->banked_r13[bank_number(mode)] = val; |
1816 |
} |
1817 |
|
1818 |
uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode) |
1819 |
{ |
1820 |
return env->banked_r13[bank_number(mode)];
|
1821 |
} |
1822 |
|
1823 |
uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) |
1824 |
{ |
1825 |
switch (reg) {
|
1826 |
case 0: /* APSR */ |
1827 |
return xpsr_read(env) & 0xf8000000; |
1828 |
case 1: /* IAPSR */ |
1829 |
return xpsr_read(env) & 0xf80001ff; |
1830 |
case 2: /* EAPSR */ |
1831 |
return xpsr_read(env) & 0xff00fc00; |
1832 |
case 3: /* xPSR */ |
1833 |
return xpsr_read(env) & 0xff00fdff; |
1834 |
case 5: /* IPSR */ |
1835 |
return xpsr_read(env) & 0x000001ff; |
1836 |
case 6: /* EPSR */ |
1837 |
return xpsr_read(env) & 0x0700fc00; |
1838 |
case 7: /* IEPSR */ |
1839 |
return xpsr_read(env) & 0x0700edff; |
1840 |
case 8: /* MSP */ |
1841 |
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13]; |
1842 |
case 9: /* PSP */ |
1843 |
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; |
1844 |
case 16: /* PRIMASK */ |
1845 |
return (env->uncached_cpsr & CPSR_I) != 0; |
1846 |
case 17: /* FAULTMASK */ |
1847 |
return (env->uncached_cpsr & CPSR_F) != 0; |
1848 |
case 18: /* BASEPRI */ |
1849 |
case 19: /* BASEPRI_MAX */ |
1850 |
return env->v7m.basepri;
|
1851 |
case 20: /* CONTROL */ |
1852 |
return env->v7m.control;
|
1853 |
default:
|
1854 |
/* ??? For debugging only. */
|
1855 |
cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
|
1856 |
return 0; |
1857 |
} |
1858 |
} |
1859 |
|
1860 |
void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
|
1861 |
{ |
1862 |
switch (reg) {
|
1863 |
case 0: /* APSR */ |
1864 |
xpsr_write(env, val, 0xf8000000);
|
1865 |
break;
|
1866 |
case 1: /* IAPSR */ |
1867 |
xpsr_write(env, val, 0xf8000000);
|
1868 |
break;
|
1869 |
case 2: /* EAPSR */ |
1870 |
xpsr_write(env, val, 0xfe00fc00);
|
1871 |
break;
|
1872 |
case 3: /* xPSR */ |
1873 |
xpsr_write(env, val, 0xfe00fc00);
|
1874 |
break;
|
1875 |
case 5: /* IPSR */ |
1876 |
/* IPSR bits are readonly. */
|
1877 |
break;
|
1878 |
case 6: /* EPSR */ |
1879 |
xpsr_write(env, val, 0x0600fc00);
|
1880 |
break;
|
1881 |
case 7: /* IEPSR */ |
1882 |
xpsr_write(env, val, 0x0600fc00);
|
1883 |
break;
|
1884 |
case 8: /* MSP */ |
1885 |
if (env->v7m.current_sp)
|
1886 |
env->v7m.other_sp = val; |
1887 |
else
|
1888 |
env->regs[13] = val;
|
1889 |
break;
|
1890 |
case 9: /* PSP */ |
1891 |
if (env->v7m.current_sp)
|
1892 |
env->regs[13] = val;
|
1893 |
else
|
1894 |
env->v7m.other_sp = val; |
1895 |
break;
|
1896 |
case 16: /* PRIMASK */ |
1897 |
if (val & 1) |
1898 |
env->uncached_cpsr |= CPSR_I; |
1899 |
else
|
1900 |
env->uncached_cpsr &= ~CPSR_I; |
1901 |
break;
|
1902 |
case 17: /* FAULTMASK */ |
1903 |
if (val & 1) |
1904 |
env->uncached_cpsr |= CPSR_F; |
1905 |
else
|
1906 |
env->uncached_cpsr &= ~CPSR_F; |
1907 |
break;
|
1908 |
case 18: /* BASEPRI */ |
1909 |
env->v7m.basepri = val & 0xff;
|
1910 |
break;
|
1911 |
case 19: /* BASEPRI_MAX */ |
1912 |
val &= 0xff;
|
1913 |
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) |
1914 |
env->v7m.basepri = val; |
1915 |
break;
|
1916 |
case 20: /* CONTROL */ |
1917 |
env->v7m.control = val & 3;
|
1918 |
switch_v7m_sp(env, (val & 2) != 0); |
1919 |
break;
|
1920 |
default:
|
1921 |
/* ??? For debugging only. */
|
1922 |
cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
|
1923 |
return;
|
1924 |
} |
1925 |
} |
1926 |
|
1927 |
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
1928 |
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
1929 |
void *opaque)
|
1930 |
{ |
1931 |
if (cpnum < 0 || cpnum > 14) { |
1932 |
cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
|
1933 |
return;
|
1934 |
} |
1935 |
|
1936 |
env->cp[cpnum].cp_read = cp_read; |
1937 |
env->cp[cpnum].cp_write = cp_write; |
1938 |
env->cp[cpnum].opaque = opaque; |
1939 |
} |
1940 |
|
1941 |
#endif
|
1942 |
|
1943 |
/* Note that signed overflow is undefined in C. The following routines are
|
1944 |
careful to use unsigned types where modulo arithmetic is required.
|
1945 |
Failure to do so _will_ break on newer gcc. */
|
1946 |
|
1947 |
/* Signed saturating arithmetic. */
|
1948 |
|
1949 |
/* Perform 16-bit signed saturating addition. */
|
1950 |
static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
1951 |
{ |
1952 |
uint16_t res; |
1953 |
|
1954 |
res = a + b; |
1955 |
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { |
1956 |
if (a & 0x8000) |
1957 |
res = 0x8000;
|
1958 |
else
|
1959 |
res = 0x7fff;
|
1960 |
} |
1961 |
return res;
|
1962 |
} |
1963 |
|
1964 |
/* Perform 8-bit signed saturating addition. */
|
1965 |
static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
1966 |
{ |
1967 |
uint8_t res; |
1968 |
|
1969 |
res = a + b; |
1970 |
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { |
1971 |
if (a & 0x80) |
1972 |
res = 0x80;
|
1973 |
else
|
1974 |
res = 0x7f;
|
1975 |
} |
1976 |
return res;
|
1977 |
} |
1978 |
|
1979 |
/* Perform 16-bit signed saturating subtraction. */
|
1980 |
static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
1981 |
{ |
1982 |
uint16_t res; |
1983 |
|
1984 |
res = a - b; |
1985 |
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { |
1986 |
if (a & 0x8000) |
1987 |
res = 0x8000;
|
1988 |
else
|
1989 |
res = 0x7fff;
|
1990 |
} |
1991 |
return res;
|
1992 |
} |
1993 |
|
1994 |
/* Perform 8-bit signed saturating subtraction. */
|
1995 |
static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
1996 |
{ |
1997 |
uint8_t res; |
1998 |
|
1999 |
res = a - b; |
2000 |
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { |
2001 |
if (a & 0x80) |
2002 |
res = 0x80;
|
2003 |
else
|
2004 |
res = 0x7f;
|
2005 |
} |
2006 |
return res;
|
2007 |
} |
2008 |
|
2009 |
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); |
2010 |
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); |
2011 |
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); |
2012 |
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); |
2013 |
#define PFX q
|
2014 |
|
2015 |
#include "op_addsub.h" |
2016 |
|
2017 |
/* Unsigned saturating arithmetic. */
|
2018 |
static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
2019 |
{ |
2020 |
uint16_t res; |
2021 |
res = a + b; |
2022 |
if (res < a)
|
2023 |
res = 0xffff;
|
2024 |
return res;
|
2025 |
} |
2026 |
|
2027 |
static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
2028 |
{ |
2029 |
if (a < b)
|
2030 |
return a - b;
|
2031 |
else
|
2032 |
return 0; |
2033 |
} |
2034 |
|
2035 |
static inline uint8_t add8_usat(uint8_t a, uint8_t b) |
2036 |
{ |
2037 |
uint8_t res; |
2038 |
res = a + b; |
2039 |
if (res < a)
|
2040 |
res = 0xff;
|
2041 |
return res;
|
2042 |
} |
2043 |
|
2044 |
static inline uint8_t sub8_usat(uint8_t a, uint8_t b) |
2045 |
{ |
2046 |
if (a < b)
|
2047 |
return a - b;
|
2048 |
else
|
2049 |
return 0; |
2050 |
} |
2051 |
|
2052 |
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); |
2053 |
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); |
2054 |
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); |
2055 |
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); |
2056 |
#define PFX uq
|
2057 |
|
2058 |
#include "op_addsub.h" |
2059 |
|
2060 |
/* Signed modulo arithmetic. */
|
2061 |
#define SARITH16(a, b, n, op) do { \ |
2062 |
int32_t sum; \ |
2063 |
sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \ |
2064 |
RESULT(sum, n, 16); \
|
2065 |
if (sum >= 0) \ |
2066 |
ge |= 3 << (n * 2); \ |
2067 |
} while(0) |
2068 |
|
2069 |
#define SARITH8(a, b, n, op) do { \ |
2070 |
int32_t sum; \ |
2071 |
sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \ |
2072 |
RESULT(sum, n, 8); \
|
2073 |
if (sum >= 0) \ |
2074 |
ge |= 1 << n; \
|
2075 |
} while(0) |
2076 |
|
2077 |
|
2078 |
#define ADD16(a, b, n) SARITH16(a, b, n, +)
|
2079 |
#define SUB16(a, b, n) SARITH16(a, b, n, -)
|
2080 |
#define ADD8(a, b, n) SARITH8(a, b, n, +)
|
2081 |
#define SUB8(a, b, n) SARITH8(a, b, n, -)
|
2082 |
#define PFX s
|
2083 |
#define ARITH_GE
|
2084 |
|
2085 |
#include "op_addsub.h" |
2086 |
|
2087 |
/* Unsigned modulo arithmetic. */
|
2088 |
#define ADD16(a, b, n) do { \ |
2089 |
uint32_t sum; \ |
2090 |
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ |
2091 |
RESULT(sum, n, 16); \
|
2092 |
if ((sum >> 16) == 1) \ |
2093 |
ge |= 3 << (n * 2); \ |
2094 |
} while(0) |
2095 |
|
2096 |
#define ADD8(a, b, n) do { \ |
2097 |
uint32_t sum; \ |
2098 |
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ |
2099 |
RESULT(sum, n, 8); \
|
2100 |
if ((sum >> 8) == 1) \ |
2101 |
ge |= 1 << n; \
|
2102 |
} while(0) |
2103 |
|
2104 |
#define SUB16(a, b, n) do { \ |
2105 |
uint32_t sum; \ |
2106 |
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ |
2107 |
RESULT(sum, n, 16); \
|
2108 |
if ((sum >> 16) == 0) \ |
2109 |
ge |= 3 << (n * 2); \ |
2110 |
} while(0) |
2111 |
|
2112 |
#define SUB8(a, b, n) do { \ |
2113 |
uint32_t sum; \ |
2114 |
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ |
2115 |
RESULT(sum, n, 8); \
|
2116 |
if ((sum >> 8) == 0) \ |
2117 |
ge |= 1 << n; \
|
2118 |
} while(0) |
2119 |
|
2120 |
#define PFX u
|
2121 |
#define ARITH_GE
|
2122 |
|
2123 |
#include "op_addsub.h" |
2124 |
|
2125 |
/* Halved signed arithmetic. */
|
2126 |
#define ADD16(a, b, n) \
|
2127 |
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) |
2128 |
#define SUB16(a, b, n) \
|
2129 |
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) |
2130 |
#define ADD8(a, b, n) \
|
2131 |
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) |
2132 |
#define SUB8(a, b, n) \
|
2133 |
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) |
2134 |
#define PFX sh
|
2135 |
|
2136 |
#include "op_addsub.h" |
2137 |
|
2138 |
/* Halved unsigned arithmetic. */
|
2139 |
#define ADD16(a, b, n) \
|
2140 |
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2141 |
#define SUB16(a, b, n) \
|
2142 |
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) |
2143 |
#define ADD8(a, b, n) \
|
2144 |
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2145 |
#define SUB8(a, b, n) \
|
2146 |
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) |
2147 |
#define PFX uh
|
2148 |
|
2149 |
#include "op_addsub.h" |
2150 |
|
2151 |
static inline uint8_t do_usad(uint8_t a, uint8_t b) |
2152 |
{ |
2153 |
if (a > b)
|
2154 |
return a - b;
|
2155 |
else
|
2156 |
return b - a;
|
2157 |
} |
2158 |
|
2159 |
/* Unsigned sum of absolute byte differences. */
|
2160 |
uint32_t HELPER(usad8)(uint32_t a, uint32_t b) |
2161 |
{ |
2162 |
uint32_t sum; |
2163 |
sum = do_usad(a, b); |
2164 |
sum += do_usad(a >> 8, b >> 8); |
2165 |
sum += do_usad(a >> 16, b >>16); |
2166 |
sum += do_usad(a >> 24, b >> 24); |
2167 |
return sum;
|
2168 |
} |
2169 |
|
2170 |
/* For ARMv6 SEL instruction. */
|
2171 |
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) |
2172 |
{ |
2173 |
uint32_t mask; |
2174 |
|
2175 |
mask = 0;
|
2176 |
if (flags & 1) |
2177 |
mask |= 0xff;
|
2178 |
if (flags & 2) |
2179 |
mask |= 0xff00;
|
2180 |
if (flags & 4) |
2181 |
mask |= 0xff0000;
|
2182 |
if (flags & 8) |
2183 |
mask |= 0xff000000;
|
2184 |
return (a & mask) | (b & ~mask);
|
2185 |
} |
2186 |
|
2187 |
uint32_t HELPER(logicq_cc)(uint64_t val) |
2188 |
{ |
2189 |
return (val >> 32) | (val != 0); |
2190 |
} |
2191 |
|
2192 |
/* VFP support. We follow the convention used for VFP instrunctions:
|
2193 |
Single precition routines have a "s" suffix, double precision a
|
2194 |
"d" suffix. */
|
2195 |
|
2196 |
/* Convert host exception flags to vfp form. */
|
2197 |
static inline int vfp_exceptbits_from_host(int host_bits) |
2198 |
{ |
2199 |
int target_bits = 0; |
2200 |
|
2201 |
if (host_bits & float_flag_invalid)
|
2202 |
target_bits |= 1;
|
2203 |
if (host_bits & float_flag_divbyzero)
|
2204 |
target_bits |= 2;
|
2205 |
if (host_bits & float_flag_overflow)
|
2206 |
target_bits |= 4;
|
2207 |
if (host_bits & float_flag_underflow)
|
2208 |
target_bits |= 8;
|
2209 |
if (host_bits & float_flag_inexact)
|
2210 |
target_bits |= 0x10;
|
2211 |
return target_bits;
|
2212 |
} |
2213 |
|
2214 |
uint32_t HELPER(vfp_get_fpscr)(CPUState *env) |
2215 |
{ |
2216 |
int i;
|
2217 |
uint32_t fpscr; |
2218 |
|
2219 |
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
|
2220 |
| (env->vfp.vec_len << 16)
|
2221 |
| (env->vfp.vec_stride << 20);
|
2222 |
i = get_float_exception_flags(&env->vfp.fp_status); |
2223 |
fpscr |= vfp_exceptbits_from_host(i); |
2224 |
return fpscr;
|
2225 |
} |
2226 |
|
2227 |
/* Convert vfp exception flags to target form. */
|
2228 |
static inline int vfp_exceptbits_to_host(int target_bits) |
2229 |
{ |
2230 |
int host_bits = 0; |
2231 |
|
2232 |
if (target_bits & 1) |
2233 |
host_bits |= float_flag_invalid; |
2234 |
if (target_bits & 2) |
2235 |
host_bits |= float_flag_divbyzero; |
2236 |
if (target_bits & 4) |
2237 |
host_bits |= float_flag_overflow; |
2238 |
if (target_bits & 8) |
2239 |
host_bits |= float_flag_underflow; |
2240 |
if (target_bits & 0x10) |
2241 |
host_bits |= float_flag_inexact; |
2242 |
return host_bits;
|
2243 |
} |
2244 |
|
2245 |
void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
|
2246 |
{ |
2247 |
int i;
|
2248 |
uint32_t changed; |
2249 |
|
2250 |
changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
2251 |
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
|
2252 |
env->vfp.vec_len = (val >> 16) & 7; |
2253 |
env->vfp.vec_stride = (val >> 20) & 3; |
2254 |
|
2255 |
changed ^= val; |
2256 |
if (changed & (3 << 22)) { |
2257 |
i = (val >> 22) & 3; |
2258 |
switch (i) {
|
2259 |
case 0: |
2260 |
i = float_round_nearest_even; |
2261 |
break;
|
2262 |
case 1: |
2263 |
i = float_round_up; |
2264 |
break;
|
2265 |
case 2: |
2266 |
i = float_round_down; |
2267 |
break;
|
2268 |
case 3: |
2269 |
i = float_round_to_zero; |
2270 |
break;
|
2271 |
} |
2272 |
set_float_rounding_mode(i, &env->vfp.fp_status); |
2273 |
} |
2274 |
if (changed & (1 << 24)) |
2275 |
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
2276 |
if (changed & (1 << 25)) |
2277 |
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); |
2278 |
|
2279 |
i = vfp_exceptbits_to_host((val >> 8) & 0x1f); |
2280 |
set_float_exception_flags(i, &env->vfp.fp_status); |
2281 |
} |
2282 |
|
2283 |
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
|
2284 |
|
2285 |
#define VFP_BINOP(name) \
|
2286 |
float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \ |
2287 |
{ \ |
2288 |
return float32_ ## name (a, b, &env->vfp.fp_status); \ |
2289 |
} \ |
2290 |
float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \ |
2291 |
{ \ |
2292 |
return float64_ ## name (a, b, &env->vfp.fp_status); \ |
2293 |
} |
2294 |
VFP_BINOP(add) |
2295 |
VFP_BINOP(sub) |
2296 |
VFP_BINOP(mul) |
2297 |
VFP_BINOP(div) |
2298 |
#undef VFP_BINOP
|
2299 |
|
2300 |
float32 VFP_HELPER(neg, s)(float32 a) |
2301 |
{ |
2302 |
return float32_chs(a);
|
2303 |
} |
2304 |
|
2305 |
float64 VFP_HELPER(neg, d)(float64 a) |
2306 |
{ |
2307 |
return float64_chs(a);
|
2308 |
} |
2309 |
|
2310 |
float32 VFP_HELPER(abs, s)(float32 a) |
2311 |
{ |
2312 |
return float32_abs(a);
|
2313 |
} |
2314 |
|
2315 |
float64 VFP_HELPER(abs, d)(float64 a) |
2316 |
{ |
2317 |
return float64_abs(a);
|
2318 |
} |
2319 |
|
2320 |
float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env) |
2321 |
{ |
2322 |
return float32_sqrt(a, &env->vfp.fp_status);
|
2323 |
} |
2324 |
|
2325 |
float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env) |
2326 |
{ |
2327 |
return float64_sqrt(a, &env->vfp.fp_status);
|
2328 |
} |
2329 |
|
2330 |
/* XXX: check quiet/signaling case */
|
2331 |
#define DO_VFP_cmp(p, type) \
|
2332 |
void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
|
2333 |
{ \ |
2334 |
uint32_t flags; \ |
2335 |
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ |
2336 |
case 0: flags = 0x6; break; \ |
2337 |
case -1: flags = 0x8; break; \ |
2338 |
case 1: flags = 0x2; break; \ |
2339 |
default: case 2: flags = 0x3; break; \ |
2340 |
} \ |
2341 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
2342 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
2343 |
} \ |
2344 |
void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
|
2345 |
{ \ |
2346 |
uint32_t flags; \ |
2347 |
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ |
2348 |
case 0: flags = 0x6; break; \ |
2349 |
case -1: flags = 0x8; break; \ |
2350 |
case 1: flags = 0x2; break; \ |
2351 |
default: case 2: flags = 0x3; break; \ |
2352 |
} \ |
2353 |
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
2354 |
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
2355 |
} |
2356 |
DO_VFP_cmp(s, float32) |
2357 |
DO_VFP_cmp(d, float64) |
2358 |
#undef DO_VFP_cmp
|
2359 |
|
2360 |
/* Helper routines to perform bitwise copies between float and int. */
|
2361 |
static inline float32 vfp_itos(uint32_t i) |
2362 |
{ |
2363 |
union {
|
2364 |
uint32_t i; |
2365 |
float32 s; |
2366 |
} v; |
2367 |
|
2368 |
v.i = i; |
2369 |
return v.s;
|
2370 |
} |
2371 |
|
2372 |
static inline uint32_t vfp_stoi(float32 s) |
2373 |
{ |
2374 |
union {
|
2375 |
uint32_t i; |
2376 |
float32 s; |
2377 |
} v; |
2378 |
|
2379 |
v.s = s; |
2380 |
return v.i;
|
2381 |
} |
2382 |
|
2383 |
static inline float64 vfp_itod(uint64_t i) |
2384 |
{ |
2385 |
union {
|
2386 |
uint64_t i; |
2387 |
float64 d; |
2388 |
} v; |
2389 |
|
2390 |
v.i = i; |
2391 |
return v.d;
|
2392 |
} |
2393 |
|
2394 |
static inline uint64_t vfp_dtoi(float64 d) |
2395 |
{ |
2396 |
union {
|
2397 |
uint64_t i; |
2398 |
float64 d; |
2399 |
} v; |
2400 |
|
2401 |
v.d = d; |
2402 |
return v.i;
|
2403 |
} |
2404 |
|
2405 |
/* Integer to float conversion. */
|
2406 |
float32 VFP_HELPER(uito, s)(float32 x, CPUState *env) |
2407 |
{ |
2408 |
return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
|
2409 |
} |
2410 |
|
2411 |
float64 VFP_HELPER(uito, d)(float32 x, CPUState *env) |
2412 |
{ |
2413 |
return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
|
2414 |
} |
2415 |
|
2416 |
float32 VFP_HELPER(sito, s)(float32 x, CPUState *env) |
2417 |
{ |
2418 |
return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
|
2419 |
} |
2420 |
|
2421 |
float64 VFP_HELPER(sito, d)(float32 x, CPUState *env) |
2422 |
{ |
2423 |
return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
|
2424 |
} |
2425 |
|
2426 |
/* Float to integer conversion. */
|
2427 |
float32 VFP_HELPER(toui, s)(float32 x, CPUState *env) |
2428 |
{ |
2429 |
return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
|
2430 |
} |
2431 |
|
2432 |
float32 VFP_HELPER(toui, d)(float64 x, CPUState *env) |
2433 |
{ |
2434 |
return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
|
2435 |
} |
2436 |
|
2437 |
float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env) |
2438 |
{ |
2439 |
return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
|
2440 |
} |
2441 |
|
2442 |
float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env) |
2443 |
{ |
2444 |
return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
|
2445 |
} |
2446 |
|
2447 |
float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env) |
2448 |
{ |
2449 |
return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
|
2450 |
} |
2451 |
|
2452 |
float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env) |
2453 |
{ |
2454 |
return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
|
2455 |
} |
2456 |
|
2457 |
float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env) |
2458 |
{ |
2459 |
return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
|
2460 |
} |
2461 |
|
2462 |
float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env) |
2463 |
{ |
2464 |
return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
|
2465 |
} |
2466 |
|
2467 |
/* floating point conversion */
|
2468 |
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env) |
2469 |
{ |
2470 |
return float32_to_float64(x, &env->vfp.fp_status);
|
2471 |
} |
2472 |
|
2473 |
float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) |
2474 |
{ |
2475 |
return float64_to_float32(x, &env->vfp.fp_status);
|
2476 |
} |
2477 |
|
2478 |
/* VFP3 fixed point conversion. */
|
2479 |
#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
|
2480 |
ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \ |
2481 |
{ \ |
2482 |
ftype tmp; \ |
2483 |
tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \ |
2484 |
&env->vfp.fp_status); \ |
2485 |
return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \ |
2486 |
} \ |
2487 |
ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \ |
2488 |
{ \ |
2489 |
ftype tmp; \ |
2490 |
tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \ |
2491 |
return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \ |
2492 |
&env->vfp.fp_status)); \ |
2493 |
} |
2494 |
|
2495 |
VFP_CONV_FIX(sh, d, float64, int16, ) |
2496 |
VFP_CONV_FIX(sl, d, float64, int32, ) |
2497 |
VFP_CONV_FIX(uh, d, float64, uint16, u) |
2498 |
VFP_CONV_FIX(ul, d, float64, uint32, u) |
2499 |
VFP_CONV_FIX(sh, s, float32, int16, ) |
2500 |
VFP_CONV_FIX(sl, s, float32, int32, ) |
2501 |
VFP_CONV_FIX(uh, s, float32, uint16, u) |
2502 |
VFP_CONV_FIX(ul, s, float32, uint32, u) |
2503 |
#undef VFP_CONV_FIX
|
2504 |
|
2505 |
/* Half precision conversions. */
|
2506 |
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env) |
2507 |
{ |
2508 |
float_status *s = &env->vfp.fp_status; |
2509 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
2510 |
return float16_to_float32(a, ieee, s);
|
2511 |
} |
2512 |
|
2513 |
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env) |
2514 |
{ |
2515 |
float_status *s = &env->vfp.fp_status; |
2516 |
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
2517 |
return float32_to_float16(a, ieee, s);
|
2518 |
} |
2519 |
|
2520 |
float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env) |
2521 |
{ |
2522 |
float_status *s = &env->vfp.fp_status; |
2523 |
float32 two = int32_to_float32(2, s);
|
2524 |
return float32_sub(two, float32_mul(a, b, s), s);
|
2525 |
} |
2526 |
|
2527 |
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env) |
2528 |
{ |
2529 |
float_status *s = &env->vfp.fp_status; |
2530 |
float32 three = int32_to_float32(3, s);
|
2531 |
return float32_sub(three, float32_mul(a, b, s), s);
|
2532 |
} |
2533 |
|
2534 |
/* NEON helpers. */
|
2535 |
|
2536 |
/* TODO: The architecture specifies the value that the estimate functions
|
2537 |
should return. We return the exact reciprocal/root instead. */
|
2538 |
float32 HELPER(recpe_f32)(float32 a, CPUState *env) |
2539 |
{ |
2540 |
float_status *s = &env->vfp.fp_status; |
2541 |
float32 one = int32_to_float32(1, s);
|
2542 |
return float32_div(one, a, s);
|
2543 |
} |
2544 |
|
2545 |
float32 HELPER(rsqrte_f32)(float32 a, CPUState *env) |
2546 |
{ |
2547 |
float_status *s = &env->vfp.fp_status; |
2548 |
float32 one = int32_to_float32(1, s);
|
2549 |
return float32_div(one, float32_sqrt(a, s), s);
|
2550 |
} |
2551 |
|
2552 |
uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env) |
2553 |
{ |
2554 |
float_status *s = &env->vfp.fp_status; |
2555 |
float32 tmp; |
2556 |
tmp = int32_to_float32(a, s); |
2557 |
tmp = float32_scalbn(tmp, -32, s);
|
2558 |
tmp = helper_recpe_f32(tmp, env); |
2559 |
tmp = float32_scalbn(tmp, 31, s);
|
2560 |
return float32_to_int32(tmp, s);
|
2561 |
} |
2562 |
|
2563 |
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env) |
2564 |
{ |
2565 |
float_status *s = &env->vfp.fp_status; |
2566 |
float32 tmp; |
2567 |
tmp = int32_to_float32(a, s); |
2568 |
tmp = float32_scalbn(tmp, -32, s);
|
2569 |
tmp = helper_rsqrte_f32(tmp, env); |
2570 |
tmp = float32_scalbn(tmp, 31, s);
|
2571 |
return float32_to_int32(tmp, s);
|
2572 |
} |
2573 |
|
2574 |
void HELPER(set_teecr)(CPUState *env, uint32_t val)
|
2575 |
{ |
2576 |
val &= 1;
|
2577 |
if (env->teecr != val) {
|
2578 |
env->teecr = val; |
2579 |
tb_flush(env); |
2580 |
} |
2581 |
} |