root / target-ppc / op_helper.c @ 30aec876
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1 | 9a64fbe4 | bellard | /*
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2 | 9a64fbe4 | bellard | * PPC emulation helpers for qemu.
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3 | 9a64fbe4 | bellard | *
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4 | 9a64fbe4 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 9a64fbe4 | bellard | *
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6 | 9a64fbe4 | bellard | * This library is free software; you can redistribute it and/or
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7 | 9a64fbe4 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 9a64fbe4 | bellard | * License as published by the Free Software Foundation; either
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9 | 9a64fbe4 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 9a64fbe4 | bellard | *
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11 | 9a64fbe4 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 9a64fbe4 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 9a64fbe4 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 9a64fbe4 | bellard | * Lesser General Public License for more details.
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15 | 9a64fbe4 | bellard | *
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16 | 9a64fbe4 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 9a64fbe4 | bellard | * License along with this library; if not, write to the Free Software
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18 | 9a64fbe4 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 9a64fbe4 | bellard | */
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20 | 9a64fbe4 | bellard | #include <math.h> |
21 | 9a64fbe4 | bellard | #include "exec.h" |
22 | 9a64fbe4 | bellard | |
23 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
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24 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
25 | a541f297 | bellard | #if !defined(CONFIG_USER_ONLY)
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26 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
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27 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
28 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
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29 | 9a64fbe4 | bellard | #include "op_helper_mem.h" |
30 | 9a64fbe4 | bellard | #endif
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31 | 9a64fbe4 | bellard | |
32 | 9a64fbe4 | bellard | /*****************************************************************************/
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33 | 9a64fbe4 | bellard | /* Exceptions processing helpers */
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34 | 9fddaa0c | bellard | void cpu_loop_exit(void) |
35 | 9a64fbe4 | bellard | { |
36 | 9fddaa0c | bellard | longjmp(env->jmp_env, 1);
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37 | 9a64fbe4 | bellard | } |
38 | 9a64fbe4 | bellard | |
39 | 9fddaa0c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
40 | 9a64fbe4 | bellard | { |
41 | 9fddaa0c | bellard | #if 0
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42 | 9fddaa0c | bellard | printf("Raise exception %3x code : %d\n", exception, error_code);
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43 | 9fddaa0c | bellard | #endif
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44 | 9fddaa0c | bellard | switch (exception) {
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45 | 9fddaa0c | bellard | case EXCP_EXTERNAL:
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46 | 9fddaa0c | bellard | case EXCP_DECR:
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47 | 9fddaa0c | bellard | printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
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48 | 9fddaa0c | bellard | if (msr_ee == 0) |
49 | 9fddaa0c | bellard | return;
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50 | 9fddaa0c | bellard | break;
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51 | 9fddaa0c | bellard | case EXCP_PROGRAM:
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52 | 9fddaa0c | bellard | if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0) |
53 | 9fddaa0c | bellard | return;
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54 | 9fddaa0c | bellard | break;
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55 | 9fddaa0c | bellard | default:
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56 | 9fddaa0c | bellard | break;
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57 | 9a64fbe4 | bellard | } |
58 | 9fddaa0c | bellard | env->exception_index = exception; |
59 | 9fddaa0c | bellard | env->error_code = error_code; |
60 | 9a64fbe4 | bellard | cpu_loop_exit(); |
61 | 9a64fbe4 | bellard | } |
62 | 9fddaa0c | bellard | |
63 | 9fddaa0c | bellard | void do_raise_exception (uint32_t exception)
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64 | 9fddaa0c | bellard | { |
65 | 9fddaa0c | bellard | do_raise_exception_err(exception, 0);
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66 | 9a64fbe4 | bellard | } |
67 | 9a64fbe4 | bellard | |
68 | 9a64fbe4 | bellard | /*****************************************************************************/
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69 | 9a64fbe4 | bellard | /* Helpers for "fat" micro operations */
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70 | 9a64fbe4 | bellard | /* Special registers load and store */
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71 | 9a64fbe4 | bellard | void do_load_cr (void) |
72 | 9a64fbe4 | bellard | { |
73 | 9a64fbe4 | bellard | T0 = (env->crf[0] << 28) | |
74 | 9a64fbe4 | bellard | (env->crf[1] << 24) | |
75 | 9a64fbe4 | bellard | (env->crf[2] << 20) | |
76 | 9a64fbe4 | bellard | (env->crf[3] << 16) | |
77 | 9a64fbe4 | bellard | (env->crf[4] << 12) | |
78 | 9a64fbe4 | bellard | (env->crf[5] << 8) | |
79 | 9a64fbe4 | bellard | (env->crf[6] << 4) | |
80 | 9a64fbe4 | bellard | (env->crf[7] << 0); |
81 | 9a64fbe4 | bellard | } |
82 | 9a64fbe4 | bellard | |
83 | 9a64fbe4 | bellard | void do_store_cr (uint32_t mask)
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84 | 9a64fbe4 | bellard | { |
85 | 9a64fbe4 | bellard | int i, sh;
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86 | 9a64fbe4 | bellard | |
87 | 9a64fbe4 | bellard | for (i = 0, sh = 7; i < 8; i++, sh --) { |
88 | 9a64fbe4 | bellard | if (mask & (1 << sh)) |
89 | 9a64fbe4 | bellard | env->crf[i] = (T0 >> (sh * 4)) & 0xF; |
90 | 9a64fbe4 | bellard | } |
91 | 9a64fbe4 | bellard | } |
92 | 9a64fbe4 | bellard | |
93 | 9a64fbe4 | bellard | void do_load_xer (void) |
94 | 9a64fbe4 | bellard | { |
95 | 9a64fbe4 | bellard | T0 = (xer_so << XER_SO) | |
96 | 9a64fbe4 | bellard | (xer_ov << XER_OV) | |
97 | 9a64fbe4 | bellard | (xer_ca << XER_CA) | |
98 | 9a64fbe4 | bellard | (xer_bc << XER_BC); |
99 | 9a64fbe4 | bellard | } |
100 | 9a64fbe4 | bellard | |
101 | 9a64fbe4 | bellard | void do_store_xer (void) |
102 | 9a64fbe4 | bellard | { |
103 | 9a64fbe4 | bellard | xer_so = (T0 >> XER_SO) & 0x01;
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104 | 9a64fbe4 | bellard | xer_ov = (T0 >> XER_OV) & 0x01;
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105 | 9a64fbe4 | bellard | xer_ca = (T0 >> XER_CA) & 0x01;
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106 | 30aec876 | bellard | xer_bc = (T0 >> XER_BC) & 0x3f;
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107 | 9a64fbe4 | bellard | } |
108 | 9a64fbe4 | bellard | |
109 | 9a64fbe4 | bellard | void do_load_msr (void) |
110 | 9a64fbe4 | bellard | { |
111 | 9a64fbe4 | bellard | T0 = (msr_pow << MSR_POW) | |
112 | 9a64fbe4 | bellard | (msr_ile << MSR_ILE) | |
113 | 9a64fbe4 | bellard | (msr_ee << MSR_EE) | |
114 | 9a64fbe4 | bellard | (msr_pr << MSR_PR) | |
115 | 9a64fbe4 | bellard | (msr_fp << MSR_FP) | |
116 | 9a64fbe4 | bellard | (msr_me << MSR_ME) | |
117 | 9a64fbe4 | bellard | (msr_fe0 << MSR_FE0) | |
118 | 9a64fbe4 | bellard | (msr_se << MSR_SE) | |
119 | 9a64fbe4 | bellard | (msr_be << MSR_BE) | |
120 | 9a64fbe4 | bellard | (msr_fe1 << MSR_FE1) | |
121 | 9a64fbe4 | bellard | (msr_ip << MSR_IP) | |
122 | 9a64fbe4 | bellard | (msr_ir << MSR_IR) | |
123 | 9a64fbe4 | bellard | (msr_dr << MSR_DR) | |
124 | 9a64fbe4 | bellard | (msr_ri << MSR_RI) | |
125 | 9a64fbe4 | bellard | (msr_le << MSR_LE); |
126 | 9a64fbe4 | bellard | } |
127 | 9a64fbe4 | bellard | |
128 | 9a64fbe4 | bellard | void do_store_msr (void) |
129 | 9a64fbe4 | bellard | { |
130 | 4b3686fa | bellard | #if 1 // TRY |
131 | 9a64fbe4 | bellard | if (((T0 >> MSR_IR) & 0x01) != msr_ir || |
132 | 4b3686fa | bellard | ((T0 >> MSR_DR) & 0x01) != msr_dr ||
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133 | 4b3686fa | bellard | ((T0 >> MSR_PR) & 0x01) != msr_pr)
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134 | 4b3686fa | bellard | { |
135 | 9a64fbe4 | bellard | do_tlbia(); |
136 | 9a64fbe4 | bellard | } |
137 | 4b3686fa | bellard | #endif
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138 | 9a64fbe4 | bellard | msr_pow = (T0 >> MSR_POW) & 0x03;
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139 | 9a64fbe4 | bellard | msr_ile = (T0 >> MSR_ILE) & 0x01;
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140 | 9a64fbe4 | bellard | msr_ee = (T0 >> MSR_EE) & 0x01;
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141 | 9a64fbe4 | bellard | msr_pr = (T0 >> MSR_PR) & 0x01;
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142 | 9a64fbe4 | bellard | msr_fp = (T0 >> MSR_FP) & 0x01;
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143 | 9a64fbe4 | bellard | msr_me = (T0 >> MSR_ME) & 0x01;
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144 | 9a64fbe4 | bellard | msr_fe0 = (T0 >> MSR_FE0) & 0x01;
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145 | 9a64fbe4 | bellard | msr_se = (T0 >> MSR_SE) & 0x01;
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146 | 9a64fbe4 | bellard | msr_be = (T0 >> MSR_BE) & 0x01;
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147 | 9a64fbe4 | bellard | msr_fe1 = (T0 >> MSR_FE1) & 0x01;
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148 | 9a64fbe4 | bellard | msr_ip = (T0 >> MSR_IP) & 0x01;
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149 | 9a64fbe4 | bellard | msr_ir = (T0 >> MSR_IR) & 0x01;
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150 | 9a64fbe4 | bellard | msr_dr = (T0 >> MSR_DR) & 0x01;
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151 | 9a64fbe4 | bellard | msr_ri = (T0 >> MSR_RI) & 0x01;
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152 | 9a64fbe4 | bellard | msr_le = (T0 >> MSR_LE) & 0x01;
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153 | 9a64fbe4 | bellard | } |
154 | 9a64fbe4 | bellard | |
155 | 9a64fbe4 | bellard | /* shift right arithmetic helper */
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156 | 9a64fbe4 | bellard | void do_sraw (void) |
157 | 9a64fbe4 | bellard | { |
158 | 9a64fbe4 | bellard | int32_t ret; |
159 | 9a64fbe4 | bellard | |
160 | 9a64fbe4 | bellard | xer_ca = 0;
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161 | 9a64fbe4 | bellard | if (T1 & 0x20) { |
162 | 9a64fbe4 | bellard | ret = (-1) * (T0 >> 31); |
163 | 4b3686fa | bellard | if (ret < 0 && (T0 & ~0x80000000) != 0) |
164 | 9a64fbe4 | bellard | xer_ca = 1;
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165 | 4b3686fa | bellard | #if 1 // TRY |
166 | 4b3686fa | bellard | } else if (T1 == 0) { |
167 | 4b3686fa | bellard | ret = T0; |
168 | 4b3686fa | bellard | #endif
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169 | 9a64fbe4 | bellard | } else {
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170 | 9a64fbe4 | bellard | ret = (int32_t)T0 >> (T1 & 0x1f);
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171 | 9a64fbe4 | bellard | if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0) |
172 | 9a64fbe4 | bellard | xer_ca = 1;
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173 | 9a64fbe4 | bellard | } |
174 | 4b3686fa | bellard | T0 = ret; |
175 | 9a64fbe4 | bellard | } |
176 | 9a64fbe4 | bellard | |
177 | 9a64fbe4 | bellard | /* Floating point operations helpers */
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178 | 9a64fbe4 | bellard | void do_load_fpscr (void) |
179 | 9a64fbe4 | bellard | { |
180 | 9a64fbe4 | bellard | /* The 32 MSB of the target fpr are undefined.
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181 | 9a64fbe4 | bellard | * They'll be zero...
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182 | 9a64fbe4 | bellard | */
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183 | 9a64fbe4 | bellard | union {
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184 | 9a64fbe4 | bellard | double d;
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185 | 9a64fbe4 | bellard | struct {
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186 | 9a64fbe4 | bellard | uint32_t u[2];
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187 | 9a64fbe4 | bellard | } s; |
188 | 9a64fbe4 | bellard | } u; |
189 | 9a64fbe4 | bellard | int i;
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190 | 9a64fbe4 | bellard | |
191 | 3cc62370 | bellard | #ifdef WORDS_BIGENDIAN
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192 | 3cc62370 | bellard | #define WORD0 0 |
193 | 3cc62370 | bellard | #define WORD1 1 |
194 | 3cc62370 | bellard | #else
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195 | 3cc62370 | bellard | #define WORD0 1 |
196 | 3cc62370 | bellard | #define WORD1 0 |
197 | 3cc62370 | bellard | #endif
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198 | 3cc62370 | bellard | u.s.u[WORD0] = 0;
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199 | 3cc62370 | bellard | u.s.u[WORD1] = 0;
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200 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) |
201 | 3cc62370 | bellard | u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
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202 | 9a64fbe4 | bellard | FT0 = u.d; |
203 | 9a64fbe4 | bellard | } |
204 | 9a64fbe4 | bellard | |
205 | 9a64fbe4 | bellard | void do_store_fpscr (uint32_t mask)
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206 | 9a64fbe4 | bellard | { |
207 | 9a64fbe4 | bellard | /*
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208 | 9a64fbe4 | bellard | * We use only the 32 LSB of the incoming fpr
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209 | 9a64fbe4 | bellard | */
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210 | 9a64fbe4 | bellard | union {
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211 | 9a64fbe4 | bellard | double d;
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212 | 9a64fbe4 | bellard | struct {
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213 | 9a64fbe4 | bellard | uint32_t u[2];
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214 | 9a64fbe4 | bellard | } s; |
215 | 9a64fbe4 | bellard | } u; |
216 | 4ecc3190 | bellard | int i, rnd_type;
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217 | 9a64fbe4 | bellard | |
218 | 9a64fbe4 | bellard | u.d = FT0; |
219 | 9a64fbe4 | bellard | if (mask & 0x80) |
220 | 3cc62370 | bellard | env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9); |
221 | 9a64fbe4 | bellard | for (i = 1; i < 7; i++) { |
222 | 9a64fbe4 | bellard | if (mask & (1 << (7 - i))) |
223 | 3cc62370 | bellard | env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF; |
224 | 9a64fbe4 | bellard | } |
225 | 9a64fbe4 | bellard | /* TODO: update FEX & VX */
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226 | 9a64fbe4 | bellard | /* Set rounding mode */
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227 | 9a64fbe4 | bellard | switch (env->fpscr[0] & 0x3) { |
228 | 9a64fbe4 | bellard | case 0: |
229 | 9a64fbe4 | bellard | /* Best approximation (round to nearest) */
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230 | 4ecc3190 | bellard | rnd_type = float_round_nearest_even; |
231 | 9a64fbe4 | bellard | break;
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232 | 9a64fbe4 | bellard | case 1: |
233 | 9a64fbe4 | bellard | /* Smaller magnitude (round toward zero) */
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234 | 4ecc3190 | bellard | rnd_type = float_round_to_zero; |
235 | 9a64fbe4 | bellard | break;
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236 | 9a64fbe4 | bellard | case 2: |
237 | 9a64fbe4 | bellard | /* Round toward +infinite */
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238 | 4ecc3190 | bellard | rnd_type = float_round_up; |
239 | 9a64fbe4 | bellard | break;
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240 | 4ecc3190 | bellard | default:
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241 | 9a64fbe4 | bellard | case 3: |
242 | 9a64fbe4 | bellard | /* Round toward -infinite */
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243 | 4ecc3190 | bellard | rnd_type = float_round_down; |
244 | 9a64fbe4 | bellard | break;
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245 | 9a64fbe4 | bellard | } |
246 | 4ecc3190 | bellard | set_float_rounding_mode(rnd_type, &env->fp_status); |
247 | 9a64fbe4 | bellard | } |
248 | 9a64fbe4 | bellard | |
249 | 9a64fbe4 | bellard | void do_fctiw (void) |
250 | 9a64fbe4 | bellard | { |
251 | 9a64fbe4 | bellard | union {
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252 | 9a64fbe4 | bellard | double d;
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253 | 9a64fbe4 | bellard | uint64_t i; |
254 | 4ecc3190 | bellard | } p; |
255 | 9a64fbe4 | bellard | |
256 | 4ecc3190 | bellard | /* XXX: higher bits are not supposed to be significant.
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257 | 4ecc3190 | bellard | * to make tests easier, return the same as a real PPC 750 (aka G3)
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258 | 4ecc3190 | bellard | */
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259 | 4ecc3190 | bellard | p.i = float64_to_int32(FT0, &env->fp_status); |
260 | 4ecc3190 | bellard | p.i |= 0xFFF80000ULL << 32; |
261 | 4ecc3190 | bellard | FT0 = p.d; |
262 | 9a64fbe4 | bellard | } |
263 | 9a64fbe4 | bellard | |
264 | 9a64fbe4 | bellard | void do_fctiwz (void) |
265 | 9a64fbe4 | bellard | { |
266 | 9a64fbe4 | bellard | union {
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267 | 9a64fbe4 | bellard | double d;
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268 | 9a64fbe4 | bellard | uint64_t i; |
269 | 4ecc3190 | bellard | } p; |
270 | 4ecc3190 | bellard | |
271 | 4ecc3190 | bellard | /* XXX: higher bits are not supposed to be significant.
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272 | 4ecc3190 | bellard | * to make tests easier, return the same as a real PPC 750 (aka G3)
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273 | 4ecc3190 | bellard | */
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274 | 4ecc3190 | bellard | p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status); |
275 | 4ecc3190 | bellard | p.i |= 0xFFF80000ULL << 32; |
276 | 4ecc3190 | bellard | FT0 = p.d; |
277 | 9a64fbe4 | bellard | } |
278 | 9a64fbe4 | bellard | |
279 | 4b3686fa | bellard | void do_fnmadd (void) |
280 | 4b3686fa | bellard | { |
281 | 4ecc3190 | bellard | FT0 = (FT0 * FT1) + FT2; |
282 | 4ecc3190 | bellard | if (!isnan(FT0))
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283 | 4ecc3190 | bellard | FT0 = -FT0; |
284 | 4b3686fa | bellard | } |
285 | 4b3686fa | bellard | |
286 | 4b3686fa | bellard | void do_fnmsub (void) |
287 | 4b3686fa | bellard | { |
288 | 4ecc3190 | bellard | FT0 = (FT0 * FT1) - FT2; |
289 | 4ecc3190 | bellard | if (!isnan(FT0))
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290 | 4ecc3190 | bellard | FT0 = -FT0; |
291 | 4b3686fa | bellard | } |
292 | 4b3686fa | bellard | |
293 | 4ecc3190 | bellard | void do_fdiv (void) |
294 | 1ef59d0a | bellard | { |
295 | 4ecc3190 | bellard | if (FT0 == -0.0 && FT1 == -0.0) |
296 | 4ecc3190 | bellard | FT0 = 0.0 / 0.0; |
297 | 4ecc3190 | bellard | else
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298 | 4ecc3190 | bellard | FT0 /= FT1; |
299 | 1ef59d0a | bellard | } |
300 | 1ef59d0a | bellard | |
301 | 9a64fbe4 | bellard | void do_fsqrt (void) |
302 | 9a64fbe4 | bellard | { |
303 | 9a64fbe4 | bellard | FT0 = sqrt(FT0); |
304 | 9a64fbe4 | bellard | } |
305 | 9a64fbe4 | bellard | |
306 | 9a64fbe4 | bellard | void do_fres (void) |
307 | 9a64fbe4 | bellard | { |
308 | 4ecc3190 | bellard | union {
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309 | 4ecc3190 | bellard | double d;
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310 | 4ecc3190 | bellard | uint64_t i; |
311 | 4ecc3190 | bellard | } p; |
312 | 4ecc3190 | bellard | |
313 | 4ecc3190 | bellard | if (isnormal(FT0)) {
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314 | 4ecc3190 | bellard | FT0 = (float)(1.0 / FT0); |
315 | 4ecc3190 | bellard | } else {
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316 | 4ecc3190 | bellard | p.d = FT0; |
317 | 4ecc3190 | bellard | if (p.i == 0x8000000000000000ULL) { |
318 | 4ecc3190 | bellard | p.i = 0xFFF0000000000000ULL;
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319 | 4ecc3190 | bellard | } else if (p.i == 0x0000000000000000ULL) { |
320 | 4ecc3190 | bellard | p.i = 0x7FF0000000000000ULL;
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321 | 4ecc3190 | bellard | } else if (isnan(FT0)) { |
322 | 4ecc3190 | bellard | p.i = 0x7FF8000000000000ULL;
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323 | 4ecc3190 | bellard | } else if (FT0 < 0.0) { |
324 | 4ecc3190 | bellard | p.i = 0x8000000000000000ULL;
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325 | 4ecc3190 | bellard | } else {
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326 | 4ecc3190 | bellard | p.i = 0x0000000000000000ULL;
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327 | 4ecc3190 | bellard | } |
328 | 4ecc3190 | bellard | FT0 = p.d; |
329 | 4ecc3190 | bellard | } |
330 | 9a64fbe4 | bellard | } |
331 | 9a64fbe4 | bellard | |
332 | 4ecc3190 | bellard | void do_frsqrte (void) |
333 | 9a64fbe4 | bellard | { |
334 | 4ecc3190 | bellard | union {
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335 | 4ecc3190 | bellard | double d;
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336 | 4ecc3190 | bellard | uint64_t i; |
337 | 4ecc3190 | bellard | } p; |
338 | 4ecc3190 | bellard | |
339 | 4ecc3190 | bellard | if (isnormal(FT0) && FT0 > 0.0) { |
340 | 4ecc3190 | bellard | FT0 = (float)(1.0 / sqrt(FT0)); |
341 | 4ecc3190 | bellard | } else {
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342 | 4ecc3190 | bellard | p.d = FT0; |
343 | 4ecc3190 | bellard | if (p.i == 0x8000000000000000ULL) { |
344 | 4ecc3190 | bellard | p.i = 0xFFF0000000000000ULL;
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345 | 4ecc3190 | bellard | } else if (p.i == 0x0000000000000000ULL) { |
346 | 4ecc3190 | bellard | p.i = 0x7FF0000000000000ULL;
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347 | 4ecc3190 | bellard | } else if (isnan(FT0)) { |
348 | 4ecc3190 | bellard | if (!(p.i & 0x0008000000000000ULL)) |
349 | 4ecc3190 | bellard | p.i |= 0x000FFFFFFFFFFFFFULL;
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350 | 4ecc3190 | bellard | } else if (FT0 < 0) { |
351 | 4ecc3190 | bellard | p.i = 0x7FF8000000000000ULL;
|
352 | 4ecc3190 | bellard | } else {
|
353 | 4ecc3190 | bellard | p.i = 0x0000000000000000ULL;
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354 | 4ecc3190 | bellard | } |
355 | 4ecc3190 | bellard | FT0 = p.d; |
356 | 4ecc3190 | bellard | } |
357 | 9a64fbe4 | bellard | } |
358 | 9a64fbe4 | bellard | |
359 | 9a64fbe4 | bellard | void do_fsel (void) |
360 | 9a64fbe4 | bellard | { |
361 | 9a64fbe4 | bellard | if (FT0 >= 0) |
362 | 9a64fbe4 | bellard | FT0 = FT1; |
363 | 4ecc3190 | bellard | else
|
364 | 4ecc3190 | bellard | FT0 = FT2; |
365 | 9a64fbe4 | bellard | } |
366 | 9a64fbe4 | bellard | |
367 | 9a64fbe4 | bellard | void do_fcmpu (void) |
368 | 9a64fbe4 | bellard | { |
369 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
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370 | 9a64fbe4 | bellard | T0 = 0x01;
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371 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
372 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
373 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
374 | 9a64fbe4 | bellard | T0 = 0x08;
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375 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
376 | 9a64fbe4 | bellard | T0 = 0x04;
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377 | 9a64fbe4 | bellard | } else {
|
378 | 9a64fbe4 | bellard | T0 = 0x02;
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379 | 9a64fbe4 | bellard | } |
380 | 4b3686fa | bellard | env->fpscr[3] = T0;
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381 | 9a64fbe4 | bellard | } |
382 | 9a64fbe4 | bellard | |
383 | 9a64fbe4 | bellard | void do_fcmpo (void) |
384 | 9a64fbe4 | bellard | { |
385 | 9a64fbe4 | bellard | env->fpscr[4] &= ~0x1; |
386 | 9a64fbe4 | bellard | if (isnan(FT0) || isnan(FT1)) {
|
387 | 9a64fbe4 | bellard | T0 = 0x01;
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388 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x1; |
389 | 9a64fbe4 | bellard | /* I don't know how to test "quiet" nan... */
|
390 | 9a64fbe4 | bellard | if (0 /* || ! quiet_nan(...) */) { |
391 | 9a64fbe4 | bellard | env->fpscr[6] |= 0x1; |
392 | 9a64fbe4 | bellard | if (!(env->fpscr[1] & 0x8)) |
393 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
394 | 9a64fbe4 | bellard | } else {
|
395 | 9a64fbe4 | bellard | env->fpscr[4] |= 0x8; |
396 | 9a64fbe4 | bellard | } |
397 | 9a64fbe4 | bellard | } else if (FT0 < FT1) { |
398 | 9a64fbe4 | bellard | T0 = 0x08;
|
399 | 9a64fbe4 | bellard | } else if (FT0 > FT1) { |
400 | 9a64fbe4 | bellard | T0 = 0x04;
|
401 | 9a64fbe4 | bellard | } else {
|
402 | 9a64fbe4 | bellard | T0 = 0x02;
|
403 | 9a64fbe4 | bellard | } |
404 | 4b3686fa | bellard | env->fpscr[3] = T0;
|
405 | 9a64fbe4 | bellard | } |
406 | 9a64fbe4 | bellard | |
407 | 9a64fbe4 | bellard | void do_fabs (void) |
408 | 9a64fbe4 | bellard | { |
409 | 4ecc3190 | bellard | union {
|
410 | 4ecc3190 | bellard | double d;
|
411 | 4ecc3190 | bellard | uint64_t i; |
412 | 4ecc3190 | bellard | } p; |
413 | 4ecc3190 | bellard | |
414 | 4ecc3190 | bellard | p.d = FT0; |
415 | 4ecc3190 | bellard | p.i &= ~0x8000000000000000ULL;
|
416 | 4ecc3190 | bellard | FT0 = p.d; |
417 | 9a64fbe4 | bellard | } |
418 | 9a64fbe4 | bellard | |
419 | 9a64fbe4 | bellard | void do_fnabs (void) |
420 | 9a64fbe4 | bellard | { |
421 | 4ecc3190 | bellard | union {
|
422 | 4ecc3190 | bellard | double d;
|
423 | 4ecc3190 | bellard | uint64_t i; |
424 | 4ecc3190 | bellard | } p; |
425 | 4ecc3190 | bellard | |
426 | 4ecc3190 | bellard | p.d = FT0; |
427 | 4ecc3190 | bellard | p.i |= 0x8000000000000000ULL;
|
428 | 4ecc3190 | bellard | FT0 = p.d; |
429 | 9a64fbe4 | bellard | } |
430 | 9a64fbe4 | bellard | |
431 | 9a64fbe4 | bellard | /* Instruction cache invalidation helper */
|
432 | 985a19d6 | bellard | #define ICACHE_LINE_SIZE 32 |
433 | 985a19d6 | bellard | |
434 | 4b3686fa | bellard | void do_check_reservation (void) |
435 | 4b3686fa | bellard | { |
436 | 18fba28c | bellard | if ((env->reserve & ~0x03) == T0) |
437 | 4b3686fa | bellard | env->reserve = -1;
|
438 | 4b3686fa | bellard | } |
439 | 4b3686fa | bellard | |
440 | 9a64fbe4 | bellard | void do_icbi (void) |
441 | 9a64fbe4 | bellard | { |
442 | 985a19d6 | bellard | /* Invalidate one cache line */
|
443 | 985a19d6 | bellard | T0 &= ~(ICACHE_LINE_SIZE - 1);
|
444 | 985a19d6 | bellard | tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE); |
445 | 9a64fbe4 | bellard | } |
446 | 9a64fbe4 | bellard | |
447 | 9a64fbe4 | bellard | /* TLB invalidation helpers */
|
448 | 9a64fbe4 | bellard | void do_tlbia (void) |
449 | 9a64fbe4 | bellard | { |
450 | ad081323 | bellard | tlb_flush(env, 1);
|
451 | 9a64fbe4 | bellard | } |
452 | 9a64fbe4 | bellard | |
453 | 9a64fbe4 | bellard | void do_tlbie (void) |
454 | 9a64fbe4 | bellard | { |
455 | 9a64fbe4 | bellard | tlb_flush_page(env, T0); |
456 | 9a64fbe4 | bellard | } |
457 | 9a64fbe4 | bellard | |
458 | 4b3686fa | bellard | void do_store_sr (uint32_t srnum)
|
459 | 4b3686fa | bellard | { |
460 | 4b3686fa | bellard | #if defined (DEBUG_OP)
|
461 | 4b3686fa | bellard | dump_store_sr(srnum); |
462 | 4b3686fa | bellard | #endif
|
463 | 4b3686fa | bellard | #if 0 // TRY
|
464 | 4b3686fa | bellard | {
|
465 | 4b3686fa | bellard | uint32_t base, page;
|
466 | 4b3686fa | bellard |
|
467 | 4b3686fa | bellard | base = srnum << 28;
|
468 | 4b3686fa | bellard | for (page = base; page != base + 0x100000000; page += 0x1000)
|
469 | 4b3686fa | bellard | tlb_flush_page(env, page);
|
470 | 4b3686fa | bellard | }
|
471 | 4b3686fa | bellard | #else
|
472 | 4b3686fa | bellard | tlb_flush(env, 1);
|
473 | 4b3686fa | bellard | #endif
|
474 | 4b3686fa | bellard | env->sr[srnum] = T0; |
475 | 4b3686fa | bellard | } |
476 | 4b3686fa | bellard | |
477 | 4b3686fa | bellard | /* For BATs, we may not invalidate any TLBs if the change is only on
|
478 | 4b3686fa | bellard | * protection bits for user mode.
|
479 | 4b3686fa | bellard | */
|
480 | 4b3686fa | bellard | void do_store_ibat (int ul, int nr) |
481 | 4b3686fa | bellard | { |
482 | 4b3686fa | bellard | #if defined (DEBUG_OP)
|
483 | 4b3686fa | bellard | dump_store_ibat(ul, nr); |
484 | 4b3686fa | bellard | #endif
|
485 | 4b3686fa | bellard | #if 0 // TRY
|
486 | 4b3686fa | bellard | {
|
487 | 4b3686fa | bellard | uint32_t base, length, page;
|
488 | 4b3686fa | bellard | |
489 | 4b3686fa | bellard | base = env->IBAT[0][nr];
|
490 | 4b3686fa | bellard | length = (((base >> 2) & 0x000007FF) + 1) << 17;
|
491 | 4b3686fa | bellard | base &= 0xFFFC0000;
|
492 | 4b3686fa | bellard | for (page = base; page != base + length; page += 0x1000)
|
493 | 4b3686fa | bellard | tlb_flush_page(env, page);
|
494 | 4b3686fa | bellard | }
|
495 | 4b3686fa | bellard | #else
|
496 | 4b3686fa | bellard | tlb_flush(env, 1);
|
497 | 4b3686fa | bellard | #endif
|
498 | 4b3686fa | bellard | env->IBAT[ul][nr] = T0; |
499 | 4b3686fa | bellard | } |
500 | 4b3686fa | bellard | |
501 | 4b3686fa | bellard | void do_store_dbat (int ul, int nr) |
502 | 4b3686fa | bellard | { |
503 | 4b3686fa | bellard | #if defined (DEBUG_OP)
|
504 | 4b3686fa | bellard | dump_store_dbat(ul, nr); |
505 | 4b3686fa | bellard | #endif
|
506 | 4b3686fa | bellard | #if 0 // TRY
|
507 | 4b3686fa | bellard | {
|
508 | 4b3686fa | bellard | uint32_t base, length, page;
|
509 | 4b3686fa | bellard | base = env->DBAT[0][nr];
|
510 | 4b3686fa | bellard | length = (((base >> 2) & 0x000007FF) + 1) << 17;
|
511 | 4b3686fa | bellard | base &= 0xFFFC0000;
|
512 | 4b3686fa | bellard | for (page = base; page != base + length; page += 0x1000)
|
513 | 4b3686fa | bellard | tlb_flush_page(env, page);
|
514 | 4b3686fa | bellard | }
|
515 | 4b3686fa | bellard | #else
|
516 | 4b3686fa | bellard | tlb_flush(env, 1);
|
517 | 4b3686fa | bellard | #endif
|
518 | 4b3686fa | bellard | env->DBAT[ul][nr] = T0; |
519 | 4b3686fa | bellard | } |
520 | 4b3686fa | bellard | |
521 | 9a64fbe4 | bellard | /*****************************************************************************/
|
522 | 9a64fbe4 | bellard | /* Special helpers for debug */
|
523 | a541f297 | bellard | void dump_state (void) |
524 | a541f297 | bellard | { |
525 | 7fe48483 | bellard | // cpu_dump_state(env, stdout, fprintf, 0);
|
526 | a541f297 | bellard | } |
527 | a541f297 | bellard | |
528 | 9a64fbe4 | bellard | void dump_rfi (void) |
529 | 9a64fbe4 | bellard | { |
530 | 9a64fbe4 | bellard | #if 0
|
531 | 4b3686fa | bellard | printf("Return from interrupt => 0x%08x\n", env->nip);
|
532 | 7fe48483 | bellard | // cpu_dump_state(env, stdout, fprintf, 0);
|
533 | 9a64fbe4 | bellard | #endif
|
534 | 9a64fbe4 | bellard | } |
535 | 9a64fbe4 | bellard | |
536 | 9a64fbe4 | bellard | void dump_store_sr (int srnum) |
537 | 9a64fbe4 | bellard | { |
538 | 9a64fbe4 | bellard | #if 0
|
539 | 9a64fbe4 | bellard | printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
|
540 | 9a64fbe4 | bellard | #endif
|
541 | 9a64fbe4 | bellard | } |
542 | 9a64fbe4 | bellard | |
543 | 9a64fbe4 | bellard | static void _dump_store_bat (char ID, int ul, int nr) |
544 | 9a64fbe4 | bellard | { |
545 | 9a64fbe4 | bellard | printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
|
546 | 9a64fbe4 | bellard | ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip); |
547 | 9a64fbe4 | bellard | } |
548 | 9a64fbe4 | bellard | |
549 | 9a64fbe4 | bellard | void dump_store_ibat (int ul, int nr) |
550 | 9a64fbe4 | bellard | { |
551 | 9a64fbe4 | bellard | _dump_store_bat('I', ul, nr);
|
552 | 9a64fbe4 | bellard | } |
553 | 9a64fbe4 | bellard | |
554 | 9a64fbe4 | bellard | void dump_store_dbat (int ul, int nr) |
555 | 9a64fbe4 | bellard | { |
556 | 9a64fbe4 | bellard | _dump_store_bat('D', ul, nr);
|
557 | 9a64fbe4 | bellard | } |
558 | 9a64fbe4 | bellard | |
559 | 9a64fbe4 | bellard | void dump_store_tb (int ul) |
560 | 9a64fbe4 | bellard | { |
561 | 9a64fbe4 | bellard | printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0); |
562 | 9a64fbe4 | bellard | } |
563 | 9a64fbe4 | bellard | |
564 | 9a64fbe4 | bellard | void dump_update_tb(uint32_t param)
|
565 | 9a64fbe4 | bellard | { |
566 | 9a64fbe4 | bellard | #if 0
|
567 | 9a64fbe4 | bellard | printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
|
568 | 9a64fbe4 | bellard | #endif
|
569 | 9a64fbe4 | bellard | } |