Revision 30c0c76c tcg/sparc/tcg-target.c

b/tcg/sparc/tcg-target.c
1319 1319
    case INDEX_op_qemu_ld32u:
1320 1320
        tcg_out_qemu_ld(s, args, 2);
1321 1321
        break;
1322
#if TCG_TARGET_REG_BITS == 64
1322 1323
    case INDEX_op_qemu_ld32s:
1323 1324
        tcg_out_qemu_ld(s, args, 2 | 4);
1324 1325
        break;
1326
#endif
1325 1327
    case INDEX_op_qemu_st8:
1326 1328
        tcg_out_qemu_st(s, args, 0);
1327 1329
        break;
......
1471 1473
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1472 1474
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1473 1475
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1476
#if TCG_TARGET_REG_BITS == 64
1474 1477
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1478
#endif
1475 1479

  
1476 1480
    { INDEX_op_qemu_st8, { "L", "L" } },
1477 1481
    { INDEX_op_qemu_st16, { "L", "L" } },

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