tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-sparc: Implement ORC.
tcg-sparc: Implement ANDC.
tcg-sparc: Implement not.
The fallback implementation of "ret = arg1 ^ -1" isn't idealbecause of the extra tcg op to load the minus one.
tcg-sparc: Implement neg.
The fallback implementation of "ret = 0 - arg1" isn't ideal,first because of the extra tcg op to load the zero, and secondbecause we fail to handle zero as %g0 for arg1 of the sub.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg-sparc: Implement setcond, setcond2.
tcg-sparc: Implement ext32[su]_i64
The 32-bit right-shift instructions is defined to extend the shiftedoutput to 64-bits. A shift count of zero therefore is a simpleextension without actually shifting.
tcg-sparc: Implement division properly.
The {div,divu}2 opcodes are intended for systems for which thedivision instruction produces both quotient and remainder. Sparcis not such a system. Indeed, the remainder must be computed as
quot = a / b rem = a - (quot * b)...
tcg-sparc: Do not remove %o012 from 'r' constraint.
Only 'L' constraint needs that.
View revisions
Also available in: Atom