Revision 30ca2aab

b/hw/ne2000.c
538 538
    return 0;
539 539
}
540 540

  
541
static void ne2000_save(QEMUFile* f,void* opaque)
542
{
543
	NE2000State* s=(NE2000State*)opaque;
544

  
545
	qemu_put_8s(f, &s->cmd);
546
	qemu_put_be32s(f, &s->start);
547
	qemu_put_be32s(f, &s->stop);
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	qemu_put_8s(f, &s->boundary);
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	qemu_put_8s(f, &s->tsr);
550
	qemu_put_8s(f, &s->tpsr);
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	qemu_put_be16s(f, &s->tcnt);
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	qemu_put_be16s(f, &s->rcnt);
553
	qemu_put_be32s(f, &s->rsar);
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	qemu_put_8s(f, &s->rsr);
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	qemu_put_8s(f, &s->isr);
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	qemu_put_8s(f, &s->dcfg);
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	qemu_put_8s(f, &s->imr);
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	qemu_put_buffer(f, s->phys, 6);
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	qemu_put_8s(f, &s->curpag);
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	qemu_put_buffer(f, s->mult, 8);
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	qemu_put_be32s(f, &s->irq);
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	qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
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}
564

  
565
static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
566
{
567
	NE2000State* s=(NE2000State*)opaque;
568

  
569
	if (version_id != 1)
570
            return -EINVAL;
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572
	qemu_get_8s(f, &s->cmd);
573
	qemu_get_be32s(f, &s->start);
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	qemu_get_be32s(f, &s->stop);
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	qemu_get_8s(f, &s->boundary);
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	qemu_get_8s(f, &s->tsr);
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	qemu_get_8s(f, &s->tpsr);
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	qemu_get_be16s(f, &s->tcnt);
579
	qemu_get_be16s(f, &s->rcnt);
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	qemu_get_be32s(f, &s->rsar);
581
	qemu_get_8s(f, &s->rsr);
582
	qemu_get_8s(f, &s->isr);
583
	qemu_get_8s(f, &s->dcfg);
584
	qemu_get_8s(f, &s->imr);
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	qemu_get_buffer(f, s->phys, 6);
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	qemu_get_8s(f, &s->curpag);
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	qemu_get_buffer(f, s->mult, 8);
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	qemu_get_be32s(f, &s->irq);
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	qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
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591
	return 0;
592
}
593

  
541 594
void isa_ne2000_init(int base, int irq, NetDriverState *nd)
542 595
{
543 596
    NE2000State *s;
......
562 615
    ne2000_reset(s);
563 616

  
564 617
    qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
618

  
619
    register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
620

  
565 621
}
566 622

  
567 623
/***********************************************************/
......
612 668
    pci_conf[0x0e] = 0x00; // header_type
613 669
    pci_conf[0x3d] = 1; // interrupt pin 0
614 670
    
615
    pci_register_io_region((PCIDevice *)d, 0, 0x100, 
671
    pci_register_io_region(&d->dev, 0, 0x100, 
616 672
                           PCI_ADDRESS_SPACE_IO, ne2000_map);
617 673
    s = &d->ne2000;
618 674
    s->irq = 16; // PCI interrupt
......
620 676
    s->nd = nd;
621 677
    ne2000_reset(s);
622 678
    qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
679

  
680
    /* XXX: instance number ? */
681
    register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
682
    register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load, 
683
                    &d->dev);
623 684
}
b/hw/pci.c
62 62
    return bus;
63 63
}
64 64

  
65
void generic_pci_save(QEMUFile* f, void *opaque)
66
{
67
    PCIDevice* s=(PCIDevice*)opaque;
68

  
69
    qemu_put_buffer(f, s->config, 256);
70
}
71

  
72
int generic_pci_load(QEMUFile* f, void *opaque, int version_id)
73
{
74
    PCIDevice* s=(PCIDevice*)opaque;
75

  
76
    if (version_id != 1)
77
        return -EINVAL;
78

  
79
    qemu_get_buffer(f, s->config, 256);
80
    return 0;
81
}
82

  
65 83
/* -1 for devfn means auto assign */
66 84
PCIDevice *pci_register_device(PCIBus *bus, const char *name, 
67 85
                               int instance_size, int devfn,
......
558 576

  
559 577
    d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
560 578
                                          -1, NULL, NULL);
579
    register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
580

  
561 581
    piix3_state = d;
562 582
    pci_conf = d->dev.config;
563 583

  
b/vl.h
480 480
                                 uint32_t address, int len);
481 481
void pci_default_write_config(PCIDevice *d, 
482 482
                              uint32_t address, uint32_t val, int len);
483
void generic_pci_save(QEMUFile* f, void *opaque);
484
int generic_pci_load(QEMUFile* f, void *opaque, int version_id);
483 485

  
484 486
extern struct PIIX3State *piix3_state;
485 487

  

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