Revision 3101e99c
| b/target-sh4/translate.c | ||
|---|---|---|
| 664 | 664 |
TCGv addr = tcg_temp_new(); |
| 665 | 665 |
tcg_gen_subi_i32(addr, REG(B11_8), 1); |
| 666 | 666 |
tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ |
| 667 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */
|
|
| 667 |
tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
|
|
| 668 | 668 |
tcg_temp_free(addr); |
| 669 | 669 |
} |
| 670 | 670 |
return; |
| ... | ... | |
| 673 | 673 |
TCGv addr = tcg_temp_new(); |
| 674 | 674 |
tcg_gen_subi_i32(addr, REG(B11_8), 2); |
| 675 | 675 |
tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
| 676 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
|
|
| 676 |
tcg_gen_mov_i32(REG(B11_8), addr);
|
|
| 677 | 677 |
tcg_temp_free(addr); |
| 678 | 678 |
} |
| 679 | 679 |
return; |
| ... | ... | |
| 682 | 682 |
TCGv addr = tcg_temp_new(); |
| 683 | 683 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 684 | 684 |
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
| 685 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
|
| 685 |
tcg_gen_mov_i32(REG(B11_8), addr);
|
|
| 686 | 686 |
} |
| 687 | 687 |
return; |
| 688 | 688 |
case 0x6004: /* mov.b @Rm+,Rn */ |
| ... | ... | |
| 750 | 750 |
return; |
| 751 | 751 |
case 0x6008: /* swap.b Rm,Rn */ |
| 752 | 752 |
{
|
| 753 |
TCGv highw, high, low; |
|
| 754 |
highw = tcg_temp_new(); |
|
| 755 |
tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000); |
|
| 753 |
TCGv high, low; |
|
| 756 | 754 |
high = tcg_temp_new(); |
| 757 |
tcg_gen_ext8u_i32(high, REG(B7_4)); |
|
| 758 |
tcg_gen_shli_i32(high, high, 8); |
|
| 755 |
tcg_gen_andi_i32(high, REG(B7_4), 0xffff0000); |
|
| 759 | 756 |
low = tcg_temp_new(); |
| 760 |
tcg_gen_shri_i32(low, REG(B7_4), 8);
|
|
| 761 |
tcg_gen_ext8u_i32(low, low);
|
|
| 757 |
tcg_gen_ext16u_i32(low, REG(B7_4));
|
|
| 758 |
tcg_gen_bswap16_i32(low, low);
|
|
| 762 | 759 |
tcg_gen_or_i32(REG(B11_8), high, low); |
| 763 |
tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw); |
|
| 764 | 760 |
tcg_temp_free(low); |
| 765 | 761 |
tcg_temp_free(high); |
| 766 | 762 |
} |
| ... | ... | |
| 769 | 765 |
{
|
| 770 | 766 |
TCGv high, low; |
| 771 | 767 |
high = tcg_temp_new(); |
| 772 |
tcg_gen_ext16u_i32(high, REG(B7_4)); |
|
| 773 |
tcg_gen_shli_i32(high, high, 16); |
|
| 768 |
tcg_gen_shli_i32(high, REG(B7_4), 16); |
|
| 774 | 769 |
low = tcg_temp_new(); |
| 775 | 770 |
tcg_gen_shri_i32(low, REG(B7_4), 16); |
| 776 | 771 |
tcg_gen_ext16u_i32(low, low); |
| ... | ... | |
| 783 | 778 |
{
|
| 784 | 779 |
TCGv high, low; |
| 785 | 780 |
high = tcg_temp_new(); |
| 786 |
tcg_gen_ext16u_i32(high, REG(B7_4)); |
|
| 787 |
tcg_gen_shli_i32(high, high, 16); |
|
| 781 |
tcg_gen_shli_i32(high, REG(B7_4), 16); |
|
| 788 | 782 |
low = tcg_temp_new(); |
| 789 | 783 |
tcg_gen_shri_i32(low, REG(B11_8), 16); |
| 790 | 784 |
tcg_gen_ext16u_i32(low, low); |
| ... | ... | |
| 974 | 968 |
int label2 = gen_new_label(); |
| 975 | 969 |
int label3 = gen_new_label(); |
| 976 | 970 |
int label4 = gen_new_label(); |
| 977 |
TCGv shift = tcg_temp_local_new();
|
|
| 971 |
TCGv shift; |
|
| 978 | 972 |
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
| 979 | 973 |
/* Rm positive, shift to the left */ |
| 974 |
shift = tcg_temp_new(); |
|
| 980 | 975 |
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
| 981 | 976 |
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
| 977 |
tcg_temp_free(shift); |
|
| 982 | 978 |
tcg_gen_br(label4); |
| 983 | 979 |
/* Rm negative, shift to the right */ |
| 984 | 980 |
gen_set_label(label1); |
| 981 |
shift = tcg_temp_new(); |
|
| 985 | 982 |
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
| 986 | 983 |
tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); |
| 987 | 984 |
tcg_gen_not_i32(shift, REG(B7_4)); |
| 988 | 985 |
tcg_gen_andi_i32(shift, shift, 0x1f); |
| 989 | 986 |
tcg_gen_addi_i32(shift, shift, 1); |
| 990 | 987 |
tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); |
| 988 |
tcg_temp_free(shift); |
|
| 991 | 989 |
tcg_gen_br(label4); |
| 992 | 990 |
/* Rm = -32 */ |
| 993 | 991 |
gen_set_label(label2); |
| ... | ... | |
| 997 | 995 |
gen_set_label(label3); |
| 998 | 996 |
tcg_gen_movi_i32(REG(B11_8), 0xffffffff); |
| 999 | 997 |
gen_set_label(label4); |
| 1000 |
tcg_temp_free(shift); |
|
| 1001 | 998 |
} |
| 1002 | 999 |
return; |
| 1003 | 1000 |
case 0x400d: /* shld Rm,Rn */ |
| ... | ... | |
| 1005 | 1002 |
int label1 = gen_new_label(); |
| 1006 | 1003 |
int label2 = gen_new_label(); |
| 1007 | 1004 |
int label3 = gen_new_label(); |
| 1008 |
TCGv shift = tcg_temp_local_new();
|
|
| 1005 |
TCGv shift; |
|
| 1009 | 1006 |
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
| 1010 | 1007 |
/* Rm positive, shift to the left */ |
| 1008 |
shift = tcg_temp_new(); |
|
| 1011 | 1009 |
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
| 1012 | 1010 |
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
| 1011 |
tcg_temp_free(shift); |
|
| 1013 | 1012 |
tcg_gen_br(label3); |
| 1014 | 1013 |
/* Rm negative, shift to the right */ |
| 1015 | 1014 |
gen_set_label(label1); |
| 1015 |
shift = tcg_temp_new(); |
|
| 1016 | 1016 |
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
| 1017 | 1017 |
tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); |
| 1018 | 1018 |
tcg_gen_not_i32(shift, REG(B7_4)); |
| 1019 | 1019 |
tcg_gen_andi_i32(shift, shift, 0x1f); |
| 1020 | 1020 |
tcg_gen_addi_i32(shift, shift, 1); |
| 1021 | 1021 |
tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); |
| 1022 |
tcg_temp_free(shift); |
|
| 1022 | 1023 |
tcg_gen_br(label3); |
| 1023 | 1024 |
/* Rm = -32 */ |
| 1024 | 1025 |
gen_set_label(label2); |
| 1025 | 1026 |
tcg_gen_movi_i32(REG(B11_8), 0); |
| 1026 | 1027 |
gen_set_label(label3); |
| 1027 |
tcg_temp_free(shift); |
|
| 1028 | 1028 |
} |
| 1029 | 1029 |
return; |
| 1030 | 1030 |
case 0x3008: /* sub Rm,Rn */ |
| ... | ... | |
| 1106 | 1106 |
int fr = XREG(B7_4); |
| 1107 | 1107 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1108 | 1108 |
tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx); |
| 1109 |
tcg_gen_subi_i32(addr, REG(B11_8), 8);
|
|
| 1109 |
tcg_gen_subi_i32(addr, addr, 4);
|
|
| 1110 | 1110 |
tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); |
| 1111 | 1111 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 1112 | 1112 |
tcg_temp_free(addr); |
| ... | ... | |
| 1115 | 1115 |
addr = tcg_temp_new_i32(); |
| 1116 | 1116 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1117 | 1117 |
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
| 1118 |
tcg_gen_mov_i32(REG(B11_8), addr); |
|
| 1118 | 1119 |
tcg_temp_free(addr); |
| 1119 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
|
| 1120 | 1120 |
} |
| 1121 | 1121 |
return; |
| 1122 | 1122 |
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
|
| ... | ... | |
| 1436 | 1436 |
TCGv addr = tcg_temp_new(); |
| 1437 | 1437 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1438 | 1438 |
tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); |
| 1439 |
tcg_gen_mov_i32(REG(B11_8), addr); |
|
| 1439 | 1440 |
tcg_temp_free(addr); |
| 1440 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
|
| 1441 | 1441 |
} |
| 1442 | 1442 |
return; |
| 1443 | 1443 |
} |
| ... | ... | |
| 1505 | 1505 |
TCGv addr = tcg_temp_new(); |
| 1506 | 1506 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1507 | 1507 |
tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); |
| 1508 |
tcg_gen_mov_i32(REG(B11_8), addr); |
|
| 1508 | 1509 |
tcg_temp_free(addr); |
| 1509 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
|
| 1510 | 1510 |
} |
| 1511 | 1511 |
return; |
| 1512 | 1512 |
#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ |
| ... | ... | |
| 1526 | 1526 |
case stpnum: \ |
| 1527 | 1527 |
prechk \ |
| 1528 | 1528 |
{ \
|
| 1529 |
TCGv addr = tcg_temp_new(); \ |
|
| 1529 |
TCGv addr = tcg_temp_new(); \
|
|
| 1530 | 1530 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); \ |
| 1531 | 1531 |
tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ |
| 1532 |
tcg_gen_mov_i32(REG(B11_8), addr); \ |
|
| 1532 | 1533 |
tcg_temp_free(addr); \ |
| 1533 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \ |
|
| 1534 | 1534 |
} \ |
| 1535 | 1535 |
return; |
| 1536 | 1536 |
LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {})
|
| ... | ... | |
| 1571 | 1571 |
addr = tcg_temp_new(); |
| 1572 | 1572 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1573 | 1573 |
tcg_gen_qemu_st32(val, addr, ctx->memidx); |
| 1574 |
tcg_gen_mov_i32(REG(B11_8), addr); |
|
| 1574 | 1575 |
tcg_temp_free(addr); |
| 1575 | 1576 |
tcg_temp_free(val); |
| 1576 |
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
|
| 1577 | 1577 |
} |
| 1578 | 1578 |
return; |
| 1579 | 1579 |
case 0x00c3: /* movca.l R0,@Rm */ |
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