Revision 31c63201 hw/cirrus_vga.c
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 1302 | 1302 |
} |
| 1303 | 1303 |
} |
| 1304 | 1304 |
|
| 1305 |
static int |
|
| 1306 |
cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
|
| 1305 |
static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) |
|
| 1307 | 1306 |
{
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| 1308 |
switch (reg_index) {
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|
| 1307 |
switch (s->vga.sr_index) {
|
|
| 1309 | 1308 |
case 0x00: // Standard VGA |
| 1310 | 1309 |
case 0x01: // Standard VGA |
| 1311 | 1310 |
case 0x02: // Standard VGA |
| 1312 | 1311 |
case 0x03: // Standard VGA |
| 1313 | 1312 |
case 0x04: // Standard VGA |
| 1314 |
return CIRRUS_HOOK_NOT_HANDLED; |
|
| 1313 |
s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; |
|
| 1314 |
if (s->vga.sr_index == 1) |
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| 1315 |
s->vga.update_retrace_info(&s->vga); |
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| 1316 |
break; |
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| 1315 | 1317 |
case 0x06: // Unlock Cirrus extensions |
| 1316 |
reg_value &= 0x17;
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|
| 1317 |
if (reg_value == 0x12) {
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s->vga.sr[reg_index] = 0x12;
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val &= 0x17;
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if (val == 0x12) {
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s->vga.sr[s->vga.sr_index] = 0x12;
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|
| 1319 | 1321 |
} else {
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s->vga.sr[reg_index] = 0x0f;
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| 1322 |
s->vga.sr[s->vga.sr_index] = 0x0f;
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|
| 1321 | 1323 |
} |
| 1322 | 1324 |
break; |
| 1323 | 1325 |
case 0x10: |
| ... | ... | |
| 1328 | 1330 |
case 0xb0: |
| 1329 | 1331 |
case 0xd0: |
| 1330 | 1332 |
case 0xf0: // Graphics Cursor X |
| 1331 |
s->vga.sr[0x10] = reg_value;
|
|
| 1332 |
s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
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|
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s->vga.sr[0x10] = val;
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|
| 1334 |
s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
|
|
| 1333 | 1335 |
break; |
| 1334 | 1336 |
case 0x11: |
| 1335 | 1337 |
case 0x31: |
| ... | ... | |
| 1339 | 1341 |
case 0xb1: |
| 1340 | 1342 |
case 0xd1: |
| 1341 | 1343 |
case 0xf1: // Graphics Cursor Y |
| 1342 |
s->vga.sr[0x11] = reg_value;
|
|
| 1343 |
s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
|
|
| 1344 |
s->vga.sr[0x11] = val;
|
|
| 1345 |
s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
|
|
| 1344 | 1346 |
break; |
| 1345 | 1347 |
case 0x07: // Extended Sequencer Mode |
| 1346 | 1348 |
cirrus_update_memory_access(s); |
| ... | ... | |
| 1365 | 1367 |
case 0x1d: // VCLK 2 Denominator & Post |
| 1366 | 1368 |
case 0x1e: // VCLK 3 Denominator & Post |
| 1367 | 1369 |
case 0x1f: // BIOS Write Enable and MCLK select |
| 1368 |
s->vga.sr[reg_index] = reg_value;
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|
| 1370 |
s->vga.sr[s->vga.sr_index] = val;
|
|
| 1369 | 1371 |
#ifdef DEBUG_CIRRUS |
| 1370 | 1372 |
printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
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| 1371 |
reg_index, reg_value);
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s->vga.sr_index, val);
|
|
| 1372 | 1374 |
#endif |
| 1373 | 1375 |
break; |
| 1374 | 1376 |
case 0x17: // Configuration Readback and Extended Control |
| 1375 |
s->vga.sr[reg_index] = (s->vga.sr[reg_index] & 0x38) | (reg_value & 0xc7); |
|
| 1377 |
s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38) |
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| 1378 |
| (val & 0xc7); |
|
| 1376 | 1379 |
cirrus_update_memory_access(s); |
| 1377 | 1380 |
break; |
| 1378 | 1381 |
default: |
| 1379 | 1382 |
#ifdef DEBUG_CIRRUS |
| 1380 |
printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
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| 1381 |
reg_value);
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|
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printf("cirrus: outport sr_index %02x, sr_value %02x\n",
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s->vga.sr_index, val);
|
|
| 1382 | 1385 |
#endif |
| 1383 | 1386 |
break; |
| 1384 | 1387 |
} |
| 1385 |
|
|
| 1386 |
return CIRRUS_HOOK_HANDLED; |
|
| 1387 | 1388 |
} |
| 1388 | 1389 |
|
| 1389 | 1390 |
/*************************************** |
| ... | ... | |
| 2806 | 2807 |
s->sr_index = val; |
| 2807 | 2808 |
break; |
| 2808 | 2809 |
case 0x3c5: |
| 2809 |
if (cirrus_hook_write_sr(c, s->sr_index, val)) |
|
| 2810 |
break; |
|
| 2811 | 2810 |
#ifdef DEBUG_VGA_REG |
| 2812 | 2811 |
printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
| 2813 | 2812 |
#endif |
| 2814 |
s->sr[s->sr_index] = val & sr_mask[s->sr_index];
|
|
| 2815 |
if (s->sr_index == 1) s->update_retrace_info(s);
|
|
| 2813 |
cirrus_vga_write_sr(c, val);
|
|
| 2814 |
break;
|
|
| 2816 | 2815 |
break; |
| 2817 | 2816 |
case 0x3c6: |
| 2818 | 2817 |
cirrus_write_hidden_dac(c, val); |
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