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/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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|
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#include "cpu.h" |
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#include "qemu-common.h" |
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|
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//#define DEBUG_MMU
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//#define DEBUG_FEATURES
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|
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, ...) \
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do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF_MMU(fmt, ...) do {} while (0) |
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#endif
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|
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static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
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/* Sparc MMU emulation */
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#if defined(CONFIG_USER_ONLY)
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int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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if (rw & 2) |
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env1->exception_index = TT_TFAULT; |
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else
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env1->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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#else
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 8, 0, 12, 12 }, |
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{ 0, 0, 0, 0, 8, 0, 0, 0 }, |
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{ 8, 8, 0, 0, 0, 8, 12, 12 }, |
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{ 8, 8, 0, 0, 0, 8, 0, 0 }, |
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{ 8, 0, 8, 0, 8, 8, 12, 12 }, |
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{ 8, 0, 8, 0, 8, 0, 8, 0 }, |
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{ 8, 8, 8, 0, 8, 8, 12, 12 }, |
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{ 8, 8, 8, 0, 8, 8, 8, 0 } |
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}; |
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|
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static const int perm_table[2][8] = { |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC |
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}, |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ, |
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0,
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0,
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} |
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}; |
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|
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static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
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int *prot, int *access_index, |
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target_ulong address, int rw, int mmu_idx, |
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target_ulong *page_size) |
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{ |
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int access_perms = 0; |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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int error_code = 0, is_dirty, is_user; |
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unsigned long page_offset; |
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is_user = mmu_idx == MMU_USER_IDX; |
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|
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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*page_size = TARGET_PAGE_SIZE; |
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// Boot mode: instruction fetches are taken from PROM
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if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { |
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC; |
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return 0; |
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} |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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|
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xffffffffffff0000ULL;
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|
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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page_offset = (address & TARGET_PAGE_MASK) & |
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(TARGET_PAGE_SIZE - 1);
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} |
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*page_size = TARGET_PAGE_SIZE; |
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break;
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case 2: /* L2 PTE */ |
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page_offset = address & 0x3ffff;
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*page_size = 0x40000;
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} |
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break;
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case 2: /* L1 PTE */ |
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page_offset = address & 0xffffff;
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*page_size = 0x1000000;
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} |
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} |
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
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return error_code;
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty)
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pde |= PG_MODIFIED_MASK; |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms]; |
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE; |
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} |
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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target_phys_addr_t paddr; |
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target_ulong vaddr; |
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target_ulong page_size; |
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int error_code = 0, prot, access_index; |
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error_code = get_physical_address(env, &paddr, &prot, &access_index, |
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address, rw, mmu_idx, &page_size); |
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if (error_code == 0) { |
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vaddr = address & TARGET_PAGE_MASK; |
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paddr &= TARGET_PAGE_MASK; |
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); |
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return 0; |
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} |
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|
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if (env->mmuregs[3]) /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
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env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
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env->mmuregs[4] = address; /* Fault address register */ |
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|
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); |
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return 0; |
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} else {
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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} |
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|
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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{ |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
262 |
|
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/* Context base + context number */
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
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(env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
267 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
271 |
case 2: /* PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 0; |
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case 1: /* L1 PDE */ |
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if (mmulev == 3) |
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return pde;
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
279 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
283 |
case 3: /* Reserved */ |
284 |
return 0; |
285 |
case 2: /* L1 PTE */ |
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return pde;
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case 1: /* L2 PDE */ |
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if (mmulev == 2) |
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return pde;
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
292 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
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case 0: /* Invalid */ |
296 |
case 3: /* Reserved */ |
297 |
return 0; |
298 |
case 2: /* L2 PTE */ |
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return pde;
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case 1: /* L3 PDE */ |
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if (mmulev == 1) |
302 |
return pde;
|
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
305 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
309 |
case 1: /* PDE, should not happen */ |
310 |
case 3: /* Reserved */ |
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return 0; |
312 |
case 2: /* L3 PTE */ |
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return pde;
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} |
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} |
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} |
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} |
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return 0; |
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} |
320 |
|
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
|
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{ |
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target_ulong va, va1, va2; |
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unsigned int n, m, o; |
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target_phys_addr_t pde_ptr, pa; |
326 |
uint32_t pde; |
327 |
|
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
329 |
pde = ldl_phys(pde_ptr); |
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(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
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(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
333 |
pde = mmu_probe(env, va, 2);
|
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if (pde) {
|
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pa = cpu_get_phys_page_debug(env, va); |
336 |
(*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
337 |
" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
338 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
339 |
pde = mmu_probe(env, va1, 1);
|
340 |
if (pde) {
|
341 |
pa = cpu_get_phys_page_debug(env, va1); |
342 |
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " |
343 |
TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n", |
344 |
va1, pa, pde); |
345 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
346 |
pde = mmu_probe(env, va2, 0);
|
347 |
if (pde) {
|
348 |
pa = cpu_get_phys_page_debug(env, va2); |
349 |
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " |
350 |
TARGET_FMT_plx " PTE: "
|
351 |
TARGET_FMT_lx "\n",
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va2, pa, pde); |
353 |
} |
354 |
} |
355 |
} |
356 |
} |
357 |
} |
358 |
} |
359 |
} |
360 |
|
361 |
#else /* !TARGET_SPARC64 */ |
362 |
|
363 |
// 41 bit physical address space
|
364 |
static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x) |
365 |
{ |
366 |
return x & 0x1ffffffffffULL; |
367 |
} |
368 |
|
369 |
/*
|
370 |
* UltraSparc IIi I/DMMUs
|
371 |
*/
|
372 |
|
373 |
// Returns true if TTE tag is valid and matches virtual address value in context
|
374 |
// requires virtual address mask value calculated from TTE entry size
|
375 |
static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, |
376 |
uint64_t address, uint64_t context, |
377 |
target_phys_addr_t *physical) |
378 |
{ |
379 |
uint64_t mask; |
380 |
|
381 |
switch (TTE_PGSIZE(tlb->tte)) {
|
382 |
default:
|
383 |
case 0x0: // 8k |
384 |
mask = 0xffffffffffffe000ULL;
|
385 |
break;
|
386 |
case 0x1: // 64k |
387 |
mask = 0xffffffffffff0000ULL;
|
388 |
break;
|
389 |
case 0x2: // 512k |
390 |
mask = 0xfffffffffff80000ULL;
|
391 |
break;
|
392 |
case 0x3: // 4M |
393 |
mask = 0xffffffffffc00000ULL;
|
394 |
break;
|
395 |
} |
396 |
|
397 |
// valid, context match, virtual address match?
|
398 |
if (TTE_IS_VALID(tlb->tte) &&
|
399 |
(TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context)) |
400 |
&& compare_masked(address, tlb->tag, mask)) |
401 |
{ |
402 |
// decode physical address
|
403 |
*physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
|
404 |
return 1; |
405 |
} |
406 |
|
407 |
return 0; |
408 |
} |
409 |
|
410 |
static int get_physical_address_data(CPUState *env, |
411 |
target_phys_addr_t *physical, int *prot,
|
412 |
target_ulong address, int rw, int mmu_idx) |
413 |
{ |
414 |
unsigned int i; |
415 |
uint64_t context; |
416 |
uint64_t sfsr = 0;
|
417 |
|
418 |
int is_user = (mmu_idx == MMU_USER_IDX ||
|
419 |
mmu_idx == MMU_USER_SECONDARY_IDX); |
420 |
|
421 |
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
422 |
*physical = ultrasparc_truncate_physical(address); |
423 |
*prot = PAGE_READ | PAGE_WRITE; |
424 |
return 0; |
425 |
} |
426 |
|
427 |
switch(mmu_idx) {
|
428 |
case MMU_USER_IDX:
|
429 |
case MMU_KERNEL_IDX:
|
430 |
context = env->dmmu.mmu_primary_context & 0x1fff;
|
431 |
sfsr |= SFSR_CT_PRIMARY; |
432 |
break;
|
433 |
case MMU_USER_SECONDARY_IDX:
|
434 |
case MMU_KERNEL_SECONDARY_IDX:
|
435 |
context = env->dmmu.mmu_secondary_context & 0x1fff;
|
436 |
sfsr |= SFSR_CT_SECONDARY; |
437 |
break;
|
438 |
case MMU_NUCLEUS_IDX:
|
439 |
sfsr |= SFSR_CT_NUCLEUS; |
440 |
/* FALLTHRU */
|
441 |
default:
|
442 |
context = 0;
|
443 |
break;
|
444 |
} |
445 |
|
446 |
if (rw == 1) { |
447 |
sfsr |= SFSR_WRITE_BIT; |
448 |
} |
449 |
|
450 |
for (i = 0; i < 64; i++) { |
451 |
// ctx match, vaddr match, valid?
|
452 |
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
|
453 |
|
454 |
// access ok?
|
455 |
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
|
456 |
sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
|
457 |
env->exception_index = TT_DFAULT; |
458 |
|
459 |
DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64 |
460 |
" mmu_idx=%d tl=%d\n",
|
461 |
address, context, mmu_idx, env->tl); |
462 |
} else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { |
463 |
env->exception_index = TT_DPROT; |
464 |
|
465 |
DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64 |
466 |
" mmu_idx=%d tl=%d\n",
|
467 |
address, context, mmu_idx, env->tl); |
468 |
} else {
|
469 |
*prot = PAGE_READ; |
470 |
if (TTE_IS_W_OK(env->dtlb[i].tte)) {
|
471 |
*prot |= PAGE_WRITE; |
472 |
} |
473 |
|
474 |
TTE_SET_USED(env->dtlb[i].tte); |
475 |
|
476 |
return 0; |
477 |
} |
478 |
|
479 |
if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ |
480 |
sfsr |= SFSR_OW_BIT; /* overflow (not read before
|
481 |
another fault) */
|
482 |
} |
483 |
|
484 |
if (env->pstate & PS_PRIV) {
|
485 |
sfsr |= SFSR_PR_BIT; |
486 |
} |
487 |
|
488 |
/* FIXME: ASI field in SFSR must be set */
|
489 |
env->dmmu.sfsr = sfsr | SFSR_VALID_BIT; |
490 |
|
491 |
env->dmmu.sfar = address; /* Fault address register */
|
492 |
|
493 |
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
|
494 |
|
495 |
return 1; |
496 |
} |
497 |
} |
498 |
|
499 |
DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n", |
500 |
address, context); |
501 |
|
502 |
/*
|
503 |
* On MMU misses:
|
504 |
* - UltraSPARC IIi: SFSR and SFAR unmodified
|
505 |
* - JPS1: SFAR updated and some fields of SFSR updated
|
506 |
*/
|
507 |
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
|
508 |
env->exception_index = TT_DMISS; |
509 |
return 1; |
510 |
} |
511 |
|
512 |
static int get_physical_address_code(CPUState *env, |
513 |
target_phys_addr_t *physical, int *prot,
|
514 |
target_ulong address, int mmu_idx)
|
515 |
{ |
516 |
unsigned int i; |
517 |
uint64_t context; |
518 |
|
519 |
int is_user = (mmu_idx == MMU_USER_IDX ||
|
520 |
mmu_idx == MMU_USER_SECONDARY_IDX); |
521 |
|
522 |
if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) { |
523 |
/* IMMU disabled */
|
524 |
*physical = ultrasparc_truncate_physical(address); |
525 |
*prot = PAGE_EXEC; |
526 |
return 0; |
527 |
} |
528 |
|
529 |
if (env->tl == 0) { |
530 |
/* PRIMARY context */
|
531 |
context = env->dmmu.mmu_primary_context & 0x1fff;
|
532 |
} else {
|
533 |
/* NUCLEUS context */
|
534 |
context = 0;
|
535 |
} |
536 |
|
537 |
for (i = 0; i < 64; i++) { |
538 |
// ctx match, vaddr match, valid?
|
539 |
if (ultrasparc_tag_match(&env->itlb[i],
|
540 |
address, context, physical)) { |
541 |
// access ok?
|
542 |
if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
|
543 |
/* Fault status register */
|
544 |
if (env->immu.sfsr & SFSR_VALID_BIT) {
|
545 |
env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
|
546 |
another fault) */
|
547 |
} else {
|
548 |
env->immu.sfsr = 0;
|
549 |
} |
550 |
if (env->pstate & PS_PRIV) {
|
551 |
env->immu.sfsr |= SFSR_PR_BIT; |
552 |
} |
553 |
if (env->tl > 0) { |
554 |
env->immu.sfsr |= SFSR_CT_NUCLEUS; |
555 |
} |
556 |
|
557 |
/* FIXME: ASI field in SFSR must be set */
|
558 |
env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; |
559 |
env->exception_index = TT_TFAULT; |
560 |
|
561 |
env->immu.tag_access = (address & ~0x1fffULL) | context;
|
562 |
|
563 |
DPRINTF_MMU("TFAULT at %" PRIx64 " context %" PRIx64 "\n", |
564 |
address, context); |
565 |
|
566 |
return 1; |
567 |
} |
568 |
*prot = PAGE_EXEC; |
569 |
TTE_SET_USED(env->itlb[i].tte); |
570 |
return 0; |
571 |
} |
572 |
} |
573 |
|
574 |
DPRINTF_MMU("TMISS at %" PRIx64 " context %" PRIx64 "\n", |
575 |
address, context); |
576 |
|
577 |
/* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
|
578 |
env->immu.tag_access = (address & ~0x1fffULL) | context;
|
579 |
env->exception_index = TT_TMISS; |
580 |
return 1; |
581 |
} |
582 |
|
583 |
static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
584 |
int *prot, int *access_index, |
585 |
target_ulong address, int rw, int mmu_idx, |
586 |
target_ulong *page_size) |
587 |
{ |
588 |
/* ??? We treat everything as a small page, then explicitly flush
|
589 |
everything when an entry is evicted. */
|
590 |
*page_size = TARGET_PAGE_SIZE; |
591 |
|
592 |
#if defined (DEBUG_MMU)
|
593 |
/* safety net to catch wrong softmmu index use from dynamic code */
|
594 |
if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { |
595 |
DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d"
|
596 |
" primary context=%" PRIx64
|
597 |
" secondary context=%" PRIx64
|
598 |
" address=%" PRIx64
|
599 |
"\n",
|
600 |
(rw == 2 ? "CODE" : "DATA"), |
601 |
env->tl, mmu_idx, |
602 |
env->dmmu.mmu_primary_context, |
603 |
env->dmmu.mmu_secondary_context, |
604 |
address); |
605 |
} |
606 |
#endif
|
607 |
|
608 |
if (rw == 2) |
609 |
return get_physical_address_code(env, physical, prot, address,
|
610 |
mmu_idx); |
611 |
else
|
612 |
return get_physical_address_data(env, physical, prot, address, rw,
|
613 |
mmu_idx); |
614 |
} |
615 |
|
616 |
/* Perform address translation */
|
617 |
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
618 |
int mmu_idx, int is_softmmu) |
619 |
{ |
620 |
target_ulong virt_addr, vaddr; |
621 |
target_phys_addr_t paddr; |
622 |
target_ulong page_size; |
623 |
int error_code = 0, prot, access_index; |
624 |
|
625 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, |
626 |
address, rw, mmu_idx, &page_size); |
627 |
if (error_code == 0) { |
628 |
virt_addr = address & TARGET_PAGE_MASK; |
629 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
630 |
(TARGET_PAGE_SIZE - 1));
|
631 |
|
632 |
DPRINTF_MMU("Translate at %" PRIx64 " -> %" PRIx64 "," |
633 |
" vaddr %" PRIx64
|
634 |
" mmu_idx=%d"
|
635 |
" tl=%d"
|
636 |
" primary context=%" PRIx64
|
637 |
" secondary context=%" PRIx64
|
638 |
"\n",
|
639 |
address, paddr, vaddr, mmu_idx, env->tl, |
640 |
env->dmmu.mmu_primary_context, |
641 |
env->dmmu.mmu_secondary_context); |
642 |
|
643 |
tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); |
644 |
return 0; |
645 |
} |
646 |
// XXX
|
647 |
return 1; |
648 |
} |
649 |
|
650 |
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
|
651 |
{ |
652 |
unsigned int i; |
653 |
const char *mask; |
654 |
|
655 |
(*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %" |
656 |
PRId64 "\n",
|
657 |
env->dmmu.mmu_primary_context, |
658 |
env->dmmu.mmu_secondary_context); |
659 |
if ((env->lsu & DMMU_E) == 0) { |
660 |
(*cpu_fprintf)(f, "DMMU disabled\n");
|
661 |
} else {
|
662 |
(*cpu_fprintf)(f, "DMMU dump\n");
|
663 |
for (i = 0; i < 64; i++) { |
664 |
switch (TTE_PGSIZE(env->dtlb[i].tte)) {
|
665 |
default:
|
666 |
case 0x0: |
667 |
mask = " 8k";
|
668 |
break;
|
669 |
case 0x1: |
670 |
mask = " 64k";
|
671 |
break;
|
672 |
case 0x2: |
673 |
mask = "512k";
|
674 |
break;
|
675 |
case 0x3: |
676 |
mask = " 4M";
|
677 |
break;
|
678 |
} |
679 |
if (TTE_IS_VALID(env->dtlb[i].tte)) {
|
680 |
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64 |
681 |
", %s, %s, %s, %s, ctx %" PRId64 " %s\n", |
682 |
i, |
683 |
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
|
684 |
TTE_PA(env->dtlb[i].tte), |
685 |
mask, |
686 |
TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", |
687 |
TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", |
688 |
TTE_IS_LOCKED(env->dtlb[i].tte) ? |
689 |
"locked" : "unlocked", |
690 |
env->dtlb[i].tag & (uint64_t)0x1fffULL,
|
691 |
TTE_IS_GLOBAL(env->dtlb[i].tte)? |
692 |
"global" : "local"); |
693 |
} |
694 |
} |
695 |
} |
696 |
if ((env->lsu & IMMU_E) == 0) { |
697 |
(*cpu_fprintf)(f, "IMMU disabled\n");
|
698 |
} else {
|
699 |
(*cpu_fprintf)(f, "IMMU dump\n");
|
700 |
for (i = 0; i < 64; i++) { |
701 |
switch (TTE_PGSIZE(env->itlb[i].tte)) {
|
702 |
default:
|
703 |
case 0x0: |
704 |
mask = " 8k";
|
705 |
break;
|
706 |
case 0x1: |
707 |
mask = " 64k";
|
708 |
break;
|
709 |
case 0x2: |
710 |
mask = "512k";
|
711 |
break;
|
712 |
case 0x3: |
713 |
mask = " 4M";
|
714 |
break;
|
715 |
} |
716 |
if (TTE_IS_VALID(env->itlb[i].tte)) {
|
717 |
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64 |
718 |
", %s, %s, %s, ctx %" PRId64 " %s\n", |
719 |
i, |
720 |
env->itlb[i].tag & (uint64_t)~0x1fffULL,
|
721 |
TTE_PA(env->itlb[i].tte), |
722 |
mask, |
723 |
TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", |
724 |
TTE_IS_LOCKED(env->itlb[i].tte) ? |
725 |
"locked" : "unlocked", |
726 |
env->itlb[i].tag & (uint64_t)0x1fffULL,
|
727 |
TTE_IS_GLOBAL(env->itlb[i].tte)? |
728 |
"global" : "local"); |
729 |
} |
730 |
} |
731 |
} |
732 |
} |
733 |
|
734 |
#endif /* TARGET_SPARC64 */ |
735 |
#endif /* !CONFIG_USER_ONLY */ |
736 |
|
737 |
|
738 |
#if !defined(CONFIG_USER_ONLY)
|
739 |
static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys, |
740 |
target_ulong addr, int rw, int mmu_idx) |
741 |
{ |
742 |
target_ulong page_size; |
743 |
int prot, access_index;
|
744 |
|
745 |
return get_physical_address(env, phys, &prot, &access_index, addr, rw,
|
746 |
mmu_idx, &page_size); |
747 |
} |
748 |
|
749 |
target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr, |
750 |
int mmu_idx)
|
751 |
{ |
752 |
target_phys_addr_t phys_addr; |
753 |
|
754 |
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) { |
755 |
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) { |
756 |
return -1; |
757 |
} |
758 |
} |
759 |
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
760 |
return -1; |
761 |
return phys_addr;
|
762 |
} |
763 |
|
764 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
765 |
{ |
766 |
return cpu_get_phys_page_nofault(env, addr, cpu_mmu_index(env));
|
767 |
} |
768 |
#endif
|
769 |
|
770 |
#ifdef TARGET_SPARC64
|
771 |
#ifdef DEBUG_PCALL
|
772 |
static const char * const excp_names[0x80] = { |
773 |
[TT_TFAULT] = "Instruction Access Fault",
|
774 |
[TT_TMISS] = "Instruction Access MMU Miss",
|
775 |
[TT_CODE_ACCESS] = "Instruction Access Error",
|
776 |
[TT_ILL_INSN] = "Illegal Instruction",
|
777 |
[TT_PRIV_INSN] = "Privileged Instruction",
|
778 |
[TT_NFPU_INSN] = "FPU Disabled",
|
779 |
[TT_FP_EXCP] = "FPU Exception",
|
780 |
[TT_TOVF] = "Tag Overflow",
|
781 |
[TT_CLRWIN] = "Clean Windows",
|
782 |
[TT_DIV_ZERO] = "Division By Zero",
|
783 |
[TT_DFAULT] = "Data Access Fault",
|
784 |
[TT_DMISS] = "Data Access MMU Miss",
|
785 |
[TT_DATA_ACCESS] = "Data Access Error",
|
786 |
[TT_DPROT] = "Data Protection Error",
|
787 |
[TT_UNALIGNED] = "Unaligned Memory Access",
|
788 |
[TT_PRIV_ACT] = "Privileged Action",
|
789 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
790 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
791 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
792 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
793 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
794 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
795 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
796 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
797 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
798 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
799 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
800 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
801 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
802 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
803 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
804 |
}; |
805 |
#endif
|
806 |
|
807 |
void do_interrupt(CPUState *env)
|
808 |
{ |
809 |
int intno = env->exception_index;
|
810 |
trap_state *tsptr; |
811 |
|
812 |
#ifdef DEBUG_PCALL
|
813 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
814 |
static int count; |
815 |
const char *name; |
816 |
|
817 |
if (intno < 0 || intno >= 0x180) { |
818 |
name = "Unknown";
|
819 |
} else if (intno >= 0x100) { |
820 |
name = "Trap Instruction";
|
821 |
} else if (intno >= 0xc0) { |
822 |
name = "Window Fill";
|
823 |
} else if (intno >= 0x80) { |
824 |
name = "Window Spill";
|
825 |
} else {
|
826 |
name = excp_names[intno]; |
827 |
if (!name) {
|
828 |
name = "Unknown";
|
829 |
} |
830 |
} |
831 |
|
832 |
qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
833 |
" SP=%016" PRIx64 "\n", |
834 |
count, name, intno, |
835 |
env->pc, |
836 |
env->npc, env->regwptr[6]);
|
837 |
log_cpu_state(env, 0);
|
838 |
#if 0
|
839 |
{
|
840 |
int i;
|
841 |
uint8_t *ptr;
|
842 |
|
843 |
qemu_log(" code=");
|
844 |
ptr = (uint8_t *)env->pc;
|
845 |
for (i = 0; i < 16; i++) {
|
846 |
qemu_log(" %02x", ldub(ptr + i));
|
847 |
}
|
848 |
qemu_log("\n");
|
849 |
}
|
850 |
#endif
|
851 |
count++; |
852 |
} |
853 |
#endif
|
854 |
#if !defined(CONFIG_USER_ONLY)
|
855 |
if (env->tl >= env->maxtl) {
|
856 |
cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
|
857 |
" Error state", env->exception_index, env->tl, env->maxtl);
|
858 |
return;
|
859 |
} |
860 |
#endif
|
861 |
if (env->tl < env->maxtl - 1) { |
862 |
env->tl++; |
863 |
} else {
|
864 |
env->pstate |= PS_RED; |
865 |
if (env->tl < env->maxtl) {
|
866 |
env->tl++; |
867 |
} |
868 |
} |
869 |
tsptr = cpu_tsptr(env); |
870 |
|
871 |
tsptr->tstate = (cpu_get_ccr(env) << 32) |
|
872 |
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
873 |
cpu_get_cwp64(env); |
874 |
tsptr->tpc = env->pc; |
875 |
tsptr->tnpc = env->npc; |
876 |
tsptr->tt = intno; |
877 |
|
878 |
switch (intno) {
|
879 |
case TT_IVEC:
|
880 |
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG); |
881 |
break;
|
882 |
case TT_TFAULT:
|
883 |
case TT_DFAULT:
|
884 |
case TT_TMISS ... TT_TMISS + 3: |
885 |
case TT_DMISS ... TT_DMISS + 3: |
886 |
case TT_DPROT ... TT_DPROT + 3: |
887 |
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); |
888 |
break;
|
889 |
default:
|
890 |
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG); |
891 |
break;
|
892 |
} |
893 |
|
894 |
if (intno == TT_CLRWIN) {
|
895 |
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
|
896 |
} else if ((intno & 0x1c0) == TT_SPILL) { |
897 |
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
|
898 |
} else if ((intno & 0x1c0) == TT_FILL) { |
899 |
cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
|
900 |
} |
901 |
env->tbr &= ~0x7fffULL;
|
902 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
903 |
env->pc = env->tbr; |
904 |
env->npc = env->pc + 4;
|
905 |
env->exception_index = -1;
|
906 |
} |
907 |
#else
|
908 |
#ifdef DEBUG_PCALL
|
909 |
static const char * const excp_names[0x80] = { |
910 |
[TT_TFAULT] = "Instruction Access Fault",
|
911 |
[TT_ILL_INSN] = "Illegal Instruction",
|
912 |
[TT_PRIV_INSN] = "Privileged Instruction",
|
913 |
[TT_NFPU_INSN] = "FPU Disabled",
|
914 |
[TT_WIN_OVF] = "Window Overflow",
|
915 |
[TT_WIN_UNF] = "Window Underflow",
|
916 |
[TT_UNALIGNED] = "Unaligned Memory Access",
|
917 |
[TT_FP_EXCP] = "FPU Exception",
|
918 |
[TT_DFAULT] = "Data Access Fault",
|
919 |
[TT_TOVF] = "Tag Overflow",
|
920 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
921 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
922 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
923 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
924 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
925 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
926 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
927 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
928 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
929 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
930 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
931 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
932 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
933 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
934 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
935 |
[TT_TOVF] = "Tag Overflow",
|
936 |
[TT_CODE_ACCESS] = "Instruction Access Error",
|
937 |
[TT_DATA_ACCESS] = "Data Access Error",
|
938 |
[TT_DIV_ZERO] = "Division By Zero",
|
939 |
[TT_NCP_INSN] = "Coprocessor Disabled",
|
940 |
}; |
941 |
#endif
|
942 |
|
943 |
void do_interrupt(CPUState *env)
|
944 |
{ |
945 |
int cwp, intno = env->exception_index;
|
946 |
|
947 |
#ifdef DEBUG_PCALL
|
948 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
949 |
static int count; |
950 |
const char *name; |
951 |
|
952 |
if (intno < 0 || intno >= 0x100) { |
953 |
name = "Unknown";
|
954 |
} else if (intno >= 0x80) { |
955 |
name = "Trap Instruction";
|
956 |
} else {
|
957 |
name = excp_names[intno]; |
958 |
if (!name) {
|
959 |
name = "Unknown";
|
960 |
} |
961 |
} |
962 |
|
963 |
qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
964 |
count, name, intno, |
965 |
env->pc, |
966 |
env->npc, env->regwptr[6]);
|
967 |
log_cpu_state(env, 0);
|
968 |
#if 0
|
969 |
{
|
970 |
int i;
|
971 |
uint8_t *ptr;
|
972 |
|
973 |
qemu_log(" code=");
|
974 |
ptr = (uint8_t *)env->pc;
|
975 |
for (i = 0; i < 16; i++) {
|
976 |
qemu_log(" %02x", ldub(ptr + i));
|
977 |
}
|
978 |
qemu_log("\n");
|
979 |
}
|
980 |
#endif
|
981 |
count++; |
982 |
} |
983 |
#endif
|
984 |
#if !defined(CONFIG_USER_ONLY)
|
985 |
if (env->psret == 0) { |
986 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
|
987 |
env->exception_index); |
988 |
return;
|
989 |
} |
990 |
#endif
|
991 |
env->psret = 0;
|
992 |
cwp = cpu_cwp_dec(env, env->cwp - 1);
|
993 |
cpu_set_cwp(env, cwp); |
994 |
env->regwptr[9] = env->pc;
|
995 |
env->regwptr[10] = env->npc;
|
996 |
env->psrps = env->psrs; |
997 |
env->psrs = 1;
|
998 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
999 |
env->pc = env->tbr; |
1000 |
env->npc = env->pc + 4;
|
1001 |
env->exception_index = -1;
|
1002 |
|
1003 |
#if !defined(CONFIG_USER_ONLY)
|
1004 |
/* IRQ acknowledgment */
|
1005 |
if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { |
1006 |
env->qemu_irq_ack(env->irq_manager, intno); |
1007 |
} |
1008 |
#endif
|
1009 |
} |
1010 |
#endif
|
1011 |
|
1012 |
void cpu_reset(CPUSPARCState *env)
|
1013 |
{ |
1014 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
1015 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
1016 |
log_cpu_state(env, 0);
|
1017 |
} |
1018 |
|
1019 |
tlb_flush(env, 1);
|
1020 |
env->cwp = 0;
|
1021 |
#ifndef TARGET_SPARC64
|
1022 |
env->wim = 1;
|
1023 |
#endif
|
1024 |
env->regwptr = env->regbase + (env->cwp * 16);
|
1025 |
CC_OP = CC_OP_FLAGS; |
1026 |
#if defined(CONFIG_USER_ONLY)
|
1027 |
#ifdef TARGET_SPARC64
|
1028 |
env->cleanwin = env->nwindows - 2;
|
1029 |
env->cansave = env->nwindows - 2;
|
1030 |
env->pstate = PS_RMO | PS_PEF | PS_IE; |
1031 |
env->asi = 0x82; // Primary no-fault |
1032 |
#endif
|
1033 |
#else
|
1034 |
#if !defined(TARGET_SPARC64)
|
1035 |
env->psret = 0;
|
1036 |
env->psrs = 1;
|
1037 |
env->psrps = 1;
|
1038 |
#endif
|
1039 |
#ifdef TARGET_SPARC64
|
1040 |
env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG; |
1041 |
env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
|
1042 |
env->tl = env->maxtl; |
1043 |
cpu_tsptr(env)->tt = TT_POWER_ON_RESET; |
1044 |
env->lsu = 0;
|
1045 |
#else
|
1046 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
1047 |
env->mmuregs[0] |= env->def->mmu_bm;
|
1048 |
#endif
|
1049 |
env->pc = 0;
|
1050 |
env->npc = env->pc + 4;
|
1051 |
#endif
|
1052 |
env->cache_control = 0;
|
1053 |
} |
1054 |
|
1055 |
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
1056 |
{ |
1057 |
sparc_def_t def1, *def = &def1; |
1058 |
|
1059 |
if (cpu_sparc_find_by_name(def, cpu_model) < 0) |
1060 |
return -1; |
1061 |
|
1062 |
env->def = qemu_mallocz(sizeof(*def));
|
1063 |
memcpy(env->def, def, sizeof(*def));
|
1064 |
#if defined(CONFIG_USER_ONLY)
|
1065 |
if ((env->def->features & CPU_FEATURE_FLOAT))
|
1066 |
env->def->features |= CPU_FEATURE_FLOAT128; |
1067 |
#endif
|
1068 |
env->cpu_model_str = cpu_model; |
1069 |
env->version = def->iu_version; |
1070 |
env->fsr = def->fpu_version; |
1071 |
env->nwindows = def->nwindows; |
1072 |
#if !defined(TARGET_SPARC64)
|
1073 |
env->mmuregs[0] |= def->mmu_version;
|
1074 |
cpu_sparc_set_id(env, 0);
|
1075 |
env->mxccregs[7] |= def->mxcc_version;
|
1076 |
#else
|
1077 |
env->mmu_version = def->mmu_version; |
1078 |
env->maxtl = def->maxtl; |
1079 |
env->version |= def->maxtl << 8;
|
1080 |
env->version |= def->nwindows - 1;
|
1081 |
#endif
|
1082 |
return 0; |
1083 |
} |
1084 |
|
1085 |
static void cpu_sparc_close(CPUSPARCState *env) |
1086 |
{ |
1087 |
free(env->def); |
1088 |
free(env); |
1089 |
} |
1090 |
|
1091 |
CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
1092 |
{ |
1093 |
CPUSPARCState *env; |
1094 |
|
1095 |
env = qemu_mallocz(sizeof(CPUSPARCState));
|
1096 |
cpu_exec_init(env); |
1097 |
|
1098 |
gen_intermediate_code_init(env); |
1099 |
|
1100 |
if (cpu_sparc_register(env, cpu_model) < 0) { |
1101 |
cpu_sparc_close(env); |
1102 |
return NULL; |
1103 |
} |
1104 |
qemu_init_vcpu(env); |
1105 |
|
1106 |
return env;
|
1107 |
} |
1108 |
|
1109 |
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
1110 |
{ |
1111 |
#if !defined(TARGET_SPARC64)
|
1112 |
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
1113 |
#endif
|
1114 |
} |
1115 |
|
1116 |
static const sparc_def_t sparc_defs[] = { |
1117 |
#ifdef TARGET_SPARC64
|
1118 |
{ |
1119 |
.name = "Fujitsu Sparc64",
|
1120 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
1121 |
.fpu_version = 0x00000000,
|
1122 |
.mmu_version = mmu_us_12, |
1123 |
.nwindows = 4,
|
1124 |
.maxtl = 4,
|
1125 |
.features = CPU_DEFAULT_FEATURES, |
1126 |
}, |
1127 |
{ |
1128 |
.name = "Fujitsu Sparc64 III",
|
1129 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
1130 |
.fpu_version = 0x00000000,
|
1131 |
.mmu_version = mmu_us_12, |
1132 |
.nwindows = 5,
|
1133 |
.maxtl = 4,
|
1134 |
.features = CPU_DEFAULT_FEATURES, |
1135 |
}, |
1136 |
{ |
1137 |
.name = "Fujitsu Sparc64 IV",
|
1138 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
1139 |
.fpu_version = 0x00000000,
|
1140 |
.mmu_version = mmu_us_12, |
1141 |
.nwindows = 8,
|
1142 |
.maxtl = 5,
|
1143 |
.features = CPU_DEFAULT_FEATURES, |
1144 |
}, |
1145 |
{ |
1146 |
.name = "Fujitsu Sparc64 V",
|
1147 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
1148 |
.fpu_version = 0x00000000,
|
1149 |
.mmu_version = mmu_us_12, |
1150 |
.nwindows = 8,
|
1151 |
.maxtl = 5,
|
1152 |
.features = CPU_DEFAULT_FEATURES, |
1153 |
}, |
1154 |
{ |
1155 |
.name = "TI UltraSparc I",
|
1156 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
1157 |
.fpu_version = 0x00000000,
|
1158 |
.mmu_version = mmu_us_12, |
1159 |
.nwindows = 8,
|
1160 |
.maxtl = 5,
|
1161 |
.features = CPU_DEFAULT_FEATURES, |
1162 |
}, |
1163 |
{ |
1164 |
.name = "TI UltraSparc II",
|
1165 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
1166 |
.fpu_version = 0x00000000,
|
1167 |
.mmu_version = mmu_us_12, |
1168 |
.nwindows = 8,
|
1169 |
.maxtl = 5,
|
1170 |
.features = CPU_DEFAULT_FEATURES, |
1171 |
}, |
1172 |
{ |
1173 |
.name = "TI UltraSparc IIi",
|
1174 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
1175 |
.fpu_version = 0x00000000,
|
1176 |
.mmu_version = mmu_us_12, |
1177 |
.nwindows = 8,
|
1178 |
.maxtl = 5,
|
1179 |
.features = CPU_DEFAULT_FEATURES, |
1180 |
}, |
1181 |
{ |
1182 |
.name = "TI UltraSparc IIe",
|
1183 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
1184 |
.fpu_version = 0x00000000,
|
1185 |
.mmu_version = mmu_us_12, |
1186 |
.nwindows = 8,
|
1187 |
.maxtl = 5,
|
1188 |
.features = CPU_DEFAULT_FEATURES, |
1189 |
}, |
1190 |
{ |
1191 |
.name = "Sun UltraSparc III",
|
1192 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
1193 |
.fpu_version = 0x00000000,
|
1194 |
.mmu_version = mmu_us_12, |
1195 |
.nwindows = 8,
|
1196 |
.maxtl = 5,
|
1197 |
.features = CPU_DEFAULT_FEATURES, |
1198 |
}, |
1199 |
{ |
1200 |
.name = "Sun UltraSparc III Cu",
|
1201 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
1202 |
.fpu_version = 0x00000000,
|
1203 |
.mmu_version = mmu_us_3, |
1204 |
.nwindows = 8,
|
1205 |
.maxtl = 5,
|
1206 |
.features = CPU_DEFAULT_FEATURES, |
1207 |
}, |
1208 |
{ |
1209 |
.name = "Sun UltraSparc IIIi",
|
1210 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
1211 |
.fpu_version = 0x00000000,
|
1212 |
.mmu_version = mmu_us_12, |
1213 |
.nwindows = 8,
|
1214 |
.maxtl = 5,
|
1215 |
.features = CPU_DEFAULT_FEATURES, |
1216 |
}, |
1217 |
{ |
1218 |
.name = "Sun UltraSparc IV",
|
1219 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
1220 |
.fpu_version = 0x00000000,
|
1221 |
.mmu_version = mmu_us_4, |
1222 |
.nwindows = 8,
|
1223 |
.maxtl = 5,
|
1224 |
.features = CPU_DEFAULT_FEATURES, |
1225 |
}, |
1226 |
{ |
1227 |
.name = "Sun UltraSparc IV+",
|
1228 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
1229 |
.fpu_version = 0x00000000,
|
1230 |
.mmu_version = mmu_us_12, |
1231 |
.nwindows = 8,
|
1232 |
.maxtl = 5,
|
1233 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
1234 |
}, |
1235 |
{ |
1236 |
.name = "Sun UltraSparc IIIi+",
|
1237 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
1238 |
.fpu_version = 0x00000000,
|
1239 |
.mmu_version = mmu_us_3, |
1240 |
.nwindows = 8,
|
1241 |
.maxtl = 5,
|
1242 |
.features = CPU_DEFAULT_FEATURES, |
1243 |
}, |
1244 |
{ |
1245 |
.name = "Sun UltraSparc T1",
|
1246 |
// defined in sparc_ifu_fdp.v and ctu.h
|
1247 |
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
1248 |
.fpu_version = 0x00000000,
|
1249 |
.mmu_version = mmu_sun4v, |
1250 |
.nwindows = 8,
|
1251 |
.maxtl = 6,
|
1252 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
1253 |
| CPU_FEATURE_GL, |
1254 |
}, |
1255 |
{ |
1256 |
.name = "Sun UltraSparc T2",
|
1257 |
// defined in tlu_asi_ctl.v and n2_revid_cust.v
|
1258 |
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
1259 |
.fpu_version = 0x00000000,
|
1260 |
.mmu_version = mmu_sun4v, |
1261 |
.nwindows = 8,
|
1262 |
.maxtl = 6,
|
1263 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
1264 |
| CPU_FEATURE_GL, |
1265 |
}, |
1266 |
{ |
1267 |
.name = "NEC UltraSparc I",
|
1268 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
1269 |
.fpu_version = 0x00000000,
|
1270 |
.mmu_version = mmu_us_12, |
1271 |
.nwindows = 8,
|
1272 |
.maxtl = 5,
|
1273 |
.features = CPU_DEFAULT_FEATURES, |
1274 |
}, |
1275 |
#else
|
1276 |
{ |
1277 |
.name = "Fujitsu MB86900",
|
1278 |
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
1279 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1280 |
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
1281 |
.mmu_bm = 0x00004000,
|
1282 |
.mmu_ctpr_mask = 0x007ffff0,
|
1283 |
.mmu_cxr_mask = 0x0000003f,
|
1284 |
.mmu_sfsr_mask = 0xffffffff,
|
1285 |
.mmu_trcr_mask = 0xffffffff,
|
1286 |
.nwindows = 7,
|
1287 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, |
1288 |
}, |
1289 |
{ |
1290 |
.name = "Fujitsu MB86904",
|
1291 |
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
1292 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1293 |
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
1294 |
.mmu_bm = 0x00004000,
|
1295 |
.mmu_ctpr_mask = 0x00ffffc0,
|
1296 |
.mmu_cxr_mask = 0x000000ff,
|
1297 |
.mmu_sfsr_mask = 0x00016fff,
|
1298 |
.mmu_trcr_mask = 0x00ffffff,
|
1299 |
.nwindows = 8,
|
1300 |
.features = CPU_DEFAULT_FEATURES, |
1301 |
}, |
1302 |
{ |
1303 |
.name = "Fujitsu MB86907",
|
1304 |
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
1305 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1306 |
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
1307 |
.mmu_bm = 0x00004000,
|
1308 |
.mmu_ctpr_mask = 0xffffffc0,
|
1309 |
.mmu_cxr_mask = 0x000000ff,
|
1310 |
.mmu_sfsr_mask = 0x00016fff,
|
1311 |
.mmu_trcr_mask = 0xffffffff,
|
1312 |
.nwindows = 8,
|
1313 |
.features = CPU_DEFAULT_FEATURES, |
1314 |
}, |
1315 |
{ |
1316 |
.name = "LSI L64811",
|
1317 |
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
1318 |
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
1319 |
.mmu_version = 0x10 << 24, |
1320 |
.mmu_bm = 0x00004000,
|
1321 |
.mmu_ctpr_mask = 0x007ffff0,
|
1322 |
.mmu_cxr_mask = 0x0000003f,
|
1323 |
.mmu_sfsr_mask = 0xffffffff,
|
1324 |
.mmu_trcr_mask = 0xffffffff,
|
1325 |
.nwindows = 8,
|
1326 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1327 |
CPU_FEATURE_FSMULD, |
1328 |
}, |
1329 |
{ |
1330 |
.name = "Cypress CY7C601",
|
1331 |
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
1332 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
1333 |
.mmu_version = 0x10 << 24, |
1334 |
.mmu_bm = 0x00004000,
|
1335 |
.mmu_ctpr_mask = 0x007ffff0,
|
1336 |
.mmu_cxr_mask = 0x0000003f,
|
1337 |
.mmu_sfsr_mask = 0xffffffff,
|
1338 |
.mmu_trcr_mask = 0xffffffff,
|
1339 |
.nwindows = 8,
|
1340 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1341 |
CPU_FEATURE_FSMULD, |
1342 |
}, |
1343 |
{ |
1344 |
.name = "Cypress CY7C611",
|
1345 |
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
1346 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
1347 |
.mmu_version = 0x10 << 24, |
1348 |
.mmu_bm = 0x00004000,
|
1349 |
.mmu_ctpr_mask = 0x007ffff0,
|
1350 |
.mmu_cxr_mask = 0x0000003f,
|
1351 |
.mmu_sfsr_mask = 0xffffffff,
|
1352 |
.mmu_trcr_mask = 0xffffffff,
|
1353 |
.nwindows = 8,
|
1354 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1355 |
CPU_FEATURE_FSMULD, |
1356 |
}, |
1357 |
{ |
1358 |
.name = "TI MicroSparc I",
|
1359 |
.iu_version = 0x41000000,
|
1360 |
.fpu_version = 4 << 17, |
1361 |
.mmu_version = 0x41000000,
|
1362 |
.mmu_bm = 0x00004000,
|
1363 |
.mmu_ctpr_mask = 0x007ffff0,
|
1364 |
.mmu_cxr_mask = 0x0000003f,
|
1365 |
.mmu_sfsr_mask = 0x00016fff,
|
1366 |
.mmu_trcr_mask = 0x0000003f,
|
1367 |
.nwindows = 7,
|
1368 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
1369 |
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | |
1370 |
CPU_FEATURE_FMUL, |
1371 |
}, |
1372 |
{ |
1373 |
.name = "TI MicroSparc II",
|
1374 |
.iu_version = 0x42000000,
|
1375 |
.fpu_version = 4 << 17, |
1376 |
.mmu_version = 0x02000000,
|
1377 |
.mmu_bm = 0x00004000,
|
1378 |
.mmu_ctpr_mask = 0x00ffffc0,
|
1379 |
.mmu_cxr_mask = 0x000000ff,
|
1380 |
.mmu_sfsr_mask = 0x00016fff,
|
1381 |
.mmu_trcr_mask = 0x00ffffff,
|
1382 |
.nwindows = 8,
|
1383 |
.features = CPU_DEFAULT_FEATURES, |
1384 |
}, |
1385 |
{ |
1386 |
.name = "TI MicroSparc IIep",
|
1387 |
.iu_version = 0x42000000,
|
1388 |
.fpu_version = 4 << 17, |
1389 |
.mmu_version = 0x04000000,
|
1390 |
.mmu_bm = 0x00004000,
|
1391 |
.mmu_ctpr_mask = 0x00ffffc0,
|
1392 |
.mmu_cxr_mask = 0x000000ff,
|
1393 |
.mmu_sfsr_mask = 0x00016bff,
|
1394 |
.mmu_trcr_mask = 0x00ffffff,
|
1395 |
.nwindows = 8,
|
1396 |
.features = CPU_DEFAULT_FEATURES, |
1397 |
}, |
1398 |
{ |
1399 |
.name = "TI SuperSparc 40", // STP1020NPGA |
1400 |
.iu_version = 0x41000000, // SuperSPARC 2.x |
1401 |
.fpu_version = 0 << 17, |
1402 |
.mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC |
1403 |
.mmu_bm = 0x00002000,
|
1404 |
.mmu_ctpr_mask = 0xffffffc0,
|
1405 |
.mmu_cxr_mask = 0x0000ffff,
|
1406 |
.mmu_sfsr_mask = 0xffffffff,
|
1407 |
.mmu_trcr_mask = 0xffffffff,
|
1408 |
.nwindows = 8,
|
1409 |
.features = CPU_DEFAULT_FEATURES, |
1410 |
}, |
1411 |
{ |
1412 |
.name = "TI SuperSparc 50", // STP1020PGA |
1413 |
.iu_version = 0x40000000, // SuperSPARC 3.x |
1414 |
.fpu_version = 0 << 17, |
1415 |
.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
1416 |
.mmu_bm = 0x00002000,
|
1417 |
.mmu_ctpr_mask = 0xffffffc0,
|
1418 |
.mmu_cxr_mask = 0x0000ffff,
|
1419 |
.mmu_sfsr_mask = 0xffffffff,
|
1420 |
.mmu_trcr_mask = 0xffffffff,
|
1421 |
.nwindows = 8,
|
1422 |
.features = CPU_DEFAULT_FEATURES, |
1423 |
}, |
1424 |
{ |
1425 |
.name = "TI SuperSparc 51",
|
1426 |
.iu_version = 0x40000000, // SuperSPARC 3.x |
1427 |
.fpu_version = 0 << 17, |
1428 |
.mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
1429 |
.mmu_bm = 0x00002000,
|
1430 |
.mmu_ctpr_mask = 0xffffffc0,
|
1431 |
.mmu_cxr_mask = 0x0000ffff,
|
1432 |
.mmu_sfsr_mask = 0xffffffff,
|
1433 |
.mmu_trcr_mask = 0xffffffff,
|
1434 |
.mxcc_version = 0x00000104,
|
1435 |
.nwindows = 8,
|
1436 |
.features = CPU_DEFAULT_FEATURES, |
1437 |
}, |
1438 |
{ |
1439 |
.name = "TI SuperSparc 60", // STP1020APGA |
1440 |
.iu_version = 0x40000000, // SuperSPARC 3.x |
1441 |
.fpu_version = 0 << 17, |
1442 |
.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
1443 |
.mmu_bm = 0x00002000,
|
1444 |
.mmu_ctpr_mask = 0xffffffc0,
|
1445 |
.mmu_cxr_mask = 0x0000ffff,
|
1446 |
.mmu_sfsr_mask = 0xffffffff,
|
1447 |
.mmu_trcr_mask = 0xffffffff,
|
1448 |
.nwindows = 8,
|
1449 |
.features = CPU_DEFAULT_FEATURES, |
1450 |
}, |
1451 |
{ |
1452 |
.name = "TI SuperSparc 61",
|
1453 |
.iu_version = 0x44000000, // SuperSPARC 3.x |
1454 |
.fpu_version = 0 << 17, |
1455 |
.mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
1456 |
.mmu_bm = 0x00002000,
|
1457 |
.mmu_ctpr_mask = 0xffffffc0,
|
1458 |
.mmu_cxr_mask = 0x0000ffff,
|
1459 |
.mmu_sfsr_mask = 0xffffffff,
|
1460 |
.mmu_trcr_mask = 0xffffffff,
|
1461 |
.mxcc_version = 0x00000104,
|
1462 |
.nwindows = 8,
|
1463 |
.features = CPU_DEFAULT_FEATURES, |
1464 |
}, |
1465 |
{ |
1466 |
.name = "TI SuperSparc II",
|
1467 |
.iu_version = 0x40000000, // SuperSPARC II 1.x |
1468 |
.fpu_version = 0 << 17, |
1469 |
.mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC |
1470 |
.mmu_bm = 0x00002000,
|
1471 |
.mmu_ctpr_mask = 0xffffffc0,
|
1472 |
.mmu_cxr_mask = 0x0000ffff,
|
1473 |
.mmu_sfsr_mask = 0xffffffff,
|
1474 |
.mmu_trcr_mask = 0xffffffff,
|
1475 |
.mxcc_version = 0x00000104,
|
1476 |
.nwindows = 8,
|
1477 |
.features = CPU_DEFAULT_FEATURES, |
1478 |
}, |
1479 |
{ |
1480 |
.name = "Ross RT625",
|
1481 |
.iu_version = 0x1e000000,
|
1482 |
.fpu_version = 1 << 17, |
1483 |
.mmu_version = 0x1e000000,
|
1484 |
.mmu_bm = 0x00004000,
|
1485 |
.mmu_ctpr_mask = 0x007ffff0,
|
1486 |
.mmu_cxr_mask = 0x0000003f,
|
1487 |
.mmu_sfsr_mask = 0xffffffff,
|
1488 |
.mmu_trcr_mask = 0xffffffff,
|
1489 |
.nwindows = 8,
|
1490 |
.features = CPU_DEFAULT_FEATURES, |
1491 |
}, |
1492 |
{ |
1493 |
.name = "Ross RT620",
|
1494 |
.iu_version = 0x1f000000,
|
1495 |
.fpu_version = 1 << 17, |
1496 |
.mmu_version = 0x1f000000,
|
1497 |
.mmu_bm = 0x00004000,
|
1498 |
.mmu_ctpr_mask = 0x007ffff0,
|
1499 |
.mmu_cxr_mask = 0x0000003f,
|
1500 |
.mmu_sfsr_mask = 0xffffffff,
|
1501 |
.mmu_trcr_mask = 0xffffffff,
|
1502 |
.nwindows = 8,
|
1503 |
.features = CPU_DEFAULT_FEATURES, |
1504 |
}, |
1505 |
{ |
1506 |
.name = "BIT B5010",
|
1507 |
.iu_version = 0x20000000,
|
1508 |
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
1509 |
.mmu_version = 0x20000000,
|
1510 |
.mmu_bm = 0x00004000,
|
1511 |
.mmu_ctpr_mask = 0x007ffff0,
|
1512 |
.mmu_cxr_mask = 0x0000003f,
|
1513 |
.mmu_sfsr_mask = 0xffffffff,
|
1514 |
.mmu_trcr_mask = 0xffffffff,
|
1515 |
.nwindows = 8,
|
1516 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1517 |
CPU_FEATURE_FSMULD, |
1518 |
}, |
1519 |
{ |
1520 |
.name = "Matsushita MN10501",
|
1521 |
.iu_version = 0x50000000,
|
1522 |
.fpu_version = 0 << 17, |
1523 |
.mmu_version = 0x50000000,
|
1524 |
.mmu_bm = 0x00004000,
|
1525 |
.mmu_ctpr_mask = 0x007ffff0,
|
1526 |
.mmu_cxr_mask = 0x0000003f,
|
1527 |
.mmu_sfsr_mask = 0xffffffff,
|
1528 |
.mmu_trcr_mask = 0xffffffff,
|
1529 |
.nwindows = 8,
|
1530 |
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | |
1531 |
CPU_FEATURE_FSMULD, |
1532 |
}, |
1533 |
{ |
1534 |
.name = "Weitek W8601",
|
1535 |
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
1536 |
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
1537 |
.mmu_version = 0x10 << 24, |
1538 |
.mmu_bm = 0x00004000,
|
1539 |
.mmu_ctpr_mask = 0x007ffff0,
|
1540 |
.mmu_cxr_mask = 0x0000003f,
|
1541 |
.mmu_sfsr_mask = 0xffffffff,
|
1542 |
.mmu_trcr_mask = 0xffffffff,
|
1543 |
.nwindows = 8,
|
1544 |
.features = CPU_DEFAULT_FEATURES, |
1545 |
}, |
1546 |
{ |
1547 |
.name = "LEON2",
|
1548 |
.iu_version = 0xf2000000,
|
1549 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1550 |
.mmu_version = 0xf2000000,
|
1551 |
.mmu_bm = 0x00004000,
|
1552 |
.mmu_ctpr_mask = 0x007ffff0,
|
1553 |
.mmu_cxr_mask = 0x0000003f,
|
1554 |
.mmu_sfsr_mask = 0xffffffff,
|
1555 |
.mmu_trcr_mask = 0xffffffff,
|
1556 |
.nwindows = 8,
|
1557 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, |
1558 |
}, |
1559 |
{ |
1560 |
.name = "LEON3",
|
1561 |
.iu_version = 0xf3000000,
|
1562 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1563 |
.mmu_version = 0xf3000000,
|
1564 |
.mmu_bm = 0x00000000,
|
1565 |
.mmu_ctpr_mask = 0x007ffff0,
|
1566 |
.mmu_cxr_mask = 0x0000003f,
|
1567 |
.mmu_sfsr_mask = 0xffffffff,
|
1568 |
.mmu_trcr_mask = 0xffffffff,
|
1569 |
.nwindows = 8,
|
1570 |
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | |
1571 |
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL, |
1572 |
}, |
1573 |
#endif
|
1574 |
}; |
1575 |
|
1576 |
static const char * const feature_name[] = { |
1577 |
"float",
|
1578 |
"float128",
|
1579 |
"swap",
|
1580 |
"mul",
|
1581 |
"div",
|
1582 |
"flush",
|
1583 |
"fsqrt",
|
1584 |
"fmul",
|
1585 |
"vis1",
|
1586 |
"vis2",
|
1587 |
"fsmuld",
|
1588 |
"hypv",
|
1589 |
"cmt",
|
1590 |
"gl",
|
1591 |
}; |
1592 |
|
1593 |
static void print_features(FILE *f, fprintf_function cpu_fprintf, |
1594 |
uint32_t features, const char *prefix) |
1595 |
{ |
1596 |
unsigned int i; |
1597 |
|
1598 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1599 |
if (feature_name[i] && (features & (1 << i))) { |
1600 |
if (prefix)
|
1601 |
(*cpu_fprintf)(f, "%s", prefix);
|
1602 |
(*cpu_fprintf)(f, "%s ", feature_name[i]);
|
1603 |
} |
1604 |
} |
1605 |
|
1606 |
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) |
1607 |
{ |
1608 |
unsigned int i; |
1609 |
|
1610 |
for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1611 |
if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
1612 |
*features |= 1 << i;
|
1613 |
return;
|
1614 |
} |
1615 |
fprintf(stderr, "CPU feature %s not found\n", flagname);
|
1616 |
} |
1617 |
|
1618 |
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
1619 |
{ |
1620 |
unsigned int i; |
1621 |
const sparc_def_t *def = NULL; |
1622 |
char *s = strdup(cpu_model);
|
1623 |
char *featurestr, *name = strtok(s, ","); |
1624 |
uint32_t plus_features = 0;
|
1625 |
uint32_t minus_features = 0;
|
1626 |
uint64_t iu_version; |
1627 |
uint32_t fpu_version, mmu_version, nwindows; |
1628 |
|
1629 |
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
1630 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
1631 |
def = &sparc_defs[i]; |
1632 |
} |
1633 |
} |
1634 |
if (!def)
|
1635 |
goto error;
|
1636 |
memcpy(cpu_def, def, sizeof(*def));
|
1637 |
|
1638 |
featurestr = strtok(NULL, ","); |
1639 |
while (featurestr) {
|
1640 |
char *val;
|
1641 |
|
1642 |
if (featurestr[0] == '+') { |
1643 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
1644 |
} else if (featurestr[0] == '-') { |
1645 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
1646 |
} else if ((val = strchr(featurestr, '='))) { |
1647 |
*val = 0; val++;
|
1648 |
if (!strcmp(featurestr, "iu_version")) { |
1649 |
char *err;
|
1650 |
|
1651 |
iu_version = strtoll(val, &err, 0);
|
1652 |
if (!*val || *err) {
|
1653 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1654 |
goto error;
|
1655 |
} |
1656 |
cpu_def->iu_version = iu_version; |
1657 |
#ifdef DEBUG_FEATURES
|
1658 |
fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version); |
1659 |
#endif
|
1660 |
} else if (!strcmp(featurestr, "fpu_version")) { |
1661 |
char *err;
|
1662 |
|
1663 |
fpu_version = strtol(val, &err, 0);
|
1664 |
if (!*val || *err) {
|
1665 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1666 |
goto error;
|
1667 |
} |
1668 |
cpu_def->fpu_version = fpu_version; |
1669 |
#ifdef DEBUG_FEATURES
|
1670 |
fprintf(stderr, "fpu_version %x\n", fpu_version);
|
1671 |
#endif
|
1672 |
} else if (!strcmp(featurestr, "mmu_version")) { |
1673 |
char *err;
|
1674 |
|
1675 |
mmu_version = strtol(val, &err, 0);
|
1676 |
if (!*val || *err) {
|
1677 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1678 |
goto error;
|
1679 |
} |
1680 |
cpu_def->mmu_version = mmu_version; |
1681 |
#ifdef DEBUG_FEATURES
|
1682 |
fprintf(stderr, "mmu_version %x\n", mmu_version);
|
1683 |
#endif
|
1684 |
} else if (!strcmp(featurestr, "nwindows")) { |
1685 |
char *err;
|
1686 |
|
1687 |
nwindows = strtol(val, &err, 0);
|
1688 |
if (!*val || *err || nwindows > MAX_NWINDOWS ||
|
1689 |
nwindows < MIN_NWINDOWS) { |
1690 |
fprintf(stderr, "bad numerical value %s\n", val);
|
1691 |
goto error;
|
1692 |
} |
1693 |
cpu_def->nwindows = nwindows; |
1694 |
#ifdef DEBUG_FEATURES
|
1695 |
fprintf(stderr, "nwindows %d\n", nwindows);
|
1696 |
#endif
|
1697 |
} else {
|
1698 |
fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
1699 |
goto error;
|
1700 |
} |
1701 |
} else {
|
1702 |
fprintf(stderr, "feature string `%s' not in format "
|
1703 |
"(+feature|-feature|feature=xyz)\n", featurestr);
|
1704 |
goto error;
|
1705 |
} |
1706 |
featurestr = strtok(NULL, ","); |
1707 |
} |
1708 |
cpu_def->features |= plus_features; |
1709 |
cpu_def->features &= ~minus_features; |
1710 |
#ifdef DEBUG_FEATURES
|
1711 |
print_features(stderr, fprintf, cpu_def->features, NULL);
|
1712 |
#endif
|
1713 |
free(s); |
1714 |
return 0; |
1715 |
|
1716 |
error:
|
1717 |
free(s); |
1718 |
return -1; |
1719 |
} |
1720 |
|
1721 |
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
1722 |
{ |
1723 |
unsigned int i; |
1724 |
|
1725 |
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
1726 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ", |
1727 |
sparc_defs[i].name, |
1728 |
sparc_defs[i].iu_version, |
1729 |
sparc_defs[i].fpu_version, |
1730 |
sparc_defs[i].mmu_version, |
1731 |
sparc_defs[i].nwindows); |
1732 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
1733 |
~sparc_defs[i].features, "-");
|
1734 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
1735 |
sparc_defs[i].features, "+");
|
1736 |
(*cpu_fprintf)(f, "\n");
|
1737 |
} |
1738 |
(*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
|
1739 |
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
|
1740 |
(*cpu_fprintf)(f, "\n");
|
1741 |
(*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
|
1742 |
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
|
1743 |
(*cpu_fprintf)(f, "\n");
|
1744 |
(*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
|
1745 |
"fpu_version mmu_version nwindows\n");
|
1746 |
} |
1747 |
|
1748 |
static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf, |
1749 |
uint32_t cc) |
1750 |
{ |
1751 |
cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG? 'N' : '-', |
1752 |
cc & PSR_ZERO? 'Z' : '-', cc & PSR_OVF? 'V' : '-', |
1753 |
cc & PSR_CARRY? 'C' : '-'); |
1754 |
} |
1755 |
|
1756 |
#ifdef TARGET_SPARC64
|
1757 |
#define REGS_PER_LINE 4 |
1758 |
#else
|
1759 |
#define REGS_PER_LINE 8 |
1760 |
#endif
|
1761 |
|
1762 |
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
1763 |
int flags)
|
1764 |
{ |
1765 |
int i, x;
|
1766 |
|
1767 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
1768 |
env->npc); |
1769 |
cpu_fprintf(f, "General Registers:\n");
|
1770 |
|
1771 |
for (i = 0; i < 8; i++) { |
1772 |
if (i % REGS_PER_LINE == 0) { |
1773 |
cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); |
1774 |
} |
1775 |
cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
|
1776 |
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
1777 |
cpu_fprintf(f, "\n");
|
1778 |
} |
1779 |
} |
1780 |
cpu_fprintf(f, "\nCurrent Register Window:\n");
|
1781 |
for (x = 0; x < 3; x++) { |
1782 |
for (i = 0; i < 8; i++) { |
1783 |
if (i % REGS_PER_LINE == 0) { |
1784 |
cpu_fprintf(f, "%%%c%d-%d: ",
|
1785 |
x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), |
1786 |
i, i + REGS_PER_LINE - 1);
|
1787 |
} |
1788 |
cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); |
1789 |
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { |
1790 |
cpu_fprintf(f, "\n");
|
1791 |
} |
1792 |
} |
1793 |
} |
1794 |
cpu_fprintf(f, "\nFloating Point Registers:\n");
|
1795 |
for (i = 0; i < TARGET_FPREGS; i++) { |
1796 |
if ((i & 3) == 0) |
1797 |
cpu_fprintf(f, "%%f%02d:", i);
|
1798 |
cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]); |
1799 |
if ((i & 3) == 3) |
1800 |
cpu_fprintf(f, "\n");
|
1801 |
} |
1802 |
#ifdef TARGET_SPARC64
|
1803 |
cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
|
1804 |
(unsigned)cpu_get_ccr(env));
|
1805 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); |
1806 |
cpu_fprintf(f, " xcc: ");
|
1807 |
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
|
1808 |
cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
|
1809 |
env->psrpil); |
1810 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
|
1811 |
"cleanwin: %d cwp: %d\n",
|
1812 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
1813 |
env->cleanwin, env->nwindows - 1 - env->cwp);
|
1814 |
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " |
1815 |
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
|
1816 |
#else
|
1817 |
cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
|
1818 |
cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); |
1819 |
cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs? 'S' : '-', |
1820 |
env->psrps? 'P' : '-', env->psret? 'E' : '-', |
1821 |
env->wim); |
1822 |
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", |
1823 |
env->fsr, env->y); |
1824 |
#endif
|
1825 |
} |