Revision 32d98fbd
| b/tcg/arm/tcg-target.h | ||
|---|---|---|
| 69 | 69 |
// #define TCG_TARGET_HAS_orc_i32 |
| 70 | 70 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 71 | 71 |
// #define TCG_TARGET_HAS_nand_i32 |
| 72 |
// #define TCG_TARGET_HAS_nor_i32 |
|
| 72 | 73 |
|
| 73 | 74 |
#define TCG_TARGET_HAS_GUEST_BASE |
| 74 | 75 |
|
| b/tcg/i386/tcg-target.h | ||
|---|---|---|
| 59 | 59 |
// #define TCG_TARGET_HAS_orc_i32 |
| 60 | 60 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 61 | 61 |
// #define TCG_TARGET_HAS_nand_i32 |
| 62 |
// #define TCG_TARGET_HAS_nor_i32 |
|
| 62 | 63 |
|
| 63 | 64 |
#define TCG_TARGET_HAS_GUEST_BASE |
| 64 | 65 |
|
| b/tcg/mips/tcg-target.h | ||
|---|---|---|
| 89 | 89 |
#undef TCG_TARGET_HAS_orc_i32 |
| 90 | 90 |
#undef TCG_TARGET_HAS_eqv_i32 |
| 91 | 91 |
#undef TCG_TARGET_HAS_nand_i32 |
| 92 |
#undef TCG_TARGET_HAS_nor_i32 |
|
| 92 | 93 |
|
| 93 | 94 |
/* optional instructions automatically implemented */ |
| 94 | 95 |
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */ |
| b/tcg/ppc/tcg-target.h | ||
|---|---|---|
| 91 | 91 |
#define TCG_TARGET_HAS_orc_i32 |
| 92 | 92 |
/* #define TCG_TARGET_HAS_eqv_i32 */ |
| 93 | 93 |
/* #define TCG_TARGET_HAS_nand_i32 */ |
| 94 |
/* #define TCG_TARGET_HAS_nor_i32 */ |
|
| 94 | 95 |
|
| 95 | 96 |
#define TCG_AREG0 TCG_REG_R27 |
| 96 | 97 |
|
| b/tcg/ppc64/tcg-target.h | ||
|---|---|---|
| 82 | 82 |
/* #define TCG_TARGET_HAS_orc_i32 */ |
| 83 | 83 |
/* #define TCG_TARGET_HAS_eqv_i32 */ |
| 84 | 84 |
/* #define TCG_TARGET_HAS_nand_i32 */ |
| 85 |
/* #define TCG_TARGET_HAS_nor_i32 */ |
|
| 85 | 86 |
|
| 86 | 87 |
#define TCG_TARGET_HAS_div_i64 |
| 87 | 88 |
/* #define TCG_TARGET_HAS_rot_i64 */ |
| ... | ... | |
| 100 | 101 |
/* #define TCG_TARGET_HAS_orc_i64 */ |
| 101 | 102 |
/* #define TCG_TARGET_HAS_eqv_i64 */ |
| 102 | 103 |
/* #define TCG_TARGET_HAS_nand_i64 */ |
| 104 |
/* #define TCG_TARGET_HAS_nor_i64 */ |
|
| 103 | 105 |
|
| 104 | 106 |
#define TCG_AREG0 TCG_REG_R27 |
| 105 | 107 |
|
| b/tcg/s390/tcg-target.h | ||
|---|---|---|
| 61 | 61 |
// #define TCG_TARGET_HAS_orc_i32 |
| 62 | 62 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 63 | 63 |
// #define TCG_TARGET_HAS_nand_i32 |
| 64 |
// #define TCG_TARGET_HAS_nor_i32 |
|
| 64 | 65 |
|
| 65 | 66 |
// #define TCG_TARGET_HAS_div_i64 |
| 66 | 67 |
// #define TCG_TARGET_HAS_rot_i64 |
| ... | ... | |
| 79 | 80 |
// #define TCG_TARGET_HAS_orc_i64 |
| 80 | 81 |
// #define TCG_TARGET_HAS_eqv_i64 |
| 81 | 82 |
// #define TCG_TARGET_HAS_nand_i64 |
| 83 |
// #define TCG_TARGET_HAS_nor_i64 |
|
| 82 | 84 |
|
| 83 | 85 |
/* used for function call generation */ |
| 84 | 86 |
#define TCG_REG_CALL_STACK TCG_REG_R15 |
| b/tcg/sparc/tcg-target.h | ||
|---|---|---|
| 102 | 102 |
#define TCG_TARGET_HAS_orc_i32 |
| 103 | 103 |
// #define TCG_TARGET_HAS_eqv_i32 |
| 104 | 104 |
// #define TCG_TARGET_HAS_nand_i32 |
| 105 |
// #define TCG_TARGET_HAS_nor_i32 |
|
| 105 | 106 |
|
| 106 | 107 |
#if TCG_TARGET_REG_BITS == 64 |
| 107 | 108 |
#define TCG_TARGET_HAS_div_i64 |
| ... | ... | |
| 121 | 122 |
#define TCG_TARGET_HAS_orc_i64 |
| 122 | 123 |
// #define TCG_TARGET_HAS_eqv_i64 |
| 123 | 124 |
// #define TCG_TARGET_HAS_nand_i64 |
| 125 |
// #define TCG_TARGET_HAS_nor_i64 |
|
| 124 | 126 |
#endif |
| 125 | 127 |
|
| 126 | 128 |
/* Note: must be synced with dyngen-exec.h */ |
| b/tcg/tcg-op.h | ||
|---|---|---|
| 1786 | 1786 |
|
| 1787 | 1787 |
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
| 1788 | 1788 |
{
|
| 1789 |
#ifdef TCG_TARGET_HAS_nor_i32 |
|
| 1790 |
tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); |
|
| 1791 |
#else |
|
| 1789 | 1792 |
tcg_gen_or_i32(ret, arg1, arg2); |
| 1790 | 1793 |
tcg_gen_not_i32(ret, ret); |
| 1794 |
#endif |
|
| 1791 | 1795 |
} |
| 1792 | 1796 |
|
| 1793 | 1797 |
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
| 1794 | 1798 |
{
|
| 1799 |
#ifdef TCG_TARGET_HAS_nor_i64 |
|
| 1800 |
tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2); |
|
| 1801 |
#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32 |
|
| 1802 |
tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
|
| 1803 |
tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
|
| 1804 |
#else |
|
| 1795 | 1805 |
tcg_gen_or_i64(ret, arg1, arg2); |
| 1796 | 1806 |
tcg_gen_not_i64(ret, ret); |
| 1807 |
#endif |
|
| 1797 | 1808 |
} |
| 1798 | 1809 |
|
| 1799 | 1810 |
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
| b/tcg/tcg-opc.h | ||
|---|---|---|
| 122 | 122 |
#ifdef TCG_TARGET_HAS_nand_i32 |
| 123 | 123 |
DEF2(nand_i32, 1, 2, 0, 0) |
| 124 | 124 |
#endif |
| 125 |
#ifdef TCG_TARGET_HAS_nor_i32 |
|
| 126 |
DEF2(nor_i32, 1, 2, 0, 0) |
|
| 127 |
#endif |
|
| 125 | 128 |
|
| 126 | 129 |
#if TCG_TARGET_REG_BITS == 64 |
| 127 | 130 |
DEF2(mov_i64, 1, 1, 0, 0) |
| ... | ... | |
| 211 | 214 |
#ifdef TCG_TARGET_HAS_nand_i64 |
| 212 | 215 |
DEF2(nand_i64, 1, 2, 0, 0) |
| 213 | 216 |
#endif |
| 217 |
#ifdef TCG_TARGET_HAS_nor_i64 |
|
| 218 |
DEF2(nor_i64, 1, 2, 0, 0) |
|
| 219 |
#endif |
|
| 214 | 220 |
#endif |
| 215 | 221 |
|
| 216 | 222 |
/* QEMU specific */ |
| b/tcg/x86_64/tcg-target.h | ||
|---|---|---|
| 88 | 88 |
// #define TCG_TARGET_HAS_eqv_i64 |
| 89 | 89 |
// #define TCG_TARGET_HAS_nand_i32 |
| 90 | 90 |
// #define TCG_TARGET_HAS_nand_i64 |
| 91 |
// #define TCG_TARGET_HAS_nor_i32 |
|
| 92 |
// #define TCG_TARGET_HAS_nor_i64 |
|
| 91 | 93 |
|
| 92 | 94 |
#define TCG_TARGET_HAS_GUEST_BASE |
| 93 | 95 |
|
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