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1	2c0262af	bellard	/*
2	2c0262af	bellard	* i386 translation
3	2c0262af	bellard	*
4	2c0262af	bellard	* Copyright (c) 2003 Fabrice Bellard
5	2c0262af	bellard	*
6	2c0262af	bellard	* This library is free software; you can redistribute it and/or
7	2c0262af	bellard	* modify it under the terms of the GNU Lesser General Public
8	2c0262af	bellard	* License as published by the Free Software Foundation; either
9	2c0262af	bellard	* version 2 of the License, or (at your option) any later version.
10	2c0262af	bellard	*
11	2c0262af	bellard	* This library is distributed in the hope that it will be useful,
12	2c0262af	bellard	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	2c0262af	bellard	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	2c0262af	bellard	* Lesser General Public License for more details.
15	2c0262af	bellard	*
16	2c0262af	bellard	* You should have received a copy of the GNU Lesser General Public
17	2c0262af	bellard	* License along with this library; if not, write to the Free Software
18	2c0262af	bellard	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	2c0262af	bellard	*/
20	2c0262af	bellard	#include <stdarg.h>
21	2c0262af	bellard	#include <stdlib.h>
22	2c0262af	bellard	#include <stdio.h>
23	2c0262af	bellard	#include <string.h>
24	2c0262af	bellard	#include <inttypes.h>
25	2c0262af	bellard	#include <signal.h>
26	2c0262af	bellard	#include <assert.h>
27	2c0262af	bellard
28	2c0262af	bellard	#include "cpu.h"
29	2c0262af	bellard	#include "exec-all.h"
30	2c0262af	bellard	#include "disas.h"
31	2c0262af	bellard
32	2c0262af	bellard	/* XXX: move that elsewhere */
33	2c0262af	bellard	static uint16_t *gen_opc_ptr;
34	2c0262af	bellard	static uint32_t *gen_opparam_ptr;
35	2c0262af	bellard
36	2c0262af	bellard	#define PREFIX_REPZ 0x01
37	2c0262af	bellard	#define PREFIX_REPNZ 0x02
38	2c0262af	bellard	#define PREFIX_LOCK 0x04
39	2c0262af	bellard	#define PREFIX_DATA 0x08
40	2c0262af	bellard	#define PREFIX_ADR 0x10
41	2c0262af	bellard
42	14ce26e7	bellard	#ifdef TARGET_X86_64
43	14ce26e7	bellard	#define X86_64_ONLY(x) x
44	14ce26e7	bellard	#define X86_64_DEF(x...) x
45	14ce26e7	bellard	#define CODE64(s) ((s)->code64)
46	14ce26e7	bellard	#define REX_X(s) ((s)->rex_x)
47	14ce26e7	bellard	#define REX_B(s) ((s)->rex_b)
48	14ce26e7	bellard	/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
49	14ce26e7	bellard	#if 1
50	14ce26e7	bellard	#define BUGGY_64(x) NULL
51	14ce26e7	bellard	#endif
52	14ce26e7	bellard	#else
53	14ce26e7	bellard	#define X86_64_ONLY(x) NULL
54	14ce26e7	bellard	#define X86_64_DEF(x...)
55	14ce26e7	bellard	#define CODE64(s) 0
56	14ce26e7	bellard	#define REX_X(s) 0
57	14ce26e7	bellard	#define REX_B(s) 0
58	14ce26e7	bellard	#endif
59	14ce26e7	bellard
60	14ce26e7	bellard	#ifdef TARGET_X86_64
61	14ce26e7	bellard	static int x86_64_hregs;
62	14ce26e7	bellard	#endif
63	14ce26e7	bellard
64	ae063a68	bellard	#ifdef USE_DIRECT_JUMP
65	ae063a68	bellard	#define TBPARAM(x)
66	ae063a68	bellard	#else
67	ae063a68	bellard	#define TBPARAM(x) (long)(x)
68	ae063a68	bellard	#endif
69	ae063a68	bellard
70	2c0262af	bellard	typedef struct DisasContext {
71	2c0262af	bellard	/* current insn context */
72	2c0262af	bellard	int override; /* -1 if no override */
73	2c0262af	bellard	int prefix;
74	2c0262af	bellard	int aflag, dflag;
75	14ce26e7	bellard	target_ulong pc; /* pc = eip + cs_base */
76	2c0262af	bellard	int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
77	2c0262af	bellard	static state change (stop translation) */
78	2c0262af	bellard	/* current block context */
79	14ce26e7	bellard	target_ulong cs_base; /* base of CS segment */
80	2c0262af	bellard	int pe; /* protected mode */
81	2c0262af	bellard	int code32; /* 32 bit code segment */
82	14ce26e7	bellard	#ifdef TARGET_X86_64
83	14ce26e7	bellard	int lma; /* long mode active */
84	14ce26e7	bellard	int code64; /* 64 bit code segment */
85	14ce26e7	bellard	int rex_x, rex_b;
86	14ce26e7	bellard	#endif
87	2c0262af	bellard	int ss32; /* 32 bit stack segment */
88	2c0262af	bellard	int cc_op; /* current CC operation */
89	2c0262af	bellard	int addseg; /* non zero if either DS/ES/SS have a non zero base */
90	2c0262af	bellard	int f_st; /* currently unused */
91	2c0262af	bellard	int vm86; /* vm86 mode */
92	2c0262af	bellard	int cpl;
93	2c0262af	bellard	int iopl;
94	2c0262af	bellard	int tf; /* TF cpu flag */
95	34865134	bellard	int singlestep_enabled; /* "hardware" single step enabled */
96	2c0262af	bellard	int jmp_opt; /* use direct block chaining for direct jumps */
97	2c0262af	bellard	int mem_index; /* select memory access functions */
98	7eee2a50	bellard	int flags; /* all execution flags */
99	2c0262af	bellard	struct TranslationBlock *tb;
100	2c0262af	bellard	int popl_esp_hack; /* for correct popl with esp base handling */
101	14ce26e7	bellard	int rip_offset; /* only used in x86_64, but left for simplicity */
102	14ce26e7	bellard	int cpuid_features;
103	2c0262af	bellard	} DisasContext;
104	2c0262af	bellard
105	2c0262af	bellard	static void gen_eob(DisasContext *s);
106	14ce26e7	bellard	static void gen_jmp(DisasContext *s, target_ulong eip);
107	14ce26e7	bellard	static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
108	2c0262af	bellard
109	2c0262af	bellard	/* i386 arith/logic operations */
110	2c0262af	bellard	enum {
111	2c0262af	bellard	OP_ADDL,
112	2c0262af	bellard	OP_ORL,
113	2c0262af	bellard	OP_ADCL,
114	2c0262af	bellard	OP_SBBL,
115	2c0262af	bellard	OP_ANDL,
116	2c0262af	bellard	OP_SUBL,
117	2c0262af	bellard	OP_XORL,
118	2c0262af	bellard	OP_CMPL,
119	2c0262af	bellard	};
120	2c0262af	bellard
121	2c0262af	bellard	/* i386 shift ops */
122	2c0262af	bellard	enum {
123	2c0262af	bellard	OP_ROL,
124	2c0262af	bellard	OP_ROR,
125	2c0262af	bellard	OP_RCL,
126	2c0262af	bellard	OP_RCR,
127	2c0262af	bellard	OP_SHL,
128	2c0262af	bellard	OP_SHR,
129	2c0262af	bellard	OP_SHL1, /* undocumented */
130	2c0262af	bellard	OP_SAR = 7,
131	2c0262af	bellard	};
132	2c0262af	bellard
133	2c0262af	bellard	enum {
134	2c0262af	bellard	#define DEF(s, n, copy_size) INDEX_op_ ## s,
135	2c0262af	bellard	#include "opc.h"
136	2c0262af	bellard	#undef DEF
137	2c0262af	bellard	NB_OPS,
138	2c0262af	bellard	};
139	2c0262af	bellard
140	2c0262af	bellard	#include "gen-op.h"
141	2c0262af	bellard
142	2c0262af	bellard	/* operand size */
143	2c0262af	bellard	enum {
144	2c0262af	bellard	OT_BYTE = 0,
145	2c0262af	bellard	OT_WORD,
146	2c0262af	bellard	OT_LONG,
147	2c0262af	bellard	OT_QUAD,
148	2c0262af	bellard	};
149	2c0262af	bellard
150	2c0262af	bellard	enum {
151	2c0262af	bellard	/* I386 int registers */
152	2c0262af	bellard	OR_EAX, /* MUST be even numbered */
153	2c0262af	bellard	OR_ECX,
154	2c0262af	bellard	OR_EDX,
155	2c0262af	bellard	OR_EBX,
156	2c0262af	bellard	OR_ESP,
157	2c0262af	bellard	OR_EBP,
158	2c0262af	bellard	OR_ESI,
159	2c0262af	bellard	OR_EDI,
160	14ce26e7	bellard
161	14ce26e7	bellard	OR_TMP0 = 16, /* temporary operand register */
162	2c0262af	bellard	OR_TMP1,
163	2c0262af	bellard	OR_A0, /* temporary register used when doing address evaluation */
164	2c0262af	bellard	};
165	2c0262af	bellard
166	14ce26e7	bellard	#ifdef TARGET_X86_64
167	14ce26e7	bellard
168	14ce26e7	bellard	#define NB_OP_SIZES 4
169	14ce26e7	bellard
170	14ce26e7	bellard	#define DEF_REGS(prefix, suffix) \
171	14ce26e7	bellard	prefix ## EAX ## suffix,\
172	14ce26e7	bellard	prefix ## ECX ## suffix,\
173	14ce26e7	bellard	prefix ## EDX ## suffix,\
174	14ce26e7	bellard	prefix ## EBX ## suffix,\
175	14ce26e7	bellard	prefix ## ESP ## suffix,\
176	14ce26e7	bellard	prefix ## EBP ## suffix,\
177	14ce26e7	bellard	prefix ## ESI ## suffix,\
178	14ce26e7	bellard	prefix ## EDI ## suffix,\
179	14ce26e7	bellard	prefix ## R8 ## suffix,\
180	14ce26e7	bellard	prefix ## R9 ## suffix,\
181	14ce26e7	bellard	prefix ## R10 ## suffix,\
182	14ce26e7	bellard	prefix ## R11 ## suffix,\
183	14ce26e7	bellard	prefix ## R12 ## suffix,\
184	14ce26e7	bellard	prefix ## R13 ## suffix,\
185	14ce26e7	bellard	prefix ## R14 ## suffix,\
186	14ce26e7	bellard	prefix ## R15 ## suffix,
187	14ce26e7	bellard
188	14ce26e7	bellard	#define DEF_BREGS(prefixb, prefixh, suffix) \
189	14ce26e7	bellard	\
190	14ce26e7	bellard	static void prefixb ## ESP ## suffix ## _wrapper(void) \
191	14ce26e7	bellard	{ \
192	14ce26e7	bellard	if (x86_64_hregs) \
193	14ce26e7	bellard	prefixb ## ESP ## suffix (); \
194	14ce26e7	bellard	else \
195	14ce26e7	bellard	prefixh ## EAX ## suffix (); \
196	14ce26e7	bellard	} \
197	14ce26e7	bellard	\
198	14ce26e7	bellard	static void prefixb ## EBP ## suffix ## _wrapper(void) \
199	14ce26e7	bellard	{ \
200	14ce26e7	bellard	if (x86_64_hregs) \
201	14ce26e7	bellard	prefixb ## EBP ## suffix (); \
202	14ce26e7	bellard	else \
203	14ce26e7	bellard	prefixh ## ECX ## suffix (); \
204	14ce26e7	bellard	} \
205	14ce26e7	bellard	\
206	14ce26e7	bellard	static void prefixb ## ESI ## suffix ## _wrapper(void) \
207	14ce26e7	bellard	{ \
208	14ce26e7	bellard	if (x86_64_hregs) \
209	14ce26e7	bellard	prefixb ## ESI ## suffix (); \
210	14ce26e7	bellard	else \
211	14ce26e7	bellard	prefixh ## EDX ## suffix (); \
212	14ce26e7	bellard	} \
213	14ce26e7	bellard	\
214	14ce26e7	bellard	static void prefixb ## EDI ## suffix ## _wrapper(void) \
215	14ce26e7	bellard	{ \
216	14ce26e7	bellard	if (x86_64_hregs) \
217	14ce26e7	bellard	prefixb ## EDI ## suffix (); \
218	14ce26e7	bellard	else \
219	14ce26e7	bellard	prefixh ## EBX ## suffix (); \
220	14ce26e7	bellard	}
221	14ce26e7	bellard
222	14ce26e7	bellard	DEF_BREGS(gen_op_movb_, gen_op_movh_, _T0)
223	14ce26e7	bellard	DEF_BREGS(gen_op_movb_, gen_op_movh_, _T1)
224	14ce26e7	bellard	DEF_BREGS(gen_op_movl_T0_, gen_op_movh_T0_, )
225	14ce26e7	bellard	DEF_BREGS(gen_op_movl_T1_, gen_op_movh_T1_, )
226	14ce26e7	bellard
227	14ce26e7	bellard	#else /* !TARGET_X86_64 */
228	14ce26e7	bellard
229	14ce26e7	bellard	#define NB_OP_SIZES 3
230	14ce26e7	bellard
231	14ce26e7	bellard	#define DEF_REGS(prefix, suffix) \
232	14ce26e7	bellard	prefix ## EAX ## suffix,\
233	14ce26e7	bellard	prefix ## ECX ## suffix,\
234	14ce26e7	bellard	prefix ## EDX ## suffix,\
235	14ce26e7	bellard	prefix ## EBX ## suffix,\
236	14ce26e7	bellard	prefix ## ESP ## suffix,\
237	14ce26e7	bellard	prefix ## EBP ## suffix,\
238	14ce26e7	bellard	prefix ## ESI ## suffix,\
239	14ce26e7	bellard	prefix ## EDI ## suffix,
240	14ce26e7	bellard
241	14ce26e7	bellard	#endif /* !TARGET_X86_64 */
242	14ce26e7	bellard
243	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_T0[NB_OP_SIZES][CPU_NB_REGS] = {
244	2c0262af	bellard	[OT_BYTE] = {
245	2c0262af	bellard	gen_op_movb_EAX_T0,
246	2c0262af	bellard	gen_op_movb_ECX_T0,
247	2c0262af	bellard	gen_op_movb_EDX_T0,
248	2c0262af	bellard	gen_op_movb_EBX_T0,
249	14ce26e7	bellard	#ifdef TARGET_X86_64
250	14ce26e7	bellard	gen_op_movb_ESP_T0_wrapper,
251	14ce26e7	bellard	gen_op_movb_EBP_T0_wrapper,
252	14ce26e7	bellard	gen_op_movb_ESI_T0_wrapper,
253	14ce26e7	bellard	gen_op_movb_EDI_T0_wrapper,
254	14ce26e7	bellard	gen_op_movb_R8_T0,
255	14ce26e7	bellard	gen_op_movb_R9_T0,
256	14ce26e7	bellard	gen_op_movb_R10_T0,
257	14ce26e7	bellard	gen_op_movb_R11_T0,
258	14ce26e7	bellard	gen_op_movb_R12_T0,
259	14ce26e7	bellard	gen_op_movb_R13_T0,
260	14ce26e7	bellard	gen_op_movb_R14_T0,
261	14ce26e7	bellard	gen_op_movb_R15_T0,
262	14ce26e7	bellard	#else
263	2c0262af	bellard	gen_op_movh_EAX_T0,
264	2c0262af	bellard	gen_op_movh_ECX_T0,
265	2c0262af	bellard	gen_op_movh_EDX_T0,
266	2c0262af	bellard	gen_op_movh_EBX_T0,
267	14ce26e7	bellard	#endif
268	2c0262af	bellard	},
269	2c0262af	bellard	[OT_WORD] = {
270	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _T0)
271	2c0262af	bellard	},
272	2c0262af	bellard	[OT_LONG] = {
273	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _T0)
274	2c0262af	bellard	},
275	14ce26e7	bellard	#ifdef TARGET_X86_64
276	14ce26e7	bellard	[OT_QUAD] = {
277	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _T0)
278	14ce26e7	bellard	},
279	14ce26e7	bellard	#endif
280	2c0262af	bellard	};
281	2c0262af	bellard
282	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_T1[NB_OP_SIZES][CPU_NB_REGS] = {
283	2c0262af	bellard	[OT_BYTE] = {
284	2c0262af	bellard	gen_op_movb_EAX_T1,
285	2c0262af	bellard	gen_op_movb_ECX_T1,
286	2c0262af	bellard	gen_op_movb_EDX_T1,
287	2c0262af	bellard	gen_op_movb_EBX_T1,
288	14ce26e7	bellard	#ifdef TARGET_X86_64
289	14ce26e7	bellard	gen_op_movb_ESP_T1_wrapper,
290	14ce26e7	bellard	gen_op_movb_EBP_T1_wrapper,
291	14ce26e7	bellard	gen_op_movb_ESI_T1_wrapper,
292	14ce26e7	bellard	gen_op_movb_EDI_T1_wrapper,
293	14ce26e7	bellard	gen_op_movb_R8_T1,
294	14ce26e7	bellard	gen_op_movb_R9_T1,
295	14ce26e7	bellard	gen_op_movb_R10_T1,
296	14ce26e7	bellard	gen_op_movb_R11_T1,
297	14ce26e7	bellard	gen_op_movb_R12_T1,
298	14ce26e7	bellard	gen_op_movb_R13_T1,
299	14ce26e7	bellard	gen_op_movb_R14_T1,
300	14ce26e7	bellard	gen_op_movb_R15_T1,
301	14ce26e7	bellard	#else
302	2c0262af	bellard	gen_op_movh_EAX_T1,
303	2c0262af	bellard	gen_op_movh_ECX_T1,
304	2c0262af	bellard	gen_op_movh_EDX_T1,
305	2c0262af	bellard	gen_op_movh_EBX_T1,
306	14ce26e7	bellard	#endif
307	2c0262af	bellard	},
308	2c0262af	bellard	[OT_WORD] = {
309	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _T1)
310	2c0262af	bellard	},
311	2c0262af	bellard	[OT_LONG] = {
312	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _T1)
313	14ce26e7	bellard	},
314	14ce26e7	bellard	#ifdef TARGET_X86_64
315	14ce26e7	bellard	[OT_QUAD] = {
316	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _T1)
317	2c0262af	bellard	},
318	14ce26e7	bellard	#endif
319	2c0262af	bellard	};
320	2c0262af	bellard
321	14ce26e7	bellard	static GenOpFunc *gen_op_mov_reg_A0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
322	2c0262af	bellard	[0] = {
323	14ce26e7	bellard	DEF_REGS(gen_op_movw_, _A0)
324	2c0262af	bellard	},
325	2c0262af	bellard	[1] = {
326	14ce26e7	bellard	DEF_REGS(gen_op_movl_, _A0)
327	14ce26e7	bellard	},
328	14ce26e7	bellard	#ifdef TARGET_X86_64
329	14ce26e7	bellard	[2] = {
330	14ce26e7	bellard	DEF_REGS(gen_op_movq_, _A0)
331	2c0262af	bellard	},
332	14ce26e7	bellard	#endif
333	2c0262af	bellard	};
334	2c0262af	bellard
335	14ce26e7	bellard	static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] =
336	2c0262af	bellard	{
337	2c0262af	bellard	[OT_BYTE] = {
338	2c0262af	bellard	{
339	2c0262af	bellard	gen_op_movl_T0_EAX,
340	2c0262af	bellard	gen_op_movl_T0_ECX,
341	2c0262af	bellard	gen_op_movl_T0_EDX,
342	2c0262af	bellard	gen_op_movl_T0_EBX,
343	14ce26e7	bellard	#ifdef TARGET_X86_64
344	14ce26e7	bellard	gen_op_movl_T0_ESP_wrapper,
345	14ce26e7	bellard	gen_op_movl_T0_EBP_wrapper,
346	14ce26e7	bellard	gen_op_movl_T0_ESI_wrapper,
347	14ce26e7	bellard	gen_op_movl_T0_EDI_wrapper,
348	14ce26e7	bellard	gen_op_movl_T0_R8,
349	14ce26e7	bellard	gen_op_movl_T0_R9,
350	14ce26e7	bellard	gen_op_movl_T0_R10,
351	14ce26e7	bellard	gen_op_movl_T0_R11,
352	14ce26e7	bellard	gen_op_movl_T0_R12,
353	14ce26e7	bellard	gen_op_movl_T0_R13,
354	14ce26e7	bellard	gen_op_movl_T0_R14,
355	14ce26e7	bellard	gen_op_movl_T0_R15,
356	14ce26e7	bellard	#else
357	2c0262af	bellard	gen_op_movh_T0_EAX,
358	2c0262af	bellard	gen_op_movh_T0_ECX,
359	2c0262af	bellard	gen_op_movh_T0_EDX,
360	2c0262af	bellard	gen_op_movh_T0_EBX,
361	14ce26e7	bellard	#endif
362	2c0262af	bellard	},
363	2c0262af	bellard	{
364	2c0262af	bellard	gen_op_movl_T1_EAX,
365	2c0262af	bellard	gen_op_movl_T1_ECX,
366	2c0262af	bellard	gen_op_movl_T1_EDX,
367	2c0262af	bellard	gen_op_movl_T1_EBX,
368	14ce26e7	bellard	#ifdef TARGET_X86_64
369	14ce26e7	bellard	gen_op_movl_T1_ESP_wrapper,
370	14ce26e7	bellard	gen_op_movl_T1_EBP_wrapper,
371	14ce26e7	bellard	gen_op_movl_T1_ESI_wrapper,
372	14ce26e7	bellard	gen_op_movl_T1_EDI_wrapper,
373	14ce26e7	bellard	gen_op_movl_T1_R8,
374	14ce26e7	bellard	gen_op_movl_T1_R9,
375	14ce26e7	bellard	gen_op_movl_T1_R10,
376	14ce26e7	bellard	gen_op_movl_T1_R11,
377	14ce26e7	bellard	gen_op_movl_T1_R12,
378	14ce26e7	bellard	gen_op_movl_T1_R13,
379	14ce26e7	bellard	gen_op_movl_T1_R14,
380	14ce26e7	bellard	gen_op_movl_T1_R15,
381	14ce26e7	bellard	#else
382	2c0262af	bellard	gen_op_movh_T1_EAX,
383	2c0262af	bellard	gen_op_movh_T1_ECX,
384	2c0262af	bellard	gen_op_movh_T1_EDX,
385	2c0262af	bellard	gen_op_movh_T1_EBX,
386	14ce26e7	bellard	#endif
387	2c0262af	bellard	},
388	2c0262af	bellard	},
389	2c0262af	bellard	[OT_WORD] = {
390	2c0262af	bellard	{
391	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
392	2c0262af	bellard	},
393	2c0262af	bellard	{
394	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
395	2c0262af	bellard	},
396	2c0262af	bellard	},
397	2c0262af	bellard	[OT_LONG] = {
398	2c0262af	bellard	{
399	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
400	2c0262af	bellard	},
401	2c0262af	bellard	{
402	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
403	2c0262af	bellard	},
404	2c0262af	bellard	},
405	14ce26e7	bellard	#ifdef TARGET_X86_64
406	14ce26e7	bellard	[OT_QUAD] = {
407	14ce26e7	bellard	{
408	14ce26e7	bellard	DEF_REGS(gen_op_movl_T0_, )
409	14ce26e7	bellard	},
410	14ce26e7	bellard	{
411	14ce26e7	bellard	DEF_REGS(gen_op_movl_T1_, )
412	14ce26e7	bellard	},
413	14ce26e7	bellard	},
414	14ce26e7	bellard	#endif
415	2c0262af	bellard	};
416	2c0262af	bellard
417	14ce26e7	bellard	static GenOpFunc *gen_op_movl_A0_reg[CPU_NB_REGS] = {
418	14ce26e7	bellard	DEF_REGS(gen_op_movl_A0_, )
419	2c0262af	bellard	};
420	2c0262af	bellard
421	14ce26e7	bellard	static GenOpFunc *gen_op_addl_A0_reg_sN[4][CPU_NB_REGS] = {
422	2c0262af	bellard	[0] = {
423	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, )
424	2c0262af	bellard	},
425	2c0262af	bellard	[1] = {
426	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s1)
427	2c0262af	bellard	},
428	2c0262af	bellard	[2] = {
429	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s2)
430	2c0262af	bellard	},
431	2c0262af	bellard	[3] = {
432	14ce26e7	bellard	DEF_REGS(gen_op_addl_A0_, _s3)
433	2c0262af	bellard	},
434	2c0262af	bellard	};
435	2c0262af	bellard
436	14ce26e7	bellard	#ifdef TARGET_X86_64
437	14ce26e7	bellard	static GenOpFunc *gen_op_movq_A0_reg[CPU_NB_REGS] = {
438	14ce26e7	bellard	DEF_REGS(gen_op_movq_A0_, )
439	14ce26e7	bellard	};
440	14ce26e7	bellard
441	14ce26e7	bellard	static GenOpFunc *gen_op_addq_A0_reg_sN[4][CPU_NB_REGS] = {
442	2c0262af	bellard	[0] = {
443	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, )
444	2c0262af	bellard	},
445	2c0262af	bellard	[1] = {
446	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s1)
447	14ce26e7	bellard	},
448	14ce26e7	bellard	[2] = {
449	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s2)
450	14ce26e7	bellard	},
451	14ce26e7	bellard	[3] = {
452	14ce26e7	bellard	DEF_REGS(gen_op_addq_A0_, _s3)
453	2c0262af	bellard	},
454	2c0262af	bellard	};
455	14ce26e7	bellard	#endif
456	14ce26e7	bellard
457	14ce26e7	bellard	static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
458	14ce26e7	bellard	[0] = {
459	14ce26e7	bellard	DEF_REGS(gen_op_cmovw_, _T1_T0)
460	14ce26e7	bellard	},
461	14ce26e7	bellard	[1] = {
462	14ce26e7	bellard	DEF_REGS(gen_op_cmovl_, _T1_T0)
463	14ce26e7	bellard	},
464	14ce26e7	bellard	#ifdef TARGET_X86_64
465	14ce26e7	bellard	[2] = {
466	14ce26e7	bellard	DEF_REGS(gen_op_cmovq_, _T1_T0)
467	14ce26e7	bellard	},
468	14ce26e7	bellard	#endif
469	14ce26e7	bellard	};
470	2c0262af	bellard
471	2c0262af	bellard	static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
472	2c0262af	bellard	NULL,
473	2c0262af	bellard	gen_op_orl_T0_T1,
474	2c0262af	bellard	NULL,
475	2c0262af	bellard	NULL,
476	2c0262af	bellard	gen_op_andl_T0_T1,
477	2c0262af	bellard	NULL,
478	2c0262af	bellard	gen_op_xorl_T0_T1,
479	2c0262af	bellard	NULL,
480	2c0262af	bellard	};
481	2c0262af	bellard
482	4f31916f	bellard	#define DEF_ARITHC(SUFFIX)\
483	4f31916f	bellard	{\
484	4f31916f	bellard	gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
485	4f31916f	bellard	gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
486	4f31916f	bellard	},\
487	4f31916f	bellard	{\
488	4f31916f	bellard	gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
489	4f31916f	bellard	gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
490	4f31916f	bellard	},\
491	4f31916f	bellard	{\
492	4f31916f	bellard	gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
493	4f31916f	bellard	gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
494	14ce26e7	bellard	},\
495	14ce26e7	bellard	{\
496	14ce26e7	bellard	X86_64_ONLY(gen_op_adcq ## SUFFIX ## _T0_T1_cc),\
497	14ce26e7	bellard	X86_64_ONLY(gen_op_sbbq ## SUFFIX ## _T0_T1_cc),\
498	2c0262af	bellard	},
499	4f31916f	bellard
500	14ce26e7	bellard	static GenOpFunc *gen_op_arithc_T0_T1_cc[4][2] = {
501	4bb2fcc7	bellard	DEF_ARITHC( )
502	2c0262af	bellard	};
503	2c0262af	bellard
504	14ce26e7	bellard	static GenOpFunc gen_op_arithc_mem_T0_T1_cc[3 4][2] = {
505	4f31916f	bellard	DEF_ARITHC(_raw)
506	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
507	4f31916f	bellard	DEF_ARITHC(_kernel)
508	4f31916f	bellard	DEF_ARITHC(_user)
509	4f31916f	bellard	#endif
510	2c0262af	bellard	};
511	2c0262af	bellard
512	2c0262af	bellard	static const int cc_op_arithb[8] = {
513	2c0262af	bellard	CC_OP_ADDB,
514	2c0262af	bellard	CC_OP_LOGICB,
515	2c0262af	bellard	CC_OP_ADDB,
516	2c0262af	bellard	CC_OP_SUBB,
517	2c0262af	bellard	CC_OP_LOGICB,
518	2c0262af	bellard	CC_OP_SUBB,
519	2c0262af	bellard	CC_OP_LOGICB,
520	2c0262af	bellard	CC_OP_SUBB,
521	2c0262af	bellard	};
522	2c0262af	bellard
523	4f31916f	bellard	#define DEF_CMPXCHG(SUFFIX)\
524	4f31916f	bellard	gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
525	4f31916f	bellard	gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
526	14ce26e7	bellard	gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,\
527	14ce26e7	bellard	X86_64_ONLY(gen_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc),
528	4f31916f	bellard
529	14ce26e7	bellard	static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[4] = {
530	4bb2fcc7	bellard	DEF_CMPXCHG( )
531	2c0262af	bellard	};
532	2c0262af	bellard
533	14ce26e7	bellard	static GenOpFunc gen_op_cmpxchg_mem_T0_T1_EAX_cc[3 4] = {
534	4f31916f	bellard	DEF_CMPXCHG(_raw)
535	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
536	4f31916f	bellard	DEF_CMPXCHG(_kernel)
537	4f31916f	bellard	DEF_CMPXCHG(_user)
538	4f31916f	bellard	#endif
539	2c0262af	bellard	};
540	2c0262af	bellard
541	4f31916f	bellard	#define DEF_SHIFT(SUFFIX)\
542	4f31916f	bellard	{\
543	4f31916f	bellard	gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
544	4f31916f	bellard	gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
545	4f31916f	bellard	gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
546	4f31916f	bellard	gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
547	4f31916f	bellard	gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
548	4f31916f	bellard	gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
549	4f31916f	bellard	gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
550	4f31916f	bellard	gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
551	4f31916f	bellard	},\
552	4f31916f	bellard	{\
553	4f31916f	bellard	gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
554	4f31916f	bellard	gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
555	4f31916f	bellard	gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
556	4f31916f	bellard	gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
557	4f31916f	bellard	gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
558	4f31916f	bellard	gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
559	4f31916f	bellard	gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
560	4f31916f	bellard	gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
561	4f31916f	bellard	},\
562	4f31916f	bellard	{\
563	4f31916f	bellard	gen_op_roll ## SUFFIX ## _T0_T1_cc,\
564	4f31916f	bellard	gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
565	4f31916f	bellard	gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
566	4f31916f	bellard	gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
567	4f31916f	bellard	gen_op_shll ## SUFFIX ## _T0_T1_cc,\
568	4f31916f	bellard	gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
569	4f31916f	bellard	gen_op_shll ## SUFFIX ## _T0_T1_cc,\
570	4f31916f	bellard	gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
571	14ce26e7	bellard	},\
572	14ce26e7	bellard	{\
573	14ce26e7	bellard	X86_64_ONLY(gen_op_rolq ## SUFFIX ## _T0_T1_cc),\
574	14ce26e7	bellard	X86_64_ONLY(gen_op_rorq ## SUFFIX ## _T0_T1_cc),\
575	14ce26e7	bellard	X86_64_ONLY(gen_op_rclq ## SUFFIX ## _T0_T1_cc),\
576	14ce26e7	bellard	X86_64_ONLY(gen_op_rcrq ## SUFFIX ## _T0_T1_cc),\
577	14ce26e7	bellard	X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
578	14ce26e7	bellard	X86_64_ONLY(gen_op_shrq ## SUFFIX ## _T0_T1_cc),\
579	14ce26e7	bellard	X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
580	14ce26e7	bellard	X86_64_ONLY(gen_op_sarq ## SUFFIX ## _T0_T1_cc),\
581	2c0262af	bellard	},
582	4f31916f	bellard
583	14ce26e7	bellard	static GenOpFunc *gen_op_shift_T0_T1_cc[4][8] = {
584	4bb2fcc7	bellard	DEF_SHIFT( )
585	2c0262af	bellard	};
586	2c0262af	bellard
587	14ce26e7	bellard	static GenOpFunc gen_op_shift_mem_T0_T1_cc[3 4][8] = {
588	4f31916f	bellard	DEF_SHIFT(_raw)
589	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
590	4f31916f	bellard	DEF_SHIFT(_kernel)
591	4f31916f	bellard	DEF_SHIFT(_user)
592	4f31916f	bellard	#endif
593	2c0262af	bellard	};
594	2c0262af	bellard
595	4f31916f	bellard	#define DEF_SHIFTD(SUFFIX, op)\
596	4f31916f	bellard	{\
597	4f31916f	bellard	NULL,\
598	4f31916f	bellard	NULL,\
599	4f31916f	bellard	},\
600	4f31916f	bellard	{\
601	4f31916f	bellard	gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
602	4f31916f	bellard	gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
603	31313213	bellard	},\
604	4f31916f	bellard	{\
605	4f31916f	bellard	gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
606	4f31916f	bellard	gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
607	14ce26e7	bellard	},\
608	14ce26e7	bellard	{\
609	31313213	bellard	X86_64_DEF(gen_op_shldq ## SUFFIX ## _T0_T1_ ## op ## _cc,\
610	31313213	bellard	gen_op_shrdq ## SUFFIX ## _T0_T1_ ## op ## _cc,)\
611	2c0262af	bellard	},
612	4f31916f	bellard
613	14ce26e7	bellard	static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[4][2] = {
614	4f31916f	bellard	DEF_SHIFTD(, im)
615	2c0262af	bellard	};
616	2c0262af	bellard
617	14ce26e7	bellard	static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[4][2] = {
618	4f31916f	bellard	DEF_SHIFTD(, ECX)
619	2c0262af	bellard	};
620	2c0262af	bellard
621	14ce26e7	bellard	static GenOpFunc1 gen_op_shiftd_mem_T0_T1_im_cc[3 4][2] = {
622	4f31916f	bellard	DEF_SHIFTD(_raw, im)
623	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
624	4f31916f	bellard	DEF_SHIFTD(_kernel, im)
625	4f31916f	bellard	DEF_SHIFTD(_user, im)
626	4f31916f	bellard	#endif
627	2c0262af	bellard	};
628	2c0262af	bellard
629	14ce26e7	bellard	static GenOpFunc gen_op_shiftd_mem_T0_T1_ECX_cc[3 4][2] = {
630	4f31916f	bellard	DEF_SHIFTD(_raw, ECX)
631	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
632	4f31916f	bellard	DEF_SHIFTD(_kernel, ECX)
633	4f31916f	bellard	DEF_SHIFTD(_user, ECX)
634	4f31916f	bellard	#endif
635	2c0262af	bellard	};
636	2c0262af	bellard
637	14ce26e7	bellard	static GenOpFunc *gen_op_btx_T0_T1_cc[3][4] = {
638	2c0262af	bellard	[0] = {
639	2c0262af	bellard	gen_op_btw_T0_T1_cc,
640	2c0262af	bellard	gen_op_btsw_T0_T1_cc,
641	2c0262af	bellard	gen_op_btrw_T0_T1_cc,
642	2c0262af	bellard	gen_op_btcw_T0_T1_cc,
643	2c0262af	bellard	},
644	2c0262af	bellard	[1] = {
645	2c0262af	bellard	gen_op_btl_T0_T1_cc,
646	2c0262af	bellard	gen_op_btsl_T0_T1_cc,
647	2c0262af	bellard	gen_op_btrl_T0_T1_cc,
648	2c0262af	bellard	gen_op_btcl_T0_T1_cc,
649	2c0262af	bellard	},
650	14ce26e7	bellard	#ifdef TARGET_X86_64
651	14ce26e7	bellard	[2] = {
652	14ce26e7	bellard	gen_op_btq_T0_T1_cc,
653	14ce26e7	bellard	gen_op_btsq_T0_T1_cc,
654	14ce26e7	bellard	gen_op_btrq_T0_T1_cc,
655	14ce26e7	bellard	gen_op_btcq_T0_T1_cc,
656	14ce26e7	bellard	},
657	14ce26e7	bellard	#endif
658	14ce26e7	bellard	};
659	14ce26e7	bellard
660	14ce26e7	bellard	static GenOpFunc *gen_op_add_bit_A0_T1[3] = {
661	14ce26e7	bellard	gen_op_add_bitw_A0_T1,
662	14ce26e7	bellard	gen_op_add_bitl_A0_T1,
663	14ce26e7	bellard	X86_64_ONLY(gen_op_add_bitq_A0_T1),
664	2c0262af	bellard	};
665	2c0262af	bellard
666	14ce26e7	bellard	static GenOpFunc *gen_op_bsx_T0_cc[3][2] = {
667	2c0262af	bellard	[0] = {
668	2c0262af	bellard	gen_op_bsfw_T0_cc,
669	2c0262af	bellard	gen_op_bsrw_T0_cc,
670	2c0262af	bellard	},
671	2c0262af	bellard	[1] = {
672	2c0262af	bellard	gen_op_bsfl_T0_cc,
673	2c0262af	bellard	gen_op_bsrl_T0_cc,
674	2c0262af	bellard	},
675	14ce26e7	bellard	#ifdef TARGET_X86_64
676	14ce26e7	bellard	[2] = {
677	14ce26e7	bellard	gen_op_bsfq_T0_cc,
678	14ce26e7	bellard	gen_op_bsrq_T0_cc,
679	14ce26e7	bellard	},
680	14ce26e7	bellard	#endif
681	2c0262af	bellard	};
682	2c0262af	bellard
683	14ce26e7	bellard	static GenOpFunc gen_op_lds_T0_A0[3 4] = {
684	61382a50	bellard	gen_op_ldsb_raw_T0_A0,
685	61382a50	bellard	gen_op_ldsw_raw_T0_A0,
686	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_raw_T0_A0),
687	2c0262af	bellard	NULL,
688	61382a50	bellard	#ifndef CONFIG_USER_ONLY
689	2c0262af	bellard	gen_op_ldsb_kernel_T0_A0,
690	2c0262af	bellard	gen_op_ldsw_kernel_T0_A0,
691	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_kernel_T0_A0),
692	2c0262af	bellard	NULL,
693	2c0262af	bellard
694	2c0262af	bellard	gen_op_ldsb_user_T0_A0,
695	2c0262af	bellard	gen_op_ldsw_user_T0_A0,
696	14ce26e7	bellard	X86_64_ONLY(gen_op_ldsl_user_T0_A0),
697	2c0262af	bellard	NULL,
698	61382a50	bellard	#endif
699	2c0262af	bellard	};
700	2c0262af	bellard
701	14ce26e7	bellard	static GenOpFunc gen_op_ldu_T0_A0[3 4] = {
702	61382a50	bellard	gen_op_ldub_raw_T0_A0,
703	61382a50	bellard	gen_op_lduw_raw_T0_A0,
704	2c0262af	bellard	NULL,
705	14ce26e7	bellard	NULL,
706	2c0262af	bellard
707	61382a50	bellard	#ifndef CONFIG_USER_ONLY
708	2c0262af	bellard	gen_op_ldub_kernel_T0_A0,
709	2c0262af	bellard	gen_op_lduw_kernel_T0_A0,
710	2c0262af	bellard	NULL,
711	14ce26e7	bellard	NULL,
712	2c0262af	bellard
713	2c0262af	bellard	gen_op_ldub_user_T0_A0,
714	2c0262af	bellard	gen_op_lduw_user_T0_A0,
715	2c0262af	bellard	NULL,
716	14ce26e7	bellard	NULL,
717	61382a50	bellard	#endif
718	2c0262af	bellard	};
719	2c0262af	bellard
720	2c0262af	bellard	/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
721	14ce26e7	bellard	static GenOpFunc gen_op_ld_T0_A0[3 4] = {
722	61382a50	bellard	gen_op_ldub_raw_T0_A0,
723	61382a50	bellard	gen_op_lduw_raw_T0_A0,
724	61382a50	bellard	gen_op_ldl_raw_T0_A0,
725	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_raw_T0_A0),
726	2c0262af	bellard
727	61382a50	bellard	#ifndef CONFIG_USER_ONLY
728	2c0262af	bellard	gen_op_ldub_kernel_T0_A0,
729	2c0262af	bellard	gen_op_lduw_kernel_T0_A0,
730	2c0262af	bellard	gen_op_ldl_kernel_T0_A0,
731	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_kernel_T0_A0),
732	2c0262af	bellard
733	2c0262af	bellard	gen_op_ldub_user_T0_A0,
734	2c0262af	bellard	gen_op_lduw_user_T0_A0,
735	2c0262af	bellard	gen_op_ldl_user_T0_A0,
736	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_user_T0_A0),
737	61382a50	bellard	#endif
738	2c0262af	bellard	};
739	2c0262af	bellard
740	14ce26e7	bellard	static GenOpFunc gen_op_ld_T1_A0[3 4] = {
741	61382a50	bellard	gen_op_ldub_raw_T1_A0,
742	61382a50	bellard	gen_op_lduw_raw_T1_A0,
743	61382a50	bellard	gen_op_ldl_raw_T1_A0,
744	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_raw_T1_A0),
745	2c0262af	bellard
746	61382a50	bellard	#ifndef CONFIG_USER_ONLY
747	2c0262af	bellard	gen_op_ldub_kernel_T1_A0,
748	2c0262af	bellard	gen_op_lduw_kernel_T1_A0,
749	2c0262af	bellard	gen_op_ldl_kernel_T1_A0,
750	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_kernel_T1_A0),
751	2c0262af	bellard
752	2c0262af	bellard	gen_op_ldub_user_T1_A0,
753	2c0262af	bellard	gen_op_lduw_user_T1_A0,
754	2c0262af	bellard	gen_op_ldl_user_T1_A0,
755	14ce26e7	bellard	X86_64_ONLY(gen_op_ldq_user_T1_A0),
756	61382a50	bellard	#endif
757	2c0262af	bellard	};
758	2c0262af	bellard
759	14ce26e7	bellard	static GenOpFunc gen_op_st_T0_A0[3 4] = {
760	61382a50	bellard	gen_op_stb_raw_T0_A0,
761	61382a50	bellard	gen_op_stw_raw_T0_A0,
762	61382a50	bellard	gen_op_stl_raw_T0_A0,
763	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_raw_T0_A0),
764	2c0262af	bellard
765	61382a50	bellard	#ifndef CONFIG_USER_ONLY
766	2c0262af	bellard	gen_op_stb_kernel_T0_A0,
767	2c0262af	bellard	gen_op_stw_kernel_T0_A0,
768	2c0262af	bellard	gen_op_stl_kernel_T0_A0,
769	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_kernel_T0_A0),
770	2c0262af	bellard
771	2c0262af	bellard	gen_op_stb_user_T0_A0,
772	2c0262af	bellard	gen_op_stw_user_T0_A0,
773	2c0262af	bellard	gen_op_stl_user_T0_A0,
774	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_user_T0_A0),
775	61382a50	bellard	#endif
776	2c0262af	bellard	};
777	2c0262af	bellard
778	14ce26e7	bellard	static GenOpFunc gen_op_st_T1_A0[3 4] = {
779	4f31916f	bellard	NULL,
780	4f31916f	bellard	gen_op_stw_raw_T1_A0,
781	4f31916f	bellard	gen_op_stl_raw_T1_A0,
782	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_raw_T1_A0),
783	4f31916f	bellard
784	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
785	4f31916f	bellard	NULL,
786	4f31916f	bellard	gen_op_stw_kernel_T1_A0,
787	4f31916f	bellard	gen_op_stl_kernel_T1_A0,
788	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_kernel_T1_A0),
789	4f31916f	bellard
790	4f31916f	bellard	NULL,
791	4f31916f	bellard	gen_op_stw_user_T1_A0,
792	4f31916f	bellard	gen_op_stl_user_T1_A0,
793	14ce26e7	bellard	X86_64_ONLY(gen_op_stq_user_T1_A0),
794	4f31916f	bellard	#endif
795	4f31916f	bellard	};
796	4f31916f	bellard
797	14ce26e7	bellard	static inline void gen_jmp_im(target_ulong pc)
798	14ce26e7	bellard	{
799	14ce26e7	bellard	#ifdef TARGET_X86_64
800	14ce26e7	bellard	if (pc == (uint32_t)pc) {
801	14ce26e7	bellard	gen_op_movl_eip_im(pc);
802	14ce26e7	bellard	} else if (pc == (int32_t)pc) {
803	14ce26e7	bellard	gen_op_movq_eip_im(pc);
804	14ce26e7	bellard	} else {
805	14ce26e7	bellard	gen_op_movq_eip_im64(pc >> 32, pc);
806	14ce26e7	bellard	}
807	14ce26e7	bellard	#else
808	14ce26e7	bellard	gen_op_movl_eip_im(pc);
809	14ce26e7	bellard	#endif
810	14ce26e7	bellard	}
811	14ce26e7	bellard
812	2c0262af	bellard	static inline void gen_string_movl_A0_ESI(DisasContext *s)
813	2c0262af	bellard	{
814	2c0262af	bellard	int override;
815	2c0262af	bellard
816	2c0262af	bellard	override = s->override;
817	14ce26e7	bellard	#ifdef TARGET_X86_64
818	14ce26e7	bellard	if (s->aflag == 2) {
819	14ce26e7	bellard	if (override >= 0) {
820	14ce26e7	bellard	gen_op_movq_A0_seg(offsetof(CPUX86State,segs[override].base));
821	14ce26e7	bellard	gen_op_addq_A0_reg_sN[0][R_ESI]();
822	14ce26e7	bellard	} else {
823	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESI]();
824	14ce26e7	bellard	}
825	14ce26e7	bellard	} else
826	14ce26e7	bellard	#endif
827	2c0262af	bellard	if (s->aflag) {
828	2c0262af	bellard	/* 32 bit address */
829	2c0262af	bellard	if (s->addseg && override < 0)
830	2c0262af	bellard	override = R_DS;
831	2c0262af	bellard	if (override >= 0) {
832	2c0262af	bellard	gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
833	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
834	2c0262af	bellard	} else {
835	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
836	2c0262af	bellard	}
837	2c0262af	bellard	} else {
838	2c0262af	bellard	/* 16 address, always override */
839	2c0262af	bellard	if (override < 0)
840	2c0262af	bellard	override = R_DS;
841	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
842	2c0262af	bellard	gen_op_andl_A0_ffff();
843	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
844	2c0262af	bellard	}
845	2c0262af	bellard	}
846	2c0262af	bellard
847	2c0262af	bellard	static inline void gen_string_movl_A0_EDI(DisasContext *s)
848	2c0262af	bellard	{
849	14ce26e7	bellard	#ifdef TARGET_X86_64
850	14ce26e7	bellard	if (s->aflag == 2) {
851	14ce26e7	bellard	gen_op_movq_A0_reg[R_EDI]();
852	14ce26e7	bellard	} else
853	14ce26e7	bellard	#endif
854	2c0262af	bellard	if (s->aflag) {
855	2c0262af	bellard	if (s->addseg) {
856	2c0262af	bellard	gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
857	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
858	2c0262af	bellard	} else {
859	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
860	2c0262af	bellard	}
861	2c0262af	bellard	} else {
862	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
863	2c0262af	bellard	gen_op_andl_A0_ffff();
864	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
865	2c0262af	bellard	}
866	2c0262af	bellard	}
867	2c0262af	bellard
868	14ce26e7	bellard	static GenOpFunc *gen_op_movl_T0_Dshift[4] = {
869	2c0262af	bellard	gen_op_movl_T0_Dshiftb,
870	2c0262af	bellard	gen_op_movl_T0_Dshiftw,
871	2c0262af	bellard	gen_op_movl_T0_Dshiftl,
872	14ce26e7	bellard	X86_64_ONLY(gen_op_movl_T0_Dshiftq),
873	2c0262af	bellard	};
874	2c0262af	bellard
875	14ce26e7	bellard	static GenOpFunc1 *gen_op_jnz_ecx[3] = {
876	14ce26e7	bellard	gen_op_jnz_ecxw,
877	14ce26e7	bellard	gen_op_jnz_ecxl,
878	14ce26e7	bellard	X86_64_ONLY(gen_op_jnz_ecxq),
879	2c0262af	bellard	};
880	2c0262af	bellard
881	14ce26e7	bellard	static GenOpFunc1 *gen_op_jz_ecx[3] = {
882	14ce26e7	bellard	gen_op_jz_ecxw,
883	14ce26e7	bellard	gen_op_jz_ecxl,
884	14ce26e7	bellard	X86_64_ONLY(gen_op_jz_ecxq),
885	2c0262af	bellard	};
886	2c0262af	bellard
887	14ce26e7	bellard	static GenOpFunc *gen_op_dec_ECX[3] = {
888	2c0262af	bellard	gen_op_decw_ECX,
889	2c0262af	bellard	gen_op_decl_ECX,
890	14ce26e7	bellard	X86_64_ONLY(gen_op_decq_ECX),
891	2c0262af	bellard	};
892	2c0262af	bellard
893	14ce26e7	bellard	static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = {
894	2c0262af	bellard	{
895	14ce26e7	bellard	gen_op_jnz_subb,
896	14ce26e7	bellard	gen_op_jnz_subw,
897	14ce26e7	bellard	gen_op_jnz_subl,
898	14ce26e7	bellard	X86_64_ONLY(gen_op_jnz_subq),
899	2c0262af	bellard	},
900	2c0262af	bellard	{
901	14ce26e7	bellard	gen_op_jz_subb,
902	14ce26e7	bellard	gen_op_jz_subw,
903	14ce26e7	bellard	gen_op_jz_subl,
904	14ce26e7	bellard	X86_64_ONLY(gen_op_jz_subq),
905	2c0262af	bellard	},
906	2c0262af	bellard	};
907	2c0262af	bellard
908	2c0262af	bellard	static GenOpFunc *gen_op_in_DX_T0[3] = {
909	2c0262af	bellard	gen_op_inb_DX_T0,
910	2c0262af	bellard	gen_op_inw_DX_T0,
911	2c0262af	bellard	gen_op_inl_DX_T0,
912	2c0262af	bellard	};
913	2c0262af	bellard
914	2c0262af	bellard	static GenOpFunc *gen_op_out_DX_T0[3] = {
915	2c0262af	bellard	gen_op_outb_DX_T0,
916	2c0262af	bellard	gen_op_outw_DX_T0,
917	2c0262af	bellard	gen_op_outl_DX_T0,
918	2c0262af	bellard	};
919	2c0262af	bellard
920	f115e911	bellard	static GenOpFunc *gen_op_in[3] = {
921	f115e911	bellard	gen_op_inb_T0_T1,
922	f115e911	bellard	gen_op_inw_T0_T1,
923	f115e911	bellard	gen_op_inl_T0_T1,
924	f115e911	bellard	};
925	f115e911	bellard
926	f115e911	bellard	static GenOpFunc *gen_op_out[3] = {
927	f115e911	bellard	gen_op_outb_T0_T1,
928	f115e911	bellard	gen_op_outw_T0_T1,
929	f115e911	bellard	gen_op_outl_T0_T1,
930	f115e911	bellard	};
931	f115e911	bellard
932	f115e911	bellard	static GenOpFunc *gen_check_io_T0[3] = {
933	f115e911	bellard	gen_op_check_iob_T0,
934	f115e911	bellard	gen_op_check_iow_T0,
935	f115e911	bellard	gen_op_check_iol_T0,
936	f115e911	bellard	};
937	f115e911	bellard
938	f115e911	bellard	static GenOpFunc *gen_check_io_DX[3] = {
939	f115e911	bellard	gen_op_check_iob_DX,
940	f115e911	bellard	gen_op_check_iow_DX,
941	f115e911	bellard	gen_op_check_iol_DX,
942	f115e911	bellard	};
943	f115e911	bellard
944	14ce26e7	bellard	static void gen_check_io(DisasContext *s, int ot, int use_dx, target_ulong cur_eip)
945	f115e911	bellard	{
946	f115e911	bellard	if (s->pe && (s->cpl > s->iopl \|\| s->vm86)) {
947	f115e911	bellard	if (s->cc_op != CC_OP_DYNAMIC)
948	f115e911	bellard	gen_op_set_cc_op(s->cc_op);
949	14ce26e7	bellard	gen_jmp_im(cur_eip);
950	f115e911	bellard	if (use_dx)
951	f115e911	bellard	gen_check_io_DX[ot]();
952	f115e911	bellard	else
953	f115e911	bellard	gen_check_io_T0[ot]();
954	f115e911	bellard	}
955	f115e911	bellard	}
956	f115e911	bellard
957	2c0262af	bellard	static inline void gen_movs(DisasContext *s, int ot)
958	2c0262af	bellard	{
959	2c0262af	bellard	gen_string_movl_A0_ESI(s);
960	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
961	2c0262af	bellard	gen_string_movl_A0_EDI(s);
962	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
963	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
964	14ce26e7	bellard	#ifdef TARGET_X86_64
965	14ce26e7	bellard	if (s->aflag == 2) {
966	14ce26e7	bellard	gen_op_addq_ESI_T0();
967	14ce26e7	bellard	gen_op_addq_EDI_T0();
968	14ce26e7	bellard	} else
969	14ce26e7	bellard	#endif
970	2c0262af	bellard	if (s->aflag) {
971	2c0262af	bellard	gen_op_addl_ESI_T0();
972	2c0262af	bellard	gen_op_addl_EDI_T0();
973	2c0262af	bellard	} else {
974	2c0262af	bellard	gen_op_addw_ESI_T0();
975	2c0262af	bellard	gen_op_addw_EDI_T0();
976	2c0262af	bellard	}
977	2c0262af	bellard	}
978	2c0262af	bellard
979	2c0262af	bellard	static inline void gen_update_cc_op(DisasContext *s)
980	2c0262af	bellard	{
981	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
982	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
983	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC;
984	2c0262af	bellard	}
985	2c0262af	bellard	}
986	2c0262af	bellard
987	14ce26e7	bellard	/* XXX: does not work with gdbstub "ice" single step - not a
988	14ce26e7	bellard	serious problem */
989	14ce26e7	bellard	static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
990	2c0262af	bellard	{
991	14ce26e7	bellard	int l1, l2;
992	14ce26e7	bellard
993	14ce26e7	bellard	l1 = gen_new_label();
994	14ce26e7	bellard	l2 = gen_new_label();
995	14ce26e7	bellard	gen_op_jnz_ecx[s->aflag](l1);
996	14ce26e7	bellard	gen_set_label(l2);
997	14ce26e7	bellard	gen_jmp_tb(s, next_eip, 1);
998	14ce26e7	bellard	gen_set_label(l1);
999	14ce26e7	bellard	return l2;
1000	2c0262af	bellard	}
1001	2c0262af	bellard
1002	2c0262af	bellard	static inline void gen_stos(DisasContext *s, int ot)
1003	2c0262af	bellard	{
1004	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1005	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1006	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1007	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1008	14ce26e7	bellard	#ifdef TARGET_X86_64
1009	14ce26e7	bellard	if (s->aflag == 2) {
1010	14ce26e7	bellard	gen_op_addq_EDI_T0();
1011	14ce26e7	bellard	} else
1012	14ce26e7	bellard	#endif
1013	2c0262af	bellard	if (s->aflag) {
1014	2c0262af	bellard	gen_op_addl_EDI_T0();
1015	2c0262af	bellard	} else {
1016	2c0262af	bellard	gen_op_addw_EDI_T0();
1017	2c0262af	bellard	}
1018	2c0262af	bellard	}
1019	2c0262af	bellard
1020	2c0262af	bellard	static inline void gen_lods(DisasContext *s, int ot)
1021	2c0262af	bellard	{
1022	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1023	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1024	2c0262af	bellard	gen_op_mov_reg_T0[ot][R_EAX]();
1025	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1026	14ce26e7	bellard	#ifdef TARGET_X86_64
1027	14ce26e7	bellard	if (s->aflag == 2) {
1028	14ce26e7	bellard	gen_op_addq_ESI_T0();
1029	14ce26e7	bellard	} else
1030	14ce26e7	bellard	#endif
1031	2c0262af	bellard	if (s->aflag) {
1032	2c0262af	bellard	gen_op_addl_ESI_T0();
1033	2c0262af	bellard	} else {
1034	2c0262af	bellard	gen_op_addw_ESI_T0();
1035	2c0262af	bellard	}
1036	2c0262af	bellard	}
1037	2c0262af	bellard
1038	2c0262af	bellard	static inline void gen_scas(DisasContext *s, int ot)
1039	2c0262af	bellard	{
1040	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1041	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1042	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
1043	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1044	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1045	14ce26e7	bellard	#ifdef TARGET_X86_64
1046	14ce26e7	bellard	if (s->aflag == 2) {
1047	14ce26e7	bellard	gen_op_addq_EDI_T0();
1048	14ce26e7	bellard	} else
1049	14ce26e7	bellard	#endif
1050	2c0262af	bellard	if (s->aflag) {
1051	2c0262af	bellard	gen_op_addl_EDI_T0();
1052	2c0262af	bellard	} else {
1053	2c0262af	bellard	gen_op_addw_EDI_T0();
1054	2c0262af	bellard	}
1055	2c0262af	bellard	}
1056	2c0262af	bellard
1057	2c0262af	bellard	static inline void gen_cmps(DisasContext *s, int ot)
1058	2c0262af	bellard	{
1059	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1060	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1061	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1062	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
1063	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1064	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1065	14ce26e7	bellard	#ifdef TARGET_X86_64
1066	14ce26e7	bellard	if (s->aflag == 2) {
1067	14ce26e7	bellard	gen_op_addq_ESI_T0();
1068	14ce26e7	bellard	gen_op_addq_EDI_T0();
1069	14ce26e7	bellard	} else
1070	14ce26e7	bellard	#endif
1071	2c0262af	bellard	if (s->aflag) {
1072	2c0262af	bellard	gen_op_addl_ESI_T0();
1073	2c0262af	bellard	gen_op_addl_EDI_T0();
1074	2c0262af	bellard	} else {
1075	2c0262af	bellard	gen_op_addw_ESI_T0();
1076	2c0262af	bellard	gen_op_addw_EDI_T0();
1077	2c0262af	bellard	}
1078	2c0262af	bellard	}
1079	2c0262af	bellard
1080	2c0262af	bellard	static inline void gen_ins(DisasContext *s, int ot)
1081	2c0262af	bellard	{
1082	2c0262af	bellard	gen_string_movl_A0_EDI(s);
1083	9772c73b	bellard	gen_op_movl_T0_0();
1084	9772c73b	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1085	9772c73b	bellard	gen_op_in_DX_T0[ot]();
1086	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1087	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1088	14ce26e7	bellard	#ifdef TARGET_X86_64
1089	14ce26e7	bellard	if (s->aflag == 2) {
1090	14ce26e7	bellard	gen_op_addq_EDI_T0();
1091	14ce26e7	bellard	} else
1092	14ce26e7	bellard	#endif
1093	2c0262af	bellard	if (s->aflag) {
1094	2c0262af	bellard	gen_op_addl_EDI_T0();
1095	2c0262af	bellard	} else {
1096	2c0262af	bellard	gen_op_addw_EDI_T0();
1097	2c0262af	bellard	}
1098	2c0262af	bellard	}
1099	2c0262af	bellard
1100	2c0262af	bellard	static inline void gen_outs(DisasContext *s, int ot)
1101	2c0262af	bellard	{
1102	2c0262af	bellard	gen_string_movl_A0_ESI(s);
1103	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1104	2c0262af	bellard	gen_op_out_DX_T0[ot]();
1105	2c0262af	bellard	gen_op_movl_T0_Dshift[ot]();
1106	14ce26e7	bellard	#ifdef TARGET_X86_64
1107	14ce26e7	bellard	if (s->aflag == 2) {
1108	14ce26e7	bellard	gen_op_addq_ESI_T0();
1109	14ce26e7	bellard	} else
1110	14ce26e7	bellard	#endif
1111	2c0262af	bellard	if (s->aflag) {
1112	2c0262af	bellard	gen_op_addl_ESI_T0();
1113	2c0262af	bellard	} else {
1114	2c0262af	bellard	gen_op_addw_ESI_T0();
1115	2c0262af	bellard	}
1116	2c0262af	bellard	}
1117	2c0262af	bellard
1118	2c0262af	bellard	/* same method as Valgrind : we generate jumps to current or next
1119	2c0262af	bellard	instruction */
1120	2c0262af	bellard	#define GEN_REPZ(op) \
1121	2c0262af	bellard	static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1122	14ce26e7	bellard	target_ulong cur_eip, target_ulong next_eip) \
1123	2c0262af	bellard	{ \
1124	14ce26e7	bellard	int l2;\
1125	2c0262af	bellard	gen_update_cc_op(s); \
1126	14ce26e7	bellard	l2 = gen_jz_ecx_string(s, next_eip); \
1127	2c0262af	bellard	gen_ ## op(s, ot); \
1128	2c0262af	bellard	gen_op_dec_ECX[s->aflag](); \
1129	2c0262af	bellard	/* a loop would cause two single step exceptions if ECX = 1 \
1130	2c0262af	bellard	before rep string_insn */ \
1131	2c0262af	bellard	if (!s->jmp_opt) \
1132	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l2); \
1133	2c0262af	bellard	gen_jmp(s, cur_eip); \
1134	2c0262af	bellard	}
1135	2c0262af	bellard
1136	2c0262af	bellard	#define GEN_REPZ2(op) \
1137	2c0262af	bellard	static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1138	14ce26e7	bellard	target_ulong cur_eip, \
1139	14ce26e7	bellard	target_ulong next_eip, \
1140	2c0262af	bellard	int nz) \
1141	2c0262af	bellard	{ \
1142	14ce26e7	bellard	int l2;\
1143	2c0262af	bellard	gen_update_cc_op(s); \
1144	14ce26e7	bellard	l2 = gen_jz_ecx_string(s, next_eip); \
1145	2c0262af	bellard	gen_ ## op(s, ot); \
1146	2c0262af	bellard	gen_op_dec_ECX[s->aflag](); \
1147	2c0262af	bellard	gen_op_set_cc_op(CC_OP_SUBB + ot); \
1148	14ce26e7	bellard	gen_op_string_jnz_sub[nz][ot](l2);\
1149	2c0262af	bellard	if (!s->jmp_opt) \
1150	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l2); \
1151	2c0262af	bellard	gen_jmp(s, cur_eip); \
1152	2c0262af	bellard	}
1153	2c0262af	bellard
1154	2c0262af	bellard	GEN_REPZ(movs)
1155	2c0262af	bellard	GEN_REPZ(stos)
1156	2c0262af	bellard	GEN_REPZ(lods)
1157	2c0262af	bellard	GEN_REPZ(ins)
1158	2c0262af	bellard	GEN_REPZ(outs)
1159	2c0262af	bellard	GEN_REPZ2(scas)
1160	2c0262af	bellard	GEN_REPZ2(cmps)
1161	2c0262af	bellard
1162	2c0262af	bellard	enum {
1163	2c0262af	bellard	JCC_O,
1164	2c0262af	bellard	JCC_B,
1165	2c0262af	bellard	JCC_Z,
1166	2c0262af	bellard	JCC_BE,
1167	2c0262af	bellard	JCC_S,
1168	2c0262af	bellard	JCC_P,
1169	2c0262af	bellard	JCC_L,
1170	2c0262af	bellard	JCC_LE,
1171	2c0262af	bellard	};
1172	2c0262af	bellard
1173	14ce26e7	bellard	static GenOpFunc1 *gen_jcc_sub[4][8] = {
1174	2c0262af	bellard	[OT_BYTE] = {
1175	2c0262af	bellard	NULL,
1176	2c0262af	bellard	gen_op_jb_subb,
1177	2c0262af	bellard	gen_op_jz_subb,
1178	2c0262af	bellard	gen_op_jbe_subb,
1179	2c0262af	bellard	gen_op_js_subb,
1180	2c0262af	bellard	NULL,
1181	2c0262af	bellard	gen_op_jl_subb,
1182	2c0262af	bellard	gen_op_jle_subb,
1183	2c0262af	bellard	},
1184	2c0262af	bellard	[OT_WORD] = {
1185	2c0262af	bellard	NULL,
1186	2c0262af	bellard	gen_op_jb_subw,
1187	2c0262af	bellard	gen_op_jz_subw,
1188	2c0262af	bellard	gen_op_jbe_subw,
1189	2c0262af	bellard	gen_op_js_subw,
1190	2c0262af	bellard	NULL,
1191	2c0262af	bellard	gen_op_jl_subw,
1192	2c0262af	bellard	gen_op_jle_subw,
1193	2c0262af	bellard	},
1194	2c0262af	bellard	[OT_LONG] = {
1195	2c0262af	bellard	NULL,
1196	2c0262af	bellard	gen_op_jb_subl,
1197	2c0262af	bellard	gen_op_jz_subl,
1198	2c0262af	bellard	gen_op_jbe_subl,
1199	2c0262af	bellard	gen_op_js_subl,
1200	2c0262af	bellard	NULL,
1201	2c0262af	bellard	gen_op_jl_subl,
1202	2c0262af	bellard	gen_op_jle_subl,
1203	2c0262af	bellard	},
1204	14ce26e7	bellard	#ifdef TARGET_X86_64
1205	14ce26e7	bellard	[OT_QUAD] = {
1206	14ce26e7	bellard	NULL,
1207	14ce26e7	bellard	BUGGY_64(gen_op_jb_subq),
1208	14ce26e7	bellard	gen_op_jz_subq,
1209	14ce26e7	bellard	BUGGY_64(gen_op_jbe_subq),
1210	14ce26e7	bellard	gen_op_js_subq,
1211	14ce26e7	bellard	NULL,
1212	14ce26e7	bellard	BUGGY_64(gen_op_jl_subq),
1213	14ce26e7	bellard	BUGGY_64(gen_op_jle_subq),
1214	14ce26e7	bellard	},
1215	14ce26e7	bellard	#endif
1216	2c0262af	bellard	};
1217	14ce26e7	bellard	static GenOpFunc1 *gen_op_loop[3][4] = {
1218	2c0262af	bellard	[0] = {
1219	2c0262af	bellard	gen_op_loopnzw,
1220	2c0262af	bellard	gen_op_loopzw,
1221	14ce26e7	bellard	gen_op_jnz_ecxw,
1222	2c0262af	bellard	},
1223	2c0262af	bellard	[1] = {
1224	2c0262af	bellard	gen_op_loopnzl,
1225	2c0262af	bellard	gen_op_loopzl,
1226	14ce26e7	bellard	gen_op_jnz_ecxl,
1227	14ce26e7	bellard	},
1228	14ce26e7	bellard	#ifdef TARGET_X86_64
1229	14ce26e7	bellard	[2] = {
1230	14ce26e7	bellard	gen_op_loopnzq,
1231	14ce26e7	bellard	gen_op_loopzq,
1232	14ce26e7	bellard	gen_op_jnz_ecxq,
1233	2c0262af	bellard	},
1234	14ce26e7	bellard	#endif
1235	2c0262af	bellard	};
1236	2c0262af	bellard
1237	2c0262af	bellard	static GenOpFunc *gen_setcc_slow[8] = {
1238	2c0262af	bellard	gen_op_seto_T0_cc,
1239	2c0262af	bellard	gen_op_setb_T0_cc,
1240	2c0262af	bellard	gen_op_setz_T0_cc,
1241	2c0262af	bellard	gen_op_setbe_T0_cc,
1242	2c0262af	bellard	gen_op_sets_T0_cc,
1243	2c0262af	bellard	gen_op_setp_T0_cc,
1244	2c0262af	bellard	gen_op_setl_T0_cc,
1245	2c0262af	bellard	gen_op_setle_T0_cc,
1246	2c0262af	bellard	};
1247	2c0262af	bellard
1248	14ce26e7	bellard	static GenOpFunc *gen_setcc_sub[4][8] = {
1249	2c0262af	bellard	[OT_BYTE] = {
1250	2c0262af	bellard	NULL,
1251	2c0262af	bellard	gen_op_setb_T0_subb,
1252	2c0262af	bellard	gen_op_setz_T0_subb,
1253	2c0262af	bellard	gen_op_setbe_T0_subb,
1254	2c0262af	bellard	gen_op_sets_T0_subb,
1255	2c0262af	bellard	NULL,
1256	2c0262af	bellard	gen_op_setl_T0_subb,
1257	2c0262af	bellard	gen_op_setle_T0_subb,
1258	2c0262af	bellard	},
1259	2c0262af	bellard	[OT_WORD] = {
1260	2c0262af	bellard	NULL,
1261	2c0262af	bellard	gen_op_setb_T0_subw,
1262	2c0262af	bellard	gen_op_setz_T0_subw,
1263	2c0262af	bellard	gen_op_setbe_T0_subw,
1264	2c0262af	bellard	gen_op_sets_T0_subw,
1265	2c0262af	bellard	NULL,
1266	2c0262af	bellard	gen_op_setl_T0_subw,
1267	2c0262af	bellard	gen_op_setle_T0_subw,
1268	2c0262af	bellard	},
1269	2c0262af	bellard	[OT_LONG] = {
1270	2c0262af	bellard	NULL,
1271	2c0262af	bellard	gen_op_setb_T0_subl,
1272	2c0262af	bellard	gen_op_setz_T0_subl,
1273	2c0262af	bellard	gen_op_setbe_T0_subl,
1274	2c0262af	bellard	gen_op_sets_T0_subl,
1275	2c0262af	bellard	NULL,
1276	2c0262af	bellard	gen_op_setl_T0_subl,
1277	2c0262af	bellard	gen_op_setle_T0_subl,
1278	2c0262af	bellard	},
1279	14ce26e7	bellard	#ifdef TARGET_X86_64
1280	14ce26e7	bellard	[OT_QUAD] = {
1281	14ce26e7	bellard	NULL,
1282	14ce26e7	bellard	gen_op_setb_T0_subq,
1283	14ce26e7	bellard	gen_op_setz_T0_subq,
1284	14ce26e7	bellard	gen_op_setbe_T0_subq,
1285	14ce26e7	bellard	gen_op_sets_T0_subq,
1286	14ce26e7	bellard	NULL,
1287	14ce26e7	bellard	gen_op_setl_T0_subq,
1288	14ce26e7	bellard	gen_op_setle_T0_subq,
1289	14ce26e7	bellard	},
1290	14ce26e7	bellard	#endif
1291	2c0262af	bellard	};
1292	2c0262af	bellard
1293	2c0262af	bellard	static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1294	2c0262af	bellard	gen_op_fadd_ST0_FT0,
1295	2c0262af	bellard	gen_op_fmul_ST0_FT0,
1296	2c0262af	bellard	gen_op_fcom_ST0_FT0,
1297	2c0262af	bellard	gen_op_fcom_ST0_FT0,
1298	2c0262af	bellard	gen_op_fsub_ST0_FT0,
1299	2c0262af	bellard	gen_op_fsubr_ST0_FT0,
1300	2c0262af	bellard	gen_op_fdiv_ST0_FT0,
1301	2c0262af	bellard	gen_op_fdivr_ST0_FT0,
1302	2c0262af	bellard	};
1303	2c0262af	bellard
1304	2c0262af	bellard	/* NOTE the exception in "r" op ordering */
1305	2c0262af	bellard	static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1306	2c0262af	bellard	gen_op_fadd_STN_ST0,
1307	2c0262af	bellard	gen_op_fmul_STN_ST0,
1308	2c0262af	bellard	NULL,
1309	2c0262af	bellard	NULL,
1310	2c0262af	bellard	gen_op_fsubr_STN_ST0,
1311	2c0262af	bellard	gen_op_fsub_STN_ST0,
1312	2c0262af	bellard	gen_op_fdivr_STN_ST0,
1313	2c0262af	bellard	gen_op_fdiv_STN_ST0,
1314	2c0262af	bellard	};
1315	2c0262af	bellard
1316	2c0262af	bellard	/* if d == OR_TMP0, it means memory operand (address in A0) */
1317	2c0262af	bellard	static void gen_op(DisasContext *s1, int op, int ot, int d)
1318	2c0262af	bellard	{
1319	2c0262af	bellard	GenOpFunc *gen_update_cc;
1320	2c0262af	bellard
1321	2c0262af	bellard	if (d != OR_TMP0) {
1322	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1323	2c0262af	bellard	} else {
1324	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1325	2c0262af	bellard	}
1326	2c0262af	bellard	switch(op) {
1327	2c0262af	bellard	case OP_ADCL:
1328	2c0262af	bellard	case OP_SBBL:
1329	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1330	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1331	2c0262af	bellard	if (d != OR_TMP0) {
1332	2c0262af	bellard	gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1333	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1334	2c0262af	bellard	} else {
1335	4f31916f	bellard	gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
1336	2c0262af	bellard	}
1337	2c0262af	bellard	s1->cc_op = CC_OP_DYNAMIC;
1338	2c0262af	bellard	goto the_end;
1339	2c0262af	bellard	case OP_ADDL:
1340	2c0262af	bellard	gen_op_addl_T0_T1();
1341	2c0262af	bellard	s1->cc_op = CC_OP_ADDB + ot;
1342	2c0262af	bellard	gen_update_cc = gen_op_update2_cc;
1343	2c0262af	bellard	break;
1344	2c0262af	bellard	case OP_SUBL:
1345	2c0262af	bellard	gen_op_subl_T0_T1();
1346	2c0262af	bellard	s1->cc_op = CC_OP_SUBB + ot;
1347	2c0262af	bellard	gen_update_cc = gen_op_update2_cc;
1348	2c0262af	bellard	break;
1349	2c0262af	bellard	default:
1350	2c0262af	bellard	case OP_ANDL:
1351	2c0262af	bellard	case OP_ORL:
1352	2c0262af	bellard	case OP_XORL:
1353	2c0262af	bellard	gen_op_arith_T0_T1_cc[op]();
1354	2c0262af	bellard	s1->cc_op = CC_OP_LOGICB + ot;
1355	2c0262af	bellard	gen_update_cc = gen_op_update1_cc;
1356	2c0262af	bellard	break;
1357	2c0262af	bellard	case OP_CMPL:
1358	2c0262af	bellard	gen_op_cmpl_T0_T1_cc();
1359	2c0262af	bellard	s1->cc_op = CC_OP_SUBB + ot;
1360	2c0262af	bellard	gen_update_cc = NULL;
1361	2c0262af	bellard	break;
1362	2c0262af	bellard	}
1363	2c0262af	bellard	if (op != OP_CMPL) {
1364	2c0262af	bellard	if (d != OR_TMP0)
1365	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1366	2c0262af	bellard	else
1367	2c0262af	bellard	gen_op_st_T0_A0[ot + s1->mem_index]();
1368	2c0262af	bellard	}
1369	2c0262af	bellard	/* the flags update must happen after the memory write (precise
1370	2c0262af	bellard	exception support) */
1371	2c0262af	bellard	if (gen_update_cc)
1372	2c0262af	bellard	gen_update_cc();
1373	2c0262af	bellard	the_end: ;
1374	2c0262af	bellard	}
1375	2c0262af	bellard
1376	2c0262af	bellard	/* if d == OR_TMP0, it means memory operand (address in A0) */
1377	2c0262af	bellard	static void gen_inc(DisasContext *s1, int ot, int d, int c)
1378	2c0262af	bellard	{
1379	2c0262af	bellard	if (d != OR_TMP0)
1380	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1381	2c0262af	bellard	else
1382	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1383	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1384	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1385	2c0262af	bellard	if (c > 0) {
1386	2c0262af	bellard	gen_op_incl_T0();
1387	2c0262af	bellard	s1->cc_op = CC_OP_INCB + ot;
1388	2c0262af	bellard	} else {
1389	2c0262af	bellard	gen_op_decl_T0();
1390	2c0262af	bellard	s1->cc_op = CC_OP_DECB + ot;
1391	2c0262af	bellard	}
1392	2c0262af	bellard	if (d != OR_TMP0)
1393	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1394	2c0262af	bellard	else
1395	2c0262af	bellard	gen_op_st_T0_A0[ot + s1->mem_index]();
1396	2c0262af	bellard	gen_op_update_inc_cc();
1397	2c0262af	bellard	}
1398	2c0262af	bellard
1399	2c0262af	bellard	static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1400	2c0262af	bellard	{
1401	2c0262af	bellard	if (d != OR_TMP0)
1402	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][d]();
1403	2c0262af	bellard	else
1404	2c0262af	bellard	gen_op_ld_T0_A0[ot + s1->mem_index]();
1405	2c0262af	bellard	if (s != OR_TMP1)
1406	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][s]();
1407	2c0262af	bellard	/* for zero counts, flags are not updated, so must do it dynamically */
1408	2c0262af	bellard	if (s1->cc_op != CC_OP_DYNAMIC)
1409	2c0262af	bellard	gen_op_set_cc_op(s1->cc_op);
1410	2c0262af	bellard
1411	2c0262af	bellard	if (d != OR_TMP0)
1412	2c0262af	bellard	gen_op_shift_T0_T1_cc[ot][op]();
1413	2c0262af	bellard	else
1414	4f31916f	bellard	gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
1415	2c0262af	bellard	if (d != OR_TMP0)
1416	2c0262af	bellard	gen_op_mov_reg_T0[ot][d]();
1417	2c0262af	bellard	s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1418	2c0262af	bellard	}
1419	2c0262af	bellard
1420	2c0262af	bellard	static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1421	2c0262af	bellard	{
1422	2c0262af	bellard	/* currently not optimized */
1423	2c0262af	bellard	gen_op_movl_T1_im(c);
1424	2c0262af	bellard	gen_shift(s1, op, ot, d, OR_TMP1);
1425	2c0262af	bellard	}
1426	2c0262af	bellard
1427	2c0262af	bellard	static void gen_lea_modrm(DisasContext s, int modrm, int reg_ptr, int *offset_ptr)
1428	2c0262af	bellard	{
1429	14ce26e7	bellard	target_long disp;
1430	2c0262af	bellard	int havesib;
1431	14ce26e7	bellard	int base;
1432	2c0262af	bellard	int index;
1433	2c0262af	bellard	int scale;
1434	2c0262af	bellard	int opreg;
1435	2c0262af	bellard	int mod, rm, code, override, must_add_seg;
1436	2c0262af	bellard
1437	2c0262af	bellard	override = s->override;
1438	2c0262af	bellard	must_add_seg = s->addseg;
1439	2c0262af	bellard	if (override >= 0)
1440	2c0262af	bellard	must_add_seg = 1;
1441	2c0262af	bellard	mod = (modrm >> 6) & 3;
1442	2c0262af	bellard	rm = modrm & 7;
1443	2c0262af	bellard
1444	2c0262af	bellard	if (s->aflag) {
1445	2c0262af	bellard
1446	2c0262af	bellard	havesib = 0;
1447	2c0262af	bellard	base = rm;
1448	2c0262af	bellard	index = 0;
1449	2c0262af	bellard	scale = 0;
1450	2c0262af	bellard
1451	2c0262af	bellard	if (base == 4) {
1452	2c0262af	bellard	havesib = 1;
1453	61382a50	bellard	code = ldub_code(s->pc++);
1454	2c0262af	bellard	scale = (code >> 6) & 3;
1455	14ce26e7	bellard	index = ((code >> 3) & 7) \| REX_X(s);
1456	14ce26e7	bellard	base = (code & 7);
1457	2c0262af	bellard	}
1458	14ce26e7	bellard	base \|= REX_B(s);
1459	2c0262af	bellard
1460	2c0262af	bellard	switch (mod) {
1461	2c0262af	bellard	case 0:
1462	14ce26e7	bellard	if ((base & 7) == 5) {
1463	2c0262af	bellard	base = -1;
1464	14ce26e7	bellard	disp = (int32_t)ldl_code(s->pc);
1465	2c0262af	bellard	s->pc += 4;
1466	14ce26e7	bellard	if (CODE64(s) && !havesib) {
1467	14ce26e7	bellard	disp += s->pc + s->rip_offset;
1468	14ce26e7	bellard	}
1469	2c0262af	bellard	} else {
1470	2c0262af	bellard	disp = 0;
1471	2c0262af	bellard	}
1472	2c0262af	bellard	break;
1473	2c0262af	bellard	case 1:
1474	61382a50	bellard	disp = (int8_t)ldub_code(s->pc++);
1475	2c0262af	bellard	break;
1476	2c0262af	bellard	default:
1477	2c0262af	bellard	case 2:
1478	61382a50	bellard	disp = ldl_code(s->pc);
1479	2c0262af	bellard	s->pc += 4;
1480	2c0262af	bellard	break;
1481	2c0262af	bellard	}
1482	2c0262af	bellard
1483	2c0262af	bellard	if (base >= 0) {
1484	2c0262af	bellard	/* for correct popl handling with esp */
1485	2c0262af	bellard	if (base == 4 && s->popl_esp_hack)
1486	2c0262af	bellard	disp += s->popl_esp_hack;
1487	14ce26e7	bellard	#ifdef TARGET_X86_64
1488	14ce26e7	bellard	if (s->aflag == 2) {
1489	14ce26e7	bellard	gen_op_movq_A0_reg[base]();
1490	14ce26e7	bellard	if (disp != 0) {
1491	14ce26e7	bellard	if ((int32_t)disp == disp)
1492	14ce26e7	bellard	gen_op_addq_A0_im(disp);
1493	14ce26e7	bellard	else
1494	14ce26e7	bellard	gen_op_addq_A0_im64(disp >> 32, disp);
1495	14ce26e7	bellard	}
1496	14ce26e7	bellard	} else
1497	14ce26e7	bellard	#endif
1498	14ce26e7	bellard	{
1499	14ce26e7	bellard	gen_op_movl_A0_reg[base]();
1500	14ce26e7	bellard	if (disp != 0)
1501	14ce26e7	bellard	gen_op_addl_A0_im(disp);
1502	14ce26e7	bellard	}
1503	2c0262af	bellard	} else {
1504	14ce26e7	bellard	#ifdef TARGET_X86_64
1505	14ce26e7	bellard	if (s->aflag == 2) {
1506	14ce26e7	bellard	if ((int32_t)disp == disp)
1507	14ce26e7	bellard	gen_op_movq_A0_im(disp);
1508	14ce26e7	bellard	else
1509	14ce26e7	bellard	gen_op_movq_A0_im64(disp >> 32, disp);
1510	14ce26e7	bellard	} else
1511	14ce26e7	bellard	#endif
1512	14ce26e7	bellard	{
1513	14ce26e7	bellard	gen_op_movl_A0_im(disp);
1514	14ce26e7	bellard	}
1515	2c0262af	bellard	}
1516	2c0262af	bellard	/* XXX: index == 4 is always invalid */
1517	2c0262af	bellard	if (havesib && (index != 4 \|\| scale != 0)) {
1518	14ce26e7	bellard	#ifdef TARGET_X86_64
1519	14ce26e7	bellard	if (s->aflag == 2) {
1520	14ce26e7	bellard	gen_op_addq_A0_reg_sN[scale][index]();
1521	14ce26e7	bellard	} else
1522	14ce26e7	bellard	#endif
1523	14ce26e7	bellard	{
1524	14ce26e7	bellard	gen_op_addl_A0_reg_sN[scale][index]();
1525	14ce26e7	bellard	}
1526	2c0262af	bellard	}
1527	2c0262af	bellard	if (must_add_seg) {
1528	2c0262af	bellard	if (override < 0) {
1529	2c0262af	bellard	if (base == R_EBP \|\| base == R_ESP)
1530	2c0262af	bellard	override = R_SS;
1531	2c0262af	bellard	else
1532	2c0262af	bellard	override = R_DS;
1533	2c0262af	bellard	}
1534	14ce26e7	bellard	#ifdef TARGET_X86_64
1535	14ce26e7	bellard	if (s->aflag == 2) {
1536	14ce26e7	bellard	gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1537	14ce26e7	bellard	} else
1538	14ce26e7	bellard	#endif
1539	14ce26e7	bellard	{
1540	14ce26e7	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1541	14ce26e7	bellard	}
1542	2c0262af	bellard	}
1543	2c0262af	bellard	} else {
1544	2c0262af	bellard	switch (mod) {
1545	2c0262af	bellard	case 0:
1546	2c0262af	bellard	if (rm == 6) {
1547	61382a50	bellard	disp = lduw_code(s->pc);
1548	2c0262af	bellard	s->pc += 2;
1549	2c0262af	bellard	gen_op_movl_A0_im(disp);
1550	2c0262af	bellard	rm = 0; /* avoid SS override */
1551	2c0262af	bellard	goto no_rm;
1552	2c0262af	bellard	} else {
1553	2c0262af	bellard	disp = 0;
1554	2c0262af	bellard	}
1555	2c0262af	bellard	break;
1556	2c0262af	bellard	case 1:
1557	61382a50	bellard	disp = (int8_t)ldub_code(s->pc++);
1558	2c0262af	bellard	break;
1559	2c0262af	bellard	default:
1560	2c0262af	bellard	case 2:
1561	61382a50	bellard	disp = lduw_code(s->pc);
1562	2c0262af	bellard	s->pc += 2;
1563	2c0262af	bellard	break;
1564	2c0262af	bellard	}
1565	2c0262af	bellard	switch(rm) {
1566	2c0262af	bellard	case 0:
1567	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1568	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
1569	2c0262af	bellard	break;
1570	2c0262af	bellard	case 1:
1571	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1572	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
1573	2c0262af	bellard	break;
1574	2c0262af	bellard	case 2:
1575	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1576	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_ESI]();
1577	2c0262af	bellard	break;
1578	2c0262af	bellard	case 3:
1579	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1580	2c0262af	bellard	gen_op_addl_A0_reg_sN[0][R_EDI]();
1581	2c0262af	bellard	break;
1582	2c0262af	bellard	case 4:
1583	2c0262af	bellard	gen_op_movl_A0_reg[R_ESI]();
1584	2c0262af	bellard	break;
1585	2c0262af	bellard	case 5:
1586	2c0262af	bellard	gen_op_movl_A0_reg[R_EDI]();
1587	2c0262af	bellard	break;
1588	2c0262af	bellard	case 6:
1589	2c0262af	bellard	gen_op_movl_A0_reg[R_EBP]();
1590	2c0262af	bellard	break;
1591	2c0262af	bellard	default:
1592	2c0262af	bellard	case 7:
1593	2c0262af	bellard	gen_op_movl_A0_reg[R_EBX]();
1594	2c0262af	bellard	break;
1595	2c0262af	bellard	}
1596	2c0262af	bellard	if (disp != 0)
1597	2c0262af	bellard	gen_op_addl_A0_im(disp);
1598	2c0262af	bellard	gen_op_andl_A0_ffff();
1599	2c0262af	bellard	no_rm:
1600	2c0262af	bellard	if (must_add_seg) {
1601	2c0262af	bellard	if (override < 0) {
1602	2c0262af	bellard	if (rm == 2 \|\| rm == 3 \|\| rm == 6)
1603	2c0262af	bellard	override = R_SS;
1604	2c0262af	bellard	else
1605	2c0262af	bellard	override = R_DS;
1606	2c0262af	bellard	}
1607	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1608	2c0262af	bellard	}
1609	2c0262af	bellard	}
1610	2c0262af	bellard
1611	2c0262af	bellard	opreg = OR_A0;
1612	2c0262af	bellard	disp = 0;
1613	2c0262af	bellard	*reg_ptr = opreg;
1614	2c0262af	bellard	*offset_ptr = disp;
1615	2c0262af	bellard	}
1616	2c0262af	bellard
1617	664e0f19	bellard	/* used for LEA and MOV AX, mem */
1618	664e0f19	bellard	static void gen_add_A0_ds_seg(DisasContext *s)
1619	664e0f19	bellard	{
1620	664e0f19	bellard	int override, must_add_seg;
1621	664e0f19	bellard	must_add_seg = s->addseg;
1622	664e0f19	bellard	override = R_DS;
1623	664e0f19	bellard	if (s->override >= 0) {
1624	664e0f19	bellard	override = s->override;
1625	664e0f19	bellard	must_add_seg = 1;
1626	664e0f19	bellard	} else {
1627	664e0f19	bellard	override = R_DS;
1628	664e0f19	bellard	}
1629	664e0f19	bellard	if (must_add_seg) {
1630	8f091a59	bellard	#ifdef TARGET_X86_64
1631	8f091a59	bellard	if (CODE64(s)) {
1632	8f091a59	bellard	gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1633	8f091a59	bellard	} else
1634	8f091a59	bellard	#endif
1635	8f091a59	bellard	{
1636	8f091a59	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1637	8f091a59	bellard	}
1638	664e0f19	bellard	}
1639	664e0f19	bellard	}
1640	664e0f19	bellard
1641	2c0262af	bellard	/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1642	2c0262af	bellard	OR_TMP0 */
1643	2c0262af	bellard	static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1644	2c0262af	bellard	{
1645	2c0262af	bellard	int mod, rm, opreg, disp;
1646	2c0262af	bellard
1647	2c0262af	bellard	mod = (modrm >> 6) & 3;
1648	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
1649	2c0262af	bellard	if (mod == 3) {
1650	2c0262af	bellard	if (is_store) {
1651	2c0262af	bellard	if (reg != OR_TMP0)
1652	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
1653	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
1654	2c0262af	bellard	} else {
1655	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
1656	2c0262af	bellard	if (reg != OR_TMP0)
1657	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
1658	2c0262af	bellard	}
1659	2c0262af	bellard	} else {
1660	2c0262af	bellard	gen_lea_modrm(s, modrm, &opreg, &disp);
1661	2c0262af	bellard	if (is_store) {
1662	2c0262af	bellard	if (reg != OR_TMP0)
1663	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
1664	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
1665	2c0262af	bellard	} else {
1666	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
1667	2c0262af	bellard	if (reg != OR_TMP0)
1668	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
1669	2c0262af	bellard	}
1670	2c0262af	bellard	}
1671	2c0262af	bellard	}
1672	2c0262af	bellard
1673	2c0262af	bellard	static inline uint32_t insn_get(DisasContext *s, int ot)
1674	2c0262af	bellard	{
1675	2c0262af	bellard	uint32_t ret;
1676	2c0262af	bellard
1677	2c0262af	bellard	switch(ot) {
1678	2c0262af	bellard	case OT_BYTE:
1679	61382a50	bellard	ret = ldub_code(s->pc);
1680	2c0262af	bellard	s->pc++;
1681	2c0262af	bellard	break;
1682	2c0262af	bellard	case OT_WORD:
1683	61382a50	bellard	ret = lduw_code(s->pc);
1684	2c0262af	bellard	s->pc += 2;
1685	2c0262af	bellard	break;
1686	2c0262af	bellard	default:
1687	2c0262af	bellard	case OT_LONG:
1688	61382a50	bellard	ret = ldl_code(s->pc);
1689	2c0262af	bellard	s->pc += 4;
1690	2c0262af	bellard	break;
1691	2c0262af	bellard	}
1692	2c0262af	bellard	return ret;
1693	2c0262af	bellard	}
1694	2c0262af	bellard
1695	14ce26e7	bellard	static inline int insn_const_size(unsigned int ot)
1696	14ce26e7	bellard	{
1697	14ce26e7	bellard	if (ot <= OT_LONG)
1698	14ce26e7	bellard	return 1 << ot;
1699	14ce26e7	bellard	else
1700	14ce26e7	bellard	return 4;
1701	14ce26e7	bellard	}
1702	14ce26e7	bellard
1703	6e256c93	bellard	static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
1704	6e256c93	bellard	{
1705	6e256c93	bellard	TranslationBlock *tb;
1706	6e256c93	bellard	target_ulong pc;
1707	6e256c93	bellard
1708	6e256c93	bellard	pc = s->cs_base + eip;
1709	6e256c93	bellard	tb = s->tb;
1710	6e256c93	bellard	/* NOTE: we handle the case where the TB spans two pages here */
1711	6e256c93	bellard	if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) \|\|
1712	6e256c93	bellard	(pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
1713	6e256c93	bellard	/* jump to same page: we can use a direct jump */
1714	6e256c93	bellard	if (tb_num == 0)
1715	6e256c93	bellard	gen_op_goto_tb0(TBPARAM(tb));
1716	6e256c93	bellard	else
1717	6e256c93	bellard	gen_op_goto_tb1(TBPARAM(tb));
1718	6e256c93	bellard	gen_jmp_im(eip);
1719	6e256c93	bellard	gen_op_movl_T0_im((long)tb + tb_num);
1720	6e256c93	bellard	gen_op_exit_tb();
1721	6e256c93	bellard	} else {
1722	6e256c93	bellard	/* jump to another page: currently not optimized */
1723	6e256c93	bellard	gen_jmp_im(eip);
1724	6e256c93	bellard	gen_eob(s);
1725	6e256c93	bellard	}
1726	6e256c93	bellard	}
1727	6e256c93	bellard
1728	14ce26e7	bellard	static inline void gen_jcc(DisasContext *s, int b,
1729	14ce26e7	bellard	target_ulong val, target_ulong next_eip)
1730	2c0262af	bellard	{
1731	2c0262af	bellard	TranslationBlock *tb;
1732	2c0262af	bellard	int inv, jcc_op;
1733	14ce26e7	bellard	GenOpFunc1 *func;
1734	14ce26e7	bellard	target_ulong tmp;
1735	14ce26e7	bellard	int l1, l2;
1736	2c0262af	bellard
1737	2c0262af	bellard	inv = b & 1;
1738	2c0262af	bellard	jcc_op = (b >> 1) & 7;
1739	2c0262af	bellard
1740	2c0262af	bellard	if (s->jmp_opt) {
1741	2c0262af	bellard	switch(s->cc_op) {
1742	2c0262af	bellard	/* we optimize the cmp/jcc case */
1743	2c0262af	bellard	case CC_OP_SUBB:
1744	2c0262af	bellard	case CC_OP_SUBW:
1745	2c0262af	bellard	case CC_OP_SUBL:
1746	14ce26e7	bellard	case CC_OP_SUBQ:
1747	2c0262af	bellard	func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1748	2c0262af	bellard	break;
1749	2c0262af	bellard
1750	2c0262af	bellard	/* some jumps are easy to compute */
1751	2c0262af	bellard	case CC_OP_ADDB:
1752	2c0262af	bellard	case CC_OP_ADDW:
1753	2c0262af	bellard	case CC_OP_ADDL:
1754	14ce26e7	bellard	case CC_OP_ADDQ:
1755	14ce26e7	bellard
1756	2c0262af	bellard	case CC_OP_ADCB:
1757	2c0262af	bellard	case CC_OP_ADCW:
1758	2c0262af	bellard	case CC_OP_ADCL:
1759	14ce26e7	bellard	case CC_OP_ADCQ:
1760	14ce26e7	bellard
1761	2c0262af	bellard	case CC_OP_SBBB:
1762	2c0262af	bellard	case CC_OP_SBBW:
1763	2c0262af	bellard	case CC_OP_SBBL:
1764	14ce26e7	bellard	case CC_OP_SBBQ:
1765	14ce26e7	bellard
1766	2c0262af	bellard	case CC_OP_LOGICB:
1767	2c0262af	bellard	case CC_OP_LOGICW:
1768	2c0262af	bellard	case CC_OP_LOGICL:
1769	14ce26e7	bellard	case CC_OP_LOGICQ:
1770	14ce26e7	bellard
1771	2c0262af	bellard	case CC_OP_INCB:
1772	2c0262af	bellard	case CC_OP_INCW:
1773	2c0262af	bellard	case CC_OP_INCL:
1774	14ce26e7	bellard	case CC_OP_INCQ:
1775	14ce26e7	bellard
1776	2c0262af	bellard	case CC_OP_DECB:
1777	2c0262af	bellard	case CC_OP_DECW:
1778	2c0262af	bellard	case CC_OP_DECL:
1779	14ce26e7	bellard	case CC_OP_DECQ:
1780	14ce26e7	bellard
1781	2c0262af	bellard	case CC_OP_SHLB:
1782	2c0262af	bellard	case CC_OP_SHLW:
1783	2c0262af	bellard	case CC_OP_SHLL:
1784	14ce26e7	bellard	case CC_OP_SHLQ:
1785	14ce26e7	bellard
1786	2c0262af	bellard	case CC_OP_SARB:
1787	2c0262af	bellard	case CC_OP_SARW:
1788	2c0262af	bellard	case CC_OP_SARL:
1789	14ce26e7	bellard	case CC_OP_SARQ:
1790	2c0262af	bellard	switch(jcc_op) {
1791	2c0262af	bellard	case JCC_Z:
1792	14ce26e7	bellard	func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1793	2c0262af	bellard	break;
1794	2c0262af	bellard	case JCC_S:
1795	14ce26e7	bellard	func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1796	2c0262af	bellard	break;
1797	2c0262af	bellard	default:
1798	2c0262af	bellard	func = NULL;
1799	2c0262af	bellard	break;
1800	2c0262af	bellard	}
1801	2c0262af	bellard	break;
1802	2c0262af	bellard	default:
1803	2c0262af	bellard	func = NULL;
1804	2c0262af	bellard	break;
1805	2c0262af	bellard	}
1806	2c0262af	bellard
1807	6e256c93	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
1808	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1809	6e256c93	bellard	s->cc_op = CC_OP_DYNAMIC;
1810	6e256c93	bellard	}
1811	2c0262af	bellard
1812	2c0262af	bellard	if (!func) {
1813	2c0262af	bellard	gen_setcc_slow[jcc_op]();
1814	14ce26e7	bellard	func = gen_op_jnz_T0_label;
1815	2c0262af	bellard	}
1816	2c0262af	bellard
1817	14ce26e7	bellard	if (inv) {
1818	14ce26e7	bellard	tmp = val;
1819	14ce26e7	bellard	val = next_eip;
1820	14ce26e7	bellard	next_eip = tmp;
1821	2c0262af	bellard	}
1822	14ce26e7	bellard	tb = s->tb;
1823	14ce26e7	bellard
1824	14ce26e7	bellard	l1 = gen_new_label();
1825	14ce26e7	bellard	func(l1);
1826	14ce26e7	bellard
1827	6e256c93	bellard	gen_goto_tb(s, 0, next_eip);
1828	14ce26e7	bellard
1829	14ce26e7	bellard	gen_set_label(l1);
1830	6e256c93	bellard	gen_goto_tb(s, 1, val);
1831	14ce26e7	bellard
1832	2c0262af	bellard	s->is_jmp = 3;
1833	2c0262af	bellard	} else {
1834	14ce26e7	bellard
1835	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
1836	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1837	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC;
1838	2c0262af	bellard	}
1839	2c0262af	bellard	gen_setcc_slow[jcc_op]();
1840	14ce26e7	bellard	if (inv) {
1841	14ce26e7	bellard	tmp = val;
1842	14ce26e7	bellard	val = next_eip;
1843	14ce26e7	bellard	next_eip = tmp;
1844	2c0262af	bellard	}
1845	14ce26e7	bellard	l1 = gen_new_label();
1846	14ce26e7	bellard	l2 = gen_new_label();
1847	14ce26e7	bellard	gen_op_jnz_T0_label(l1);
1848	14ce26e7	bellard	gen_jmp_im(next_eip);
1849	14ce26e7	bellard	gen_op_jmp_label(l2);
1850	14ce26e7	bellard	gen_set_label(l1);
1851	14ce26e7	bellard	gen_jmp_im(val);
1852	14ce26e7	bellard	gen_set_label(l2);
1853	2c0262af	bellard	gen_eob(s);
1854	2c0262af	bellard	}
1855	2c0262af	bellard	}
1856	2c0262af	bellard
1857	2c0262af	bellard	static void gen_setcc(DisasContext *s, int b)
1858	2c0262af	bellard	{
1859	2c0262af	bellard	int inv, jcc_op;
1860	2c0262af	bellard	GenOpFunc *func;
1861	2c0262af	bellard
1862	2c0262af	bellard	inv = b & 1;
1863	2c0262af	bellard	jcc_op = (b >> 1) & 7;
1864	2c0262af	bellard	switch(s->cc_op) {
1865	2c0262af	bellard	/* we optimize the cmp/jcc case */
1866	2c0262af	bellard	case CC_OP_SUBB:
1867	2c0262af	bellard	case CC_OP_SUBW:
1868	2c0262af	bellard	case CC_OP_SUBL:
1869	14ce26e7	bellard	case CC_OP_SUBQ:
1870	2c0262af	bellard	func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1871	2c0262af	bellard	if (!func)
1872	2c0262af	bellard	goto slow_jcc;
1873	2c0262af	bellard	break;
1874	2c0262af	bellard
1875	2c0262af	bellard	/* some jumps are easy to compute */
1876	2c0262af	bellard	case CC_OP_ADDB:
1877	2c0262af	bellard	case CC_OP_ADDW:
1878	2c0262af	bellard	case CC_OP_ADDL:
1879	14ce26e7	bellard	case CC_OP_ADDQ:
1880	14ce26e7	bellard
1881	2c0262af	bellard	case CC_OP_LOGICB:
1882	2c0262af	bellard	case CC_OP_LOGICW:
1883	2c0262af	bellard	case CC_OP_LOGICL:
1884	14ce26e7	bellard	case CC_OP_LOGICQ:
1885	14ce26e7	bellard
1886	2c0262af	bellard	case CC_OP_INCB:
1887	2c0262af	bellard	case CC_OP_INCW:
1888	2c0262af	bellard	case CC_OP_INCL:
1889	14ce26e7	bellard	case CC_OP_INCQ:
1890	14ce26e7	bellard
1891	2c0262af	bellard	case CC_OP_DECB:
1892	2c0262af	bellard	case CC_OP_DECW:
1893	2c0262af	bellard	case CC_OP_DECL:
1894	14ce26e7	bellard	case CC_OP_DECQ:
1895	14ce26e7	bellard
1896	2c0262af	bellard	case CC_OP_SHLB:
1897	2c0262af	bellard	case CC_OP_SHLW:
1898	2c0262af	bellard	case CC_OP_SHLL:
1899	14ce26e7	bellard	case CC_OP_SHLQ:
1900	2c0262af	bellard	switch(jcc_op) {
1901	2c0262af	bellard	case JCC_Z:
1902	14ce26e7	bellard	func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1903	2c0262af	bellard	break;
1904	2c0262af	bellard	case JCC_S:
1905	14ce26e7	bellard	func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1906	2c0262af	bellard	break;
1907	2c0262af	bellard	default:
1908	2c0262af	bellard	goto slow_jcc;
1909	2c0262af	bellard	}
1910	2c0262af	bellard	break;
1911	2c0262af	bellard	default:
1912	2c0262af	bellard	slow_jcc:
1913	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1914	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
1915	2c0262af	bellard	func = gen_setcc_slow[jcc_op];
1916	2c0262af	bellard	break;
1917	2c0262af	bellard	}
1918	2c0262af	bellard	func();
1919	2c0262af	bellard	if (inv) {
1920	2c0262af	bellard	gen_op_xor_T0_1();
1921	2c0262af	bellard	}
1922	2c0262af	bellard	}
1923	2c0262af	bellard
1924	2c0262af	bellard	/* move T0 to seg_reg and compute if the CPU state may change. Never
1925	2c0262af	bellard	call this function with seg_reg == R_CS */
1926	14ce26e7	bellard	static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
1927	2c0262af	bellard	{
1928	3415a4dd	bellard	if (s->pe && !s->vm86) {
1929	3415a4dd	bellard	/* XXX: optimize by finding processor state dynamically */
1930	3415a4dd	bellard	if (s->cc_op != CC_OP_DYNAMIC)
1931	3415a4dd	bellard	gen_op_set_cc_op(s->cc_op);
1932	14ce26e7	bellard	gen_jmp_im(cur_eip);
1933	3415a4dd	bellard	gen_op_movl_seg_T0(seg_reg);
1934	dc196a57	bellard	/* abort translation because the addseg value may change or
1935	dc196a57	bellard	because ss32 may change. For R_SS, translation must always
1936	dc196a57	bellard	stop as a special handling must be done to disable hardware
1937	dc196a57	bellard	interrupts for the next instruction */
1938	dc196a57	bellard	if (seg_reg == R_SS \|\| (s->code32 && seg_reg < R_FS))
1939	dc196a57	bellard	s->is_jmp = 3;
1940	3415a4dd	bellard	} else {
1941	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1942	dc196a57	bellard	if (seg_reg == R_SS)
1943	dc196a57	bellard	s->is_jmp = 3;
1944	3415a4dd	bellard	}
1945	2c0262af	bellard	}
1946	2c0262af	bellard
1947	4f31916f	bellard	static inline void gen_stack_update(DisasContext *s, int addend)
1948	4f31916f	bellard	{
1949	14ce26e7	bellard	#ifdef TARGET_X86_64
1950	14ce26e7	bellard	if (CODE64(s)) {
1951	14ce26e7	bellard	if (addend == 8)
1952	14ce26e7	bellard	gen_op_addq_ESP_8();
1953	14ce26e7	bellard	else
1954	14ce26e7	bellard	gen_op_addq_ESP_im(addend);
1955	14ce26e7	bellard	} else
1956	14ce26e7	bellard	#endif
1957	4f31916f	bellard	if (s->ss32) {
1958	4f31916f	bellard	if (addend == 2)
1959	4f31916f	bellard	gen_op_addl_ESP_2();
1960	4f31916f	bellard	else if (addend == 4)
1961	4f31916f	bellard	gen_op_addl_ESP_4();
1962	4f31916f	bellard	else
1963	4f31916f	bellard	gen_op_addl_ESP_im(addend);
1964	4f31916f	bellard	} else {
1965	4f31916f	bellard	if (addend == 2)
1966	4f31916f	bellard	gen_op_addw_ESP_2();
1967	4f31916f	bellard	else if (addend == 4)
1968	4f31916f	bellard	gen_op_addw_ESP_4();
1969	4f31916f	bellard	else
1970	4f31916f	bellard	gen_op_addw_ESP_im(addend);
1971	4f31916f	bellard	}
1972	4f31916f	bellard	}
1973	4f31916f	bellard
1974	2c0262af	bellard	/* generate a push. It depends on ss32, addseg and dflag */
1975	2c0262af	bellard	static void gen_push_T0(DisasContext *s)
1976	2c0262af	bellard	{
1977	14ce26e7	bellard	#ifdef TARGET_X86_64
1978	14ce26e7	bellard	if (CODE64(s)) {
1979	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
1980	8f091a59	bellard	if (s->dflag) {
1981	8f091a59	bellard	gen_op_subq_A0_8();
1982	8f091a59	bellard	gen_op_st_T0_A0[OT_QUAD + s->mem_index]();
1983	8f091a59	bellard	} else {
1984	8f091a59	bellard	gen_op_subq_A0_2();
1985	8f091a59	bellard	gen_op_st_T0_A0[OT_WORD + s->mem_index]();
1986	8f091a59	bellard	}
1987	14ce26e7	bellard	gen_op_movq_ESP_A0();
1988	14ce26e7	bellard	} else
1989	14ce26e7	bellard	#endif
1990	14ce26e7	bellard	{
1991	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
1992	14ce26e7	bellard	if (!s->dflag)
1993	14ce26e7	bellard	gen_op_subl_A0_2();
1994	14ce26e7	bellard	else
1995	14ce26e7	bellard	gen_op_subl_A0_4();
1996	14ce26e7	bellard	if (s->ss32) {
1997	14ce26e7	bellard	if (s->addseg) {
1998	14ce26e7	bellard	gen_op_movl_T1_A0();
1999	14ce26e7	bellard	gen_op_addl_A0_SS();
2000	14ce26e7	bellard	}
2001	14ce26e7	bellard	} else {
2002	14ce26e7	bellard	gen_op_andl_A0_ffff();
2003	4f31916f	bellard	gen_op_movl_T1_A0();
2004	4f31916f	bellard	gen_op_addl_A0_SS();
2005	2c0262af	bellard	}
2006	14ce26e7	bellard	gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
2007	14ce26e7	bellard	if (s->ss32 && !s->addseg)
2008	14ce26e7	bellard	gen_op_movl_ESP_A0();
2009	14ce26e7	bellard	else
2010	14ce26e7	bellard	gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
2011	2c0262af	bellard	}
2012	2c0262af	bellard	}
2013	2c0262af	bellard
2014	4f31916f	bellard	/* generate a push. It depends on ss32, addseg and dflag */
2015	4f31916f	bellard	/* slower version for T1, only used for call Ev */
2016	4f31916f	bellard	static void gen_push_T1(DisasContext *s)
2017	2c0262af	bellard	{
2018	14ce26e7	bellard	#ifdef TARGET_X86_64
2019	14ce26e7	bellard	if (CODE64(s)) {
2020	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
2021	8f091a59	bellard	if (s->dflag) {
2022	8f091a59	bellard	gen_op_subq_A0_8();
2023	8f091a59	bellard	gen_op_st_T1_A0[OT_QUAD + s->mem_index]();
2024	8f091a59	bellard	} else {
2025	8f091a59	bellard	gen_op_subq_A0_2();
2026	8f091a59	bellard	gen_op_st_T0_A0[OT_WORD + s->mem_index]();
2027	8f091a59	bellard	}
2028	14ce26e7	bellard	gen_op_movq_ESP_A0();
2029	14ce26e7	bellard	} else
2030	14ce26e7	bellard	#endif
2031	14ce26e7	bellard	{
2032	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
2033	14ce26e7	bellard	if (!s->dflag)
2034	14ce26e7	bellard	gen_op_subl_A0_2();
2035	14ce26e7	bellard	else
2036	14ce26e7	bellard	gen_op_subl_A0_4();
2037	14ce26e7	bellard	if (s->ss32) {
2038	14ce26e7	bellard	if (s->addseg) {
2039	14ce26e7	bellard	gen_op_addl_A0_SS();
2040	14ce26e7	bellard	}
2041	14ce26e7	bellard	} else {
2042	14ce26e7	bellard	gen_op_andl_A0_ffff();
2043	4f31916f	bellard	gen_op_addl_A0_SS();
2044	2c0262af	bellard	}
2045	14ce26e7	bellard	gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
2046	14ce26e7	bellard
2047	14ce26e7	bellard	if (s->ss32 && !s->addseg)
2048	14ce26e7	bellard	gen_op_movl_ESP_A0();
2049	14ce26e7	bellard	else
2050	14ce26e7	bellard	gen_stack_update(s, (-2) << s->dflag);
2051	2c0262af	bellard	}
2052	2c0262af	bellard	}
2053	2c0262af	bellard
2054	4f31916f	bellard	/* two step pop is necessary for precise exceptions */
2055	4f31916f	bellard	static void gen_pop_T0(DisasContext *s)
2056	2c0262af	bellard	{
2057	14ce26e7	bellard	#ifdef TARGET_X86_64
2058	14ce26e7	bellard	if (CODE64(s)) {
2059	14ce26e7	bellard	gen_op_movq_A0_reg[R_ESP]();
2060	8f091a59	bellard	gen_op_ld_T0_A0[(s->dflag ? OT_QUAD : OT_WORD) + s->mem_index]();
2061	14ce26e7	bellard	} else
2062	14ce26e7	bellard	#endif
2063	14ce26e7	bellard	{
2064	14ce26e7	bellard	gen_op_movl_A0_reg[R_ESP]();
2065	14ce26e7	bellard	if (s->ss32) {
2066	14ce26e7	bellard	if (s->addseg)
2067	14ce26e7	bellard	gen_op_addl_A0_SS();
2068	14ce26e7	bellard	} else {
2069	14ce26e7	bellard	gen_op_andl_A0_ffff();
2070	4f31916f	bellard	gen_op_addl_A0_SS();
2071	14ce26e7	bellard	}
2072	14ce26e7	bellard	gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
2073	2c0262af	bellard	}
2074	2c0262af	bellard	}
2075	2c0262af	bellard
2076	2c0262af	bellard	static void gen_pop_update(DisasContext *s)
2077	2c0262af	bellard	{
2078	14ce26e7	bellard	#ifdef TARGET_X86_64
2079	8f091a59	bellard	if (CODE64(s) && s->dflag) {
2080	14ce26e7	bellard	gen_stack_update(s, 8);
2081	14ce26e7	bellard	} else
2082	14ce26e7	bellard	#endif
2083	14ce26e7	bellard	{
2084	14ce26e7	bellard	gen_stack_update(s, 2 << s->dflag);
2085	14ce26e7	bellard	}
2086	2c0262af	bellard	}
2087	2c0262af	bellard
2088	2c0262af	bellard	static void gen_stack_A0(DisasContext *s)
2089	2c0262af	bellard	{
2090	2c0262af	bellard	gen_op_movl_A0_ESP();
2091	2c0262af	bellard	if (!s->ss32)
2092	2c0262af	bellard	gen_op_andl_A0_ffff();
2093	2c0262af	bellard	gen_op_movl_T1_A0();
2094	2c0262af	bellard	if (s->addseg)
2095	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2096	2c0262af	bellard	}
2097	2c0262af	bellard
2098	2c0262af	bellard	/* NOTE: wrap around in 16 bit not fully handled */
2099	2c0262af	bellard	static void gen_pusha(DisasContext *s)
2100	2c0262af	bellard	{
2101	2c0262af	bellard	int i;
2102	2c0262af	bellard	gen_op_movl_A0_ESP();
2103	2c0262af	bellard	gen_op_addl_A0_im(-16 << s->dflag);
2104	2c0262af	bellard	if (!s->ss32)
2105	2c0262af	bellard	gen_op_andl_A0_ffff();
2106	2c0262af	bellard	gen_op_movl_T1_A0();
2107	2c0262af	bellard	if (s->addseg)
2108	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2109	2c0262af	bellard	for(i = 0;i < 8; i++) {
2110	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
2111	2c0262af	bellard	gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2112	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
2113	2c0262af	bellard	}
2114	90f11f95	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2115	2c0262af	bellard	}
2116	2c0262af	bellard
2117	2c0262af	bellard	/* NOTE: wrap around in 16 bit not fully handled */
2118	2c0262af	bellard	static void gen_popa(DisasContext *s)
2119	2c0262af	bellard	{
2120	2c0262af	bellard	int i;
2121	2c0262af	bellard	gen_op_movl_A0_ESP();
2122	2c0262af	bellard	if (!s->ss32)
2123	2c0262af	bellard	gen_op_andl_A0_ffff();
2124	2c0262af	bellard	gen_op_movl_T1_A0();
2125	2c0262af	bellard	gen_op_addl_T1_im(16 << s->dflag);
2126	2c0262af	bellard	if (s->addseg)
2127	2c0262af	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2128	2c0262af	bellard	for(i = 0;i < 8; i++) {
2129	2c0262af	bellard	/* ESP is not reloaded */
2130	2c0262af	bellard	if (i != 3) {
2131	2c0262af	bellard	gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2132	2c0262af	bellard	gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
2133	2c0262af	bellard	}
2134	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
2135	2c0262af	bellard	}
2136	90f11f95	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2137	2c0262af	bellard	}
2138	2c0262af	bellard
2139	2c0262af	bellard	static void gen_enter(DisasContext *s, int esp_addend, int level)
2140	2c0262af	bellard	{
2141	61a8c4ec	bellard	int ot, opsize;
2142	2c0262af	bellard
2143	2c0262af	bellard	level &= 0x1f;
2144	8f091a59	bellard	#ifdef TARGET_X86_64
2145	8f091a59	bellard	if (CODE64(s)) {
2146	8f091a59	bellard	ot = s->dflag ? OT_QUAD : OT_WORD;
2147	8f091a59	bellard	opsize = 1 << ot;
2148	8f091a59	bellard
2149	8f091a59	bellard	gen_op_movl_A0_ESP();
2150	8f091a59	bellard	gen_op_addq_A0_im(-opsize);
2151	8f091a59	bellard	gen_op_movl_T1_A0();
2152	8f091a59	bellard
2153	8f091a59	bellard	/* push bp */
2154	8f091a59	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2155	8f091a59	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
2156	8f091a59	bellard	if (level) {
2157	8f091a59	bellard	gen_op_enter64_level(level, (ot == OT_QUAD));
2158	8f091a59	bellard	}
2159	8f091a59	bellard	gen_op_mov_reg_T1[ot][R_EBP]();
2160	8f091a59	bellard	gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2161	8f091a59	bellard	gen_op_mov_reg_T1[OT_QUAD][R_ESP]();
2162	8f091a59	bellard	} else
2163	8f091a59	bellard	#endif
2164	8f091a59	bellard	{
2165	8f091a59	bellard	ot = s->dflag + OT_WORD;
2166	8f091a59	bellard	opsize = 2 << s->dflag;
2167	8f091a59	bellard
2168	8f091a59	bellard	gen_op_movl_A0_ESP();
2169	8f091a59	bellard	gen_op_addl_A0_im(-opsize);
2170	8f091a59	bellard	if (!s->ss32)
2171	8f091a59	bellard	gen_op_andl_A0_ffff();
2172	8f091a59	bellard	gen_op_movl_T1_A0();
2173	8f091a59	bellard	if (s->addseg)
2174	8f091a59	bellard	gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2175	8f091a59	bellard	/* push bp */
2176	8f091a59	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2177	8f091a59	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
2178	8f091a59	bellard	if (level) {
2179	8f091a59	bellard	gen_op_enter_level(level, s->dflag);
2180	8f091a59	bellard	}
2181	8f091a59	bellard	gen_op_mov_reg_T1[ot][R_EBP]();
2182	8f091a59	bellard	gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2183	8f091a59	bellard	gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2184	2c0262af	bellard	}
2185	2c0262af	bellard	}
2186	2c0262af	bellard
2187	14ce26e7	bellard	static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2188	2c0262af	bellard	{
2189	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2190	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2191	14ce26e7	bellard	gen_jmp_im(cur_eip);
2192	2c0262af	bellard	gen_op_raise_exception(trapno);
2193	2c0262af	bellard	s->is_jmp = 3;
2194	2c0262af	bellard	}
2195	2c0262af	bellard
2196	2c0262af	bellard	/* an interrupt is different from an exception because of the
2197	2c0262af	bellard	priviledge checks */
2198	2c0262af	bellard	static void gen_interrupt(DisasContext *s, int intno,
2199	14ce26e7	bellard	target_ulong cur_eip, target_ulong next_eip)
2200	2c0262af	bellard	{
2201	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2202	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2203	14ce26e7	bellard	gen_jmp_im(cur_eip);
2204	a8ede8ba	bellard	gen_op_raise_interrupt(intno, (int)(next_eip - cur_eip));
2205	2c0262af	bellard	s->is_jmp = 3;
2206	2c0262af	bellard	}
2207	2c0262af	bellard
2208	14ce26e7	bellard	static void gen_debug(DisasContext *s, target_ulong cur_eip)
2209	2c0262af	bellard	{
2210	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2211	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2212	14ce26e7	bellard	gen_jmp_im(cur_eip);
2213	2c0262af	bellard	gen_op_debug();
2214	2c0262af	bellard	s->is_jmp = 3;
2215	2c0262af	bellard	}
2216	2c0262af	bellard
2217	2c0262af	bellard	/* generate a generic end of block. Trace exception is also generated
2218	2c0262af	bellard	if needed */
2219	2c0262af	bellard	static void gen_eob(DisasContext *s)
2220	2c0262af	bellard	{
2221	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
2222	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2223	a2cc3b24	bellard	if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2224	a2cc3b24	bellard	gen_op_reset_inhibit_irq();
2225	a2cc3b24	bellard	}
2226	34865134	bellard	if (s->singlestep_enabled) {
2227	34865134	bellard	gen_op_debug();
2228	34865134	bellard	} else if (s->tf) {
2229	2c0262af	bellard	gen_op_raise_exception(EXCP01_SSTP);
2230	2c0262af	bellard	} else {
2231	2c0262af	bellard	gen_op_movl_T0_0();
2232	2c0262af	bellard	gen_op_exit_tb();
2233	2c0262af	bellard	}
2234	2c0262af	bellard	s->is_jmp = 3;
2235	2c0262af	bellard	}
2236	2c0262af	bellard
2237	2c0262af	bellard	/* generate a jump to eip. No segment change must happen before as a
2238	2c0262af	bellard	direct call to the next block may occur */
2239	14ce26e7	bellard	static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2240	2c0262af	bellard	{
2241	2c0262af	bellard	if (s->jmp_opt) {
2242	6e256c93	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
2243	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
2244	6e256c93	bellard	s->cc_op = CC_OP_DYNAMIC;
2245	6e256c93	bellard	}
2246	6e256c93	bellard	gen_goto_tb(s, tb_num, eip);
2247	2c0262af	bellard	s->is_jmp = 3;
2248	2c0262af	bellard	} else {
2249	14ce26e7	bellard	gen_jmp_im(eip);
2250	2c0262af	bellard	gen_eob(s);
2251	2c0262af	bellard	}
2252	2c0262af	bellard	}
2253	2c0262af	bellard
2254	14ce26e7	bellard	static void gen_jmp(DisasContext *s, target_ulong eip)
2255	14ce26e7	bellard	{
2256	14ce26e7	bellard	gen_jmp_tb(s, eip, 0);
2257	14ce26e7	bellard	}
2258	14ce26e7	bellard
2259	14ce26e7	bellard	static void gen_movtl_T0_im(target_ulong val)
2260	14ce26e7	bellard	{
2261	14ce26e7	bellard	#ifdef TARGET_X86_64
2262	14ce26e7	bellard	if ((int32_t)val == val) {
2263	14ce26e7	bellard	gen_op_movl_T0_im(val);
2264	14ce26e7	bellard	} else {
2265	14ce26e7	bellard	gen_op_movq_T0_im64(val >> 32, val);
2266	14ce26e7	bellard	}
2267	14ce26e7	bellard	#else
2268	14ce26e7	bellard	gen_op_movl_T0_im(val);
2269	14ce26e7	bellard	#endif
2270	14ce26e7	bellard	}
2271	14ce26e7	bellard
2272	1ef38687	bellard	static void gen_movtl_T1_im(target_ulong val)
2273	1ef38687	bellard	{
2274	1ef38687	bellard	#ifdef TARGET_X86_64
2275	1ef38687	bellard	if ((int32_t)val == val) {
2276	1ef38687	bellard	gen_op_movl_T1_im(val);
2277	1ef38687	bellard	} else {
2278	1ef38687	bellard	gen_op_movq_T1_im64(val >> 32, val);
2279	1ef38687	bellard	}
2280	1ef38687	bellard	#else
2281	1ef38687	bellard	gen_op_movl_T1_im(val);
2282	1ef38687	bellard	#endif
2283	1ef38687	bellard	}
2284	1ef38687	bellard
2285	aba9d61e	bellard	static void gen_add_A0_im(DisasContext *s, int val)
2286	aba9d61e	bellard	{
2287	aba9d61e	bellard	#ifdef TARGET_X86_64
2288	aba9d61e	bellard	if (CODE64(s))
2289	aba9d61e	bellard	gen_op_addq_A0_im(val);
2290	aba9d61e	bellard	else
2291	aba9d61e	bellard	#endif
2292	aba9d61e	bellard	gen_op_addl_A0_im(val);
2293	aba9d61e	bellard	}
2294	aba9d61e	bellard
2295	664e0f19	bellard	static GenOpFunc1 *gen_ldq_env_A0[3] = {
2296	664e0f19	bellard	gen_op_ldq_raw_env_A0,
2297	664e0f19	bellard	#ifndef CONFIG_USER_ONLY
2298	664e0f19	bellard	gen_op_ldq_kernel_env_A0,
2299	664e0f19	bellard	gen_op_ldq_user_env_A0,
2300	664e0f19	bellard	#endif
2301	664e0f19	bellard	};
2302	664e0f19	bellard
2303	664e0f19	bellard	static GenOpFunc1 *gen_stq_env_A0[3] = {
2304	664e0f19	bellard	gen_op_stq_raw_env_A0,
2305	664e0f19	bellard	#ifndef CONFIG_USER_ONLY
2306	664e0f19	bellard	gen_op_stq_kernel_env_A0,
2307	664e0f19	bellard	gen_op_stq_user_env_A0,
2308	664e0f19	bellard	#endif
2309	664e0f19	bellard	};
2310	664e0f19	bellard
2311	14ce26e7	bellard	static GenOpFunc1 *gen_ldo_env_A0[3] = {
2312	14ce26e7	bellard	gen_op_ldo_raw_env_A0,
2313	14ce26e7	bellard	#ifndef CONFIG_USER_ONLY
2314	14ce26e7	bellard	gen_op_ldo_kernel_env_A0,
2315	14ce26e7	bellard	gen_op_ldo_user_env_A0,
2316	14ce26e7	bellard	#endif
2317	14ce26e7	bellard	};
2318	14ce26e7	bellard
2319	14ce26e7	bellard	static GenOpFunc1 *gen_sto_env_A0[3] = {
2320	14ce26e7	bellard	gen_op_sto_raw_env_A0,
2321	14ce26e7	bellard	#ifndef CONFIG_USER_ONLY
2322	14ce26e7	bellard	gen_op_sto_kernel_env_A0,
2323	14ce26e7	bellard	gen_op_sto_user_env_A0,
2324	14ce26e7	bellard	#endif
2325	14ce26e7	bellard	};
2326	14ce26e7	bellard
2327	664e0f19	bellard	#define SSE_SPECIAL ((GenOpFunc2 *)1)
2328	664e0f19	bellard
2329	664e0f19	bellard	#define MMX_OP2(x) { gen_op_ ## x ## _mmx, gen_op_ ## x ## _xmm }
2330	664e0f19	bellard	#define SSE_FOP(x) { gen_op_ ## x ## ps, gen_op_ ## x ## pd, \
2331	664e0f19	bellard	gen_op_ ## x ## ss, gen_op_ ## x ## sd, }
2332	664e0f19	bellard
2333	664e0f19	bellard	static GenOpFunc2 *sse_op_table1[256][4] = {
2334	664e0f19	bellard	/* pure SSE operations */
2335	664e0f19	bellard	[0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2336	664e0f19	bellard	[0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2337	664e0f19	bellard	[0x12] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2338	664e0f19	bellard	[0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2339	664e0f19	bellard	[0x14] = { gen_op_punpckldq_xmm, gen_op_punpcklqdq_xmm },
2340	664e0f19	bellard	[0x15] = { gen_op_punpckhdq_xmm, gen_op_punpckhqdq_xmm },
2341	664e0f19	bellard	[0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2342	664e0f19	bellard	[0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2343	664e0f19	bellard
2344	664e0f19	bellard	[0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2345	664e0f19	bellard	[0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2346	664e0f19	bellard	[0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2347	664e0f19	bellard	[0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2348	664e0f19	bellard	[0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2349	664e0f19	bellard	[0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2350	664e0f19	bellard	[0x2e] = { gen_op_ucomiss, gen_op_ucomisd },
2351	664e0f19	bellard	[0x2f] = { gen_op_comiss, gen_op_comisd },
2352	664e0f19	bellard	[0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2353	664e0f19	bellard	[0x51] = SSE_FOP(sqrt),
2354	664e0f19	bellard	[0x52] = { gen_op_rsqrtps, NULL, gen_op_rsqrtss, NULL },
2355	664e0f19	bellard	[0x53] = { gen_op_rcpps, NULL, gen_op_rcpss, NULL },
2356	664e0f19	bellard	[0x54] = { gen_op_pand_xmm, gen_op_pand_xmm }, /* andps, andpd */
2357	664e0f19	bellard	[0x55] = { gen_op_pandn_xmm, gen_op_pandn_xmm }, /* andnps, andnpd */
2358	664e0f19	bellard	[0x56] = { gen_op_por_xmm, gen_op_por_xmm }, /* orps, orpd */
2359	664e0f19	bellard	[0x57] = { gen_op_pxor_xmm, gen_op_pxor_xmm }, /* xorps, xorpd */
2360	664e0f19	bellard	[0x58] = SSE_FOP(add),
2361	664e0f19	bellard	[0x59] = SSE_FOP(mul),
2362	664e0f19	bellard	[0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps,
2363	664e0f19	bellard	gen_op_cvtss2sd, gen_op_cvtsd2ss },
2364	664e0f19	bellard	[0x5b] = { gen_op_cvtdq2ps, gen_op_cvtps2dq, gen_op_cvttps2dq },
2365	664e0f19	bellard	[0x5c] = SSE_FOP(sub),
2366	664e0f19	bellard	[0x5d] = SSE_FOP(min),
2367	664e0f19	bellard	[0x5e] = SSE_FOP(div),
2368	664e0f19	bellard	[0x5f] = SSE_FOP(max),
2369	664e0f19	bellard
2370	664e0f19	bellard	[0xc2] = SSE_FOP(cmpeq),
2371	d52cf7a6	bellard	[0xc6] = { (GenOpFunc2 )gen_op_shufps, (GenOpFunc2 )gen_op_shufpd },
2372	664e0f19	bellard
2373	664e0f19	bellard	/* MMX ops and their SSE extensions */
2374	664e0f19	bellard	[0x60] = MMX_OP2(punpcklbw),
2375	664e0f19	bellard	[0x61] = MMX_OP2(punpcklwd),
2376	664e0f19	bellard	[0x62] = MMX_OP2(punpckldq),
2377	664e0f19	bellard	[0x63] = MMX_OP2(packsswb),
2378	664e0f19	bellard	[0x64] = MMX_OP2(pcmpgtb),
2379	664e0f19	bellard	[0x65] = MMX_OP2(pcmpgtw),
2380	664e0f19	bellard	[0x66] = MMX_OP2(pcmpgtl),
2381	664e0f19	bellard	[0x67] = MMX_OP2(packuswb),
2382	664e0f19	bellard	[0x68] = MMX_OP2(punpckhbw),
2383	664e0f19	bellard	[0x69] = MMX_OP2(punpckhwd),
2384	664e0f19	bellard	[0x6a] = MMX_OP2(punpckhdq),
2385	664e0f19	bellard	[0x6b] = MMX_OP2(packssdw),
2386	664e0f19	bellard	[0x6c] = { NULL, gen_op_punpcklqdq_xmm },
2387	664e0f19	bellard	[0x6d] = { NULL, gen_op_punpckhqdq_xmm },
2388	664e0f19	bellard	[0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2389	664e0f19	bellard	[0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2390	664e0f19	bellard	[0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx,
2391	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshufd_xmm,
2392	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshufhw_xmm,
2393	664e0f19	bellard	(GenOpFunc2 *)gen_op_pshuflw_xmm },
2394	664e0f19	bellard	[0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2395	664e0f19	bellard	[0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2396	664e0f19	bellard	[0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2397	664e0f19	bellard	[0x74] = MMX_OP2(pcmpeqb),
2398	664e0f19	bellard	[0x75] = MMX_OP2(pcmpeqw),
2399	664e0f19	bellard	[0x76] = MMX_OP2(pcmpeql),
2400	664e0f19	bellard	[0x77] = { SSE_SPECIAL }, /* emms */
2401	664e0f19	bellard	[0x7c] = { NULL, gen_op_haddpd, NULL, gen_op_haddps },
2402	664e0f19	bellard	[0x7d] = { NULL, gen_op_hsubpd, NULL, gen_op_hsubps },
2403	664e0f19	bellard	[0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2404	664e0f19	bellard	[0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2405	664e0f19	bellard	[0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2406	664e0f19	bellard	[0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2407	664e0f19	bellard	[0xd0] = { NULL, gen_op_addsubpd, NULL, gen_op_addsubps },
2408	664e0f19	bellard	[0xd1] = MMX_OP2(psrlw),
2409	664e0f19	bellard	[0xd2] = MMX_OP2(psrld),
2410	664e0f19	bellard	[0xd3] = MMX_OP2(psrlq),
2411	664e0f19	bellard	[0xd4] = MMX_OP2(paddq),
2412	664e0f19	bellard	[0xd5] = MMX_OP2(pmullw),
2413	664e0f19	bellard	[0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2414	664e0f19	bellard	[0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2415	664e0f19	bellard	[0xd8] = MMX_OP2(psubusb),
2416	664e0f19	bellard	[0xd9] = MMX_OP2(psubusw),
2417	664e0f19	bellard	[0xda] = MMX_OP2(pminub),
2418	664e0f19	bellard	[0xdb] = MMX_OP2(pand),
2419	664e0f19	bellard	[0xdc] = MMX_OP2(paddusb),
2420	664e0f19	bellard	[0xdd] = MMX_OP2(paddusw),
2421	664e0f19	bellard	[0xde] = MMX_OP2(pmaxub),
2422	664e0f19	bellard	[0xdf] = MMX_OP2(pandn),
2423	664e0f19	bellard	[0xe0] = MMX_OP2(pavgb),
2424	664e0f19	bellard	[0xe1] = MMX_OP2(psraw),
2425	664e0f19	bellard	[0xe2] = MMX_OP2(psrad),
2426	664e0f19	bellard	[0xe3] = MMX_OP2(pavgw),
2427	664e0f19	bellard	[0xe4] = MMX_OP2(pmulhuw),
2428	664e0f19	bellard	[0xe5] = MMX_OP2(pmulhw),
2429	664e0f19	bellard	[0xe6] = { NULL, gen_op_cvttpd2dq, gen_op_cvtdq2pd, gen_op_cvtpd2dq },
2430	664e0f19	bellard	[0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2431	664e0f19	bellard	[0xe8] = MMX_OP2(psubsb),
2432	664e0f19	bellard	[0xe9] = MMX_OP2(psubsw),
2433	664e0f19	bellard	[0xea] = MMX_OP2(pminsw),
2434	664e0f19	bellard	[0xeb] = MMX_OP2(por),
2435	664e0f19	bellard	[0xec] = MMX_OP2(paddsb),
2436	664e0f19	bellard	[0xed] = MMX_OP2(paddsw),
2437	664e0f19	bellard	[0xee] = MMX_OP2(pmaxsw),
2438	664e0f19	bellard	[0xef] = MMX_OP2(pxor),
2439	664e0f19	bellard	[0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu (PNI) */
2440	664e0f19	bellard	[0xf1] = MMX_OP2(psllw),
2441	664e0f19	bellard	[0xf2] = MMX_OP2(pslld),
2442	664e0f19	bellard	[0xf3] = MMX_OP2(psllq),
2443	664e0f19	bellard	[0xf4] = MMX_OP2(pmuludq),
2444	664e0f19	bellard	[0xf5] = MMX_OP2(pmaddwd),
2445	664e0f19	bellard	[0xf6] = MMX_OP2(psadbw),
2446	664e0f19	bellard	[0xf7] = MMX_OP2(maskmov),
2447	664e0f19	bellard	[0xf8] = MMX_OP2(psubb),
2448	664e0f19	bellard	[0xf9] = MMX_OP2(psubw),
2449	664e0f19	bellard	[0xfa] = MMX_OP2(psubl),
2450	664e0f19	bellard	[0xfb] = MMX_OP2(psubq),
2451	664e0f19	bellard	[0xfc] = MMX_OP2(paddb),
2452	664e0f19	bellard	[0xfd] = MMX_OP2(paddw),
2453	664e0f19	bellard	[0xfe] = MMX_OP2(paddl),
2454	664e0f19	bellard	};
2455	664e0f19	bellard
2456	664e0f19	bellard	static GenOpFunc2 sse_op_table2[3 8][2] = {
2457	664e0f19	bellard	[0 + 2] = MMX_OP2(psrlw),
2458	664e0f19	bellard	[0 + 4] = MMX_OP2(psraw),
2459	664e0f19	bellard	[0 + 6] = MMX_OP2(psllw),
2460	664e0f19	bellard	[8 + 2] = MMX_OP2(psrld),
2461	664e0f19	bellard	[8 + 4] = MMX_OP2(psrad),
2462	664e0f19	bellard	[8 + 6] = MMX_OP2(pslld),
2463	664e0f19	bellard	[16 + 2] = MMX_OP2(psrlq),
2464	664e0f19	bellard	[16 + 3] = { NULL, gen_op_psrldq_xmm },
2465	664e0f19	bellard	[16 + 6] = MMX_OP2(psllq),
2466	664e0f19	bellard	[16 + 7] = { NULL, gen_op_pslldq_xmm },
2467	664e0f19	bellard	};
2468	664e0f19	bellard
2469	664e0f19	bellard	static GenOpFunc1 sse_op_table3[4 3] = {
2470	664e0f19	bellard	gen_op_cvtsi2ss,
2471	664e0f19	bellard	gen_op_cvtsi2sd,
2472	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsq2ss),
2473	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsq2sd),
2474	664e0f19	bellard
2475	664e0f19	bellard	gen_op_cvttss2si,
2476	664e0f19	bellard	gen_op_cvttsd2si,
2477	664e0f19	bellard	X86_64_ONLY(gen_op_cvttss2sq),
2478	664e0f19	bellard	X86_64_ONLY(gen_op_cvttsd2sq),
2479	664e0f19	bellard
2480	664e0f19	bellard	gen_op_cvtss2si,
2481	664e0f19	bellard	gen_op_cvtsd2si,
2482	664e0f19	bellard	X86_64_ONLY(gen_op_cvtss2sq),
2483	664e0f19	bellard	X86_64_ONLY(gen_op_cvtsd2sq),
2484	664e0f19	bellard	};
2485	664e0f19	bellard
2486	664e0f19	bellard	static GenOpFunc2 *sse_op_table4[8][4] = {
2487	664e0f19	bellard	SSE_FOP(cmpeq),
2488	664e0f19	bellard	SSE_FOP(cmplt),
2489	664e0f19	bellard	SSE_FOP(cmple),
2490	664e0f19	bellard	SSE_FOP(cmpunord),
2491	664e0f19	bellard	SSE_FOP(cmpneq),
2492	664e0f19	bellard	SSE_FOP(cmpnlt),
2493	664e0f19	bellard	SSE_FOP(cmpnle),
2494	664e0f19	bellard	SSE_FOP(cmpord),
2495	664e0f19	bellard	};
2496	664e0f19	bellard
2497	664e0f19	bellard	static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2498	664e0f19	bellard	{
2499	664e0f19	bellard	int b1, op1_offset, op2_offset, is_xmm, val, ot;
2500	664e0f19	bellard	int modrm, mod, rm, reg, reg_addr, offset_addr;
2501	664e0f19	bellard	GenOpFunc2 *sse_op2;
2502	664e0f19	bellard	GenOpFunc3 *sse_op3;
2503	664e0f19	bellard
2504	664e0f19	bellard	b &= 0xff;
2505	664e0f19	bellard	if (s->prefix & PREFIX_DATA)
2506	664e0f19	bellard	b1 = 1;
2507	664e0f19	bellard	else if (s->prefix & PREFIX_REPZ)
2508	664e0f19	bellard	b1 = 2;
2509	664e0f19	bellard	else if (s->prefix & PREFIX_REPNZ)
2510	664e0f19	bellard	b1 = 3;
2511	664e0f19	bellard	else
2512	664e0f19	bellard	b1 = 0;
2513	664e0f19	bellard	sse_op2 = sse_op_table1[b][b1];
2514	664e0f19	bellard	if (!sse_op2)
2515	664e0f19	bellard	goto illegal_op;
2516	664e0f19	bellard	if (b <= 0x5f \|\| b == 0xc6 \|\| b == 0xc2) {
2517	664e0f19	bellard	is_xmm = 1;
2518	664e0f19	bellard	} else {
2519	664e0f19	bellard	if (b1 == 0) {
2520	664e0f19	bellard	/* MMX case */
2521	664e0f19	bellard	is_xmm = 0;
2522	664e0f19	bellard	} else {
2523	664e0f19	bellard	is_xmm = 1;
2524	664e0f19	bellard	}
2525	664e0f19	bellard	}
2526	664e0f19	bellard	/* simple MMX/SSE operation */
2527	664e0f19	bellard	if (s->flags & HF_TS_MASK) {
2528	664e0f19	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2529	664e0f19	bellard	return;
2530	664e0f19	bellard	}
2531	664e0f19	bellard	if (s->flags & HF_EM_MASK) {
2532	664e0f19	bellard	illegal_op:
2533	664e0f19	bellard	gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2534	664e0f19	bellard	return;
2535	664e0f19	bellard	}
2536	664e0f19	bellard	if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2537	664e0f19	bellard	goto illegal_op;
2538	664e0f19	bellard	if (b == 0x77) {
2539	664e0f19	bellard	/* emms */
2540	664e0f19	bellard	gen_op_emms();
2541	664e0f19	bellard	return;
2542	664e0f19	bellard	}
2543	664e0f19	bellard	/* prepare MMX state (XXX: optimize by storing fptt and fptags in
2544	664e0f19	bellard	the static cpu state) */
2545	664e0f19	bellard	if (!is_xmm) {
2546	664e0f19	bellard	gen_op_enter_mmx();
2547	664e0f19	bellard	}
2548	664e0f19	bellard
2549	664e0f19	bellard	modrm = ldub_code(s->pc++);
2550	664e0f19	bellard	reg = ((modrm >> 3) & 7);
2551	664e0f19	bellard	if (is_xmm)
2552	664e0f19	bellard	reg \|= rex_r;
2553	664e0f19	bellard	mod = (modrm >> 6) & 3;
2554	664e0f19	bellard	if (sse_op2 == SSE_SPECIAL) {
2555	664e0f19	bellard	b \|= (b1 << 8);
2556	664e0f19	bellard	switch(b) {
2557	664e0f19	bellard	case 0x0e7: /* movntq */
2558	664e0f19	bellard	if (mod == 3)
2559	664e0f19	bellard	goto illegal_op;
2560	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2561	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2562	664e0f19	bellard	break;
2563	664e0f19	bellard	case 0x1e7: /* movntdq */
2564	664e0f19	bellard	case 0x02b: /* movntps */
2565	664e0f19	bellard	case 0x12b: /* movntps */
2566	664e0f19	bellard	case 0x2f0: /* lddqu */
2567	664e0f19	bellard	if (mod == 3)
2568	664e0f19	bellard	goto illegal_op;
2569	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2570	664e0f19	bellard	gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2571	664e0f19	bellard	break;
2572	664e0f19	bellard	case 0x6e: /* movd mm, ea */
2573	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2574	664e0f19	bellard	gen_op_movl_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2575	664e0f19	bellard	break;
2576	664e0f19	bellard	case 0x16e: /* movd xmm, ea */
2577	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2578	664e0f19	bellard	gen_op_movl_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2579	664e0f19	bellard	break;
2580	664e0f19	bellard	case 0x6f: /* movq mm, ea */
2581	664e0f19	bellard	if (mod != 3) {
2582	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2583	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2584	664e0f19	bellard	} else {
2585	664e0f19	bellard	rm = (modrm & 7);
2586	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[reg].mmx),
2587	664e0f19	bellard	offsetof(CPUX86State,fpregs[rm].mmx));
2588	664e0f19	bellard	}
2589	664e0f19	bellard	break;
2590	664e0f19	bellard	case 0x010: /* movups */
2591	664e0f19	bellard	case 0x110: /* movupd */
2592	664e0f19	bellard	case 0x028: /* movaps */
2593	664e0f19	bellard	case 0x128: /* movapd */
2594	664e0f19	bellard	case 0x16f: /* movdqa xmm, ea */
2595	664e0f19	bellard	case 0x26f: /* movdqu xmm, ea */
2596	664e0f19	bellard	if (mod != 3) {
2597	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2598	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2599	664e0f19	bellard	} else {
2600	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2601	664e0f19	bellard	gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
2602	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm]));
2603	664e0f19	bellard	}
2604	664e0f19	bellard	break;
2605	664e0f19	bellard	case 0x210: /* movss xmm, ea */
2606	664e0f19	bellard	if (mod != 3) {
2607	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2608	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2609	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2610	664e0f19	bellard	gen_op_movl_T0_0();
2611	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2612	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2613	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2614	664e0f19	bellard	} else {
2615	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2616	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2617	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
2618	664e0f19	bellard	}
2619	664e0f19	bellard	break;
2620	664e0f19	bellard	case 0x310: /* movsd xmm, ea */
2621	664e0f19	bellard	if (mod != 3) {
2622	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2623	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2624	664e0f19	bellard	gen_op_movl_T0_0();
2625	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2626	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2627	664e0f19	bellard	} else {
2628	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2629	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2630	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2631	664e0f19	bellard	}
2632	664e0f19	bellard	break;
2633	664e0f19	bellard	case 0x012: /* movlps */
2634	664e0f19	bellard	case 0x112: /* movlpd */
2635	664e0f19	bellard	if (mod != 3) {
2636	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2637	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2638	664e0f19	bellard	} else {
2639	664e0f19	bellard	/* movhlps */
2640	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2641	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2642	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2643	664e0f19	bellard	}
2644	664e0f19	bellard	break;
2645	664e0f19	bellard	case 0x016: /* movhps */
2646	664e0f19	bellard	case 0x116: /* movhpd */
2647	664e0f19	bellard	if (mod != 3) {
2648	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2649	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2650	664e0f19	bellard	} else {
2651	664e0f19	bellard	/* movlhps */
2652	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2653	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
2654	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2655	664e0f19	bellard	}
2656	664e0f19	bellard	break;
2657	664e0f19	bellard	case 0x216: /* movshdup */
2658	664e0f19	bellard	if (mod != 3) {
2659	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2660	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2661	664e0f19	bellard	} else {
2662	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2663	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
2664	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
2665	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
2666	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
2667	664e0f19	bellard	}
2668	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2669	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2670	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
2671	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2672	664e0f19	bellard	break;
2673	664e0f19	bellard	case 0x7e: /* movd ea, mm */
2674	664e0f19	bellard	gen_op_movl_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2675	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2676	664e0f19	bellard	break;
2677	664e0f19	bellard	case 0x17e: /* movd ea, xmm */
2678	664e0f19	bellard	gen_op_movl_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2679	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2680	664e0f19	bellard	break;
2681	664e0f19	bellard	case 0x27e: /* movq xmm, ea */
2682	664e0f19	bellard	if (mod != 3) {
2683	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2684	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2685	664e0f19	bellard	} else {
2686	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2687	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2688	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2689	664e0f19	bellard	}
2690	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2691	664e0f19	bellard	break;
2692	664e0f19	bellard	case 0x7f: /* movq ea, mm */
2693	664e0f19	bellard	if (mod != 3) {
2694	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2695	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2696	664e0f19	bellard	} else {
2697	664e0f19	bellard	rm = (modrm & 7);
2698	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2699	664e0f19	bellard	offsetof(CPUX86State,fpregs[reg].mmx));
2700	664e0f19	bellard	}
2701	664e0f19	bellard	break;
2702	664e0f19	bellard	case 0x011: /* movups */
2703	664e0f19	bellard	case 0x111: /* movupd */
2704	664e0f19	bellard	case 0x029: /* movaps */
2705	664e0f19	bellard	case 0x129: /* movapd */
2706	664e0f19	bellard	case 0x17f: /* movdqa ea, xmm */
2707	664e0f19	bellard	case 0x27f: /* movdqu ea, xmm */
2708	664e0f19	bellard	if (mod != 3) {
2709	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2710	664e0f19	bellard	gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2711	664e0f19	bellard	} else {
2712	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2713	664e0f19	bellard	gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
2714	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg]));
2715	664e0f19	bellard	}
2716	664e0f19	bellard	break;
2717	664e0f19	bellard	case 0x211: /* movss ea, xmm */
2718	664e0f19	bellard	if (mod != 3) {
2719	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2720	664e0f19	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2721	664e0f19	bellard	gen_op_st_T0_A0[OT_LONG + s->mem_index]();
2722	664e0f19	bellard	} else {
2723	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2724	664e0f19	bellard	gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
2725	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2726	664e0f19	bellard	}
2727	664e0f19	bellard	break;
2728	664e0f19	bellard	case 0x311: /* movsd ea, xmm */
2729	664e0f19	bellard	if (mod != 3) {
2730	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2731	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2732	664e0f19	bellard	} else {
2733	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2734	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2735	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2736	664e0f19	bellard	}
2737	664e0f19	bellard	break;
2738	664e0f19	bellard	case 0x013: /* movlps */
2739	664e0f19	bellard	case 0x113: /* movlpd */
2740	664e0f19	bellard	if (mod != 3) {
2741	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2742	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2743	664e0f19	bellard	} else {
2744	664e0f19	bellard	goto illegal_op;
2745	664e0f19	bellard	}
2746	664e0f19	bellard	break;
2747	664e0f19	bellard	case 0x017: /* movhps */
2748	664e0f19	bellard	case 0x117: /* movhpd */
2749	664e0f19	bellard	if (mod != 3) {
2750	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2751	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2752	664e0f19	bellard	} else {
2753	664e0f19	bellard	goto illegal_op;
2754	664e0f19	bellard	}
2755	664e0f19	bellard	break;
2756	664e0f19	bellard	case 0x71: /* shift mm, im */
2757	664e0f19	bellard	case 0x72:
2758	664e0f19	bellard	case 0x73:
2759	664e0f19	bellard	case 0x171: /* shift xmm, im */
2760	664e0f19	bellard	case 0x172:
2761	664e0f19	bellard	case 0x173:
2762	664e0f19	bellard	val = ldub_code(s->pc++);
2763	664e0f19	bellard	if (is_xmm) {
2764	664e0f19	bellard	gen_op_movl_T0_im(val);
2765	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2766	664e0f19	bellard	gen_op_movl_T0_0();
2767	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1)));
2768	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_t0);
2769	664e0f19	bellard	} else {
2770	664e0f19	bellard	gen_op_movl_T0_im(val);
2771	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0)));
2772	664e0f19	bellard	gen_op_movl_T0_0();
2773	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1)));
2774	664e0f19	bellard	op1_offset = offsetof(CPUX86State,mmx_t0);
2775	664e0f19	bellard	}
2776	664e0f19	bellard	sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
2777	664e0f19	bellard	if (!sse_op2)
2778	664e0f19	bellard	goto illegal_op;
2779	664e0f19	bellard	if (is_xmm) {
2780	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2781	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2782	664e0f19	bellard	} else {
2783	664e0f19	bellard	rm = (modrm & 7);
2784	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2785	664e0f19	bellard	}
2786	664e0f19	bellard	sse_op2(op2_offset, op1_offset);
2787	664e0f19	bellard	break;
2788	664e0f19	bellard	case 0x050: /* movmskps */
2789	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2790	31313213	bellard	gen_op_movmskps(offsetof(CPUX86State,xmm_regs[rm]));
2791	31313213	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2792	664e0f19	bellard	break;
2793	664e0f19	bellard	case 0x150: /* movmskpd */
2794	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2795	31313213	bellard	gen_op_movmskpd(offsetof(CPUX86State,xmm_regs[rm]));
2796	31313213	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2797	664e0f19	bellard	break;
2798	664e0f19	bellard	case 0x02a: /* cvtpi2ps */
2799	664e0f19	bellard	case 0x12a: /* cvtpi2pd */
2800	664e0f19	bellard	gen_op_enter_mmx();
2801	664e0f19	bellard	if (mod != 3) {
2802	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2803	664e0f19	bellard	op2_offset = offsetof(CPUX86State,mmx_t0);
2804	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2805	664e0f19	bellard	} else {
2806	664e0f19	bellard	rm = (modrm & 7);
2807	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2808	664e0f19	bellard	}
2809	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2810	664e0f19	bellard	switch(b >> 8) {
2811	664e0f19	bellard	case 0x0:
2812	664e0f19	bellard	gen_op_cvtpi2ps(op1_offset, op2_offset);
2813	664e0f19	bellard	break;
2814	664e0f19	bellard	default:
2815	664e0f19	bellard	case 0x1:
2816	664e0f19	bellard	gen_op_cvtpi2pd(op1_offset, op2_offset);
2817	664e0f19	bellard	break;
2818	664e0f19	bellard	}
2819	664e0f19	bellard	break;
2820	664e0f19	bellard	case 0x22a: /* cvtsi2ss */
2821	664e0f19	bellard	case 0x32a: /* cvtsi2sd */
2822	664e0f19	bellard	ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2823	664e0f19	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2824	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2825	664e0f19	bellard	sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)](op1_offset);
2826	664e0f19	bellard	break;
2827	664e0f19	bellard	case 0x02c: /* cvttps2pi */
2828	664e0f19	bellard	case 0x12c: /* cvttpd2pi */
2829	664e0f19	bellard	case 0x02d: /* cvtps2pi */
2830	664e0f19	bellard	case 0x12d: /* cvtpd2pi */
2831	664e0f19	bellard	gen_op_enter_mmx();
2832	664e0f19	bellard	if (mod != 3) {
2833	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2834	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2835	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2836	664e0f19	bellard	} else {
2837	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2838	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2839	664e0f19	bellard	}
2840	664e0f19	bellard	op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
2841	664e0f19	bellard	switch(b) {
2842	664e0f19	bellard	case 0x02c:
2843	664e0f19	bellard	gen_op_cvttps2pi(op1_offset, op2_offset);
2844	664e0f19	bellard	break;
2845	664e0f19	bellard	case 0x12c:
2846	664e0f19	bellard	gen_op_cvttpd2pi(op1_offset, op2_offset);
2847	664e0f19	bellard	break;
2848	664e0f19	bellard	case 0x02d:
2849	664e0f19	bellard	gen_op_cvtps2pi(op1_offset, op2_offset);
2850	664e0f19	bellard	break;
2851	664e0f19	bellard	case 0x12d:
2852	664e0f19	bellard	gen_op_cvtpd2pi(op1_offset, op2_offset);
2853	664e0f19	bellard	break;
2854	664e0f19	bellard	}
2855	664e0f19	bellard	break;
2856	664e0f19	bellard	case 0x22c: /* cvttss2si */
2857	664e0f19	bellard	case 0x32c: /* cvttsd2si */
2858	664e0f19	bellard	case 0x22d: /* cvtss2si */
2859	664e0f19	bellard	case 0x32d: /* cvtsd2si */
2860	664e0f19	bellard	ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2861	31313213	bellard	if (mod != 3) {
2862	31313213	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2863	31313213	bellard	if ((b >> 8) & 1) {
2864	31313213	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
2865	31313213	bellard	} else {
2866	31313213	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2867	31313213	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2868	31313213	bellard	}
2869	31313213	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2870	31313213	bellard	} else {
2871	31313213	bellard	rm = (modrm & 7) \| REX_B(s);
2872	31313213	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2873	31313213	bellard	}
2874	664e0f19	bellard	sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
2875	31313213	bellard	(b & 1) * 4](op2_offset);
2876	31313213	bellard	gen_op_mov_reg_T0[ot][reg]();
2877	664e0f19	bellard	break;
2878	664e0f19	bellard	case 0xc4: /* pinsrw */
2879	664e0f19	bellard	case 0x1c4:
2880	664e0f19	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2881	664e0f19	bellard	val = ldub_code(s->pc++);
2882	664e0f19	bellard	if (b1) {
2883	664e0f19	bellard	val &= 7;
2884	664e0f19	bellard	gen_op_pinsrw_xmm(offsetof(CPUX86State,xmm_regs[reg]), val);
2885	664e0f19	bellard	} else {
2886	664e0f19	bellard	val &= 3;
2887	664e0f19	bellard	gen_op_pinsrw_mmx(offsetof(CPUX86State,fpregs[reg].mmx), val);
2888	664e0f19	bellard	}
2889	664e0f19	bellard	break;
2890	664e0f19	bellard	case 0xc5: /* pextrw */
2891	664e0f19	bellard	case 0x1c5:
2892	664e0f19	bellard	if (mod != 3)
2893	664e0f19	bellard	goto illegal_op;
2894	664e0f19	bellard	val = ldub_code(s->pc++);
2895	664e0f19	bellard	if (b1) {
2896	664e0f19	bellard	val &= 7;
2897	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2898	664e0f19	bellard	gen_op_pextrw_xmm(offsetof(CPUX86State,xmm_regs[rm]), val);
2899	664e0f19	bellard	} else {
2900	664e0f19	bellard	val &= 3;
2901	664e0f19	bellard	rm = (modrm & 7);
2902	664e0f19	bellard	gen_op_pextrw_mmx(offsetof(CPUX86State,fpregs[rm].mmx), val);
2903	664e0f19	bellard	}
2904	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
2905	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2906	664e0f19	bellard	break;
2907	664e0f19	bellard	case 0x1d6: /* movq ea, xmm */
2908	664e0f19	bellard	if (mod != 3) {
2909	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2910	664e0f19	bellard	gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2911	664e0f19	bellard	} else {
2912	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2913	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2914	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2915	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2916	664e0f19	bellard	}
2917	664e0f19	bellard	break;
2918	664e0f19	bellard	case 0x2d6: /* movq2dq */
2919	664e0f19	bellard	gen_op_enter_mmx();
2920	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2921	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2922	664e0f19	bellard	offsetof(CPUX86State,fpregs[reg & 7].mmx));
2923	664e0f19	bellard	gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2924	664e0f19	bellard	break;
2925	664e0f19	bellard	case 0x3d6: /* movdq2q */
2926	664e0f19	bellard	gen_op_enter_mmx();
2927	664e0f19	bellard	rm = (modrm & 7);
2928	664e0f19	bellard	gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2929	664e0f19	bellard	offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2930	664e0f19	bellard	break;
2931	664e0f19	bellard	case 0xd7: /* pmovmskb */
2932	664e0f19	bellard	case 0x1d7:
2933	664e0f19	bellard	if (mod != 3)
2934	664e0f19	bellard	goto illegal_op;
2935	664e0f19	bellard	if (b1) {
2936	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2937	664e0f19	bellard	gen_op_pmovmskb_xmm(offsetof(CPUX86State,xmm_regs[rm]));
2938	664e0f19	bellard	} else {
2939	664e0f19	bellard	rm = (modrm & 7);
2940	664e0f19	bellard	gen_op_pmovmskb_mmx(offsetof(CPUX86State,fpregs[rm].mmx));
2941	664e0f19	bellard	}
2942	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
2943	664e0f19	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
2944	664e0f19	bellard	break;
2945	664e0f19	bellard	default:
2946	664e0f19	bellard	goto illegal_op;
2947	664e0f19	bellard	}
2948	664e0f19	bellard	} else {
2949	664e0f19	bellard	/* generic MMX or SSE operation */
2950	664e0f19	bellard	if (b == 0xf7) {
2951	664e0f19	bellard	/* maskmov : we must prepare A0 */
2952	664e0f19	bellard	if (mod != 3)
2953	664e0f19	bellard	goto illegal_op;
2954	664e0f19	bellard	#ifdef TARGET_X86_64
2955	8f091a59	bellard	if (s->aflag == 2) {
2956	664e0f19	bellard	gen_op_movq_A0_reg[R_EDI]();
2957	664e0f19	bellard	} else
2958	664e0f19	bellard	#endif
2959	664e0f19	bellard	{
2960	664e0f19	bellard	gen_op_movl_A0_reg[R_EDI]();
2961	664e0f19	bellard	if (s->aflag == 0)
2962	664e0f19	bellard	gen_op_andl_A0_ffff();
2963	664e0f19	bellard	}
2964	664e0f19	bellard	gen_add_A0_ds_seg(s);
2965	664e0f19	bellard	}
2966	664e0f19	bellard	if (is_xmm) {
2967	664e0f19	bellard	op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2968	664e0f19	bellard	if (mod != 3) {
2969	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2970	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_t0);
2971	664e0f19	bellard	if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f) \|\|
2972	664e0f19	bellard	b == 0xc2)) {
2973	664e0f19	bellard	/* specific case for SSE single instructions */
2974	664e0f19	bellard	if (b1 == 2) {
2975	664e0f19	bellard	/* 32 bit access */
2976	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2977	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2978	664e0f19	bellard	} else {
2979	664e0f19	bellard	/* 64 bit access */
2980	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_D(0)));
2981	664e0f19	bellard	}
2982	664e0f19	bellard	} else {
2983	664e0f19	bellard	gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2984	664e0f19	bellard	}
2985	664e0f19	bellard	} else {
2986	664e0f19	bellard	rm = (modrm & 7) \| REX_B(s);
2987	664e0f19	bellard	op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2988	664e0f19	bellard	}
2989	664e0f19	bellard	} else {
2990	664e0f19	bellard	op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
2991	664e0f19	bellard	if (mod != 3) {
2992	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2993	664e0f19	bellard	op2_offset = offsetof(CPUX86State,mmx_t0);
2994	664e0f19	bellard	gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2995	664e0f19	bellard	} else {
2996	664e0f19	bellard	rm = (modrm & 7);
2997	664e0f19	bellard	op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2998	664e0f19	bellard	}
2999	664e0f19	bellard	}
3000	664e0f19	bellard	switch(b) {
3001	664e0f19	bellard	case 0x70: /* pshufx insn */
3002	664e0f19	bellard	case 0xc6: /* pshufx insn */
3003	664e0f19	bellard	val = ldub_code(s->pc++);
3004	664e0f19	bellard	sse_op3 = (GenOpFunc3 *)sse_op2;
3005	664e0f19	bellard	sse_op3(op1_offset, op2_offset, val);
3006	664e0f19	bellard	break;
3007	664e0f19	bellard	case 0xc2:
3008	664e0f19	bellard	/* compare insns */
3009	664e0f19	bellard	val = ldub_code(s->pc++);
3010	664e0f19	bellard	if (val >= 8)
3011	664e0f19	bellard	goto illegal_op;
3012	664e0f19	bellard	sse_op2 = sse_op_table4[val][b1];
3013	664e0f19	bellard	sse_op2(op1_offset, op2_offset);
3014	664e0f19	bellard	break;
3015	664e0f19	bellard	default:
3016	664e0f19	bellard	sse_op2(op1_offset, op2_offset);
3017	664e0f19	bellard	break;
3018	664e0f19	bellard	}
3019	664e0f19	bellard	if (b == 0x2e \|\| b == 0x2f) {
3020	664e0f19	bellard	s->cc_op = CC_OP_EFLAGS;
3021	664e0f19	bellard	}
3022	664e0f19	bellard	}
3023	664e0f19	bellard	}
3024	664e0f19	bellard
3025	664e0f19	bellard
3026	2c0262af	bellard	/* convert one instruction. s->is_jmp is set if the translation must
3027	2c0262af	bellard	be stopped. Return the next pc value */
3028	14ce26e7	bellard	static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3029	2c0262af	bellard	{
3030	2c0262af	bellard	int b, prefixes, aflag, dflag;
3031	2c0262af	bellard	int shift, ot;
3032	2c0262af	bellard	int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3033	14ce26e7	bellard	target_ulong next_eip, tval;
3034	14ce26e7	bellard	int rex_w, rex_r;
3035	2c0262af	bellard
3036	2c0262af	bellard	s->pc = pc_start;
3037	2c0262af	bellard	prefixes = 0;
3038	2c0262af	bellard	aflag = s->code32;
3039	2c0262af	bellard	dflag = s->code32;
3040	2c0262af	bellard	s->override = -1;
3041	14ce26e7	bellard	rex_w = -1;
3042	14ce26e7	bellard	rex_r = 0;
3043	14ce26e7	bellard	#ifdef TARGET_X86_64
3044	14ce26e7	bellard	s->rex_x = 0;
3045	14ce26e7	bellard	s->rex_b = 0;
3046	14ce26e7	bellard	x86_64_hregs = 0;
3047	14ce26e7	bellard	#endif
3048	14ce26e7	bellard	s->rip_offset = 0; /* for relative ip address */
3049	2c0262af	bellard	next_byte:
3050	61382a50	bellard	b = ldub_code(s->pc);
3051	2c0262af	bellard	s->pc++;
3052	2c0262af	bellard	/* check prefixes */
3053	14ce26e7	bellard	#ifdef TARGET_X86_64
3054	14ce26e7	bellard	if (CODE64(s)) {
3055	14ce26e7	bellard	switch (b) {
3056	14ce26e7	bellard	case 0xf3:
3057	14ce26e7	bellard	prefixes \|= PREFIX_REPZ;
3058	14ce26e7	bellard	goto next_byte;
3059	14ce26e7	bellard	case 0xf2:
3060	14ce26e7	bellard	prefixes \|= PREFIX_REPNZ;
3061	14ce26e7	bellard	goto next_byte;
3062	14ce26e7	bellard	case 0xf0:
3063	14ce26e7	bellard	prefixes \|= PREFIX_LOCK;
3064	14ce26e7	bellard	goto next_byte;
3065	14ce26e7	bellard	case 0x2e:
3066	14ce26e7	bellard	s->override = R_CS;
3067	14ce26e7	bellard	goto next_byte;
3068	14ce26e7	bellard	case 0x36:
3069	14ce26e7	bellard	s->override = R_SS;
3070	14ce26e7	bellard	goto next_byte;
3071	14ce26e7	bellard	case 0x3e:
3072	14ce26e7	bellard	s->override = R_DS;
3073	14ce26e7	bellard	goto next_byte;
3074	14ce26e7	bellard	case 0x26:
3075	14ce26e7	bellard	s->override = R_ES;
3076	14ce26e7	bellard	goto next_byte;
3077	14ce26e7	bellard	case 0x64:
3078	14ce26e7	bellard	s->override = R_FS;
3079	14ce26e7	bellard	goto next_byte;
3080	14ce26e7	bellard	case 0x65:
3081	14ce26e7	bellard	s->override = R_GS;
3082	14ce26e7	bellard	goto next_byte;
3083	14ce26e7	bellard	case 0x66:
3084	14ce26e7	bellard	prefixes \|= PREFIX_DATA;
3085	14ce26e7	bellard	goto next_byte;
3086	14ce26e7	bellard	case 0x67:
3087	14ce26e7	bellard	prefixes \|= PREFIX_ADR;
3088	14ce26e7	bellard	goto next_byte;
3089	14ce26e7	bellard	case 0x40 ... 0x4f:
3090	14ce26e7	bellard	/* REX prefix */
3091	14ce26e7	bellard	rex_w = (b >> 3) & 1;
3092	14ce26e7	bellard	rex_r = (b & 0x4) << 1;
3093	14ce26e7	bellard	s->rex_x = (b & 0x2) << 2;
3094	14ce26e7	bellard	REX_B(s) = (b & 0x1) << 3;
3095	14ce26e7	bellard	x86_64_hregs = 1; /* select uniform byte register addressing */
3096	14ce26e7	bellard	goto next_byte;
3097	14ce26e7	bellard	}
3098	14ce26e7	bellard	if (rex_w == 1) {
3099	14ce26e7	bellard	/* 0x66 is ignored if rex.w is set */
3100	14ce26e7	bellard	dflag = 2;
3101	14ce26e7	bellard	} else {
3102	14ce26e7	bellard	if (prefixes & PREFIX_DATA)
3103	14ce26e7	bellard	dflag ^= 1;
3104	14ce26e7	bellard	}
3105	14ce26e7	bellard	if (!(prefixes & PREFIX_ADR))
3106	14ce26e7	bellard	aflag = 2;
3107	14ce26e7	bellard	} else
3108	14ce26e7	bellard	#endif
3109	14ce26e7	bellard	{
3110	14ce26e7	bellard	switch (b) {
3111	14ce26e7	bellard	case 0xf3:
3112	14ce26e7	bellard	prefixes \|= PREFIX_REPZ;
3113	14ce26e7	bellard	goto next_byte;
3114	14ce26e7	bellard	case 0xf2:
3115	14ce26e7	bellard	prefixes \|= PREFIX_REPNZ;
3116	14ce26e7	bellard	goto next_byte;
3117	14ce26e7	bellard	case 0xf0:
3118	14ce26e7	bellard	prefixes \|= PREFIX_LOCK;
3119	14ce26e7	bellard	goto next_byte;
3120	14ce26e7	bellard	case 0x2e:
3121	14ce26e7	bellard	s->override = R_CS;
3122	14ce26e7	bellard	goto next_byte;
3123	14ce26e7	bellard	case 0x36:
3124	14ce26e7	bellard	s->override = R_SS;
3125	14ce26e7	bellard	goto next_byte;
3126	14ce26e7	bellard	case 0x3e:
3127	14ce26e7	bellard	s->override = R_DS;
3128	14ce26e7	bellard	goto next_byte;
3129	14ce26e7	bellard	case 0x26:
3130	14ce26e7	bellard	s->override = R_ES;
3131	14ce26e7	bellard	goto next_byte;
3132	14ce26e7	bellard	case 0x64:
3133	14ce26e7	bellard	s->override = R_FS;
3134	14ce26e7	bellard	goto next_byte;
3135	14ce26e7	bellard	case 0x65:
3136	14ce26e7	bellard	s->override = R_GS;
3137	14ce26e7	bellard	goto next_byte;
3138	14ce26e7	bellard	case 0x66:
3139	14ce26e7	bellard	prefixes \|= PREFIX_DATA;
3140	14ce26e7	bellard	goto next_byte;
3141	14ce26e7	bellard	case 0x67:
3142	14ce26e7	bellard	prefixes \|= PREFIX_ADR;
3143	14ce26e7	bellard	goto next_byte;
3144	14ce26e7	bellard	}
3145	14ce26e7	bellard	if (prefixes & PREFIX_DATA)
3146	14ce26e7	bellard	dflag ^= 1;
3147	14ce26e7	bellard	if (prefixes & PREFIX_ADR)
3148	14ce26e7	bellard	aflag ^= 1;
3149	2c0262af	bellard	}
3150	2c0262af	bellard
3151	2c0262af	bellard	s->prefix = prefixes;
3152	2c0262af	bellard	s->aflag = aflag;
3153	2c0262af	bellard	s->dflag = dflag;
3154	2c0262af	bellard
3155	2c0262af	bellard	/* lock generation */
3156	2c0262af	bellard	if (prefixes & PREFIX_LOCK)
3157	2c0262af	bellard	gen_op_lock();
3158	2c0262af	bellard
3159	2c0262af	bellard	/* now check op code */
3160	2c0262af	bellard	reswitch:
3161	2c0262af	bellard	switch(b) {
3162	2c0262af	bellard	case 0x0f:
3163	2c0262af	bellard	/**************************/
3164	2c0262af	bellard	/* extended op code */
3165	61382a50	bellard	b = ldub_code(s->pc++) \| 0x100;
3166	2c0262af	bellard	goto reswitch;
3167	2c0262af	bellard
3168	2c0262af	bellard	/**************************/
3169	2c0262af	bellard	/* arith & logic */
3170	2c0262af	bellard	case 0x00 ... 0x05:
3171	2c0262af	bellard	case 0x08 ... 0x0d:
3172	2c0262af	bellard	case 0x10 ... 0x15:
3173	2c0262af	bellard	case 0x18 ... 0x1d:
3174	2c0262af	bellard	case 0x20 ... 0x25:
3175	2c0262af	bellard	case 0x28 ... 0x2d:
3176	2c0262af	bellard	case 0x30 ... 0x35:
3177	2c0262af	bellard	case 0x38 ... 0x3d:
3178	2c0262af	bellard	{
3179	2c0262af	bellard	int op, f, val;
3180	2c0262af	bellard	op = (b >> 3) & 7;
3181	2c0262af	bellard	f = (b >> 1) & 3;
3182	2c0262af	bellard
3183	2c0262af	bellard	if ((b & 1) == 0)
3184	2c0262af	bellard	ot = OT_BYTE;
3185	2c0262af	bellard	else
3186	14ce26e7	bellard	ot = dflag + OT_WORD;
3187	2c0262af	bellard
3188	2c0262af	bellard	switch(f) {
3189	2c0262af	bellard	case 0: /* OP Ev, Gv */
3190	61382a50	bellard	modrm = ldub_code(s->pc++);
3191	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3192	2c0262af	bellard	mod = (modrm >> 6) & 3;
3193	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3194	2c0262af	bellard	if (mod != 3) {
3195	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3196	2c0262af	bellard	opreg = OR_TMP0;
3197	2c0262af	bellard	} else if (op == OP_XORL && rm == reg) {
3198	2c0262af	bellard	xor_zero:
3199	2c0262af	bellard	/* xor reg, reg optimisation */
3200	2c0262af	bellard	gen_op_movl_T0_0();
3201	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3202	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3203	2c0262af	bellard	gen_op_update1_cc();
3204	2c0262af	bellard	break;
3205	2c0262af	bellard	} else {
3206	2c0262af	bellard	opreg = rm;
3207	2c0262af	bellard	}
3208	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3209	2c0262af	bellard	gen_op(s, op, ot, opreg);
3210	2c0262af	bellard	break;
3211	2c0262af	bellard	case 1: /* OP Gv, Ev */
3212	61382a50	bellard	modrm = ldub_code(s->pc++);
3213	2c0262af	bellard	mod = (modrm >> 6) & 3;
3214	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3215	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3216	2c0262af	bellard	if (mod != 3) {
3217	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3218	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3219	2c0262af	bellard	} else if (op == OP_XORL && rm == reg) {
3220	2c0262af	bellard	goto xor_zero;
3221	2c0262af	bellard	} else {
3222	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
3223	2c0262af	bellard	}
3224	2c0262af	bellard	gen_op(s, op, ot, reg);
3225	2c0262af	bellard	break;
3226	2c0262af	bellard	case 2: /* OP A, Iv */
3227	2c0262af	bellard	val = insn_get(s, ot);
3228	2c0262af	bellard	gen_op_movl_T1_im(val);
3229	2c0262af	bellard	gen_op(s, op, ot, OR_EAX);
3230	2c0262af	bellard	break;
3231	2c0262af	bellard	}
3232	2c0262af	bellard	}
3233	2c0262af	bellard	break;
3234	2c0262af	bellard
3235	2c0262af	bellard	case 0x80: /* GRP1 */
3236	2c0262af	bellard	case 0x81:
3237	d64477af	bellard	case 0x82:
3238	2c0262af	bellard	case 0x83:
3239	2c0262af	bellard	{
3240	2c0262af	bellard	int val;
3241	2c0262af	bellard
3242	2c0262af	bellard	if ((b & 1) == 0)
3243	2c0262af	bellard	ot = OT_BYTE;
3244	2c0262af	bellard	else
3245	14ce26e7	bellard	ot = dflag + OT_WORD;
3246	2c0262af	bellard
3247	61382a50	bellard	modrm = ldub_code(s->pc++);
3248	2c0262af	bellard	mod = (modrm >> 6) & 3;
3249	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3250	2c0262af	bellard	op = (modrm >> 3) & 7;
3251	2c0262af	bellard
3252	2c0262af	bellard	if (mod != 3) {
3253	14ce26e7	bellard	if (b == 0x83)
3254	14ce26e7	bellard	s->rip_offset = 1;
3255	14ce26e7	bellard	else
3256	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3257	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3258	2c0262af	bellard	opreg = OR_TMP0;
3259	2c0262af	bellard	} else {
3260	14ce26e7	bellard	opreg = rm;
3261	2c0262af	bellard	}
3262	2c0262af	bellard
3263	2c0262af	bellard	switch(b) {
3264	2c0262af	bellard	default:
3265	2c0262af	bellard	case 0x80:
3266	2c0262af	bellard	case 0x81:
3267	d64477af	bellard	case 0x82:
3268	2c0262af	bellard	val = insn_get(s, ot);
3269	2c0262af	bellard	break;
3270	2c0262af	bellard	case 0x83:
3271	2c0262af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3272	2c0262af	bellard	break;
3273	2c0262af	bellard	}
3274	2c0262af	bellard	gen_op_movl_T1_im(val);
3275	2c0262af	bellard	gen_op(s, op, ot, opreg);
3276	2c0262af	bellard	}
3277	2c0262af	bellard	break;
3278	2c0262af	bellard
3279	2c0262af	bellard	/**************************/
3280	2c0262af	bellard	/* inc, dec, and other misc arith */
3281	2c0262af	bellard	case 0x40 ... 0x47: /* inc Gv */
3282	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
3283	2c0262af	bellard	gen_inc(s, ot, OR_EAX + (b & 7), 1);
3284	2c0262af	bellard	break;
3285	2c0262af	bellard	case 0x48 ... 0x4f: /* dec Gv */
3286	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
3287	2c0262af	bellard	gen_inc(s, ot, OR_EAX + (b & 7), -1);
3288	2c0262af	bellard	break;
3289	2c0262af	bellard	case 0xf6: /* GRP3 */
3290	2c0262af	bellard	case 0xf7:
3291	2c0262af	bellard	if ((b & 1) == 0)
3292	2c0262af	bellard	ot = OT_BYTE;
3293	2c0262af	bellard	else
3294	14ce26e7	bellard	ot = dflag + OT_WORD;
3295	2c0262af	bellard
3296	61382a50	bellard	modrm = ldub_code(s->pc++);
3297	2c0262af	bellard	mod = (modrm >> 6) & 3;
3298	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3299	2c0262af	bellard	op = (modrm >> 3) & 7;
3300	2c0262af	bellard	if (mod != 3) {
3301	14ce26e7	bellard	if (op == 0)
3302	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3303	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3304	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3305	2c0262af	bellard	} else {
3306	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3307	2c0262af	bellard	}
3308	2c0262af	bellard
3309	2c0262af	bellard	switch(op) {
3310	2c0262af	bellard	case 0: /* test */
3311	2c0262af	bellard	val = insn_get(s, ot);
3312	2c0262af	bellard	gen_op_movl_T1_im(val);
3313	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3314	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3315	2c0262af	bellard	break;
3316	2c0262af	bellard	case 2: /* not */
3317	2c0262af	bellard	gen_op_notl_T0();
3318	2c0262af	bellard	if (mod != 3) {
3319	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3320	2c0262af	bellard	} else {
3321	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3322	2c0262af	bellard	}
3323	2c0262af	bellard	break;
3324	2c0262af	bellard	case 3: /* neg */
3325	2c0262af	bellard	gen_op_negl_T0();
3326	2c0262af	bellard	if (mod != 3) {
3327	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3328	2c0262af	bellard	} else {
3329	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3330	2c0262af	bellard	}
3331	2c0262af	bellard	gen_op_update_neg_cc();
3332	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
3333	2c0262af	bellard	break;
3334	2c0262af	bellard	case 4: /* mul */
3335	2c0262af	bellard	switch(ot) {
3336	2c0262af	bellard	case OT_BYTE:
3337	2c0262af	bellard	gen_op_mulb_AL_T0();
3338	d36cd60e	bellard	s->cc_op = CC_OP_MULB;
3339	2c0262af	bellard	break;
3340	2c0262af	bellard	case OT_WORD:
3341	2c0262af	bellard	gen_op_mulw_AX_T0();
3342	d36cd60e	bellard	s->cc_op = CC_OP_MULW;
3343	2c0262af	bellard	break;
3344	2c0262af	bellard	default:
3345	2c0262af	bellard	case OT_LONG:
3346	2c0262af	bellard	gen_op_mull_EAX_T0();
3347	d36cd60e	bellard	s->cc_op = CC_OP_MULL;
3348	2c0262af	bellard	break;
3349	14ce26e7	bellard	#ifdef TARGET_X86_64
3350	14ce26e7	bellard	case OT_QUAD:
3351	14ce26e7	bellard	gen_op_mulq_EAX_T0();
3352	14ce26e7	bellard	s->cc_op = CC_OP_MULQ;
3353	14ce26e7	bellard	break;
3354	14ce26e7	bellard	#endif
3355	2c0262af	bellard	}
3356	2c0262af	bellard	break;
3357	2c0262af	bellard	case 5: /* imul */
3358	2c0262af	bellard	switch(ot) {
3359	2c0262af	bellard	case OT_BYTE:
3360	2c0262af	bellard	gen_op_imulb_AL_T0();
3361	d36cd60e	bellard	s->cc_op = CC_OP_MULB;
3362	2c0262af	bellard	break;
3363	2c0262af	bellard	case OT_WORD:
3364	2c0262af	bellard	gen_op_imulw_AX_T0();
3365	d36cd60e	bellard	s->cc_op = CC_OP_MULW;
3366	2c0262af	bellard	break;
3367	2c0262af	bellard	default:
3368	2c0262af	bellard	case OT_LONG:
3369	2c0262af	bellard	gen_op_imull_EAX_T0();
3370	d36cd60e	bellard	s->cc_op = CC_OP_MULL;
3371	2c0262af	bellard	break;
3372	14ce26e7	bellard	#ifdef TARGET_X86_64
3373	14ce26e7	bellard	case OT_QUAD:
3374	14ce26e7	bellard	gen_op_imulq_EAX_T0();
3375	14ce26e7	bellard	s->cc_op = CC_OP_MULQ;
3376	14ce26e7	bellard	break;
3377	14ce26e7	bellard	#endif
3378	2c0262af	bellard	}
3379	2c0262af	bellard	break;
3380	2c0262af	bellard	case 6: /* div */
3381	2c0262af	bellard	switch(ot) {
3382	2c0262af	bellard	case OT_BYTE:
3383	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3384	14ce26e7	bellard	gen_op_divb_AL_T0();
3385	2c0262af	bellard	break;
3386	2c0262af	bellard	case OT_WORD:
3387	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3388	14ce26e7	bellard	gen_op_divw_AX_T0();
3389	2c0262af	bellard	break;
3390	2c0262af	bellard	default:
3391	2c0262af	bellard	case OT_LONG:
3392	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3393	14ce26e7	bellard	gen_op_divl_EAX_T0();
3394	14ce26e7	bellard	break;
3395	14ce26e7	bellard	#ifdef TARGET_X86_64
3396	14ce26e7	bellard	case OT_QUAD:
3397	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3398	14ce26e7	bellard	gen_op_divq_EAX_T0();
3399	2c0262af	bellard	break;
3400	14ce26e7	bellard	#endif
3401	2c0262af	bellard	}
3402	2c0262af	bellard	break;
3403	2c0262af	bellard	case 7: /* idiv */
3404	2c0262af	bellard	switch(ot) {
3405	2c0262af	bellard	case OT_BYTE:
3406	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3407	14ce26e7	bellard	gen_op_idivb_AL_T0();
3408	2c0262af	bellard	break;
3409	2c0262af	bellard	case OT_WORD:
3410	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3411	14ce26e7	bellard	gen_op_idivw_AX_T0();
3412	2c0262af	bellard	break;
3413	2c0262af	bellard	default:
3414	2c0262af	bellard	case OT_LONG:
3415	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3416	14ce26e7	bellard	gen_op_idivl_EAX_T0();
3417	14ce26e7	bellard	break;
3418	14ce26e7	bellard	#ifdef TARGET_X86_64
3419	14ce26e7	bellard	case OT_QUAD:
3420	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3421	14ce26e7	bellard	gen_op_idivq_EAX_T0();
3422	2c0262af	bellard	break;
3423	14ce26e7	bellard	#endif
3424	2c0262af	bellard	}
3425	2c0262af	bellard	break;
3426	2c0262af	bellard	default:
3427	2c0262af	bellard	goto illegal_op;
3428	2c0262af	bellard	}
3429	2c0262af	bellard	break;
3430	2c0262af	bellard
3431	2c0262af	bellard	case 0xfe: /* GRP4 */
3432	2c0262af	bellard	case 0xff: /* GRP5 */
3433	2c0262af	bellard	if ((b & 1) == 0)
3434	2c0262af	bellard	ot = OT_BYTE;
3435	2c0262af	bellard	else
3436	14ce26e7	bellard	ot = dflag + OT_WORD;
3437	2c0262af	bellard
3438	61382a50	bellard	modrm = ldub_code(s->pc++);
3439	2c0262af	bellard	mod = (modrm >> 6) & 3;
3440	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3441	2c0262af	bellard	op = (modrm >> 3) & 7;
3442	2c0262af	bellard	if (op >= 2 && b == 0xfe) {
3443	2c0262af	bellard	goto illegal_op;
3444	2c0262af	bellard	}
3445	14ce26e7	bellard	if (CODE64(s)) {
3446	aba9d61e	bellard	if (op == 2 \|\| op == 4) {
3447	14ce26e7	bellard	/* operand size for jumps is 64 bit */
3448	14ce26e7	bellard	ot = OT_QUAD;
3449	aba9d61e	bellard	} else if (op == 3 \|\| op == 5) {
3450	aba9d61e	bellard	/* for call calls, the operand is 16 or 32 bit, even
3451	aba9d61e	bellard	in long mode */
3452	aba9d61e	bellard	ot = dflag ? OT_LONG : OT_WORD;
3453	14ce26e7	bellard	} else if (op == 6) {
3454	14ce26e7	bellard	/* default push size is 64 bit */
3455	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3456	14ce26e7	bellard	}
3457	14ce26e7	bellard	}
3458	2c0262af	bellard	if (mod != 3) {
3459	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3460	2c0262af	bellard	if (op >= 2 && op != 3 && op != 5)
3461	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3462	2c0262af	bellard	} else {
3463	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3464	2c0262af	bellard	}
3465	2c0262af	bellard
3466	2c0262af	bellard	switch(op) {
3467	2c0262af	bellard	case 0: /* inc Ev */
3468	2c0262af	bellard	if (mod != 3)
3469	2c0262af	bellard	opreg = OR_TMP0;
3470	2c0262af	bellard	else
3471	2c0262af	bellard	opreg = rm;
3472	2c0262af	bellard	gen_inc(s, ot, opreg, 1);
3473	2c0262af	bellard	break;
3474	2c0262af	bellard	case 1: /* dec Ev */
3475	2c0262af	bellard	if (mod != 3)
3476	2c0262af	bellard	opreg = OR_TMP0;
3477	2c0262af	bellard	else
3478	2c0262af	bellard	opreg = rm;
3479	2c0262af	bellard	gen_inc(s, ot, opreg, -1);
3480	2c0262af	bellard	break;
3481	2c0262af	bellard	case 2: /* call Ev */
3482	4f31916f	bellard	/* XXX: optimize if memory (no 'and' is necessary) */
3483	2c0262af	bellard	if (s->dflag == 0)
3484	2c0262af	bellard	gen_op_andl_T0_ffff();
3485	2c0262af	bellard	next_eip = s->pc - s->cs_base;
3486	1ef38687	bellard	gen_movtl_T1_im(next_eip);
3487	4f31916f	bellard	gen_push_T1(s);
3488	4f31916f	bellard	gen_op_jmp_T0();
3489	2c0262af	bellard	gen_eob(s);
3490	2c0262af	bellard	break;
3491	61382a50	bellard	case 3: /* lcall Ev */
3492	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3493	aba9d61e	bellard	gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
3494	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3495	2c0262af	bellard	do_lcall:
3496	2c0262af	bellard	if (s->pe && !s->vm86) {
3497	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3498	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3499	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3500	aba9d61e	bellard	gen_op_lcall_protected_T0_T1(dflag, s->pc - pc_start);
3501	2c0262af	bellard	} else {
3502	2c0262af	bellard	gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
3503	2c0262af	bellard	}
3504	2c0262af	bellard	gen_eob(s);
3505	2c0262af	bellard	break;
3506	2c0262af	bellard	case 4: /* jmp Ev */
3507	2c0262af	bellard	if (s->dflag == 0)
3508	2c0262af	bellard	gen_op_andl_T0_ffff();
3509	2c0262af	bellard	gen_op_jmp_T0();
3510	2c0262af	bellard	gen_eob(s);
3511	2c0262af	bellard	break;
3512	2c0262af	bellard	case 5: /* ljmp Ev */
3513	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3514	aba9d61e	bellard	gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
3515	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3516	2c0262af	bellard	do_ljmp:
3517	2c0262af	bellard	if (s->pe && !s->vm86) {
3518	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3519	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3520	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
3521	aba9d61e	bellard	gen_op_ljmp_protected_T0_T1(s->pc - pc_start);
3522	2c0262af	bellard	} else {
3523	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3524	2c0262af	bellard	gen_op_movl_T0_T1();
3525	2c0262af	bellard	gen_op_jmp_T0();
3526	2c0262af	bellard	}
3527	2c0262af	bellard	gen_eob(s);
3528	2c0262af	bellard	break;
3529	2c0262af	bellard	case 6: /* push Ev */
3530	2c0262af	bellard	gen_push_T0(s);
3531	2c0262af	bellard	break;
3532	2c0262af	bellard	default:
3533	2c0262af	bellard	goto illegal_op;
3534	2c0262af	bellard	}
3535	2c0262af	bellard	break;
3536	2c0262af	bellard
3537	2c0262af	bellard	case 0x84: /* test Ev, Gv */
3538	2c0262af	bellard	case 0x85:
3539	2c0262af	bellard	if ((b & 1) == 0)
3540	2c0262af	bellard	ot = OT_BYTE;
3541	2c0262af	bellard	else
3542	14ce26e7	bellard	ot = dflag + OT_WORD;
3543	2c0262af	bellard
3544	61382a50	bellard	modrm = ldub_code(s->pc++);
3545	2c0262af	bellard	mod = (modrm >> 6) & 3;
3546	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3547	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3548	2c0262af	bellard
3549	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3550	14ce26e7	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3551	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3552	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3553	2c0262af	bellard	break;
3554	2c0262af	bellard
3555	2c0262af	bellard	case 0xa8: /* test eAX, Iv */
3556	2c0262af	bellard	case 0xa9:
3557	2c0262af	bellard	if ((b & 1) == 0)
3558	2c0262af	bellard	ot = OT_BYTE;
3559	2c0262af	bellard	else
3560	14ce26e7	bellard	ot = dflag + OT_WORD;
3561	2c0262af	bellard	val = insn_get(s, ot);
3562	2c0262af	bellard
3563	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][OR_EAX]();
3564	2c0262af	bellard	gen_op_movl_T1_im(val);
3565	2c0262af	bellard	gen_op_testl_T0_T1_cc();
3566	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
3567	2c0262af	bellard	break;
3568	2c0262af	bellard
3569	2c0262af	bellard	case 0x98: /* CWDE/CBW */
3570	14ce26e7	bellard	#ifdef TARGET_X86_64
3571	14ce26e7	bellard	if (dflag == 2) {
3572	14ce26e7	bellard	gen_op_movslq_RAX_EAX();
3573	14ce26e7	bellard	} else
3574	14ce26e7	bellard	#endif
3575	14ce26e7	bellard	if (dflag == 1)
3576	2c0262af	bellard	gen_op_movswl_EAX_AX();
3577	2c0262af	bellard	else
3578	2c0262af	bellard	gen_op_movsbw_AX_AL();
3579	2c0262af	bellard	break;
3580	2c0262af	bellard	case 0x99: /* CDQ/CWD */
3581	14ce26e7	bellard	#ifdef TARGET_X86_64
3582	14ce26e7	bellard	if (dflag == 2) {
3583	14ce26e7	bellard	gen_op_movsqo_RDX_RAX();
3584	14ce26e7	bellard	} else
3585	14ce26e7	bellard	#endif
3586	14ce26e7	bellard	if (dflag == 1)
3587	2c0262af	bellard	gen_op_movslq_EDX_EAX();
3588	2c0262af	bellard	else
3589	2c0262af	bellard	gen_op_movswl_DX_AX();
3590	2c0262af	bellard	break;
3591	2c0262af	bellard	case 0x1af: /* imul Gv, Ev */
3592	2c0262af	bellard	case 0x69: /* imul Gv, Ev, I */
3593	2c0262af	bellard	case 0x6b:
3594	14ce26e7	bellard	ot = dflag + OT_WORD;
3595	61382a50	bellard	modrm = ldub_code(s->pc++);
3596	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3597	14ce26e7	bellard	if (b == 0x69)
3598	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3599	14ce26e7	bellard	else if (b == 0x6b)
3600	14ce26e7	bellard	s->rip_offset = 1;
3601	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3602	2c0262af	bellard	if (b == 0x69) {
3603	2c0262af	bellard	val = insn_get(s, ot);
3604	2c0262af	bellard	gen_op_movl_T1_im(val);
3605	2c0262af	bellard	} else if (b == 0x6b) {
3606	d64477af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3607	2c0262af	bellard	gen_op_movl_T1_im(val);
3608	2c0262af	bellard	} else {
3609	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3610	2c0262af	bellard	}
3611	2c0262af	bellard
3612	14ce26e7	bellard	#ifdef TARGET_X86_64
3613	14ce26e7	bellard	if (ot == OT_QUAD) {
3614	14ce26e7	bellard	gen_op_imulq_T0_T1();
3615	14ce26e7	bellard	} else
3616	14ce26e7	bellard	#endif
3617	2c0262af	bellard	if (ot == OT_LONG) {
3618	2c0262af	bellard	gen_op_imull_T0_T1();
3619	2c0262af	bellard	} else {
3620	2c0262af	bellard	gen_op_imulw_T0_T1();
3621	2c0262af	bellard	}
3622	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3623	d36cd60e	bellard	s->cc_op = CC_OP_MULB + ot;
3624	2c0262af	bellard	break;
3625	2c0262af	bellard	case 0x1c0:
3626	2c0262af	bellard	case 0x1c1: /* xadd Ev, Gv */
3627	2c0262af	bellard	if ((b & 1) == 0)
3628	2c0262af	bellard	ot = OT_BYTE;
3629	2c0262af	bellard	else
3630	14ce26e7	bellard	ot = dflag + OT_WORD;
3631	61382a50	bellard	modrm = ldub_code(s->pc++);
3632	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3633	2c0262af	bellard	mod = (modrm >> 6) & 3;
3634	2c0262af	bellard	if (mod == 3) {
3635	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3636	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3637	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
3638	2c0262af	bellard	gen_op_addl_T0_T1();
3639	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
3640	5a1388b6	bellard	gen_op_mov_reg_T0[ot][rm]();
3641	2c0262af	bellard	} else {
3642	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3643	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
3644	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
3645	2c0262af	bellard	gen_op_addl_T0_T1();
3646	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3647	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
3648	2c0262af	bellard	}
3649	2c0262af	bellard	gen_op_update2_cc();
3650	2c0262af	bellard	s->cc_op = CC_OP_ADDB + ot;
3651	2c0262af	bellard	break;
3652	2c0262af	bellard	case 0x1b0:
3653	2c0262af	bellard	case 0x1b1: /* cmpxchg Ev, Gv */
3654	2c0262af	bellard	if ((b & 1) == 0)
3655	2c0262af	bellard	ot = OT_BYTE;
3656	2c0262af	bellard	else
3657	14ce26e7	bellard	ot = dflag + OT_WORD;
3658	61382a50	bellard	modrm = ldub_code(s->pc++);
3659	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3660	2c0262af	bellard	mod = (modrm >> 6) & 3;
3661	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
3662	2c0262af	bellard	if (mod == 3) {
3663	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3664	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3665	2c0262af	bellard	gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
3666	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
3667	2c0262af	bellard	} else {
3668	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3669	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3670	4f31916f	bellard	gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
3671	2c0262af	bellard	}
3672	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
3673	2c0262af	bellard	break;
3674	2c0262af	bellard	case 0x1c7: /* cmpxchg8b */
3675	61382a50	bellard	modrm = ldub_code(s->pc++);
3676	2c0262af	bellard	mod = (modrm >> 6) & 3;
3677	2c0262af	bellard	if (mod == 3)
3678	2c0262af	bellard	goto illegal_op;
3679	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
3680	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
3681	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3682	2c0262af	bellard	gen_op_cmpxchg8b();
3683	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
3684	2c0262af	bellard	break;
3685	2c0262af	bellard
3686	2c0262af	bellard	/**************************/
3687	2c0262af	bellard	/* push/pop */
3688	2c0262af	bellard	case 0x50 ... 0x57: /* push */
3689	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][(b & 7) \| REX_B(s)]();
3690	2c0262af	bellard	gen_push_T0(s);
3691	2c0262af	bellard	break;
3692	2c0262af	bellard	case 0x58 ... 0x5f: /* pop */
3693	14ce26e7	bellard	if (CODE64(s)) {
3694	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3695	14ce26e7	bellard	} else {
3696	14ce26e7	bellard	ot = dflag + OT_WORD;
3697	14ce26e7	bellard	}
3698	2c0262af	bellard	gen_pop_T0(s);
3699	77729c24	bellard	/* NOTE: order is important for pop %sp */
3700	2c0262af	bellard	gen_pop_update(s);
3701	14ce26e7	bellard	gen_op_mov_reg_T0[ot][(b & 7) \| REX_B(s)]();
3702	2c0262af	bellard	break;
3703	2c0262af	bellard	case 0x60: /* pusha */
3704	14ce26e7	bellard	if (CODE64(s))
3705	14ce26e7	bellard	goto illegal_op;
3706	2c0262af	bellard	gen_pusha(s);
3707	2c0262af	bellard	break;
3708	2c0262af	bellard	case 0x61: /* popa */
3709	14ce26e7	bellard	if (CODE64(s))
3710	14ce26e7	bellard	goto illegal_op;
3711	2c0262af	bellard	gen_popa(s);
3712	2c0262af	bellard	break;
3713	2c0262af	bellard	case 0x68: /* push Iv */
3714	2c0262af	bellard	case 0x6a:
3715	14ce26e7	bellard	if (CODE64(s)) {
3716	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3717	14ce26e7	bellard	} else {
3718	14ce26e7	bellard	ot = dflag + OT_WORD;
3719	14ce26e7	bellard	}
3720	2c0262af	bellard	if (b == 0x68)
3721	2c0262af	bellard	val = insn_get(s, ot);
3722	2c0262af	bellard	else
3723	2c0262af	bellard	val = (int8_t)insn_get(s, OT_BYTE);
3724	2c0262af	bellard	gen_op_movl_T0_im(val);
3725	2c0262af	bellard	gen_push_T0(s);
3726	2c0262af	bellard	break;
3727	2c0262af	bellard	case 0x8f: /* pop Ev */
3728	14ce26e7	bellard	if (CODE64(s)) {
3729	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3730	14ce26e7	bellard	} else {
3731	14ce26e7	bellard	ot = dflag + OT_WORD;
3732	14ce26e7	bellard	}
3733	61382a50	bellard	modrm = ldub_code(s->pc++);
3734	77729c24	bellard	mod = (modrm >> 6) & 3;
3735	2c0262af	bellard	gen_pop_T0(s);
3736	77729c24	bellard	if (mod == 3) {
3737	77729c24	bellard	/* NOTE: order is important for pop %sp */
3738	77729c24	bellard	gen_pop_update(s);
3739	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3740	77729c24	bellard	gen_op_mov_reg_T0[ot][rm]();
3741	77729c24	bellard	} else {
3742	77729c24	bellard	/* NOTE: order is important too for MMU exceptions */
3743	14ce26e7	bellard	s->popl_esp_hack = 1 << ot;
3744	77729c24	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3745	77729c24	bellard	s->popl_esp_hack = 0;
3746	77729c24	bellard	gen_pop_update(s);
3747	77729c24	bellard	}
3748	2c0262af	bellard	break;
3749	2c0262af	bellard	case 0xc8: /* enter */
3750	2c0262af	bellard	{
3751	2c0262af	bellard	int level;
3752	61382a50	bellard	val = lduw_code(s->pc);
3753	2c0262af	bellard	s->pc += 2;
3754	61382a50	bellard	level = ldub_code(s->pc++);
3755	2c0262af	bellard	gen_enter(s, val, level);
3756	2c0262af	bellard	}
3757	2c0262af	bellard	break;
3758	2c0262af	bellard	case 0xc9: /* leave */
3759	2c0262af	bellard	/* XXX: exception not precise (ESP is updated before potential exception) */
3760	14ce26e7	bellard	if (CODE64(s)) {
3761	14ce26e7	bellard	gen_op_mov_TN_reg[OT_QUAD][0][R_EBP]();
3762	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][R_ESP]();
3763	14ce26e7	bellard	} else if (s->ss32) {
3764	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
3765	2c0262af	bellard	gen_op_mov_reg_T0[OT_LONG][R_ESP]();
3766	2c0262af	bellard	} else {
3767	2c0262af	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
3768	2c0262af	bellard	gen_op_mov_reg_T0[OT_WORD][R_ESP]();
3769	2c0262af	bellard	}
3770	2c0262af	bellard	gen_pop_T0(s);
3771	14ce26e7	bellard	if (CODE64(s)) {
3772	14ce26e7	bellard	ot = dflag ? OT_QUAD : OT_WORD;
3773	14ce26e7	bellard	} else {
3774	14ce26e7	bellard	ot = dflag + OT_WORD;
3775	14ce26e7	bellard	}
3776	2c0262af	bellard	gen_op_mov_reg_T0[ot][R_EBP]();
3777	2c0262af	bellard	gen_pop_update(s);
3778	2c0262af	bellard	break;
3779	2c0262af	bellard	case 0x06: /* push es */
3780	2c0262af	bellard	case 0x0e: /* push cs */
3781	2c0262af	bellard	case 0x16: /* push ss */
3782	2c0262af	bellard	case 0x1e: /* push ds */
3783	14ce26e7	bellard	if (CODE64(s))
3784	14ce26e7	bellard	goto illegal_op;
3785	2c0262af	bellard	gen_op_movl_T0_seg(b >> 3);
3786	2c0262af	bellard	gen_push_T0(s);
3787	2c0262af	bellard	break;
3788	2c0262af	bellard	case 0x1a0: /* push fs */
3789	2c0262af	bellard	case 0x1a8: /* push gs */
3790	2c0262af	bellard	gen_op_movl_T0_seg((b >> 3) & 7);
3791	2c0262af	bellard	gen_push_T0(s);
3792	2c0262af	bellard	break;
3793	2c0262af	bellard	case 0x07: /* pop es */
3794	2c0262af	bellard	case 0x17: /* pop ss */
3795	2c0262af	bellard	case 0x1f: /* pop ds */
3796	14ce26e7	bellard	if (CODE64(s))
3797	14ce26e7	bellard	goto illegal_op;
3798	2c0262af	bellard	reg = b >> 3;
3799	2c0262af	bellard	gen_pop_T0(s);
3800	2c0262af	bellard	gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3801	2c0262af	bellard	gen_pop_update(s);
3802	2c0262af	bellard	if (reg == R_SS) {
3803	a2cc3b24	bellard	/* if reg == SS, inhibit interrupts/trace. */
3804	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
3805	a2cc3b24	bellard	_first_ does it */
3806	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3807	a2cc3b24	bellard	gen_op_set_inhibit_irq();
3808	2c0262af	bellard	s->tf = 0;
3809	2c0262af	bellard	}
3810	2c0262af	bellard	if (s->is_jmp) {
3811	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3812	2c0262af	bellard	gen_eob(s);
3813	2c0262af	bellard	}
3814	2c0262af	bellard	break;
3815	2c0262af	bellard	case 0x1a1: /* pop fs */
3816	2c0262af	bellard	case 0x1a9: /* pop gs */
3817	2c0262af	bellard	gen_pop_T0(s);
3818	2c0262af	bellard	gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
3819	2c0262af	bellard	gen_pop_update(s);
3820	2c0262af	bellard	if (s->is_jmp) {
3821	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3822	2c0262af	bellard	gen_eob(s);
3823	2c0262af	bellard	}
3824	2c0262af	bellard	break;
3825	2c0262af	bellard
3826	2c0262af	bellard	/**************************/
3827	2c0262af	bellard	/* mov */
3828	2c0262af	bellard	case 0x88:
3829	2c0262af	bellard	case 0x89: /* mov Gv, Ev */
3830	2c0262af	bellard	if ((b & 1) == 0)
3831	2c0262af	bellard	ot = OT_BYTE;
3832	2c0262af	bellard	else
3833	14ce26e7	bellard	ot = dflag + OT_WORD;
3834	61382a50	bellard	modrm = ldub_code(s->pc++);
3835	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3836	2c0262af	bellard
3837	2c0262af	bellard	/* generate a generic store */
3838	14ce26e7	bellard	gen_ldst_modrm(s, modrm, ot, reg, 1);
3839	2c0262af	bellard	break;
3840	2c0262af	bellard	case 0xc6:
3841	2c0262af	bellard	case 0xc7: /* mov Ev, Iv */
3842	2c0262af	bellard	if ((b & 1) == 0)
3843	2c0262af	bellard	ot = OT_BYTE;
3844	2c0262af	bellard	else
3845	14ce26e7	bellard	ot = dflag + OT_WORD;
3846	61382a50	bellard	modrm = ldub_code(s->pc++);
3847	2c0262af	bellard	mod = (modrm >> 6) & 3;
3848	14ce26e7	bellard	if (mod != 3) {
3849	14ce26e7	bellard	s->rip_offset = insn_const_size(ot);
3850	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3851	14ce26e7	bellard	}
3852	2c0262af	bellard	val = insn_get(s, ot);
3853	2c0262af	bellard	gen_op_movl_T0_im(val);
3854	2c0262af	bellard	if (mod != 3)
3855	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
3856	2c0262af	bellard	else
3857	14ce26e7	bellard	gen_op_mov_reg_T0[ot][(modrm & 7) \| REX_B(s)]();
3858	2c0262af	bellard	break;
3859	2c0262af	bellard	case 0x8a:
3860	2c0262af	bellard	case 0x8b: /* mov Ev, Gv */
3861	2c0262af	bellard	if ((b & 1) == 0)
3862	2c0262af	bellard	ot = OT_BYTE;
3863	2c0262af	bellard	else
3864	14ce26e7	bellard	ot = OT_WORD + dflag;
3865	61382a50	bellard	modrm = ldub_code(s->pc++);
3866	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3867	2c0262af	bellard
3868	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3869	2c0262af	bellard	gen_op_mov_reg_T0[ot][reg]();
3870	2c0262af	bellard	break;
3871	2c0262af	bellard	case 0x8e: /* mov seg, Gv */
3872	61382a50	bellard	modrm = ldub_code(s->pc++);
3873	2c0262af	bellard	reg = (modrm >> 3) & 7;
3874	2c0262af	bellard	if (reg >= 6 \|\| reg == R_CS)
3875	2c0262af	bellard	goto illegal_op;
3876	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3877	2c0262af	bellard	gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3878	2c0262af	bellard	if (reg == R_SS) {
3879	2c0262af	bellard	/* if reg == SS, inhibit interrupts/trace */
3880	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
3881	a2cc3b24	bellard	_first_ does it */
3882	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3883	a2cc3b24	bellard	gen_op_set_inhibit_irq();
3884	2c0262af	bellard	s->tf = 0;
3885	2c0262af	bellard	}
3886	2c0262af	bellard	if (s->is_jmp) {
3887	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
3888	2c0262af	bellard	gen_eob(s);
3889	2c0262af	bellard	}
3890	2c0262af	bellard	break;
3891	2c0262af	bellard	case 0x8c: /* mov Gv, seg */
3892	61382a50	bellard	modrm = ldub_code(s->pc++);
3893	2c0262af	bellard	reg = (modrm >> 3) & 7;
3894	2c0262af	bellard	mod = (modrm >> 6) & 3;
3895	2c0262af	bellard	if (reg >= 6)
3896	2c0262af	bellard	goto illegal_op;
3897	2c0262af	bellard	gen_op_movl_T0_seg(reg);
3898	14ce26e7	bellard	if (mod == 3)
3899	14ce26e7	bellard	ot = OT_WORD + dflag;
3900	14ce26e7	bellard	else
3901	14ce26e7	bellard	ot = OT_WORD;
3902	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3903	2c0262af	bellard	break;
3904	2c0262af	bellard
3905	2c0262af	bellard	case 0x1b6: /* movzbS Gv, Eb */
3906	2c0262af	bellard	case 0x1b7: /* movzwS Gv, Eb */
3907	2c0262af	bellard	case 0x1be: /* movsbS Gv, Eb */
3908	2c0262af	bellard	case 0x1bf: /* movswS Gv, Eb */
3909	2c0262af	bellard	{
3910	2c0262af	bellard	int d_ot;
3911	2c0262af	bellard	/* d_ot is the size of destination */
3912	2c0262af	bellard	d_ot = dflag + OT_WORD;
3913	2c0262af	bellard	/* ot is the size of source */
3914	2c0262af	bellard	ot = (b & 1) + OT_BYTE;
3915	61382a50	bellard	modrm = ldub_code(s->pc++);
3916	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3917	2c0262af	bellard	mod = (modrm >> 6) & 3;
3918	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
3919	2c0262af	bellard
3920	2c0262af	bellard	if (mod == 3) {
3921	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
3922	2c0262af	bellard	switch(ot \| (b & 8)) {
3923	2c0262af	bellard	case OT_BYTE:
3924	2c0262af	bellard	gen_op_movzbl_T0_T0();
3925	2c0262af	bellard	break;
3926	2c0262af	bellard	case OT_BYTE \| 8:
3927	2c0262af	bellard	gen_op_movsbl_T0_T0();
3928	2c0262af	bellard	break;
3929	2c0262af	bellard	case OT_WORD:
3930	2c0262af	bellard	gen_op_movzwl_T0_T0();
3931	2c0262af	bellard	break;
3932	2c0262af	bellard	default:
3933	2c0262af	bellard	case OT_WORD \| 8:
3934	2c0262af	bellard	gen_op_movswl_T0_T0();
3935	2c0262af	bellard	break;
3936	2c0262af	bellard	}
3937	2c0262af	bellard	gen_op_mov_reg_T0[d_ot][reg]();
3938	2c0262af	bellard	} else {
3939	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3940	2c0262af	bellard	if (b & 8) {
3941	2c0262af	bellard	gen_op_lds_T0_A0[ot + s->mem_index]();
3942	2c0262af	bellard	} else {
3943	2c0262af	bellard	gen_op_ldu_T0_A0[ot + s->mem_index]();
3944	2c0262af	bellard	}
3945	2c0262af	bellard	gen_op_mov_reg_T0[d_ot][reg]();
3946	2c0262af	bellard	}
3947	2c0262af	bellard	}
3948	2c0262af	bellard	break;
3949	2c0262af	bellard
3950	2c0262af	bellard	case 0x8d: /* lea */
3951	14ce26e7	bellard	ot = dflag + OT_WORD;
3952	61382a50	bellard	modrm = ldub_code(s->pc++);
3953	3a1d9b8b	bellard	mod = (modrm >> 6) & 3;
3954	3a1d9b8b	bellard	if (mod == 3)
3955	3a1d9b8b	bellard	goto illegal_op;
3956	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
3957	2c0262af	bellard	/* we must ensure that no segment is added */
3958	2c0262af	bellard	s->override = -1;
3959	2c0262af	bellard	val = s->addseg;
3960	2c0262af	bellard	s->addseg = 0;
3961	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3962	2c0262af	bellard	s->addseg = val;
3963	2c0262af	bellard	gen_op_mov_reg_A0[ot - OT_WORD][reg]();
3964	2c0262af	bellard	break;
3965	2c0262af	bellard
3966	2c0262af	bellard	case 0xa0: /* mov EAX, Ov */
3967	2c0262af	bellard	case 0xa1:
3968	2c0262af	bellard	case 0xa2: /* mov Ov, EAX */
3969	2c0262af	bellard	case 0xa3:
3970	2c0262af	bellard	{
3971	14ce26e7	bellard	target_ulong offset_addr;
3972	14ce26e7	bellard
3973	14ce26e7	bellard	if ((b & 1) == 0)
3974	14ce26e7	bellard	ot = OT_BYTE;
3975	14ce26e7	bellard	else
3976	14ce26e7	bellard	ot = dflag + OT_WORD;
3977	14ce26e7	bellard	#ifdef TARGET_X86_64
3978	8f091a59	bellard	if (s->aflag == 2) {
3979	14ce26e7	bellard	offset_addr = ldq_code(s->pc);
3980	14ce26e7	bellard	s->pc += 8;
3981	14ce26e7	bellard	if (offset_addr == (int32_t)offset_addr)
3982	14ce26e7	bellard	gen_op_movq_A0_im(offset_addr);
3983	14ce26e7	bellard	else
3984	14ce26e7	bellard	gen_op_movq_A0_im64(offset_addr >> 32, offset_addr);
3985	14ce26e7	bellard	} else
3986	14ce26e7	bellard	#endif
3987	14ce26e7	bellard	{
3988	14ce26e7	bellard	if (s->aflag) {
3989	14ce26e7	bellard	offset_addr = insn_get(s, OT_LONG);
3990	14ce26e7	bellard	} else {
3991	14ce26e7	bellard	offset_addr = insn_get(s, OT_WORD);
3992	14ce26e7	bellard	}
3993	14ce26e7	bellard	gen_op_movl_A0_im(offset_addr);
3994	14ce26e7	bellard	}
3995	664e0f19	bellard	gen_add_A0_ds_seg(s);
3996	14ce26e7	bellard	if ((b & 2) == 0) {
3997	14ce26e7	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
3998	14ce26e7	bellard	gen_op_mov_reg_T0[ot][R_EAX]();
3999	14ce26e7	bellard	} else {
4000	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][R_EAX]();
4001	14ce26e7	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
4002	2c0262af	bellard	}
4003	2c0262af	bellard	}
4004	2c0262af	bellard	break;
4005	2c0262af	bellard	case 0xd7: /* xlat */
4006	14ce26e7	bellard	#ifdef TARGET_X86_64
4007	8f091a59	bellard	if (s->aflag == 2) {
4008	14ce26e7	bellard	gen_op_movq_A0_reg[R_EBX]();
4009	14ce26e7	bellard	gen_op_addq_A0_AL();
4010	14ce26e7	bellard	} else
4011	14ce26e7	bellard	#endif
4012	14ce26e7	bellard	{
4013	14ce26e7	bellard	gen_op_movl_A0_reg[R_EBX]();
4014	14ce26e7	bellard	gen_op_addl_A0_AL();
4015	14ce26e7	bellard	if (s->aflag == 0)
4016	14ce26e7	bellard	gen_op_andl_A0_ffff();
4017	14ce26e7	bellard	}
4018	664e0f19	bellard	gen_add_A0_ds_seg(s);
4019	2c0262af	bellard	gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
4020	2c0262af	bellard	gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
4021	2c0262af	bellard	break;
4022	2c0262af	bellard	case 0xb0 ... 0xb7: /* mov R, Ib */
4023	2c0262af	bellard	val = insn_get(s, OT_BYTE);
4024	2c0262af	bellard	gen_op_movl_T0_im(val);
4025	14ce26e7	bellard	gen_op_mov_reg_T0[OT_BYTE][(b & 7) \| REX_B(s)]();
4026	2c0262af	bellard	break;
4027	2c0262af	bellard	case 0xb8 ... 0xbf: /* mov R, Iv */
4028	14ce26e7	bellard	#ifdef TARGET_X86_64
4029	14ce26e7	bellard	if (dflag == 2) {
4030	14ce26e7	bellard	uint64_t tmp;
4031	14ce26e7	bellard	/* 64 bit case */
4032	14ce26e7	bellard	tmp = ldq_code(s->pc);
4033	14ce26e7	bellard	s->pc += 8;
4034	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
4035	14ce26e7	bellard	gen_movtl_T0_im(tmp);
4036	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][reg]();
4037	14ce26e7	bellard	} else
4038	14ce26e7	bellard	#endif
4039	14ce26e7	bellard	{
4040	14ce26e7	bellard	ot = dflag ? OT_LONG : OT_WORD;
4041	14ce26e7	bellard	val = insn_get(s, ot);
4042	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
4043	14ce26e7	bellard	gen_op_movl_T0_im(val);
4044	14ce26e7	bellard	gen_op_mov_reg_T0[ot][reg]();
4045	14ce26e7	bellard	}
4046	2c0262af	bellard	break;
4047	2c0262af	bellard
4048	2c0262af	bellard	case 0x91 ... 0x97: /* xchg R, EAX */
4049	14ce26e7	bellard	ot = dflag + OT_WORD;
4050	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
4051	2c0262af	bellard	rm = R_EAX;
4052	2c0262af	bellard	goto do_xchg_reg;
4053	2c0262af	bellard	case 0x86:
4054	2c0262af	bellard	case 0x87: /* xchg Ev, Gv */
4055	2c0262af	bellard	if ((b & 1) == 0)
4056	2c0262af	bellard	ot = OT_BYTE;
4057	2c0262af	bellard	else
4058	14ce26e7	bellard	ot = dflag + OT_WORD;
4059	61382a50	bellard	modrm = ldub_code(s->pc++);
4060	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4061	2c0262af	bellard	mod = (modrm >> 6) & 3;
4062	2c0262af	bellard	if (mod == 3) {
4063	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4064	2c0262af	bellard	do_xchg_reg:
4065	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
4066	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
4067	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
4068	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4069	2c0262af	bellard	} else {
4070	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4071	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][reg]();
4072	2c0262af	bellard	/* for xchg, lock is implicit */
4073	2c0262af	bellard	if (!(prefixes & PREFIX_LOCK))
4074	2c0262af	bellard	gen_op_lock();
4075	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4076	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
4077	2c0262af	bellard	if (!(prefixes & PREFIX_LOCK))
4078	2c0262af	bellard	gen_op_unlock();
4079	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4080	2c0262af	bellard	}
4081	2c0262af	bellard	break;
4082	2c0262af	bellard	case 0xc4: /* les Gv */
4083	14ce26e7	bellard	if (CODE64(s))
4084	14ce26e7	bellard	goto illegal_op;
4085	2c0262af	bellard	op = R_ES;
4086	2c0262af	bellard	goto do_lxx;
4087	2c0262af	bellard	case 0xc5: /* lds Gv */
4088	14ce26e7	bellard	if (CODE64(s))
4089	14ce26e7	bellard	goto illegal_op;
4090	2c0262af	bellard	op = R_DS;
4091	2c0262af	bellard	goto do_lxx;
4092	2c0262af	bellard	case 0x1b2: /* lss Gv */
4093	2c0262af	bellard	op = R_SS;
4094	2c0262af	bellard	goto do_lxx;
4095	2c0262af	bellard	case 0x1b4: /* lfs Gv */
4096	2c0262af	bellard	op = R_FS;
4097	2c0262af	bellard	goto do_lxx;
4098	2c0262af	bellard	case 0x1b5: /* lgs Gv */
4099	2c0262af	bellard	op = R_GS;
4100	2c0262af	bellard	do_lxx:
4101	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4102	61382a50	bellard	modrm = ldub_code(s->pc++);
4103	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4104	2c0262af	bellard	mod = (modrm >> 6) & 3;
4105	2c0262af	bellard	if (mod == 3)
4106	2c0262af	bellard	goto illegal_op;
4107	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4108	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4109	aba9d61e	bellard	gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4110	2c0262af	bellard	/* load the segment first to handle exceptions properly */
4111	61382a50	bellard	gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
4112	2c0262af	bellard	gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4113	2c0262af	bellard	/* then put the data */
4114	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
4115	2c0262af	bellard	if (s->is_jmp) {
4116	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
4117	2c0262af	bellard	gen_eob(s);
4118	2c0262af	bellard	}
4119	2c0262af	bellard	break;
4120	2c0262af	bellard
4121	2c0262af	bellard	/************************/
4122	2c0262af	bellard	/* shifts */
4123	2c0262af	bellard	case 0xc0:
4124	2c0262af	bellard	case 0xc1:
4125	2c0262af	bellard	/* shift Ev,Ib */
4126	2c0262af	bellard	shift = 2;
4127	2c0262af	bellard	grp2:
4128	2c0262af	bellard	{
4129	2c0262af	bellard	if ((b & 1) == 0)
4130	2c0262af	bellard	ot = OT_BYTE;
4131	2c0262af	bellard	else
4132	14ce26e7	bellard	ot = dflag + OT_WORD;
4133	2c0262af	bellard
4134	61382a50	bellard	modrm = ldub_code(s->pc++);
4135	2c0262af	bellard	mod = (modrm >> 6) & 3;
4136	2c0262af	bellard	op = (modrm >> 3) & 7;
4137	2c0262af	bellard
4138	2c0262af	bellard	if (mod != 3) {
4139	14ce26e7	bellard	if (shift == 2) {
4140	14ce26e7	bellard	s->rip_offset = 1;
4141	14ce26e7	bellard	}
4142	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4143	2c0262af	bellard	opreg = OR_TMP0;
4144	2c0262af	bellard	} else {
4145	14ce26e7	bellard	opreg = (modrm & 7) \| REX_B(s);
4146	2c0262af	bellard	}
4147	2c0262af	bellard
4148	2c0262af	bellard	/* simpler op */
4149	2c0262af	bellard	if (shift == 0) {
4150	2c0262af	bellard	gen_shift(s, op, ot, opreg, OR_ECX);
4151	2c0262af	bellard	} else {
4152	2c0262af	bellard	if (shift == 2) {
4153	61382a50	bellard	shift = ldub_code(s->pc++);
4154	2c0262af	bellard	}
4155	2c0262af	bellard	gen_shifti(s, op, ot, opreg, shift);
4156	2c0262af	bellard	}
4157	2c0262af	bellard	}
4158	2c0262af	bellard	break;
4159	2c0262af	bellard	case 0xd0:
4160	2c0262af	bellard	case 0xd1:
4161	2c0262af	bellard	/* shift Ev,1 */
4162	2c0262af	bellard	shift = 1;
4163	2c0262af	bellard	goto grp2;
4164	2c0262af	bellard	case 0xd2:
4165	2c0262af	bellard	case 0xd3:
4166	2c0262af	bellard	/* shift Ev,cl */
4167	2c0262af	bellard	shift = 0;
4168	2c0262af	bellard	goto grp2;
4169	2c0262af	bellard
4170	2c0262af	bellard	case 0x1a4: /* shld imm */
4171	2c0262af	bellard	op = 0;
4172	2c0262af	bellard	shift = 1;
4173	2c0262af	bellard	goto do_shiftd;
4174	2c0262af	bellard	case 0x1a5: /* shld cl */
4175	2c0262af	bellard	op = 0;
4176	2c0262af	bellard	shift = 0;
4177	2c0262af	bellard	goto do_shiftd;
4178	2c0262af	bellard	case 0x1ac: /* shrd imm */
4179	2c0262af	bellard	op = 1;
4180	2c0262af	bellard	shift = 1;
4181	2c0262af	bellard	goto do_shiftd;
4182	2c0262af	bellard	case 0x1ad: /* shrd cl */
4183	2c0262af	bellard	op = 1;
4184	2c0262af	bellard	shift = 0;
4185	2c0262af	bellard	do_shiftd:
4186	14ce26e7	bellard	ot = dflag + OT_WORD;
4187	61382a50	bellard	modrm = ldub_code(s->pc++);
4188	2c0262af	bellard	mod = (modrm >> 6) & 3;
4189	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4190	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4191	2c0262af	bellard
4192	2c0262af	bellard	if (mod != 3) {
4193	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4194	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
4195	2c0262af	bellard	} else {
4196	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
4197	2c0262af	bellard	}
4198	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
4199	2c0262af	bellard
4200	2c0262af	bellard	if (shift) {
4201	61382a50	bellard	val = ldub_code(s->pc++);
4202	14ce26e7	bellard	if (ot == OT_QUAD)
4203	14ce26e7	bellard	val &= 0x3f;
4204	14ce26e7	bellard	else
4205	14ce26e7	bellard	val &= 0x1f;
4206	2c0262af	bellard	if (val) {
4207	2c0262af	bellard	if (mod == 3)
4208	4f31916f	bellard	gen_op_shiftd_T0_T1_im_cc[ot][op](val);
4209	2c0262af	bellard	else
4210	4f31916f	bellard	gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
4211	2c0262af	bellard	if (op == 0 && ot != OT_WORD)
4212	2c0262af	bellard	s->cc_op = CC_OP_SHLB + ot;
4213	2c0262af	bellard	else
4214	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
4215	2c0262af	bellard	}
4216	2c0262af	bellard	} else {
4217	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4218	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4219	2c0262af	bellard	if (mod == 3)
4220	4f31916f	bellard	gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
4221	2c0262af	bellard	else
4222	4f31916f	bellard	gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
4223	2c0262af	bellard	s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
4224	2c0262af	bellard	}
4225	2c0262af	bellard	if (mod == 3) {
4226	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
4227	2c0262af	bellard	}
4228	2c0262af	bellard	break;
4229	2c0262af	bellard
4230	2c0262af	bellard	/************************/
4231	2c0262af	bellard	/* floats */
4232	2c0262af	bellard	case 0xd8 ... 0xdf:
4233	7eee2a50	bellard	if (s->flags & (HF_EM_MASK \| HF_TS_MASK)) {
4234	7eee2a50	bellard	/* if CR0.EM or CR0.TS are set, generate an FPU exception */
4235	7eee2a50	bellard	/* XXX: what to do if illegal op ? */
4236	7eee2a50	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
4237	7eee2a50	bellard	break;
4238	7eee2a50	bellard	}
4239	61382a50	bellard	modrm = ldub_code(s->pc++);
4240	2c0262af	bellard	mod = (modrm >> 6) & 3;
4241	2c0262af	bellard	rm = modrm & 7;
4242	2c0262af	bellard	op = ((b & 7) << 3) \| ((modrm >> 3) & 7);
4243	2c0262af	bellard	if (mod != 3) {
4244	2c0262af	bellard	/* memory op */
4245	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4246	2c0262af	bellard	switch(op) {
4247	2c0262af	bellard	case 0x00 ... 0x07: /* fxxxs */
4248	2c0262af	bellard	case 0x10 ... 0x17: /* fixxxl */
4249	2c0262af	bellard	case 0x20 ... 0x27: /* fxxxl */
4250	2c0262af	bellard	case 0x30 ... 0x37: /* fixxx */
4251	2c0262af	bellard	{
4252	2c0262af	bellard	int op1;
4253	2c0262af	bellard	op1 = op & 7;
4254	2c0262af	bellard
4255	2c0262af	bellard	switch(op >> 4) {
4256	2c0262af	bellard	case 0:
4257	2c0262af	bellard	gen_op_flds_FT0_A0();
4258	2c0262af	bellard	break;
4259	2c0262af	bellard	case 1:
4260	2c0262af	bellard	gen_op_fildl_FT0_A0();
4261	2c0262af	bellard	break;
4262	2c0262af	bellard	case 2:
4263	2c0262af	bellard	gen_op_fldl_FT0_A0();
4264	2c0262af	bellard	break;
4265	2c0262af	bellard	case 3:
4266	2c0262af	bellard	default:
4267	2c0262af	bellard	gen_op_fild_FT0_A0();
4268	2c0262af	bellard	break;
4269	2c0262af	bellard	}
4270	2c0262af	bellard
4271	2c0262af	bellard	gen_op_fp_arith_ST0_FT0[op1]();
4272	2c0262af	bellard	if (op1 == 3) {
4273	2c0262af	bellard	/* fcomp needs pop */
4274	2c0262af	bellard	gen_op_fpop();
4275	2c0262af	bellard	}
4276	2c0262af	bellard	}
4277	2c0262af	bellard	break;
4278	2c0262af	bellard	case 0x08: /* flds */
4279	2c0262af	bellard	case 0x0a: /* fsts */
4280	2c0262af	bellard	case 0x0b: /* fstps */
4281	2c0262af	bellard	case 0x18: /* fildl */
4282	2c0262af	bellard	case 0x1a: /* fistl */
4283	2c0262af	bellard	case 0x1b: /* fistpl */
4284	2c0262af	bellard	case 0x28: /* fldl */
4285	2c0262af	bellard	case 0x2a: /* fstl */
4286	2c0262af	bellard	case 0x2b: /* fstpl */
4287	2c0262af	bellard	case 0x38: /* filds */
4288	2c0262af	bellard	case 0x3a: /* fists */
4289	2c0262af	bellard	case 0x3b: /* fistps */
4290	2c0262af	bellard
4291	2c0262af	bellard	switch(op & 7) {
4292	2c0262af	bellard	case 0:
4293	2c0262af	bellard	switch(op >> 4) {
4294	2c0262af	bellard	case 0:
4295	2c0262af	bellard	gen_op_flds_ST0_A0();
4296	2c0262af	bellard	break;
4297	2c0262af	bellard	case 1:
4298	2c0262af	bellard	gen_op_fildl_ST0_A0();
4299	2c0262af	bellard	break;
4300	2c0262af	bellard	case 2:
4301	2c0262af	bellard	gen_op_fldl_ST0_A0();
4302	2c0262af	bellard	break;
4303	2c0262af	bellard	case 3:
4304	2c0262af	bellard	default:
4305	2c0262af	bellard	gen_op_fild_ST0_A0();
4306	2c0262af	bellard	break;
4307	2c0262af	bellard	}
4308	2c0262af	bellard	break;
4309	2c0262af	bellard	default:
4310	2c0262af	bellard	switch(op >> 4) {
4311	2c0262af	bellard	case 0:
4312	2c0262af	bellard	gen_op_fsts_ST0_A0();
4313	2c0262af	bellard	break;
4314	2c0262af	bellard	case 1:
4315	2c0262af	bellard	gen_op_fistl_ST0_A0();
4316	2c0262af	bellard	break;
4317	2c0262af	bellard	case 2:
4318	2c0262af	bellard	gen_op_fstl_ST0_A0();
4319	2c0262af	bellard	break;
4320	2c0262af	bellard	case 3:
4321	2c0262af	bellard	default:
4322	2c0262af	bellard	gen_op_fist_ST0_A0();
4323	2c0262af	bellard	break;
4324	2c0262af	bellard	}
4325	2c0262af	bellard	if ((op & 7) == 3)
4326	2c0262af	bellard	gen_op_fpop();
4327	2c0262af	bellard	break;
4328	2c0262af	bellard	}
4329	2c0262af	bellard	break;
4330	2c0262af	bellard	case 0x0c: /* fldenv mem */
4331	2c0262af	bellard	gen_op_fldenv_A0(s->dflag);
4332	2c0262af	bellard	break;
4333	2c0262af	bellard	case 0x0d: /* fldcw mem */
4334	2c0262af	bellard	gen_op_fldcw_A0();
4335	2c0262af	bellard	break;
4336	2c0262af	bellard	case 0x0e: /* fnstenv mem */
4337	2c0262af	bellard	gen_op_fnstenv_A0(s->dflag);
4338	2c0262af	bellard	break;
4339	2c0262af	bellard	case 0x0f: /* fnstcw mem */
4340	2c0262af	bellard	gen_op_fnstcw_A0();
4341	2c0262af	bellard	break;
4342	2c0262af	bellard	case 0x1d: /* fldt mem */
4343	2c0262af	bellard	gen_op_fldt_ST0_A0();
4344	2c0262af	bellard	break;
4345	2c0262af	bellard	case 0x1f: /* fstpt mem */
4346	2c0262af	bellard	gen_op_fstt_ST0_A0();
4347	2c0262af	bellard	gen_op_fpop();
4348	2c0262af	bellard	break;
4349	2c0262af	bellard	case 0x2c: /* frstor mem */
4350	2c0262af	bellard	gen_op_frstor_A0(s->dflag);
4351	2c0262af	bellard	break;
4352	2c0262af	bellard	case 0x2e: /* fnsave mem */
4353	2c0262af	bellard	gen_op_fnsave_A0(s->dflag);
4354	2c0262af	bellard	break;
4355	2c0262af	bellard	case 0x2f: /* fnstsw mem */
4356	2c0262af	bellard	gen_op_fnstsw_A0();
4357	2c0262af	bellard	break;
4358	2c0262af	bellard	case 0x3c: /* fbld */
4359	2c0262af	bellard	gen_op_fbld_ST0_A0();
4360	2c0262af	bellard	break;
4361	2c0262af	bellard	case 0x3e: /* fbstp */
4362	2c0262af	bellard	gen_op_fbst_ST0_A0();
4363	2c0262af	bellard	gen_op_fpop();
4364	2c0262af	bellard	break;
4365	2c0262af	bellard	case 0x3d: /* fildll */
4366	2c0262af	bellard	gen_op_fildll_ST0_A0();
4367	2c0262af	bellard	break;
4368	2c0262af	bellard	case 0x3f: /* fistpll */
4369	2c0262af	bellard	gen_op_fistll_ST0_A0();
4370	2c0262af	bellard	gen_op_fpop();
4371	2c0262af	bellard	break;
4372	2c0262af	bellard	default:
4373	2c0262af	bellard	goto illegal_op;
4374	2c0262af	bellard	}
4375	2c0262af	bellard	} else {
4376	2c0262af	bellard	/* register float ops */
4377	2c0262af	bellard	opreg = rm;
4378	2c0262af	bellard
4379	2c0262af	bellard	switch(op) {
4380	2c0262af	bellard	case 0x08: /* fld sti */
4381	2c0262af	bellard	gen_op_fpush();
4382	2c0262af	bellard	gen_op_fmov_ST0_STN((opreg + 1) & 7);
4383	2c0262af	bellard	break;
4384	2c0262af	bellard	case 0x09: /* fxchg sti */
4385	c169c906	bellard	case 0x29: /* fxchg4 sti, undocumented op */
4386	c169c906	bellard	case 0x39: /* fxchg7 sti, undocumented op */
4387	2c0262af	bellard	gen_op_fxchg_ST0_STN(opreg);
4388	2c0262af	bellard	break;
4389	2c0262af	bellard	case 0x0a: /* grp d9/2 */
4390	2c0262af	bellard	switch(rm) {
4391	2c0262af	bellard	case 0: /* fnop */
4392	023fe10d	bellard	/* check exceptions (FreeBSD FPU probe) */
4393	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4394	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
4395	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4396	023fe10d	bellard	gen_op_fwait();
4397	2c0262af	bellard	break;
4398	2c0262af	bellard	default:
4399	2c0262af	bellard	goto illegal_op;
4400	2c0262af	bellard	}
4401	2c0262af	bellard	break;
4402	2c0262af	bellard	case 0x0c: /* grp d9/4 */
4403	2c0262af	bellard	switch(rm) {
4404	2c0262af	bellard	case 0: /* fchs */
4405	2c0262af	bellard	gen_op_fchs_ST0();
4406	2c0262af	bellard	break;
4407	2c0262af	bellard	case 1: /* fabs */
4408	2c0262af	bellard	gen_op_fabs_ST0();
4409	2c0262af	bellard	break;
4410	2c0262af	bellard	case 4: /* ftst */
4411	2c0262af	bellard	gen_op_fldz_FT0();
4412	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4413	2c0262af	bellard	break;
4414	2c0262af	bellard	case 5: /* fxam */
4415	2c0262af	bellard	gen_op_fxam_ST0();
4416	2c0262af	bellard	break;
4417	2c0262af	bellard	default:
4418	2c0262af	bellard	goto illegal_op;
4419	2c0262af	bellard	}
4420	2c0262af	bellard	break;
4421	2c0262af	bellard	case 0x0d: /* grp d9/5 */
4422	2c0262af	bellard	{
4423	2c0262af	bellard	switch(rm) {
4424	2c0262af	bellard	case 0:
4425	2c0262af	bellard	gen_op_fpush();
4426	2c0262af	bellard	gen_op_fld1_ST0();
4427	2c0262af	bellard	break;
4428	2c0262af	bellard	case 1:
4429	2c0262af	bellard	gen_op_fpush();
4430	2c0262af	bellard	gen_op_fldl2t_ST0();
4431	2c0262af	bellard	break;
4432	2c0262af	bellard	case 2:
4433	2c0262af	bellard	gen_op_fpush();
4434	2c0262af	bellard	gen_op_fldl2e_ST0();
4435	2c0262af	bellard	break;
4436	2c0262af	bellard	case 3:
4437	2c0262af	bellard	gen_op_fpush();
4438	2c0262af	bellard	gen_op_fldpi_ST0();
4439	2c0262af	bellard	break;
4440	2c0262af	bellard	case 4:
4441	2c0262af	bellard	gen_op_fpush();
4442	2c0262af	bellard	gen_op_fldlg2_ST0();
4443	2c0262af	bellard	break;
4444	2c0262af	bellard	case 5:
4445	2c0262af	bellard	gen_op_fpush();
4446	2c0262af	bellard	gen_op_fldln2_ST0();
4447	2c0262af	bellard	break;
4448	2c0262af	bellard	case 6:
4449	2c0262af	bellard	gen_op_fpush();
4450	2c0262af	bellard	gen_op_fldz_ST0();
4451	2c0262af	bellard	break;
4452	2c0262af	bellard	default:
4453	2c0262af	bellard	goto illegal_op;
4454	2c0262af	bellard	}
4455	2c0262af	bellard	}
4456	2c0262af	bellard	break;
4457	2c0262af	bellard	case 0x0e: /* grp d9/6 */
4458	2c0262af	bellard	switch(rm) {
4459	2c0262af	bellard	case 0: /* f2xm1 */
4460	2c0262af	bellard	gen_op_f2xm1();
4461	2c0262af	bellard	break;
4462	2c0262af	bellard	case 1: /* fyl2x */
4463	2c0262af	bellard	gen_op_fyl2x();
4464	2c0262af	bellard	break;
4465	2c0262af	bellard	case 2: /* fptan */
4466	2c0262af	bellard	gen_op_fptan();
4467	2c0262af	bellard	break;
4468	2c0262af	bellard	case 3: /* fpatan */
4469	2c0262af	bellard	gen_op_fpatan();
4470	2c0262af	bellard	break;
4471	2c0262af	bellard	case 4: /* fxtract */
4472	2c0262af	bellard	gen_op_fxtract();
4473	2c0262af	bellard	break;
4474	2c0262af	bellard	case 5: /* fprem1 */
4475	2c0262af	bellard	gen_op_fprem1();
4476	2c0262af	bellard	break;
4477	2c0262af	bellard	case 6: /* fdecstp */
4478	2c0262af	bellard	gen_op_fdecstp();
4479	2c0262af	bellard	break;
4480	2c0262af	bellard	default:
4481	2c0262af	bellard	case 7: /* fincstp */
4482	2c0262af	bellard	gen_op_fincstp();
4483	2c0262af	bellard	break;
4484	2c0262af	bellard	}
4485	2c0262af	bellard	break;
4486	2c0262af	bellard	case 0x0f: /* grp d9/7 */
4487	2c0262af	bellard	switch(rm) {
4488	2c0262af	bellard	case 0: /* fprem */
4489	2c0262af	bellard	gen_op_fprem();
4490	2c0262af	bellard	break;
4491	2c0262af	bellard	case 1: /* fyl2xp1 */
4492	2c0262af	bellard	gen_op_fyl2xp1();
4493	2c0262af	bellard	break;
4494	2c0262af	bellard	case 2: /* fsqrt */
4495	2c0262af	bellard	gen_op_fsqrt();
4496	2c0262af	bellard	break;
4497	2c0262af	bellard	case 3: /* fsincos */
4498	2c0262af	bellard	gen_op_fsincos();
4499	2c0262af	bellard	break;
4500	2c0262af	bellard	case 5: /* fscale */
4501	2c0262af	bellard	gen_op_fscale();
4502	2c0262af	bellard	break;
4503	2c0262af	bellard	case 4: /* frndint */
4504	2c0262af	bellard	gen_op_frndint();
4505	2c0262af	bellard	break;
4506	2c0262af	bellard	case 6: /* fsin */
4507	2c0262af	bellard	gen_op_fsin();
4508	2c0262af	bellard	break;
4509	2c0262af	bellard	default:
4510	2c0262af	bellard	case 7: /* fcos */
4511	2c0262af	bellard	gen_op_fcos();
4512	2c0262af	bellard	break;
4513	2c0262af	bellard	}
4514	2c0262af	bellard	break;
4515	2c0262af	bellard	case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
4516	2c0262af	bellard	case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
4517	2c0262af	bellard	case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
4518	2c0262af	bellard	{
4519	2c0262af	bellard	int op1;
4520	2c0262af	bellard
4521	2c0262af	bellard	op1 = op & 7;
4522	2c0262af	bellard	if (op >= 0x20) {
4523	2c0262af	bellard	gen_op_fp_arith_STN_ST0[op1](opreg);
4524	2c0262af	bellard	if (op >= 0x30)
4525	2c0262af	bellard	gen_op_fpop();
4526	2c0262af	bellard	} else {
4527	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4528	2c0262af	bellard	gen_op_fp_arith_ST0_FT0[op1]();
4529	2c0262af	bellard	}
4530	2c0262af	bellard	}
4531	2c0262af	bellard	break;
4532	2c0262af	bellard	case 0x02: /* fcom */
4533	c169c906	bellard	case 0x22: /* fcom2, undocumented op */
4534	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4535	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4536	2c0262af	bellard	break;
4537	2c0262af	bellard	case 0x03: /* fcomp */
4538	c169c906	bellard	case 0x23: /* fcomp3, undocumented op */
4539	c169c906	bellard	case 0x32: /* fcomp5, undocumented op */
4540	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4541	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4542	2c0262af	bellard	gen_op_fpop();
4543	2c0262af	bellard	break;
4544	2c0262af	bellard	case 0x15: /* da/5 */
4545	2c0262af	bellard	switch(rm) {
4546	2c0262af	bellard	case 1: /* fucompp */
4547	2c0262af	bellard	gen_op_fmov_FT0_STN(1);
4548	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4549	2c0262af	bellard	gen_op_fpop();
4550	2c0262af	bellard	gen_op_fpop();
4551	2c0262af	bellard	break;
4552	2c0262af	bellard	default:
4553	2c0262af	bellard	goto illegal_op;
4554	2c0262af	bellard	}
4555	2c0262af	bellard	break;
4556	2c0262af	bellard	case 0x1c:
4557	2c0262af	bellard	switch(rm) {
4558	2c0262af	bellard	case 0: /* feni (287 only, just do nop here) */
4559	2c0262af	bellard	break;
4560	2c0262af	bellard	case 1: /* fdisi (287 only, just do nop here) */
4561	2c0262af	bellard	break;
4562	2c0262af	bellard	case 2: /* fclex */
4563	2c0262af	bellard	gen_op_fclex();
4564	2c0262af	bellard	break;
4565	2c0262af	bellard	case 3: /* fninit */
4566	2c0262af	bellard	gen_op_fninit();
4567	2c0262af	bellard	break;
4568	2c0262af	bellard	case 4: /* fsetpm (287 only, just do nop here) */
4569	2c0262af	bellard	break;
4570	2c0262af	bellard	default:
4571	2c0262af	bellard	goto illegal_op;
4572	2c0262af	bellard	}
4573	2c0262af	bellard	break;
4574	2c0262af	bellard	case 0x1d: /* fucomi */
4575	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4576	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4577	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4578	2c0262af	bellard	gen_op_fucomi_ST0_FT0();
4579	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4580	2c0262af	bellard	break;
4581	2c0262af	bellard	case 0x1e: /* fcomi */
4582	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4583	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4584	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4585	2c0262af	bellard	gen_op_fcomi_ST0_FT0();
4586	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4587	2c0262af	bellard	break;
4588	658c8bda	bellard	case 0x28: /* ffree sti */
4589	658c8bda	bellard	gen_op_ffree_STN(opreg);
4590	658c8bda	bellard	break;
4591	2c0262af	bellard	case 0x2a: /* fst sti */
4592	2c0262af	bellard	gen_op_fmov_STN_ST0(opreg);
4593	2c0262af	bellard	break;
4594	2c0262af	bellard	case 0x2b: /* fstp sti */
4595	c169c906	bellard	case 0x0b: /* fstp1 sti, undocumented op */
4596	c169c906	bellard	case 0x3a: /* fstp8 sti, undocumented op */
4597	c169c906	bellard	case 0x3b: /* fstp9 sti, undocumented op */
4598	2c0262af	bellard	gen_op_fmov_STN_ST0(opreg);
4599	2c0262af	bellard	gen_op_fpop();
4600	2c0262af	bellard	break;
4601	2c0262af	bellard	case 0x2c: /* fucom st(i) */
4602	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4603	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4604	2c0262af	bellard	break;
4605	2c0262af	bellard	case 0x2d: /* fucomp st(i) */
4606	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4607	2c0262af	bellard	gen_op_fucom_ST0_FT0();
4608	2c0262af	bellard	gen_op_fpop();
4609	2c0262af	bellard	break;
4610	2c0262af	bellard	case 0x33: /* de/3 */
4611	2c0262af	bellard	switch(rm) {
4612	2c0262af	bellard	case 1: /* fcompp */
4613	2c0262af	bellard	gen_op_fmov_FT0_STN(1);
4614	2c0262af	bellard	gen_op_fcom_ST0_FT0();
4615	2c0262af	bellard	gen_op_fpop();
4616	2c0262af	bellard	gen_op_fpop();
4617	2c0262af	bellard	break;
4618	2c0262af	bellard	default:
4619	2c0262af	bellard	goto illegal_op;
4620	2c0262af	bellard	}
4621	2c0262af	bellard	break;
4622	c169c906	bellard	case 0x38: /* ffreep sti, undocumented op */
4623	c169c906	bellard	gen_op_ffree_STN(opreg);
4624	c169c906	bellard	gen_op_fpop();
4625	c169c906	bellard	break;
4626	2c0262af	bellard	case 0x3c: /* df/4 */
4627	2c0262af	bellard	switch(rm) {
4628	2c0262af	bellard	case 0:
4629	2c0262af	bellard	gen_op_fnstsw_EAX();
4630	2c0262af	bellard	break;
4631	2c0262af	bellard	default:
4632	2c0262af	bellard	goto illegal_op;
4633	2c0262af	bellard	}
4634	2c0262af	bellard	break;
4635	2c0262af	bellard	case 0x3d: /* fucomip */
4636	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4637	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4638	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4639	2c0262af	bellard	gen_op_fucomi_ST0_FT0();
4640	2c0262af	bellard	gen_op_fpop();
4641	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4642	2c0262af	bellard	break;
4643	2c0262af	bellard	case 0x3e: /* fcomip */
4644	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4645	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4646	2c0262af	bellard	gen_op_fmov_FT0_STN(opreg);
4647	2c0262af	bellard	gen_op_fcomi_ST0_FT0();
4648	2c0262af	bellard	gen_op_fpop();
4649	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4650	2c0262af	bellard	break;
4651	a2cc3b24	bellard	case 0x10 ... 0x13: /* fcmovxx */
4652	a2cc3b24	bellard	case 0x18 ... 0x1b:
4653	a2cc3b24	bellard	{
4654	a2cc3b24	bellard	int op1;
4655	a2cc3b24	bellard	const static uint8_t fcmov_cc[8] = {
4656	a2cc3b24	bellard	(JCC_B << 1),
4657	a2cc3b24	bellard	(JCC_Z << 1),
4658	a2cc3b24	bellard	(JCC_BE << 1),
4659	a2cc3b24	bellard	(JCC_P << 1),
4660	a2cc3b24	bellard	};
4661	a2cc3b24	bellard	op1 = fcmov_cc[op & 3] \| ((op >> 3) & 1);
4662	a2cc3b24	bellard	gen_setcc(s, op1);
4663	a2cc3b24	bellard	gen_op_fcmov_ST0_STN_T0(opreg);
4664	a2cc3b24	bellard	}
4665	a2cc3b24	bellard	break;
4666	2c0262af	bellard	default:
4667	2c0262af	bellard	goto illegal_op;
4668	2c0262af	bellard	}
4669	2c0262af	bellard	}
4670	7eee2a50	bellard	#ifdef USE_CODE_COPY
4671	7eee2a50	bellard	s->tb->cflags \|= CF_TB_FP_USED;
4672	7eee2a50	bellard	#endif
4673	2c0262af	bellard	break;
4674	2c0262af	bellard	/************************/
4675	2c0262af	bellard	/* string ops */
4676	2c0262af	bellard
4677	2c0262af	bellard	case 0xa4: /* movsS */
4678	2c0262af	bellard	case 0xa5:
4679	2c0262af	bellard	if ((b & 1) == 0)
4680	2c0262af	bellard	ot = OT_BYTE;
4681	2c0262af	bellard	else
4682	14ce26e7	bellard	ot = dflag + OT_WORD;
4683	2c0262af	bellard
4684	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4685	2c0262af	bellard	gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4686	2c0262af	bellard	} else {
4687	2c0262af	bellard	gen_movs(s, ot);
4688	2c0262af	bellard	}
4689	2c0262af	bellard	break;
4690	2c0262af	bellard
4691	2c0262af	bellard	case 0xaa: /* stosS */
4692	2c0262af	bellard	case 0xab:
4693	2c0262af	bellard	if ((b & 1) == 0)
4694	2c0262af	bellard	ot = OT_BYTE;
4695	2c0262af	bellard	else
4696	14ce26e7	bellard	ot = dflag + OT_WORD;
4697	2c0262af	bellard
4698	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4699	2c0262af	bellard	gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4700	2c0262af	bellard	} else {
4701	2c0262af	bellard	gen_stos(s, ot);
4702	2c0262af	bellard	}
4703	2c0262af	bellard	break;
4704	2c0262af	bellard	case 0xac: /* lodsS */
4705	2c0262af	bellard	case 0xad:
4706	2c0262af	bellard	if ((b & 1) == 0)
4707	2c0262af	bellard	ot = OT_BYTE;
4708	2c0262af	bellard	else
4709	14ce26e7	bellard	ot = dflag + OT_WORD;
4710	2c0262af	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4711	2c0262af	bellard	gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4712	2c0262af	bellard	} else {
4713	2c0262af	bellard	gen_lods(s, ot);
4714	2c0262af	bellard	}
4715	2c0262af	bellard	break;
4716	2c0262af	bellard	case 0xae: /* scasS */
4717	2c0262af	bellard	case 0xaf:
4718	2c0262af	bellard	if ((b & 1) == 0)
4719	2c0262af	bellard	ot = OT_BYTE;
4720	2c0262af	bellard	else
4721	14ce26e7	bellard	ot = dflag + OT_WORD;
4722	2c0262af	bellard	if (prefixes & PREFIX_REPNZ) {
4723	2c0262af	bellard	gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4724	2c0262af	bellard	} else if (prefixes & PREFIX_REPZ) {
4725	2c0262af	bellard	gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4726	2c0262af	bellard	} else {
4727	2c0262af	bellard	gen_scas(s, ot);
4728	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
4729	2c0262af	bellard	}
4730	2c0262af	bellard	break;
4731	2c0262af	bellard
4732	2c0262af	bellard	case 0xa6: /* cmpsS */
4733	2c0262af	bellard	case 0xa7:
4734	2c0262af	bellard	if ((b & 1) == 0)
4735	2c0262af	bellard	ot = OT_BYTE;
4736	2c0262af	bellard	else
4737	14ce26e7	bellard	ot = dflag + OT_WORD;
4738	2c0262af	bellard	if (prefixes & PREFIX_REPNZ) {
4739	2c0262af	bellard	gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4740	2c0262af	bellard	} else if (prefixes & PREFIX_REPZ) {
4741	2c0262af	bellard	gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4742	2c0262af	bellard	} else {
4743	2c0262af	bellard	gen_cmps(s, ot);
4744	2c0262af	bellard	s->cc_op = CC_OP_SUBB + ot;
4745	2c0262af	bellard	}
4746	2c0262af	bellard	break;
4747	2c0262af	bellard	case 0x6c: /* insS */
4748	2c0262af	bellard	case 0x6d:
4749	f115e911	bellard	if ((b & 1) == 0)
4750	f115e911	bellard	ot = OT_BYTE;
4751	f115e911	bellard	else
4752	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4753	f115e911	bellard	gen_check_io(s, ot, 1, pc_start - s->cs_base);
4754	f115e911	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4755	f115e911	bellard	gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4756	2c0262af	bellard	} else {
4757	f115e911	bellard	gen_ins(s, ot);
4758	2c0262af	bellard	}
4759	2c0262af	bellard	break;
4760	2c0262af	bellard	case 0x6e: /* outsS */
4761	2c0262af	bellard	case 0x6f:
4762	f115e911	bellard	if ((b & 1) == 0)
4763	f115e911	bellard	ot = OT_BYTE;
4764	f115e911	bellard	else
4765	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4766	f115e911	bellard	gen_check_io(s, ot, 1, pc_start - s->cs_base);
4767	f115e911	bellard	if (prefixes & (PREFIX_REPZ \| PREFIX_REPNZ)) {
4768	f115e911	bellard	gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4769	2c0262af	bellard	} else {
4770	f115e911	bellard	gen_outs(s, ot);
4771	2c0262af	bellard	}
4772	2c0262af	bellard	break;
4773	2c0262af	bellard
4774	2c0262af	bellard	/************************/
4775	2c0262af	bellard	/* port I/O */
4776	2c0262af	bellard	case 0xe4:
4777	2c0262af	bellard	case 0xe5:
4778	f115e911	bellard	if ((b & 1) == 0)
4779	f115e911	bellard	ot = OT_BYTE;
4780	f115e911	bellard	else
4781	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4782	f115e911	bellard	val = ldub_code(s->pc++);
4783	f115e911	bellard	gen_op_movl_T0_im(val);
4784	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4785	f115e911	bellard	gen_op_in[ot]();
4786	f115e911	bellard	gen_op_mov_reg_T1[ot][R_EAX]();
4787	2c0262af	bellard	break;
4788	2c0262af	bellard	case 0xe6:
4789	2c0262af	bellard	case 0xe7:
4790	f115e911	bellard	if ((b & 1) == 0)
4791	f115e911	bellard	ot = OT_BYTE;
4792	f115e911	bellard	else
4793	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4794	f115e911	bellard	val = ldub_code(s->pc++);
4795	f115e911	bellard	gen_op_movl_T0_im(val);
4796	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4797	f115e911	bellard	gen_op_mov_TN_reg[ot][1][R_EAX]();
4798	f115e911	bellard	gen_op_out[ot]();
4799	2c0262af	bellard	break;
4800	2c0262af	bellard	case 0xec:
4801	2c0262af	bellard	case 0xed:
4802	f115e911	bellard	if ((b & 1) == 0)
4803	f115e911	bellard	ot = OT_BYTE;
4804	f115e911	bellard	else
4805	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4806	f115e911	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4807	4f31916f	bellard	gen_op_andl_T0_ffff();
4808	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4809	f115e911	bellard	gen_op_in[ot]();
4810	f115e911	bellard	gen_op_mov_reg_T1[ot][R_EAX]();
4811	2c0262af	bellard	break;
4812	2c0262af	bellard	case 0xee:
4813	2c0262af	bellard	case 0xef:
4814	f115e911	bellard	if ((b & 1) == 0)
4815	f115e911	bellard	ot = OT_BYTE;
4816	f115e911	bellard	else
4817	f115e911	bellard	ot = dflag ? OT_LONG : OT_WORD;
4818	f115e911	bellard	gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4819	4f31916f	bellard	gen_op_andl_T0_ffff();
4820	f115e911	bellard	gen_check_io(s, ot, 0, pc_start - s->cs_base);
4821	f115e911	bellard	gen_op_mov_TN_reg[ot][1][R_EAX]();
4822	f115e911	bellard	gen_op_out[ot]();
4823	2c0262af	bellard	break;
4824	2c0262af	bellard
4825	2c0262af	bellard	/************************/
4826	2c0262af	bellard	/* control */
4827	2c0262af	bellard	case 0xc2: /* ret im */
4828	61382a50	bellard	val = ldsw_code(s->pc);
4829	2c0262af	bellard	s->pc += 2;
4830	2c0262af	bellard	gen_pop_T0(s);
4831	8f091a59	bellard	if (CODE64(s) && s->dflag)
4832	8f091a59	bellard	s->dflag = 2;
4833	2c0262af	bellard	gen_stack_update(s, val + (2 << s->dflag));
4834	2c0262af	bellard	if (s->dflag == 0)
4835	2c0262af	bellard	gen_op_andl_T0_ffff();
4836	2c0262af	bellard	gen_op_jmp_T0();
4837	2c0262af	bellard	gen_eob(s);
4838	2c0262af	bellard	break;
4839	2c0262af	bellard	case 0xc3: /* ret */
4840	2c0262af	bellard	gen_pop_T0(s);
4841	2c0262af	bellard	gen_pop_update(s);
4842	2c0262af	bellard	if (s->dflag == 0)
4843	2c0262af	bellard	gen_op_andl_T0_ffff();
4844	2c0262af	bellard	gen_op_jmp_T0();
4845	2c0262af	bellard	gen_eob(s);
4846	2c0262af	bellard	break;
4847	2c0262af	bellard	case 0xca: /* lret im */
4848	61382a50	bellard	val = ldsw_code(s->pc);
4849	2c0262af	bellard	s->pc += 2;
4850	2c0262af	bellard	do_lret:
4851	2c0262af	bellard	if (s->pe && !s->vm86) {
4852	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4853	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4854	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4855	2c0262af	bellard	gen_op_lret_protected(s->dflag, val);
4856	2c0262af	bellard	} else {
4857	2c0262af	bellard	gen_stack_A0(s);
4858	2c0262af	bellard	/* pop offset */
4859	2c0262af	bellard	gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4860	2c0262af	bellard	if (s->dflag == 0)
4861	2c0262af	bellard	gen_op_andl_T0_ffff();
4862	2c0262af	bellard	/* NOTE: keeping EIP updated is not a problem in case of
4863	2c0262af	bellard	exception */
4864	2c0262af	bellard	gen_op_jmp_T0();
4865	2c0262af	bellard	/* pop selector */
4866	2c0262af	bellard	gen_op_addl_A0_im(2 << s->dflag);
4867	2c0262af	bellard	gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4868	2c0262af	bellard	gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
4869	2c0262af	bellard	/* add stack offset */
4870	2c0262af	bellard	gen_stack_update(s, val + (4 << s->dflag));
4871	2c0262af	bellard	}
4872	2c0262af	bellard	gen_eob(s);
4873	2c0262af	bellard	break;
4874	2c0262af	bellard	case 0xcb: /* lret */
4875	2c0262af	bellard	val = 0;
4876	2c0262af	bellard	goto do_lret;
4877	2c0262af	bellard	case 0xcf: /* iret */
4878	2c0262af	bellard	if (!s->pe) {
4879	2c0262af	bellard	/* real mode */
4880	2c0262af	bellard	gen_op_iret_real(s->dflag);
4881	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4882	f115e911	bellard	} else if (s->vm86) {
4883	f115e911	bellard	if (s->iopl != 3) {
4884	f115e911	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4885	f115e911	bellard	} else {
4886	f115e911	bellard	gen_op_iret_real(s->dflag);
4887	f115e911	bellard	s->cc_op = CC_OP_EFLAGS;
4888	f115e911	bellard	}
4889	2c0262af	bellard	} else {
4890	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
4891	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
4892	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
4893	08cea4ee	bellard	gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
4894	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
4895	2c0262af	bellard	}
4896	2c0262af	bellard	gen_eob(s);
4897	2c0262af	bellard	break;
4898	2c0262af	bellard	case 0xe8: /* call im */
4899	2c0262af	bellard	{
4900	14ce26e7	bellard	if (dflag)
4901	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4902	14ce26e7	bellard	else
4903	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4904	2c0262af	bellard	next_eip = s->pc - s->cs_base;
4905	14ce26e7	bellard	tval += next_eip;
4906	2c0262af	bellard	if (s->dflag == 0)
4907	14ce26e7	bellard	tval &= 0xffff;
4908	14ce26e7	bellard	gen_movtl_T0_im(next_eip);
4909	2c0262af	bellard	gen_push_T0(s);
4910	14ce26e7	bellard	gen_jmp(s, tval);
4911	2c0262af	bellard	}
4912	2c0262af	bellard	break;
4913	2c0262af	bellard	case 0x9a: /* lcall im */
4914	2c0262af	bellard	{
4915	2c0262af	bellard	unsigned int selector, offset;
4916	14ce26e7	bellard
4917	14ce26e7	bellard	if (CODE64(s))
4918	14ce26e7	bellard	goto illegal_op;
4919	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4920	2c0262af	bellard	offset = insn_get(s, ot);
4921	2c0262af	bellard	selector = insn_get(s, OT_WORD);
4922	2c0262af	bellard
4923	2c0262af	bellard	gen_op_movl_T0_im(selector);
4924	14ce26e7	bellard	gen_op_movl_T1_imu(offset);
4925	2c0262af	bellard	}
4926	2c0262af	bellard	goto do_lcall;
4927	ecada8a2	bellard	case 0xe9: /* jmp im */
4928	14ce26e7	bellard	if (dflag)
4929	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4930	14ce26e7	bellard	else
4931	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4932	14ce26e7	bellard	tval += s->pc - s->cs_base;
4933	2c0262af	bellard	if (s->dflag == 0)
4934	14ce26e7	bellard	tval &= 0xffff;
4935	14ce26e7	bellard	gen_jmp(s, tval);
4936	2c0262af	bellard	break;
4937	2c0262af	bellard	case 0xea: /* ljmp im */
4938	2c0262af	bellard	{
4939	2c0262af	bellard	unsigned int selector, offset;
4940	2c0262af	bellard
4941	14ce26e7	bellard	if (CODE64(s))
4942	14ce26e7	bellard	goto illegal_op;
4943	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
4944	2c0262af	bellard	offset = insn_get(s, ot);
4945	2c0262af	bellard	selector = insn_get(s, OT_WORD);
4946	2c0262af	bellard
4947	2c0262af	bellard	gen_op_movl_T0_im(selector);
4948	14ce26e7	bellard	gen_op_movl_T1_imu(offset);
4949	2c0262af	bellard	}
4950	2c0262af	bellard	goto do_ljmp;
4951	2c0262af	bellard	case 0xeb: /* jmp Jb */
4952	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
4953	14ce26e7	bellard	tval += s->pc - s->cs_base;
4954	2c0262af	bellard	if (s->dflag == 0)
4955	14ce26e7	bellard	tval &= 0xffff;
4956	14ce26e7	bellard	gen_jmp(s, tval);
4957	2c0262af	bellard	break;
4958	2c0262af	bellard	case 0x70 ... 0x7f: /* jcc Jb */
4959	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
4960	2c0262af	bellard	goto do_jcc;
4961	2c0262af	bellard	case 0x180 ... 0x18f: /* jcc Jv */
4962	2c0262af	bellard	if (dflag) {
4963	14ce26e7	bellard	tval = (int32_t)insn_get(s, OT_LONG);
4964	2c0262af	bellard	} else {
4965	14ce26e7	bellard	tval = (int16_t)insn_get(s, OT_WORD);
4966	2c0262af	bellard	}
4967	2c0262af	bellard	do_jcc:
4968	2c0262af	bellard	next_eip = s->pc - s->cs_base;
4969	14ce26e7	bellard	tval += next_eip;
4970	2c0262af	bellard	if (s->dflag == 0)
4971	14ce26e7	bellard	tval &= 0xffff;
4972	14ce26e7	bellard	gen_jcc(s, b, tval, next_eip);
4973	2c0262af	bellard	break;
4974	2c0262af	bellard
4975	2c0262af	bellard	case 0x190 ... 0x19f: /* setcc Gv */
4976	61382a50	bellard	modrm = ldub_code(s->pc++);
4977	2c0262af	bellard	gen_setcc(s, b);
4978	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
4979	2c0262af	bellard	break;
4980	2c0262af	bellard	case 0x140 ... 0x14f: /* cmov Gv, Ev */
4981	14ce26e7	bellard	ot = dflag + OT_WORD;
4982	61382a50	bellard	modrm = ldub_code(s->pc++);
4983	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
4984	2c0262af	bellard	mod = (modrm >> 6) & 3;
4985	2c0262af	bellard	gen_setcc(s, b);
4986	2c0262af	bellard	if (mod != 3) {
4987	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4988	2c0262af	bellard	gen_op_ld_T1_A0[ot + s->mem_index]();
4989	2c0262af	bellard	} else {
4990	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
4991	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][rm]();
4992	2c0262af	bellard	}
4993	2c0262af	bellard	gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
4994	2c0262af	bellard	break;
4995	2c0262af	bellard
4996	2c0262af	bellard	/************************/
4997	2c0262af	bellard	/* flags */
4998	2c0262af	bellard	case 0x9c: /* pushf */
4999	2c0262af	bellard	if (s->vm86 && s->iopl != 3) {
5000	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5001	2c0262af	bellard	} else {
5002	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5003	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5004	2c0262af	bellard	gen_op_movl_T0_eflags();
5005	2c0262af	bellard	gen_push_T0(s);
5006	2c0262af	bellard	}
5007	2c0262af	bellard	break;
5008	2c0262af	bellard	case 0x9d: /* popf */
5009	2c0262af	bellard	if (s->vm86 && s->iopl != 3) {
5010	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5011	2c0262af	bellard	} else {
5012	2c0262af	bellard	gen_pop_T0(s);
5013	2c0262af	bellard	if (s->cpl == 0) {
5014	2c0262af	bellard	if (s->dflag) {
5015	2c0262af	bellard	gen_op_movl_eflags_T0_cpl0();
5016	2c0262af	bellard	} else {
5017	2c0262af	bellard	gen_op_movw_eflags_T0_cpl0();
5018	2c0262af	bellard	}
5019	2c0262af	bellard	} else {
5020	4136f33c	bellard	if (s->cpl <= s->iopl) {
5021	4136f33c	bellard	if (s->dflag) {
5022	4136f33c	bellard	gen_op_movl_eflags_T0_io();
5023	4136f33c	bellard	} else {
5024	4136f33c	bellard	gen_op_movw_eflags_T0_io();
5025	4136f33c	bellard	}
5026	2c0262af	bellard	} else {
5027	4136f33c	bellard	if (s->dflag) {
5028	4136f33c	bellard	gen_op_movl_eflags_T0();
5029	4136f33c	bellard	} else {
5030	4136f33c	bellard	gen_op_movw_eflags_T0();
5031	4136f33c	bellard	}
5032	2c0262af	bellard	}
5033	2c0262af	bellard	}
5034	2c0262af	bellard	gen_pop_update(s);
5035	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5036	2c0262af	bellard	/* abort translation because TF flag may change */
5037	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5038	2c0262af	bellard	gen_eob(s);
5039	2c0262af	bellard	}
5040	2c0262af	bellard	break;
5041	2c0262af	bellard	case 0x9e: /* sahf */
5042	14ce26e7	bellard	if (CODE64(s))
5043	14ce26e7	bellard	goto illegal_op;
5044	2c0262af	bellard	gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
5045	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5046	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5047	2c0262af	bellard	gen_op_movb_eflags_T0();
5048	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5049	2c0262af	bellard	break;
5050	2c0262af	bellard	case 0x9f: /* lahf */
5051	14ce26e7	bellard	if (CODE64(s))
5052	14ce26e7	bellard	goto illegal_op;
5053	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5054	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5055	2c0262af	bellard	gen_op_movl_T0_eflags();
5056	2c0262af	bellard	gen_op_mov_reg_T0[OT_BYTE][R_AH]();
5057	2c0262af	bellard	break;
5058	2c0262af	bellard	case 0xf5: /* cmc */
5059	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5060	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5061	2c0262af	bellard	gen_op_cmc();
5062	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5063	2c0262af	bellard	break;
5064	2c0262af	bellard	case 0xf8: /* clc */
5065	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5066	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5067	2c0262af	bellard	gen_op_clc();
5068	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5069	2c0262af	bellard	break;
5070	2c0262af	bellard	case 0xf9: /* stc */
5071	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5072	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5073	2c0262af	bellard	gen_op_stc();
5074	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5075	2c0262af	bellard	break;
5076	2c0262af	bellard	case 0xfc: /* cld */
5077	2c0262af	bellard	gen_op_cld();
5078	2c0262af	bellard	break;
5079	2c0262af	bellard	case 0xfd: /* std */
5080	2c0262af	bellard	gen_op_std();
5081	2c0262af	bellard	break;
5082	2c0262af	bellard
5083	2c0262af	bellard	/************************/
5084	2c0262af	bellard	/* bit operations */
5085	2c0262af	bellard	case 0x1ba: /* bt/bts/btr/btc Gv, im */
5086	14ce26e7	bellard	ot = dflag + OT_WORD;
5087	61382a50	bellard	modrm = ldub_code(s->pc++);
5088	33698e5f	bellard	op = (modrm >> 3) & 7;
5089	2c0262af	bellard	mod = (modrm >> 6) & 3;
5090	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5091	2c0262af	bellard	if (mod != 3) {
5092	14ce26e7	bellard	s->rip_offset = 1;
5093	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5094	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5095	2c0262af	bellard	} else {
5096	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5097	2c0262af	bellard	}
5098	2c0262af	bellard	/* load shift */
5099	61382a50	bellard	val = ldub_code(s->pc++);
5100	2c0262af	bellard	gen_op_movl_T1_im(val);
5101	2c0262af	bellard	if (op < 4)
5102	2c0262af	bellard	goto illegal_op;
5103	2c0262af	bellard	op -= 4;
5104	2c0262af	bellard	gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5105	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
5106	2c0262af	bellard	if (op != 0) {
5107	2c0262af	bellard	if (mod != 3)
5108	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5109	2c0262af	bellard	else
5110	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
5111	2c0262af	bellard	gen_op_update_bt_cc();
5112	2c0262af	bellard	}
5113	2c0262af	bellard	break;
5114	2c0262af	bellard	case 0x1a3: /* bt Gv, Ev */
5115	2c0262af	bellard	op = 0;
5116	2c0262af	bellard	goto do_btx;
5117	2c0262af	bellard	case 0x1ab: /* bts */
5118	2c0262af	bellard	op = 1;
5119	2c0262af	bellard	goto do_btx;
5120	2c0262af	bellard	case 0x1b3: /* btr */
5121	2c0262af	bellard	op = 2;
5122	2c0262af	bellard	goto do_btx;
5123	2c0262af	bellard	case 0x1bb: /* btc */
5124	2c0262af	bellard	op = 3;
5125	2c0262af	bellard	do_btx:
5126	14ce26e7	bellard	ot = dflag + OT_WORD;
5127	61382a50	bellard	modrm = ldub_code(s->pc++);
5128	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5129	2c0262af	bellard	mod = (modrm >> 6) & 3;
5130	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5131	2c0262af	bellard	gen_op_mov_TN_reg[OT_LONG][1][reg]();
5132	2c0262af	bellard	if (mod != 3) {
5133	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5134	2c0262af	bellard	/* specific case: we need to add a displacement */
5135	14ce26e7	bellard	gen_op_add_bit_A0_T1[ot - OT_WORD]();
5136	2c0262af	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5137	2c0262af	bellard	} else {
5138	2c0262af	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5139	2c0262af	bellard	}
5140	2c0262af	bellard	gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5141	2c0262af	bellard	s->cc_op = CC_OP_SARB + ot;
5142	2c0262af	bellard	if (op != 0) {
5143	2c0262af	bellard	if (mod != 3)
5144	2c0262af	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5145	2c0262af	bellard	else
5146	2c0262af	bellard	gen_op_mov_reg_T0[ot][rm]();
5147	2c0262af	bellard	gen_op_update_bt_cc();
5148	2c0262af	bellard	}
5149	2c0262af	bellard	break;
5150	2c0262af	bellard	case 0x1bc: /* bsf */
5151	2c0262af	bellard	case 0x1bd: /* bsr */
5152	14ce26e7	bellard	ot = dflag + OT_WORD;
5153	61382a50	bellard	modrm = ldub_code(s->pc++);
5154	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5155	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5156	686f3f26	bellard	/* NOTE: in order to handle the 0 case, we must load the
5157	686f3f26	bellard	result. It could be optimized with a generated jump */
5158	686f3f26	bellard	gen_op_mov_TN_reg[ot][1][reg]();
5159	2c0262af	bellard	gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
5160	686f3f26	bellard	gen_op_mov_reg_T1[ot][reg]();
5161	2c0262af	bellard	s->cc_op = CC_OP_LOGICB + ot;
5162	2c0262af	bellard	break;
5163	2c0262af	bellard	/************************/
5164	2c0262af	bellard	/* bcd */
5165	2c0262af	bellard	case 0x27: /* daa */
5166	14ce26e7	bellard	if (CODE64(s))
5167	14ce26e7	bellard	goto illegal_op;
5168	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5169	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5170	2c0262af	bellard	gen_op_daa();
5171	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5172	2c0262af	bellard	break;
5173	2c0262af	bellard	case 0x2f: /* das */
5174	14ce26e7	bellard	if (CODE64(s))
5175	14ce26e7	bellard	goto illegal_op;
5176	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5177	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5178	2c0262af	bellard	gen_op_das();
5179	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5180	2c0262af	bellard	break;
5181	2c0262af	bellard	case 0x37: /* aaa */
5182	14ce26e7	bellard	if (CODE64(s))
5183	14ce26e7	bellard	goto illegal_op;
5184	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5185	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5186	2c0262af	bellard	gen_op_aaa();
5187	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5188	2c0262af	bellard	break;
5189	2c0262af	bellard	case 0x3f: /* aas */
5190	14ce26e7	bellard	if (CODE64(s))
5191	14ce26e7	bellard	goto illegal_op;
5192	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5193	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5194	2c0262af	bellard	gen_op_aas();
5195	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5196	2c0262af	bellard	break;
5197	2c0262af	bellard	case 0xd4: /* aam */
5198	14ce26e7	bellard	if (CODE64(s))
5199	14ce26e7	bellard	goto illegal_op;
5200	61382a50	bellard	val = ldub_code(s->pc++);
5201	2c0262af	bellard	gen_op_aam(val);
5202	2c0262af	bellard	s->cc_op = CC_OP_LOGICB;
5203	2c0262af	bellard	break;
5204	2c0262af	bellard	case 0xd5: /* aad */
5205	14ce26e7	bellard	if (CODE64(s))
5206	14ce26e7	bellard	goto illegal_op;
5207	61382a50	bellard	val = ldub_code(s->pc++);
5208	2c0262af	bellard	gen_op_aad(val);
5209	2c0262af	bellard	s->cc_op = CC_OP_LOGICB;
5210	2c0262af	bellard	break;
5211	2c0262af	bellard	/************************/
5212	2c0262af	bellard	/* misc */
5213	2c0262af	bellard	case 0x90: /* nop */
5214	14ce26e7	bellard	/* XXX: xchg + rex handling */
5215	ab1f142b	bellard	/* XXX: correct lock test for all insn */
5216	ab1f142b	bellard	if (prefixes & PREFIX_LOCK)
5217	ab1f142b	bellard	goto illegal_op;
5218	2c0262af	bellard	break;
5219	2c0262af	bellard	case 0x9b: /* fwait */
5220	7eee2a50	bellard	if ((s->flags & (HF_MP_MASK \| HF_TS_MASK)) ==
5221	7eee2a50	bellard	(HF_MP_MASK \| HF_TS_MASK)) {
5222	7eee2a50	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5223	2ee73ac3	bellard	} else {
5224	2ee73ac3	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5225	2ee73ac3	bellard	gen_op_set_cc_op(s->cc_op);
5226	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5227	2ee73ac3	bellard	gen_op_fwait();
5228	7eee2a50	bellard	}
5229	2c0262af	bellard	break;
5230	2c0262af	bellard	case 0xcc: /* int3 */
5231	2c0262af	bellard	gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
5232	2c0262af	bellard	break;
5233	2c0262af	bellard	case 0xcd: /* int N */
5234	61382a50	bellard	val = ldub_code(s->pc++);
5235	f115e911	bellard	if (s->vm86 && s->iopl != 3) {
5236	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5237	f115e911	bellard	} else {
5238	f115e911	bellard	gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
5239	f115e911	bellard	}
5240	2c0262af	bellard	break;
5241	2c0262af	bellard	case 0xce: /* into */
5242	14ce26e7	bellard	if (CODE64(s))
5243	14ce26e7	bellard	goto illegal_op;
5244	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5245	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5246	a8ede8ba	bellard	gen_jmp_im(pc_start - s->cs_base);
5247	a8ede8ba	bellard	gen_op_into(s->pc - pc_start);
5248	2c0262af	bellard	break;
5249	2c0262af	bellard	case 0xf1: /* icebp (undocumented, exits to external debugger) */
5250	aba9d61e	bellard	#if 1
5251	2c0262af	bellard	gen_debug(s, pc_start - s->cs_base);
5252	aba9d61e	bellard	#else
5253	aba9d61e	bellard	/* start debug */
5254	aba9d61e	bellard	tb_flush(cpu_single_env);
5255	aba9d61e	bellard	cpu_set_log(CPU_LOG_INT \| CPU_LOG_TB_IN_ASM);
5256	aba9d61e	bellard	#endif
5257	2c0262af	bellard	break;
5258	2c0262af	bellard	case 0xfa: /* cli */
5259	2c0262af	bellard	if (!s->vm86) {
5260	2c0262af	bellard	if (s->cpl <= s->iopl) {
5261	2c0262af	bellard	gen_op_cli();
5262	2c0262af	bellard	} else {
5263	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5264	2c0262af	bellard	}
5265	2c0262af	bellard	} else {
5266	2c0262af	bellard	if (s->iopl == 3) {
5267	2c0262af	bellard	gen_op_cli();
5268	2c0262af	bellard	} else {
5269	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5270	2c0262af	bellard	}
5271	2c0262af	bellard	}
5272	2c0262af	bellard	break;
5273	2c0262af	bellard	case 0xfb: /* sti */
5274	2c0262af	bellard	if (!s->vm86) {
5275	2c0262af	bellard	if (s->cpl <= s->iopl) {
5276	2c0262af	bellard	gen_sti:
5277	2c0262af	bellard	gen_op_sti();
5278	2c0262af	bellard	/* interruptions are enabled only the first insn after sti */
5279	a2cc3b24	bellard	/* If several instructions disable interrupts, only the
5280	a2cc3b24	bellard	_first_ does it */
5281	a2cc3b24	bellard	if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5282	a2cc3b24	bellard	gen_op_set_inhibit_irq();
5283	2c0262af	bellard	/* give a chance to handle pending irqs */
5284	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5285	2c0262af	bellard	gen_eob(s);
5286	2c0262af	bellard	} else {
5287	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5288	2c0262af	bellard	}
5289	2c0262af	bellard	} else {
5290	2c0262af	bellard	if (s->iopl == 3) {
5291	2c0262af	bellard	goto gen_sti;
5292	2c0262af	bellard	} else {
5293	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5294	2c0262af	bellard	}
5295	2c0262af	bellard	}
5296	2c0262af	bellard	break;
5297	2c0262af	bellard	case 0x62: /* bound */
5298	14ce26e7	bellard	if (CODE64(s))
5299	14ce26e7	bellard	goto illegal_op;
5300	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
5301	61382a50	bellard	modrm = ldub_code(s->pc++);
5302	2c0262af	bellard	reg = (modrm >> 3) & 7;
5303	2c0262af	bellard	mod = (modrm >> 6) & 3;
5304	2c0262af	bellard	if (mod == 3)
5305	2c0262af	bellard	goto illegal_op;
5306	cabf23c3	bellard	gen_op_mov_TN_reg[ot][0][reg]();
5307	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5308	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5309	2c0262af	bellard	if (ot == OT_WORD)
5310	14ce26e7	bellard	gen_op_boundw();
5311	2c0262af	bellard	else
5312	14ce26e7	bellard	gen_op_boundl();
5313	2c0262af	bellard	break;
5314	2c0262af	bellard	case 0x1c8 ... 0x1cf: /* bswap reg */
5315	14ce26e7	bellard	reg = (b & 7) \| REX_B(s);
5316	14ce26e7	bellard	#ifdef TARGET_X86_64
5317	14ce26e7	bellard	if (dflag == 2) {
5318	14ce26e7	bellard	gen_op_mov_TN_reg[OT_QUAD][0][reg]();
5319	14ce26e7	bellard	gen_op_bswapq_T0();
5320	14ce26e7	bellard	gen_op_mov_reg_T0[OT_QUAD][reg]();
5321	14ce26e7	bellard	} else
5322	14ce26e7	bellard	#endif
5323	14ce26e7	bellard	{
5324	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][reg]();
5325	14ce26e7	bellard	gen_op_bswapl_T0();
5326	14ce26e7	bellard	gen_op_mov_reg_T0[OT_LONG][reg]();
5327	14ce26e7	bellard	}
5328	2c0262af	bellard	break;
5329	2c0262af	bellard	case 0xd6: /* salc */
5330	14ce26e7	bellard	if (CODE64(s))
5331	14ce26e7	bellard	goto illegal_op;
5332	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5333	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5334	2c0262af	bellard	gen_op_salc();
5335	2c0262af	bellard	break;
5336	2c0262af	bellard	case 0xe0: /* loopnz */
5337	2c0262af	bellard	case 0xe1: /* loopz */
5338	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5339	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5340	2c0262af	bellard	/* FALL THRU */
5341	2c0262af	bellard	case 0xe2: /* loop */
5342	2c0262af	bellard	case 0xe3: /* jecxz */
5343	14ce26e7	bellard	{
5344	14ce26e7	bellard	int l1, l2;
5345	14ce26e7	bellard
5346	14ce26e7	bellard	tval = (int8_t)insn_get(s, OT_BYTE);
5347	14ce26e7	bellard	next_eip = s->pc - s->cs_base;
5348	14ce26e7	bellard	tval += next_eip;
5349	14ce26e7	bellard	if (s->dflag == 0)
5350	14ce26e7	bellard	tval &= 0xffff;
5351	14ce26e7	bellard
5352	14ce26e7	bellard	l1 = gen_new_label();
5353	14ce26e7	bellard	l2 = gen_new_label();
5354	14ce26e7	bellard	b &= 3;
5355	14ce26e7	bellard	if (b == 3) {
5356	14ce26e7	bellard	gen_op_jz_ecx[s->aflag](l1);
5357	14ce26e7	bellard	} else {
5358	14ce26e7	bellard	gen_op_dec_ECX[s->aflag]();
5359	0b9dc5e4	bellard	if (b <= 1)
5360	0b9dc5e4	bellard	gen_op_mov_T0_cc();
5361	14ce26e7	bellard	gen_op_loop[s->aflag][b](l1);
5362	14ce26e7	bellard	}
5363	14ce26e7	bellard
5364	14ce26e7	bellard	gen_jmp_im(next_eip);
5365	14ce26e7	bellard	gen_op_jmp_label(l2);
5366	14ce26e7	bellard	gen_set_label(l1);
5367	14ce26e7	bellard	gen_jmp_im(tval);
5368	14ce26e7	bellard	gen_set_label(l2);
5369	14ce26e7	bellard	gen_eob(s);
5370	14ce26e7	bellard	}
5371	2c0262af	bellard	break;
5372	2c0262af	bellard	case 0x130: /* wrmsr */
5373	2c0262af	bellard	case 0x132: /* rdmsr */
5374	2c0262af	bellard	if (s->cpl != 0) {
5375	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5376	2c0262af	bellard	} else {
5377	2c0262af	bellard	if (b & 2)
5378	2c0262af	bellard	gen_op_rdmsr();
5379	2c0262af	bellard	else
5380	2c0262af	bellard	gen_op_wrmsr();
5381	2c0262af	bellard	}
5382	2c0262af	bellard	break;
5383	2c0262af	bellard	case 0x131: /* rdtsc */
5384	ecada8a2	bellard	gen_jmp_im(pc_start - s->cs_base);
5385	2c0262af	bellard	gen_op_rdtsc();
5386	2c0262af	bellard	break;
5387	023fe10d	bellard	case 0x134: /* sysenter */
5388	14ce26e7	bellard	if (CODE64(s))
5389	14ce26e7	bellard	goto illegal_op;
5390	023fe10d	bellard	if (!s->pe) {
5391	023fe10d	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5392	023fe10d	bellard	} else {
5393	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5394	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
5395	023fe10d	bellard	s->cc_op = CC_OP_DYNAMIC;
5396	023fe10d	bellard	}
5397	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5398	023fe10d	bellard	gen_op_sysenter();
5399	023fe10d	bellard	gen_eob(s);
5400	023fe10d	bellard	}
5401	023fe10d	bellard	break;
5402	023fe10d	bellard	case 0x135: /* sysexit */
5403	14ce26e7	bellard	if (CODE64(s))
5404	14ce26e7	bellard	goto illegal_op;
5405	023fe10d	bellard	if (!s->pe) {
5406	023fe10d	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5407	023fe10d	bellard	} else {
5408	023fe10d	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5409	023fe10d	bellard	gen_op_set_cc_op(s->cc_op);
5410	023fe10d	bellard	s->cc_op = CC_OP_DYNAMIC;
5411	023fe10d	bellard	}
5412	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5413	023fe10d	bellard	gen_op_sysexit();
5414	023fe10d	bellard	gen_eob(s);
5415	023fe10d	bellard	}
5416	023fe10d	bellard	break;
5417	14ce26e7	bellard	#ifdef TARGET_X86_64
5418	14ce26e7	bellard	case 0x105: /* syscall */
5419	14ce26e7	bellard	/* XXX: is it usable in real mode ? */
5420	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5421	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5422	14ce26e7	bellard	s->cc_op = CC_OP_DYNAMIC;
5423	14ce26e7	bellard	}
5424	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5425	06c2f506	bellard	gen_op_syscall(s->pc - pc_start);
5426	14ce26e7	bellard	gen_eob(s);
5427	14ce26e7	bellard	break;
5428	14ce26e7	bellard	case 0x107: /* sysret */
5429	14ce26e7	bellard	if (!s->pe) {
5430	14ce26e7	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5431	14ce26e7	bellard	} else {
5432	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC) {
5433	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5434	14ce26e7	bellard	s->cc_op = CC_OP_DYNAMIC;
5435	14ce26e7	bellard	}
5436	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5437	14ce26e7	bellard	gen_op_sysret(s->dflag);
5438	aba9d61e	bellard	/* condition codes are modified only in long mode */
5439	aba9d61e	bellard	if (s->lma)
5440	aba9d61e	bellard	s->cc_op = CC_OP_EFLAGS;
5441	14ce26e7	bellard	gen_eob(s);
5442	14ce26e7	bellard	}
5443	14ce26e7	bellard	break;
5444	14ce26e7	bellard	#endif
5445	2c0262af	bellard	case 0x1a2: /* cpuid */
5446	2c0262af	bellard	gen_op_cpuid();
5447	2c0262af	bellard	break;
5448	2c0262af	bellard	case 0xf4: /* hlt */
5449	2c0262af	bellard	if (s->cpl != 0) {
5450	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5451	2c0262af	bellard	} else {
5452	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5453	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5454	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5455	2c0262af	bellard	gen_op_hlt();
5456	2c0262af	bellard	s->is_jmp = 3;
5457	2c0262af	bellard	}
5458	2c0262af	bellard	break;
5459	2c0262af	bellard	case 0x100:
5460	61382a50	bellard	modrm = ldub_code(s->pc++);
5461	2c0262af	bellard	mod = (modrm >> 6) & 3;
5462	2c0262af	bellard	op = (modrm >> 3) & 7;
5463	2c0262af	bellard	switch(op) {
5464	2c0262af	bellard	case 0: /* sldt */
5465	f115e911	bellard	if (!s->pe \|\| s->vm86)
5466	f115e911	bellard	goto illegal_op;
5467	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
5468	2c0262af	bellard	ot = OT_WORD;
5469	2c0262af	bellard	if (mod == 3)
5470	2c0262af	bellard	ot += s->dflag;
5471	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5472	2c0262af	bellard	break;
5473	2c0262af	bellard	case 2: /* lldt */
5474	f115e911	bellard	if (!s->pe \|\| s->vm86)
5475	f115e911	bellard	goto illegal_op;
5476	2c0262af	bellard	if (s->cpl != 0) {
5477	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5478	2c0262af	bellard	} else {
5479	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5480	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5481	2c0262af	bellard	gen_op_lldt_T0();
5482	2c0262af	bellard	}
5483	2c0262af	bellard	break;
5484	2c0262af	bellard	case 1: /* str */
5485	f115e911	bellard	if (!s->pe \|\| s->vm86)
5486	f115e911	bellard	goto illegal_op;
5487	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
5488	2c0262af	bellard	ot = OT_WORD;
5489	2c0262af	bellard	if (mod == 3)
5490	2c0262af	bellard	ot += s->dflag;
5491	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5492	2c0262af	bellard	break;
5493	2c0262af	bellard	case 3: /* ltr */
5494	f115e911	bellard	if (!s->pe \|\| s->vm86)
5495	f115e911	bellard	goto illegal_op;
5496	2c0262af	bellard	if (s->cpl != 0) {
5497	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5498	2c0262af	bellard	} else {
5499	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5500	14ce26e7	bellard	gen_jmp_im(pc_start - s->cs_base);
5501	2c0262af	bellard	gen_op_ltr_T0();
5502	2c0262af	bellard	}
5503	2c0262af	bellard	break;
5504	2c0262af	bellard	case 4: /* verr */
5505	2c0262af	bellard	case 5: /* verw */
5506	f115e911	bellard	if (!s->pe \|\| s->vm86)
5507	f115e911	bellard	goto illegal_op;
5508	f115e911	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5509	f115e911	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5510	f115e911	bellard	gen_op_set_cc_op(s->cc_op);
5511	f115e911	bellard	if (op == 4)
5512	f115e911	bellard	gen_op_verr();
5513	f115e911	bellard	else
5514	f115e911	bellard	gen_op_verw();
5515	f115e911	bellard	s->cc_op = CC_OP_EFLAGS;
5516	f115e911	bellard	break;
5517	2c0262af	bellard	default:
5518	2c0262af	bellard	goto illegal_op;
5519	2c0262af	bellard	}
5520	2c0262af	bellard	break;
5521	2c0262af	bellard	case 0x101:
5522	61382a50	bellard	modrm = ldub_code(s->pc++);
5523	2c0262af	bellard	mod = (modrm >> 6) & 3;
5524	2c0262af	bellard	op = (modrm >> 3) & 7;
5525	2c0262af	bellard	switch(op) {
5526	2c0262af	bellard	case 0: /* sgdt */
5527	2c0262af	bellard	case 1: /* sidt */
5528	2c0262af	bellard	if (mod == 3)
5529	2c0262af	bellard	goto illegal_op;
5530	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5531	2c0262af	bellard	if (op == 0)
5532	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
5533	2c0262af	bellard	else
5534	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
5535	2c0262af	bellard	gen_op_st_T0_A0[OT_WORD + s->mem_index]();
5536	aba9d61e	bellard	gen_add_A0_im(s, 2);
5537	2c0262af	bellard	if (op == 0)
5538	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,gdt.base));
5539	2c0262af	bellard	else
5540	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,idt.base));
5541	2c0262af	bellard	if (!s->dflag)
5542	2c0262af	bellard	gen_op_andl_T0_im(0xffffff);
5543	14ce26e7	bellard	gen_op_st_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5544	2c0262af	bellard	break;
5545	2c0262af	bellard	case 2: /* lgdt */
5546	2c0262af	bellard	case 3: /* lidt */
5547	2c0262af	bellard	if (mod == 3)
5548	2c0262af	bellard	goto illegal_op;
5549	2c0262af	bellard	if (s->cpl != 0) {
5550	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5551	2c0262af	bellard	} else {
5552	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5553	2c0262af	bellard	gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
5554	aba9d61e	bellard	gen_add_A0_im(s, 2);
5555	14ce26e7	bellard	gen_op_ld_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5556	2c0262af	bellard	if (!s->dflag)
5557	2c0262af	bellard	gen_op_andl_T0_im(0xffffff);
5558	2c0262af	bellard	if (op == 2) {
5559	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base));
5560	2c0262af	bellard	gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
5561	2c0262af	bellard	} else {
5562	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base));
5563	2c0262af	bellard	gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
5564	2c0262af	bellard	}
5565	2c0262af	bellard	}
5566	2c0262af	bellard	break;
5567	2c0262af	bellard	case 4: /* smsw */
5568	2c0262af	bellard	gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
5569	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
5570	2c0262af	bellard	break;
5571	2c0262af	bellard	case 6: /* lmsw */
5572	2c0262af	bellard	if (s->cpl != 0) {
5573	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5574	2c0262af	bellard	} else {
5575	2c0262af	bellard	gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5576	2c0262af	bellard	gen_op_lmsw_T0();
5577	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5578	d71b9a8b	bellard	gen_eob(s);
5579	2c0262af	bellard	}
5580	2c0262af	bellard	break;
5581	2c0262af	bellard	case 7: /* invlpg */
5582	2c0262af	bellard	if (s->cpl != 0) {
5583	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5584	2c0262af	bellard	} else {
5585	14ce26e7	bellard	if (mod == 3) {
5586	14ce26e7	bellard	#ifdef TARGET_X86_64
5587	14ce26e7	bellard	if (CODE64(s) && (modrm & 7) == 0) {
5588	14ce26e7	bellard	/* swapgs */
5589	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base));
5590	14ce26e7	bellard	gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase));
5591	14ce26e7	bellard	gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
5592	14ce26e7	bellard	gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
5593	14ce26e7	bellard	} else
5594	14ce26e7	bellard	#endif
5595	14ce26e7	bellard	{
5596	14ce26e7	bellard	goto illegal_op;
5597	14ce26e7	bellard	}
5598	14ce26e7	bellard	} else {
5599	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5600	14ce26e7	bellard	gen_op_invlpg_A0();
5601	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5602	14ce26e7	bellard	gen_eob(s);
5603	14ce26e7	bellard	}
5604	2c0262af	bellard	}
5605	2c0262af	bellard	break;
5606	2c0262af	bellard	default:
5607	2c0262af	bellard	goto illegal_op;
5608	2c0262af	bellard	}
5609	2c0262af	bellard	break;
5610	3415a4dd	bellard	case 0x108: /* invd */
5611	3415a4dd	bellard	case 0x109: /* wbinvd */
5612	3415a4dd	bellard	if (s->cpl != 0) {
5613	3415a4dd	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5614	3415a4dd	bellard	} else {
5615	3415a4dd	bellard	/* nothing to do */
5616	3415a4dd	bellard	}
5617	3415a4dd	bellard	break;
5618	14ce26e7	bellard	case 0x63: /* arpl or movslS (x86_64) */
5619	14ce26e7	bellard	#ifdef TARGET_X86_64
5620	14ce26e7	bellard	if (CODE64(s)) {
5621	14ce26e7	bellard	int d_ot;
5622	14ce26e7	bellard	/* d_ot is the size of destination */
5623	14ce26e7	bellard	d_ot = dflag + OT_WORD;
5624	14ce26e7	bellard
5625	14ce26e7	bellard	modrm = ldub_code(s->pc++);
5626	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5627	14ce26e7	bellard	mod = (modrm >> 6) & 3;
5628	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5629	14ce26e7	bellard
5630	14ce26e7	bellard	if (mod == 3) {
5631	14ce26e7	bellard	gen_op_mov_TN_reg[OT_LONG][0][rm]();
5632	14ce26e7	bellard	/* sign extend */
5633	14ce26e7	bellard	if (d_ot == OT_QUAD)
5634	14ce26e7	bellard	gen_op_movslq_T0_T0();
5635	14ce26e7	bellard	gen_op_mov_reg_T0[d_ot][reg]();
5636	14ce26e7	bellard	} else {
5637	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5638	14ce26e7	bellard	if (d_ot == OT_QUAD) {
5639	14ce26e7	bellard	gen_op_lds_T0_A0[OT_LONG + s->mem_index]();
5640	14ce26e7	bellard	} else {
5641	14ce26e7	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5642	14ce26e7	bellard	}
5643	14ce26e7	bellard	gen_op_mov_reg_T0[d_ot][reg]();
5644	14ce26e7	bellard	}
5645	14ce26e7	bellard	} else
5646	14ce26e7	bellard	#endif
5647	14ce26e7	bellard	{
5648	14ce26e7	bellard	if (!s->pe \|\| s->vm86)
5649	14ce26e7	bellard	goto illegal_op;
5650	14ce26e7	bellard	ot = dflag ? OT_LONG : OT_WORD;
5651	14ce26e7	bellard	modrm = ldub_code(s->pc++);
5652	14ce26e7	bellard	reg = (modrm >> 3) & 7;
5653	14ce26e7	bellard	mod = (modrm >> 6) & 3;
5654	14ce26e7	bellard	rm = modrm & 7;
5655	14ce26e7	bellard	if (mod != 3) {
5656	14ce26e7	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5657	14ce26e7	bellard	gen_op_ld_T0_A0[ot + s->mem_index]();
5658	14ce26e7	bellard	} else {
5659	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5660	14ce26e7	bellard	}
5661	14ce26e7	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5662	14ce26e7	bellard	gen_op_set_cc_op(s->cc_op);
5663	14ce26e7	bellard	gen_op_arpl();
5664	14ce26e7	bellard	s->cc_op = CC_OP_EFLAGS;
5665	14ce26e7	bellard	if (mod != 3) {
5666	14ce26e7	bellard	gen_op_st_T0_A0[ot + s->mem_index]();
5667	14ce26e7	bellard	} else {
5668	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5669	14ce26e7	bellard	}
5670	14ce26e7	bellard	gen_op_arpl_update();
5671	f115e911	bellard	}
5672	f115e911	bellard	break;
5673	2c0262af	bellard	case 0x102: /* lar */
5674	2c0262af	bellard	case 0x103: /* lsl */
5675	2c0262af	bellard	if (!s->pe \|\| s->vm86)
5676	2c0262af	bellard	goto illegal_op;
5677	2c0262af	bellard	ot = dflag ? OT_LONG : OT_WORD;
5678	61382a50	bellard	modrm = ldub_code(s->pc++);
5679	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5680	2c0262af	bellard	gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5681	2c0262af	bellard	gen_op_mov_TN_reg[ot][1][reg]();
5682	2c0262af	bellard	if (s->cc_op != CC_OP_DYNAMIC)
5683	2c0262af	bellard	gen_op_set_cc_op(s->cc_op);
5684	2c0262af	bellard	if (b == 0x102)
5685	2c0262af	bellard	gen_op_lar();
5686	2c0262af	bellard	else
5687	2c0262af	bellard	gen_op_lsl();
5688	2c0262af	bellard	s->cc_op = CC_OP_EFLAGS;
5689	2c0262af	bellard	gen_op_mov_reg_T1[ot][reg]();
5690	2c0262af	bellard	break;
5691	2c0262af	bellard	case 0x118:
5692	61382a50	bellard	modrm = ldub_code(s->pc++);
5693	2c0262af	bellard	mod = (modrm >> 6) & 3;
5694	2c0262af	bellard	op = (modrm >> 3) & 7;
5695	2c0262af	bellard	switch(op) {
5696	2c0262af	bellard	case 0: /* prefetchnta */
5697	2c0262af	bellard	case 1: /* prefetchnt0 */
5698	2c0262af	bellard	case 2: /* prefetchnt0 */
5699	2c0262af	bellard	case 3: /* prefetchnt0 */
5700	2c0262af	bellard	if (mod == 3)
5701	2c0262af	bellard	goto illegal_op;
5702	2c0262af	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5703	2c0262af	bellard	/* nothing more to do */
5704	2c0262af	bellard	break;
5705	2c0262af	bellard	default:
5706	2c0262af	bellard	goto illegal_op;
5707	2c0262af	bellard	}
5708	2c0262af	bellard	break;
5709	2c0262af	bellard	case 0x120: /* mov reg, crN */
5710	2c0262af	bellard	case 0x122: /* mov crN, reg */
5711	2c0262af	bellard	if (s->cpl != 0) {
5712	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5713	2c0262af	bellard	} else {
5714	61382a50	bellard	modrm = ldub_code(s->pc++);
5715	2c0262af	bellard	if ((modrm & 0xc0) != 0xc0)
5716	2c0262af	bellard	goto illegal_op;
5717	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5718	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5719	14ce26e7	bellard	if (CODE64(s))
5720	14ce26e7	bellard	ot = OT_QUAD;
5721	14ce26e7	bellard	else
5722	14ce26e7	bellard	ot = OT_LONG;
5723	2c0262af	bellard	switch(reg) {
5724	2c0262af	bellard	case 0:
5725	2c0262af	bellard	case 2:
5726	2c0262af	bellard	case 3:
5727	2c0262af	bellard	case 4:
5728	9230e66e	bellard	case 8:
5729	2c0262af	bellard	if (b & 2) {
5730	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5731	2c0262af	bellard	gen_op_movl_crN_T0(reg);
5732	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5733	2c0262af	bellard	gen_eob(s);
5734	2c0262af	bellard	} else {
5735	82e41634	bellard	#if !defined(CONFIG_USER_ONLY)
5736	9230e66e	bellard	if (reg == 8)
5737	9230e66e	bellard	gen_op_movtl_T0_cr8();
5738	9230e66e	bellard	else
5739	82e41634	bellard	#endif
5740	9230e66e	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
5741	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5742	2c0262af	bellard	}
5743	2c0262af	bellard	break;
5744	2c0262af	bellard	default:
5745	2c0262af	bellard	goto illegal_op;
5746	2c0262af	bellard	}
5747	2c0262af	bellard	}
5748	2c0262af	bellard	break;
5749	2c0262af	bellard	case 0x121: /* mov reg, drN */
5750	2c0262af	bellard	case 0x123: /* mov drN, reg */
5751	2c0262af	bellard	if (s->cpl != 0) {
5752	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5753	2c0262af	bellard	} else {
5754	61382a50	bellard	modrm = ldub_code(s->pc++);
5755	2c0262af	bellard	if ((modrm & 0xc0) != 0xc0)
5756	2c0262af	bellard	goto illegal_op;
5757	14ce26e7	bellard	rm = (modrm & 7) \| REX_B(s);
5758	14ce26e7	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5759	14ce26e7	bellard	if (CODE64(s))
5760	14ce26e7	bellard	ot = OT_QUAD;
5761	14ce26e7	bellard	else
5762	14ce26e7	bellard	ot = OT_LONG;
5763	2c0262af	bellard	/* XXX: do it dynamically with CR4.DE bit */
5764	14ce26e7	bellard	if (reg == 4 \|\| reg == 5 \|\| reg >= 8)
5765	2c0262af	bellard	goto illegal_op;
5766	2c0262af	bellard	if (b & 2) {
5767	14ce26e7	bellard	gen_op_mov_TN_reg[ot][0][rm]();
5768	2c0262af	bellard	gen_op_movl_drN_T0(reg);
5769	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5770	2c0262af	bellard	gen_eob(s);
5771	2c0262af	bellard	} else {
5772	14ce26e7	bellard	gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg]));
5773	14ce26e7	bellard	gen_op_mov_reg_T0[ot][rm]();
5774	2c0262af	bellard	}
5775	2c0262af	bellard	}
5776	2c0262af	bellard	break;
5777	2c0262af	bellard	case 0x106: /* clts */
5778	2c0262af	bellard	if (s->cpl != 0) {
5779	2c0262af	bellard	gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5780	2c0262af	bellard	} else {
5781	2c0262af	bellard	gen_op_clts();
5782	7eee2a50	bellard	/* abort block because static cpu state changed */
5783	14ce26e7	bellard	gen_jmp_im(s->pc - s->cs_base);
5784	7eee2a50	bellard	gen_eob(s);
5785	2c0262af	bellard	}
5786	2c0262af	bellard	break;
5787	664e0f19	bellard	/* MMX/SSE/SSE2/PNI support */
5788	664e0f19	bellard	case 0x1c3: /* MOVNTI reg, mem */
5789	664e0f19	bellard	if (!(s->cpuid_features & CPUID_SSE2))
5790	14ce26e7	bellard	goto illegal_op;
5791	664e0f19	bellard	ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
5792	664e0f19	bellard	modrm = ldub_code(s->pc++);
5793	664e0f19	bellard	mod = (modrm >> 6) & 3;
5794	664e0f19	bellard	if (mod == 3)
5795	664e0f19	bellard	goto illegal_op;
5796	664e0f19	bellard	reg = ((modrm >> 3) & 7) \| rex_r;
5797	664e0f19	bellard	/* generate a generic store */
5798	664e0f19	bellard	gen_ldst_modrm(s, modrm, ot, reg, 1);
5799	14ce26e7	bellard	break;
5800	664e0f19	bellard	case 0x1ae:
5801	664e0f19	bellard	modrm = ldub_code(s->pc++);
5802	664e0f19	bellard	mod = (modrm >> 6) & 3;
5803	664e0f19	bellard	op = (modrm >> 3) & 7;
5804	664e0f19	bellard	switch(op) {
5805	664e0f19	bellard	case 0: /* fxsave */
5806	0fd14b72	bellard	if (mod == 3 \|\| !(s->cpuid_features & CPUID_FXSR) \|\|
5807	0fd14b72	bellard	(s->flags & HF_EM_MASK))
5808	14ce26e7	bellard	goto illegal_op;
5809	0fd14b72	bellard	if (s->flags & HF_TS_MASK) {
5810	0fd14b72	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5811	0fd14b72	bellard	break;
5812	0fd14b72	bellard	}
5813	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5814	664e0f19	bellard	gen_op_fxsave_A0((s->dflag == 2));
5815	664e0f19	bellard	break;
5816	664e0f19	bellard	case 1: /* fxrstor */
5817	0fd14b72	bellard	if (mod == 3 \|\| !(s->cpuid_features & CPUID_FXSR) \|\|
5818	0fd14b72	bellard	(s->flags & HF_EM_MASK))
5819	14ce26e7	bellard	goto illegal_op;
5820	0fd14b72	bellard	if (s->flags & HF_TS_MASK) {
5821	0fd14b72	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5822	0fd14b72	bellard	break;
5823	0fd14b72	bellard	}
5824	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5825	664e0f19	bellard	gen_op_fxrstor_A0((s->dflag == 2));
5826	664e0f19	bellard	break;
5827	664e0f19	bellard	case 2: /* ldmxcsr */
5828	664e0f19	bellard	case 3: /* stmxcsr */
5829	664e0f19	bellard	if (s->flags & HF_TS_MASK) {
5830	664e0f19	bellard	gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5831	664e0f19	bellard	break;
5832	14ce26e7	bellard	}
5833	664e0f19	bellard	if ((s->flags & HF_EM_MASK) \|\| !(s->flags & HF_OSFXSR_MASK) \|\|
5834	664e0f19	bellard	mod == 3)
5835	14ce26e7	bellard	goto illegal_op;
5836	664e0f19	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5837	664e0f19	bellard	if (op == 2) {
5838	664e0f19	bellard	gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5839	664e0f19	bellard	gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr));
5840	14ce26e7	bellard	} else {
5841	664e0f19	bellard	gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr));
5842	664e0f19	bellard	gen_op_st_T0_A0[OT_LONG + s->mem_index]();
5843	14ce26e7	bellard	}
5844	664e0f19	bellard	break;
5845	664e0f19	bellard	case 5: /* lfence */
5846	664e0f19	bellard	case 6: /* mfence */
5847	664e0f19	bellard	if ((modrm & 0xc7) != 0xc0 \|\| !(s->cpuid_features & CPUID_SSE))
5848	664e0f19	bellard	goto illegal_op;
5849	664e0f19	bellard	break;
5850	8f091a59	bellard	case 7: /* sfence / clflush */
5851	8f091a59	bellard	if ((modrm & 0xc7) == 0xc0) {
5852	8f091a59	bellard	/* sfence */
5853	8f091a59	bellard	if (!(s->cpuid_features & CPUID_SSE))
5854	8f091a59	bellard	goto illegal_op;
5855	8f091a59	bellard	} else {
5856	8f091a59	bellard	/* clflush */
5857	8f091a59	bellard	if (!(s->cpuid_features & CPUID_CLFLUSH))
5858	8f091a59	bellard	goto illegal_op;
5859	8f091a59	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5860	8f091a59	bellard	}
5861	8f091a59	bellard	break;
5862	664e0f19	bellard	default:
5863	14ce26e7	bellard	goto illegal_op;
5864	14ce26e7	bellard	}
5865	14ce26e7	bellard	break;
5866	8f091a59	bellard	case 0x10d: /* prefetch */
5867	8f091a59	bellard	modrm = ldub_code(s->pc++);
5868	8f091a59	bellard	gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5869	8f091a59	bellard	/* ignore for now */
5870	8f091a59	bellard	break;
5871	664e0f19	bellard	case 0x110 ... 0x117:
5872	664e0f19	bellard	case 0x128 ... 0x12f:
5873	664e0f19	bellard	case 0x150 ... 0x177:
5874	664e0f19	bellard	case 0x17c ... 0x17f:
5875	664e0f19	bellard	case 0x1c2:
5876	664e0f19	bellard	case 0x1c4 ... 0x1c6:
5877	664e0f19	bellard	case 0x1d0 ... 0x1fe:
5878	664e0f19	bellard	gen_sse(s, b, pc_start, rex_r);
5879	664e0f19	bellard	break;
5880	2c0262af	bellard	default:
5881	2c0262af	bellard	goto illegal_op;
5882	2c0262af	bellard	}
5883	2c0262af	bellard	/* lock generation */
5884	2c0262af	bellard	if (s->prefix & PREFIX_LOCK)
5885	2c0262af	bellard	gen_op_unlock();
5886	2c0262af	bellard	return s->pc;
5887	2c0262af	bellard	illegal_op:
5888	ab1f142b	bellard	if (s->prefix & PREFIX_LOCK)
5889	ab1f142b	bellard	gen_op_unlock();
5890	2c0262af	bellard	/* XXX: ensure that no lock was generated */
5891	2c0262af	bellard	gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
5892	2c0262af	bellard	return s->pc;
5893	2c0262af	bellard	}
5894	2c0262af	bellard
5895	2c0262af	bellard	#define CC_OSZAPC (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C)
5896	2c0262af	bellard	#define CC_OSZAP (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P)
5897	2c0262af	bellard
5898	2c0262af	bellard	/* flags read by an operation */
5899	2c0262af	bellard	static uint16_t opc_read_flags[NB_OPS] = {
5900	2c0262af	bellard	[INDEX_op_aas] = CC_A,
5901	2c0262af	bellard	[INDEX_op_aaa] = CC_A,
5902	2c0262af	bellard	[INDEX_op_das] = CC_A \| CC_C,
5903	2c0262af	bellard	[INDEX_op_daa] = CC_A \| CC_C,
5904	2c0262af	bellard
5905	2c0262af	bellard	/* subtle: due to the incl/decl implementation, C is used */
5906	2c0262af	bellard	[INDEX_op_update_inc_cc] = CC_C,
5907	2c0262af	bellard
5908	2c0262af	bellard	[INDEX_op_into] = CC_O,
5909	2c0262af	bellard
5910	2c0262af	bellard	[INDEX_op_jb_subb] = CC_C,
5911	2c0262af	bellard	[INDEX_op_jb_subw] = CC_C,
5912	2c0262af	bellard	[INDEX_op_jb_subl] = CC_C,
5913	2c0262af	bellard
5914	2c0262af	bellard	[INDEX_op_jz_subb] = CC_Z,
5915	2c0262af	bellard	[INDEX_op_jz_subw] = CC_Z,
5916	2c0262af	bellard	[INDEX_op_jz_subl] = CC_Z,
5917	2c0262af	bellard
5918	2c0262af	bellard	[INDEX_op_jbe_subb] = CC_Z \| CC_C,
5919	2c0262af	bellard	[INDEX_op_jbe_subw] = CC_Z \| CC_C,
5920	2c0262af	bellard	[INDEX_op_jbe_subl] = CC_Z \| CC_C,
5921	2c0262af	bellard
5922	2c0262af	bellard	[INDEX_op_js_subb] = CC_S,
5923	2c0262af	bellard	[INDEX_op_js_subw] = CC_S,
5924	2c0262af	bellard	[INDEX_op_js_subl] = CC_S,
5925	2c0262af	bellard
5926	2c0262af	bellard	[INDEX_op_jl_subb] = CC_O \| CC_S,
5927	2c0262af	bellard	[INDEX_op_jl_subw] = CC_O \| CC_S,
5928	2c0262af	bellard	[INDEX_op_jl_subl] = CC_O \| CC_S,
5929	2c0262af	bellard
5930	2c0262af	bellard	[INDEX_op_jle_subb] = CC_O \| CC_S \| CC_Z,
5931	2c0262af	bellard	[INDEX_op_jle_subw] = CC_O \| CC_S \| CC_Z,
5932	2c0262af	bellard	[INDEX_op_jle_subl] = CC_O \| CC_S \| CC_Z,
5933	2c0262af	bellard
5934	2c0262af	bellard	[INDEX_op_loopnzw] = CC_Z,
5935	2c0262af	bellard	[INDEX_op_loopnzl] = CC_Z,
5936	2c0262af	bellard	[INDEX_op_loopzw] = CC_Z,
5937	2c0262af	bellard	[INDEX_op_loopzl] = CC_Z,
5938	2c0262af	bellard
5939	2c0262af	bellard	[INDEX_op_seto_T0_cc] = CC_O,
5940	2c0262af	bellard	[INDEX_op_setb_T0_cc] = CC_C,
5941	2c0262af	bellard	[INDEX_op_setz_T0_cc] = CC_Z,
5942	2c0262af	bellard	[INDEX_op_setbe_T0_cc] = CC_Z \| CC_C,
5943	2c0262af	bellard	[INDEX_op_sets_T0_cc] = CC_S,
5944	2c0262af	bellard	[INDEX_op_setp_T0_cc] = CC_P,
5945	2c0262af	bellard	[INDEX_op_setl_T0_cc] = CC_O \| CC_S,
5946	2c0262af	bellard	[INDEX_op_setle_T0_cc] = CC_O \| CC_S \| CC_Z,
5947	2c0262af	bellard
5948	2c0262af	bellard	[INDEX_op_setb_T0_subb] = CC_C,
5949	2c0262af	bellard	[INDEX_op_setb_T0_subw] = CC_C,
5950	2c0262af	bellard	[INDEX_op_setb_T0_subl] = CC_C,
5951	2c0262af	bellard
5952	2c0262af	bellard	[INDEX_op_setz_T0_subb] = CC_Z,
5953	2c0262af	bellard	[INDEX_op_setz_T0_subw] = CC_Z,
5954	2c0262af	bellard	[INDEX_op_setz_T0_subl] = CC_Z,
5955	2c0262af	bellard
5956	2c0262af	bellard	[INDEX_op_setbe_T0_subb] = CC_Z \| CC_C,
5957	2c0262af	bellard	[INDEX_op_setbe_T0_subw] = CC_Z \| CC_C,
5958	2c0262af	bellard	[INDEX_op_setbe_T0_subl] = CC_Z \| CC_C,
5959	2c0262af	bellard
5960	2c0262af	bellard	[INDEX_op_sets_T0_subb] = CC_S,
5961	2c0262af	bellard	[INDEX_op_sets_T0_subw] = CC_S,
5962	2c0262af	bellard	[INDEX_op_sets_T0_subl] = CC_S,
5963	2c0262af	bellard
5964	2c0262af	bellard	[INDEX_op_setl_T0_subb] = CC_O \| CC_S,
5965	2c0262af	bellard	[INDEX_op_setl_T0_subw] = CC_O \| CC_S,
5966	2c0262af	bellard	[INDEX_op_setl_T0_subl] = CC_O \| CC_S,
5967	2c0262af	bellard
5968	2c0262af	bellard	[INDEX_op_setle_T0_subb] = CC_O \| CC_S \| CC_Z,
5969	2c0262af	bellard	[INDEX_op_setle_T0_subw] = CC_O \| CC_S \| CC_Z,
5970	2c0262af	bellard	[INDEX_op_setle_T0_subl] = CC_O \| CC_S \| CC_Z,
5971	2c0262af	bellard
5972	2c0262af	bellard	[INDEX_op_movl_T0_eflags] = CC_OSZAPC,
5973	2c0262af	bellard	[INDEX_op_cmc] = CC_C,
5974	2c0262af	bellard	[INDEX_op_salc] = CC_C,
5975	2c0262af	bellard
5976	7399c5a9	bellard	/* needed for correct flag optimisation before string ops */
5977	14ce26e7	bellard	[INDEX_op_jnz_ecxw] = CC_OSZAPC,
5978	14ce26e7	bellard	[INDEX_op_jnz_ecxl] = CC_OSZAPC,
5979	7399c5a9	bellard	[INDEX_op_jz_ecxw] = CC_OSZAPC,
5980	7399c5a9	bellard	[INDEX_op_jz_ecxl] = CC_OSZAPC,
5981	14ce26e7	bellard
5982	14ce26e7	bellard	#ifdef TARGET_X86_64
5983	14ce26e7	bellard	[INDEX_op_jb_subq] = CC_C,
5984	14ce26e7	bellard	[INDEX_op_jz_subq] = CC_Z,
5985	14ce26e7	bellard	[INDEX_op_jbe_subq] = CC_Z \| CC_C,
5986	14ce26e7	bellard	[INDEX_op_js_subq] = CC_S,
5987	14ce26e7	bellard	[INDEX_op_jl_subq] = CC_O \| CC_S,
5988	14ce26e7	bellard	[INDEX_op_jle_subq] = CC_O \| CC_S \| CC_Z,
5989	14ce26e7	bellard
5990	14ce26e7	bellard	[INDEX_op_loopnzq] = CC_Z,
5991	14ce26e7	bellard	[INDEX_op_loopzq] = CC_Z,
5992	14ce26e7	bellard
5993	14ce26e7	bellard	[INDEX_op_setb_T0_subq] = CC_C,
5994	14ce26e7	bellard	[INDEX_op_setz_T0_subq] = CC_Z,
5995	14ce26e7	bellard	[INDEX_op_setbe_T0_subq] = CC_Z \| CC_C,
5996	14ce26e7	bellard	[INDEX_op_sets_T0_subq] = CC_S,
5997	14ce26e7	bellard	[INDEX_op_setl_T0_subq] = CC_O \| CC_S,
5998	14ce26e7	bellard	[INDEX_op_setle_T0_subq] = CC_O \| CC_S \| CC_Z,
5999	14ce26e7	bellard
6000	14ce26e7	bellard	[INDEX_op_jnz_ecxq] = CC_OSZAPC,
6001	14ce26e7	bellard	[INDEX_op_jz_ecxq] = CC_OSZAPC,
6002	14ce26e7	bellard	#endif
6003	7399c5a9	bellard
6004	4f31916f	bellard	#define DEF_READF(SUFFIX)\
6005	4f31916f	bellard	[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6006	4f31916f	bellard	[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6007	4f31916f	bellard	[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6008	14ce26e7	bellard	X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6009	4f31916f	bellard	[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6010	4f31916f	bellard	[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6011	4f31916f	bellard	[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6012	14ce26e7	bellard	X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6013	4f31916f	bellard	\
6014	4f31916f	bellard	[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6015	4f31916f	bellard	[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6016	4f31916f	bellard	[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
6017	14ce26e7	bellard	X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6018	4f31916f	bellard	[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6019	4f31916f	bellard	[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6020	14ce26e7	bellard	[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6021	14ce26e7	bellard	X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_C,)
6022	4f31916f	bellard
6023	4bb2fcc7	bellard	DEF_READF( )
6024	4f31916f	bellard	DEF_READF(_raw)
6025	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6026	4f31916f	bellard	DEF_READF(_kernel)
6027	4f31916f	bellard	DEF_READF(_user)
6028	4f31916f	bellard	#endif
6029	2c0262af	bellard	};
6030	2c0262af	bellard
6031	2c0262af	bellard	/* flags written by an operation */
6032	2c0262af	bellard	static uint16_t opc_write_flags[NB_OPS] = {
6033	2c0262af	bellard	[INDEX_op_update2_cc] = CC_OSZAPC,
6034	2c0262af	bellard	[INDEX_op_update1_cc] = CC_OSZAPC,
6035	2c0262af	bellard	[INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
6036	2c0262af	bellard	[INDEX_op_update_neg_cc] = CC_OSZAPC,
6037	2c0262af	bellard	/* subtle: due to the incl/decl implementation, C is used */
6038	2c0262af	bellard	[INDEX_op_update_inc_cc] = CC_OSZAPC,
6039	2c0262af	bellard	[INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
6040	2c0262af	bellard
6041	2c0262af	bellard	[INDEX_op_mulb_AL_T0] = CC_OSZAPC,
6042	2c0262af	bellard	[INDEX_op_mulw_AX_T0] = CC_OSZAPC,
6043	2c0262af	bellard	[INDEX_op_mull_EAX_T0] = CC_OSZAPC,
6044	14ce26e7	bellard	X86_64_DEF([INDEX_op_mulq_EAX_T0] = CC_OSZAPC,)
6045	14ce26e7	bellard	[INDEX_op_imulb_AL_T0] = CC_OSZAPC,
6046	14ce26e7	bellard	[INDEX_op_imulw_AX_T0] = CC_OSZAPC,
6047	2c0262af	bellard	[INDEX_op_imull_EAX_T0] = CC_OSZAPC,
6048	14ce26e7	bellard	X86_64_DEF([INDEX_op_imulq_EAX_T0] = CC_OSZAPC,)
6049	2c0262af	bellard	[INDEX_op_imulw_T0_T1] = CC_OSZAPC,
6050	2c0262af	bellard	[INDEX_op_imull_T0_T1] = CC_OSZAPC,
6051	14ce26e7	bellard	X86_64_DEF([INDEX_op_imulq_T0_T1] = CC_OSZAPC,)
6052	14ce26e7	bellard
6053	664e0f19	bellard	/* sse */
6054	664e0f19	bellard	[INDEX_op_ucomiss] = CC_OSZAPC,
6055	664e0f19	bellard	[INDEX_op_ucomisd] = CC_OSZAPC,
6056	664e0f19	bellard	[INDEX_op_comiss] = CC_OSZAPC,
6057	664e0f19	bellard	[INDEX_op_comisd] = CC_OSZAPC,
6058	664e0f19	bellard
6059	2c0262af	bellard	/* bcd */
6060	2c0262af	bellard	[INDEX_op_aam] = CC_OSZAPC,
6061	2c0262af	bellard	[INDEX_op_aad] = CC_OSZAPC,
6062	2c0262af	bellard	[INDEX_op_aas] = CC_OSZAPC,
6063	2c0262af	bellard	[INDEX_op_aaa] = CC_OSZAPC,
6064	2c0262af	bellard	[INDEX_op_das] = CC_OSZAPC,
6065	2c0262af	bellard	[INDEX_op_daa] = CC_OSZAPC,
6066	2c0262af	bellard
6067	2c0262af	bellard	[INDEX_op_movb_eflags_T0] = CC_S \| CC_Z \| CC_A \| CC_P \| CC_C,
6068	2c0262af	bellard	[INDEX_op_movw_eflags_T0] = CC_OSZAPC,
6069	2c0262af	bellard	[INDEX_op_movl_eflags_T0] = CC_OSZAPC,
6070	4136f33c	bellard	[INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
6071	4136f33c	bellard	[INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
6072	4136f33c	bellard	[INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
6073	4136f33c	bellard	[INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
6074	2c0262af	bellard	[INDEX_op_clc] = CC_C,
6075	2c0262af	bellard	[INDEX_op_stc] = CC_C,
6076	2c0262af	bellard	[INDEX_op_cmc] = CC_C,
6077	2c0262af	bellard
6078	2c0262af	bellard	[INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
6079	2c0262af	bellard	[INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
6080	14ce26e7	bellard	X86_64_DEF([INDEX_op_btq_T0_T1_cc] = CC_OSZAPC,)
6081	2c0262af	bellard	[INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
6082	2c0262af	bellard	[INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
6083	14ce26e7	bellard	X86_64_DEF([INDEX_op_btsq_T0_T1_cc] = CC_OSZAPC,)
6084	2c0262af	bellard	[INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
6085	2c0262af	bellard	[INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
6086	14ce26e7	bellard	X86_64_DEF([INDEX_op_btrq_T0_T1_cc] = CC_OSZAPC,)
6087	2c0262af	bellard	[INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
6088	2c0262af	bellard	[INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
6089	14ce26e7	bellard	X86_64_DEF([INDEX_op_btcq_T0_T1_cc] = CC_OSZAPC,)
6090	2c0262af	bellard
6091	2c0262af	bellard	[INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
6092	2c0262af	bellard	[INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
6093	14ce26e7	bellard	X86_64_DEF([INDEX_op_bsfq_T0_cc] = CC_OSZAPC,)
6094	2c0262af	bellard	[INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
6095	2c0262af	bellard	[INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
6096	14ce26e7	bellard	X86_64_DEF([INDEX_op_bsrq_T0_cc] = CC_OSZAPC,)
6097	2c0262af	bellard
6098	2c0262af	bellard	[INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
6099	2c0262af	bellard	[INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
6100	2c0262af	bellard	[INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
6101	14ce26e7	bellard	X86_64_DEF([INDEX_op_cmpxchgq_T0_T1_EAX_cc] = CC_OSZAPC,)
6102	2c0262af	bellard
6103	2c0262af	bellard	[INDEX_op_cmpxchg8b] = CC_Z,
6104	2c0262af	bellard	[INDEX_op_lar] = CC_Z,
6105	2c0262af	bellard	[INDEX_op_lsl] = CC_Z,
6106	cc6f538b	bellard	[INDEX_op_verr] = CC_Z,
6107	cc6f538b	bellard	[INDEX_op_verw] = CC_Z,
6108	2c0262af	bellard	[INDEX_op_fcomi_ST0_FT0] = CC_Z \| CC_P \| CC_C,
6109	2c0262af	bellard	[INDEX_op_fucomi_ST0_FT0] = CC_Z \| CC_P \| CC_C,
6110	4f31916f	bellard
6111	4f31916f	bellard	#define DEF_WRITEF(SUFFIX)\
6112	4f31916f	bellard	[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6113	4f31916f	bellard	[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6114	4f31916f	bellard	[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6115	14ce26e7	bellard	X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6116	4f31916f	bellard	[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6117	4f31916f	bellard	[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6118	4f31916f	bellard	[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6119	14ce26e7	bellard	X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6120	4f31916f	bellard	\
6121	4f31916f	bellard	[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6122	4f31916f	bellard	[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6123	4f31916f	bellard	[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6124	14ce26e7	bellard	X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6125	4f31916f	bellard	[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6126	4f31916f	bellard	[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6127	4f31916f	bellard	[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6128	14ce26e7	bellard	X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6129	4f31916f	bellard	\
6130	4f31916f	bellard	[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6131	4f31916f	bellard	[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6132	4f31916f	bellard	[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6133	14ce26e7	bellard	X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6134	4f31916f	bellard	[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6135	4f31916f	bellard	[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6136	4f31916f	bellard	[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,\
6137	14ce26e7	bellard	X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_O \| CC_C,)\
6138	4f31916f	bellard	\
6139	4f31916f	bellard	[INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6140	4f31916f	bellard	[INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6141	4f31916f	bellard	[INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6142	14ce26e7	bellard	X86_64_DEF([INDEX_op_shlq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6143	4f31916f	bellard	\
6144	4f31916f	bellard	[INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6145	4f31916f	bellard	[INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6146	4f31916f	bellard	[INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6147	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6148	4f31916f	bellard	\
6149	4f31916f	bellard	[INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6150	4f31916f	bellard	[INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6151	4f31916f	bellard	[INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6152	14ce26e7	bellard	X86_64_DEF([INDEX_op_sarq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6153	4f31916f	bellard	\
6154	4f31916f	bellard	[INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6155	4f31916f	bellard	[INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6156	14ce26e7	bellard	X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6157	4f31916f	bellard	[INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6158	4f31916f	bellard	[INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6159	14ce26e7	bellard	X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6160	4f31916f	bellard	\
6161	4f31916f	bellard	[INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6162	4f31916f	bellard	[INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6163	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6164	4f31916f	bellard	[INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6165	4f31916f	bellard	[INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6166	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6167	4f31916f	bellard	\
6168	4f31916f	bellard	[INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6169	4f31916f	bellard	[INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6170	14ce26e7	bellard	[INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6171	14ce26e7	bellard	X86_64_DEF([INDEX_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,)
6172	4f31916f	bellard
6173	4f31916f	bellard
6174	4bb2fcc7	bellard	DEF_WRITEF( )
6175	4f31916f	bellard	DEF_WRITEF(_raw)
6176	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6177	4f31916f	bellard	DEF_WRITEF(_kernel)
6178	4f31916f	bellard	DEF_WRITEF(_user)
6179	4f31916f	bellard	#endif
6180	2c0262af	bellard	};
6181	2c0262af	bellard
6182	2c0262af	bellard	/* simpler form of an operation if no flags need to be generated */
6183	2c0262af	bellard	static uint16_t opc_simpler[NB_OPS] = {
6184	2c0262af	bellard	[INDEX_op_update2_cc] = INDEX_op_nop,
6185	2c0262af	bellard	[INDEX_op_update1_cc] = INDEX_op_nop,
6186	2c0262af	bellard	[INDEX_op_update_neg_cc] = INDEX_op_nop,
6187	2c0262af	bellard	#if 0
6188	2c0262af	bellard	/* broken: CC_OP logic must be rewritten */
6189	2c0262af	bellard	[INDEX_op_update_inc_cc] = INDEX_op_nop,
6190	2c0262af	bellard	#endif
6191	2c0262af	bellard
6192	2c0262af	bellard	[INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
6193	2c0262af	bellard	[INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
6194	2c0262af	bellard	[INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
6195	14ce26e7	bellard	X86_64_DEF([INDEX_op_shlq_T0_T1_cc] = INDEX_op_shlq_T0_T1,)
6196	2c0262af	bellard
6197	2c0262af	bellard	[INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
6198	2c0262af	bellard	[INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
6199	2c0262af	bellard	[INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
6200	14ce26e7	bellard	X86_64_DEF([INDEX_op_shrq_T0_T1_cc] = INDEX_op_shrq_T0_T1,)
6201	2c0262af	bellard
6202	2c0262af	bellard	[INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
6203	2c0262af	bellard	[INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
6204	2c0262af	bellard	[INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
6205	14ce26e7	bellard	X86_64_DEF([INDEX_op_sarq_T0_T1_cc] = INDEX_op_sarq_T0_T1,)
6206	4f31916f	bellard
6207	4f31916f	bellard	#define DEF_SIMPLER(SUFFIX)\
6208	4f31916f	bellard	[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
6209	4f31916f	bellard	[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
6210	4f31916f	bellard	[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
6211	14ce26e7	bellard	X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolq ## SUFFIX ## _T0_T1,)\
6212	4f31916f	bellard	\
6213	4f31916f	bellard	[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
6214	4f31916f	bellard	[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
6215	14ce26e7	bellard	[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,\
6216	14ce26e7	bellard	X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorq ## SUFFIX ## _T0_T1,)
6217	4f31916f	bellard
6218	4bb2fcc7	bellard	DEF_SIMPLER( )
6219	4f31916f	bellard	DEF_SIMPLER(_raw)
6220	4f31916f	bellard	#ifndef CONFIG_USER_ONLY
6221	4f31916f	bellard	DEF_SIMPLER(_kernel)
6222	4f31916f	bellard	DEF_SIMPLER(_user)
6223	4f31916f	bellard	#endif
6224	2c0262af	bellard	};
6225	2c0262af	bellard
6226	2c0262af	bellard	void optimize_flags_init(void)
6227	2c0262af	bellard	{
6228	2c0262af	bellard	int i;
6229	2c0262af	bellard	/* put default values in arrays */
6230	2c0262af	bellard	for(i = 0; i < NB_OPS; i++) {
6231	2c0262af	bellard	if (opc_simpler[i] == 0)
6232	2c0262af	bellard	opc_simpler[i] = i;
6233	2c0262af	bellard	}
6234	2c0262af	bellard	}
6235	2c0262af	bellard
6236	2c0262af	bellard	/* CPU flags computation optimization: we move backward thru the
6237	2c0262af	bellard	generated code to see which flags are needed. The operation is
6238	2c0262af	bellard	modified if suitable */
6239	2c0262af	bellard	static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
6240	2c0262af	bellard	{
6241	2c0262af	bellard	uint16_t *opc_ptr;
6242	2c0262af	bellard	int live_flags, write_flags, op;
6243	2c0262af	bellard
6244	2c0262af	bellard	opc_ptr = opc_buf + opc_buf_len;
6245	2c0262af	bellard	/* live_flags contains the flags needed by the next instructions
6246	2c0262af	bellard	in the code. At the end of the bloc, we consider that all the
6247	2c0262af	bellard	flags are live. */
6248	2c0262af	bellard	live_flags = CC_OSZAPC;
6249	2c0262af	bellard	while (opc_ptr > opc_buf) {
6250	2c0262af	bellard	op = *--opc_ptr;
6251	2c0262af	bellard	/* if none of the flags written by the instruction is used,
6252	2c0262af	bellard	then we can try to find a simpler instruction */
6253	2c0262af	bellard	write_flags = opc_write_flags[op];
6254	2c0262af	bellard	if ((live_flags & write_flags) == 0) {
6255	2c0262af	bellard	*opc_ptr = opc_simpler[op];
6256	2c0262af	bellard	}
6257	2c0262af	bellard	/* compute the live flags before the instruction */
6258	2c0262af	bellard	live_flags &= ~write_flags;
6259	2c0262af	bellard	live_flags \|= opc_read_flags[op];
6260	2c0262af	bellard	}
6261	2c0262af	bellard	}
6262	2c0262af	bellard
6263	2c0262af	bellard	/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
6264	2c0262af	bellard	basic block 'tb'. If search_pc is TRUE, also generate PC
6265	2c0262af	bellard	information for each intermediate instruction. */
6266	2c0262af	bellard	static inline int gen_intermediate_code_internal(CPUState *env,
6267	2c0262af	bellard	TranslationBlock *tb,
6268	2c0262af	bellard	int search_pc)
6269	2c0262af	bellard	{
6270	2c0262af	bellard	DisasContext dc1, *dc = &dc1;
6271	14ce26e7	bellard	target_ulong pc_ptr;
6272	2c0262af	bellard	uint16_t *gen_opc_end;
6273	d720b93d	bellard	int flags, j, lj, cflags;
6274	14ce26e7	bellard	target_ulong pc_start;
6275	14ce26e7	bellard	target_ulong cs_base;
6276	2c0262af	bellard
6277	2c0262af	bellard	/* generate intermediate code */
6278	14ce26e7	bellard	pc_start = tb->pc;
6279	14ce26e7	bellard	cs_base = tb->cs_base;
6280	2c0262af	bellard	flags = tb->flags;
6281	d720b93d	bellard	cflags = tb->cflags;
6282	3a1d9b8b	bellard
6283	4f31916f	bellard	dc->pe = (flags >> HF_PE_SHIFT) & 1;
6284	2c0262af	bellard	dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
6285	2c0262af	bellard	dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
6286	2c0262af	bellard	dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
6287	2c0262af	bellard	dc->f_st = 0;
6288	2c0262af	bellard	dc->vm86 = (flags >> VM_SHIFT) & 1;
6289	2c0262af	bellard	dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
6290	2c0262af	bellard	dc->iopl = (flags >> IOPL_SHIFT) & 3;
6291	2c0262af	bellard	dc->tf = (flags >> TF_SHIFT) & 1;
6292	34865134	bellard	dc->singlestep_enabled = env->singlestep_enabled;
6293	2c0262af	bellard	dc->cc_op = CC_OP_DYNAMIC;
6294	2c0262af	bellard	dc->cs_base = cs_base;
6295	2c0262af	bellard	dc->tb = tb;
6296	2c0262af	bellard	dc->popl_esp_hack = 0;
6297	2c0262af	bellard	/* select memory access functions */
6298	2c0262af	bellard	dc->mem_index = 0;
6299	2c0262af	bellard	if (flags & HF_SOFTMMU_MASK) {
6300	2c0262af	bellard	if (dc->cpl == 3)
6301	14ce26e7	bellard	dc->mem_index = 2 * 4;
6302	2c0262af	bellard	else
6303	14ce26e7	bellard	dc->mem_index = 1 * 4;
6304	2c0262af	bellard	}
6305	14ce26e7	bellard	dc->cpuid_features = env->cpuid_features;
6306	14ce26e7	bellard	#ifdef TARGET_X86_64
6307	14ce26e7	bellard	dc->lma = (flags >> HF_LMA_SHIFT) & 1;
6308	14ce26e7	bellard	dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
6309	14ce26e7	bellard	#endif
6310	7eee2a50	bellard	dc->flags = flags;
6311	a2cc3b24	bellard	dc->jmp_opt = !(dc->tf \|\| env->singlestep_enabled \|\|
6312	a2cc3b24	bellard	(flags & HF_INHIBIT_IRQ_MASK)
6313	415fa2ea	bellard	#ifndef CONFIG_SOFTMMU
6314	2c0262af	bellard	\|\| (flags & HF_SOFTMMU_MASK)
6315	2c0262af	bellard	#endif
6316	2c0262af	bellard	);
6317	4f31916f	bellard	#if 0
6318	4f31916f	bellard	/* check addseg logic */
6319	dc196a57	bellard	if (!dc->addseg && (dc->vm86 \|\| !dc->pe \|\| !dc->code32))
6320	4f31916f	bellard	printf("ERROR addseg\n");
6321	4f31916f	bellard	#endif
6322	4f31916f	bellard
6323	2c0262af	bellard	gen_opc_ptr = gen_opc_buf;
6324	2c0262af	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6325	2c0262af	bellard	gen_opparam_ptr = gen_opparam_buf;
6326	14ce26e7	bellard	nb_gen_labels = 0;
6327	2c0262af	bellard
6328	2c0262af	bellard	dc->is_jmp = DISAS_NEXT;
6329	2c0262af	bellard	pc_ptr = pc_start;
6330	2c0262af	bellard	lj = -1;
6331	2c0262af	bellard
6332	2c0262af	bellard	for(;;) {
6333	2c0262af	bellard	if (env->nb_breakpoints > 0) {
6334	2c0262af	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
6335	14ce26e7	bellard	if (env->breakpoints[j] == pc_ptr) {
6336	2c0262af	bellard	gen_debug(dc, pc_ptr - dc->cs_base);
6337	2c0262af	bellard	break;
6338	2c0262af	bellard	}
6339	2c0262af	bellard	}
6340	2c0262af	bellard	}
6341	2c0262af	bellard	if (search_pc) {
6342	2c0262af	bellard	j = gen_opc_ptr - gen_opc_buf;
6343	2c0262af	bellard	if (lj < j) {
6344	2c0262af	bellard	lj++;
6345	2c0262af	bellard	while (lj < j)
6346	2c0262af	bellard	gen_opc_instr_start[lj++] = 0;
6347	2c0262af	bellard	}
6348	14ce26e7	bellard	gen_opc_pc[lj] = pc_ptr;
6349	2c0262af	bellard	gen_opc_cc_op[lj] = dc->cc_op;
6350	2c0262af	bellard	gen_opc_instr_start[lj] = 1;
6351	2c0262af	bellard	}
6352	2c0262af	bellard	pc_ptr = disas_insn(dc, pc_ptr);
6353	2c0262af	bellard	/* stop translation if indicated */
6354	2c0262af	bellard	if (dc->is_jmp)
6355	2c0262af	bellard	break;
6356	2c0262af	bellard	/* if single step mode, we generate only one instruction and
6357	2c0262af	bellard	generate an exception */
6358	a2cc3b24	bellard	/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
6359	a2cc3b24	bellard	the flag and abort the translation to give the irqs a
6360	a2cc3b24	bellard	change to be happen */
6361	a2cc3b24	bellard	if (dc->tf \|\| dc->singlestep_enabled \|\|
6362	d720b93d	bellard	(flags & HF_INHIBIT_IRQ_MASK) \|\|
6363	d720b93d	bellard	(cflags & CF_SINGLE_INSN)) {
6364	14ce26e7	bellard	gen_jmp_im(pc_ptr - dc->cs_base);
6365	2c0262af	bellard	gen_eob(dc);
6366	2c0262af	bellard	break;
6367	2c0262af	bellard	}
6368	2c0262af	bellard	/* if too long translation, stop generation too */
6369	2c0262af	bellard	if (gen_opc_ptr >= gen_opc_end \|\|
6370	2c0262af	bellard	(pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
6371	14ce26e7	bellard	gen_jmp_im(pc_ptr - dc->cs_base);
6372	2c0262af	bellard	gen_eob(dc);
6373	2c0262af	bellard	break;
6374	2c0262af	bellard	}
6375	2c0262af	bellard	}
6376	2c0262af	bellard	*gen_opc_ptr = INDEX_op_end;
6377	2c0262af	bellard	/* we don't forget to fill the last values */
6378	2c0262af	bellard	if (search_pc) {
6379	2c0262af	bellard	j = gen_opc_ptr - gen_opc_buf;
6380	2c0262af	bellard	lj++;
6381	2c0262af	bellard	while (lj <= j)
6382	2c0262af	bellard	gen_opc_instr_start[lj++] = 0;
6383	2c0262af	bellard	}
6384	2c0262af	bellard
6385	2c0262af	bellard	#ifdef DEBUG_DISAS
6386	658c8bda	bellard	if (loglevel & CPU_LOG_TB_CPU) {
6387	7fe48483	bellard	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
6388	658c8bda	bellard	}
6389	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
6390	14ce26e7	bellard	int disas_flags;
6391	2c0262af	bellard	fprintf(logfile, "----------------\n");
6392	2c0262af	bellard	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6393	14ce26e7	bellard	#ifdef TARGET_X86_64
6394	14ce26e7	bellard	if (dc->code64)
6395	14ce26e7	bellard	disas_flags = 2;
6396	14ce26e7	bellard	else
6397	14ce26e7	bellard	#endif
6398	14ce26e7	bellard	disas_flags = !dc->code32;
6399	14ce26e7	bellard	target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
6400	2c0262af	bellard	fprintf(logfile, "\n");
6401	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_OP) {
6402	e19e89a5	bellard	fprintf(logfile, "OP:\n");
6403	e19e89a5	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
6404	e19e89a5	bellard	fprintf(logfile, "\n");
6405	e19e89a5	bellard	}
6406	2c0262af	bellard	}
6407	2c0262af	bellard	#endif
6408	2c0262af	bellard
6409	2c0262af	bellard	/* optimize flag computations */
6410	2c0262af	bellard	optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
6411	2c0262af	bellard
6412	2c0262af	bellard	#ifdef DEBUG_DISAS
6413	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_OP_OPT) {
6414	2c0262af	bellard	fprintf(logfile, "AFTER FLAGS OPT:\n");
6415	2c0262af	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
6416	2c0262af	bellard	fprintf(logfile, "\n");
6417	2c0262af	bellard	}
6418	2c0262af	bellard	#endif
6419	2c0262af	bellard	if (!search_pc)
6420	2c0262af	bellard	tb->size = pc_ptr - pc_start;
6421	2c0262af	bellard	return 0;
6422	2c0262af	bellard	}
6423	2c0262af	bellard
6424	2c0262af	bellard	int gen_intermediate_code(CPUState env, TranslationBlock tb)
6425	2c0262af	bellard	{
6426	2c0262af	bellard	return gen_intermediate_code_internal(env, tb, 0);
6427	2c0262af	bellard	}
6428	2c0262af	bellard
6429	2c0262af	bellard	int gen_intermediate_code_pc(CPUState env, TranslationBlock tb)
6430	2c0262af	bellard	{
6431	2c0262af	bellard	return gen_intermediate_code_internal(env, tb, 1);
6432	2c0262af	bellard	}

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